# Fri Aug 30 13:35:27 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-063

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 198MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 199MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)


Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)


Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:03s; Memory used current: 219MB peak: 221MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.47ns		 510 /       388
   2		0h:00m:03s		    -2.47ns		 509 /       388
   3		0h:00m:03s		    -2.21ns		 506 /       388
   4		0h:00m:03s		    -2.39ns		 506 /       388
   5		0h:00m:03s		    -2.21ns		 507 /       388
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   6		0h:00m:04s		    -2.21ns		 515 /       390
   7		0h:00m:04s		    -2.35ns		 516 /       390


   8		0h:00m:04s		    -2.21ns		 516 /       390

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:04s; Memory used current: 224MB peak: 225MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:04s; Memory used current: 224MB peak: 225MB)


Start Writing Netlists (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:04s; Memory used current: 153MB peak: 226MB)

Writing Analyst data base E:\W-File\Advanced_FIR_Fliter2\RefDesign\Reload\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:05s; Memory used current: 223MB peak: 226MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:06s; Memory used current: 223MB peak: 226MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:06s; Memory used current: 222MB peak: 226MB)


Start final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 226MB)

@W: MT420 |Found inferred clock ao_top_0|clk_i with period 4.57ns. Please declare a user-defined clock on port clk_i.
@W: MT420 |Found inferred clock ao_top_0|control[0] with period 5.69ns. Please declare a user-defined clock on port control[0].


##### START OF TIMING REPORT #####[
# Timing report written on Fri Aug 30 13:35:40 2019
#


Top view:               ao_top_0
Requested Frequency:    175.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.004

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          219.0 MHz     186.2 MHz     4.566         5.371         -0.806     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     175.8 MHz     149.5 MHz     5.687         6.690         -1.004     inferred     Autoconstr_clkgroup_1
System                  150.0 MHz     235.7 MHz     6.667         4.243         2.424      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  4.566       2.424   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  5.687       3.771   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  4.566       3.788   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  4.566       -0.806  |  4.566       3.727  |  No paths    -      |  2.283       1.444
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  5.687       4.909   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  5.687       -1.004  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                                 Arrival           
Instance                             Reference          Type     Pin     Net                                  Time        Slack 
                                     Clock                                                                                      
--------------------------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.243       -0.806
genblk3\.u_ao_match_2.match_sep      ao_top_0|clk_i     DFFC     Q       match                                0.243       -0.785
triger_level_cnt[0]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[0]                  0.243       -0.698
triger_level_cnt[1]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[1]                  0.243       -0.607
capture_window_sel[2]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[2]                0.243       -0.577
capture_window_sel[3]                ao_top_0|clk_i     DFFC     Q       un6_start_reg_ac0_6                  0.243       -0.399
u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC     Q       capture_length[0]                    0.243       -0.275
u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC     Q       capture_length[1]                    0.243       -0.167
triger_level_cnt[3]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[3]                  0.243       0.058 
triger_level_cnt[2]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[2]                  0.243       0.079 
================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                        Required           
Instance                              Reference          Type      Pin     Net                        Time         Slack 
                                      Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]      4.505        -0.806
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]      4.505        -0.698
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]      4.505        -0.607
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      un1_start_reg              4.505        -0.577
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      g0                         4.505        -0.352
triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]      4.505        0.212 
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6       4.505        0.214 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]     4.505        0.214 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]     4.505        0.214 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]     4.505        0.214 
=========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      5.310
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.806

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                 Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     DFFC     Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]     Net      -        -       0.535     -           1         
un1_match_final_3                    LUT4     I1       In      -         0.778       -         
un1_match_final_3                    LUT4     F        Out     0.570     1.348       -         
un1_match_final_3                    Net      -        -       0.401     -           1         
un1_match_final                      LUT3     I2       In      -         1.749       -         
un1_match_final                      LUT3     F        Out     0.462     2.211       -         
un1_match_final                      Net      -        -       0.535     -           3         
triger_level_cnt13                   LUT3     I2       In      -         2.746       -         
triger_level_cnt13                   LUT3     F        Out     0.462     3.208       -         
triger_level_cnt13                   Net      -        -       0.535     -           4         
un1_triger_level_cnt12               LUT4     I2       In      -         3.743       -         
un1_triger_level_cnt12               LUT4     F        Out     0.462     4.205       -         
un1_triger_level_cnt12               Net      -        -       0.535     -           3         
triger_level_cnt_4[2]                LUT3     I1       In      -         4.740       -         
triger_level_cnt_4[2]                LUT3     F        Out     0.570     5.310       -         
triger_level_cnt_4[2]                Net      -        -       0.000     -           1         
triger_level_cnt[2]                  DFFC     D        In      -         5.310       -         
===============================================================================================
Total path delay (propagation time + setup) of 5.371 is 2.830(52.7%) logic and 2.541(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      5.289
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.785

    Number of logic level(s):                5
    Starting point:                          genblk3\.u_ao_match_2.match_sep / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
genblk3\.u_ao_match_2.match_sep     DFFC     Q        Out     0.243     0.243       -         
match                               Net      -        -       0.535     -           1         
un1_match_final_3                   LUT4     I0       In      -         0.778       -         
un1_match_final_3                   LUT4     F        Out     0.549     1.327       -         
un1_match_final_3                   Net      -        -       0.401     -           1         
un1_match_final                     LUT3     I2       In      -         1.728       -         
un1_match_final                     LUT3     F        Out     0.462     2.190       -         
un1_match_final                     Net      -        -       0.535     -           3         
triger_level_cnt13                  LUT3     I2       In      -         2.725       -         
triger_level_cnt13                  LUT3     F        Out     0.462     3.187       -         
triger_level_cnt13                  Net      -        -       0.535     -           4         
un1_triger_level_cnt12              LUT4     I2       In      -         3.722       -         
un1_triger_level_cnt12              LUT4     F        Out     0.462     4.184       -         
un1_triger_level_cnt12              Net      -        -       0.535     -           3         
triger_level_cnt_4[2]               LUT3     I1       In      -         4.719       -         
triger_level_cnt_4[2]               LUT3     F        Out     0.570     5.289       -         
triger_level_cnt_4[2]               Net      -        -       0.000     -           1         
triger_level_cnt[2]                 DFFC     D        In      -         5.289       -         
==============================================================================================
Total path delay (propagation time + setup) of 5.350 is 2.809(52.5%) logic and 2.541(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      5.289
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.785

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                 Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     DFFC     Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]     Net      -        -       0.535     -           1         
un1_match_final_3                    LUT4     I1       In      -         0.778       -         
un1_match_final_3                    LUT4     F        Out     0.570     1.348       -         
un1_match_final_3                    Net      -        -       0.401     -           1         
un1_match_final                      LUT3     I2       In      -         1.749       -         
un1_match_final                      LUT3     F        Out     0.462     2.211       -         
un1_match_final                      Net      -        -       0.535     -           3         
triger_level_cnt13                   LUT3     I2       In      -         2.746       -         
triger_level_cnt13                   LUT3     F        Out     0.462     3.208       -         
triger_level_cnt13                   Net      -        -       0.535     -           4         
un1_triger_level_cnt_ac0_1           LUT3     I0       In      -         3.743       -         
un1_triger_level_cnt_ac0_1           LUT3     F        Out     0.549     4.292       -         
un1_triger_level_cnt_c2              Net      -        -       0.535     -           2         
triger_level_cnt_4[2]                LUT3     I2       In      -         4.827       -         
triger_level_cnt_4[2]                LUT3     F        Out     0.462     5.289       -         
triger_level_cnt_4[2]                Net      -        -       0.000     -           1         
triger_level_cnt[2]                  DFFC     D        In      -         5.289       -         
===============================================================================================
Total path delay (propagation time + setup) of 5.350 is 2.809(52.5%) logic and 2.541(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      5.268
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.764

    Number of logic level(s):                5
    Starting point:                          genblk3\.u_ao_match_2.match_sep / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
genblk3\.u_ao_match_2.match_sep     DFFC     Q        Out     0.243     0.243       -         
match                               Net      -        -       0.535     -           1         
un1_match_final_3                   LUT4     I0       In      -         0.778       -         
un1_match_final_3                   LUT4     F        Out     0.549     1.327       -         
un1_match_final_3                   Net      -        -       0.401     -           1         
un1_match_final                     LUT3     I2       In      -         1.728       -         
un1_match_final                     LUT3     F        Out     0.462     2.190       -         
un1_match_final                     Net      -        -       0.535     -           3         
triger_level_cnt13                  LUT3     I2       In      -         2.725       -         
triger_level_cnt13                  LUT3     F        Out     0.462     3.187       -         
triger_level_cnt13                  Net      -        -       0.535     -           4         
un1_triger_level_cnt_ac0_1          LUT3     I0       In      -         3.722       -         
un1_triger_level_cnt_ac0_1          LUT3     F        Out     0.549     4.271       -         
un1_triger_level_cnt_c2             Net      -        -       0.535     -           2         
triger_level_cnt_4[2]               LUT3     I2       In      -         4.806       -         
triger_level_cnt_4[2]               LUT3     F        Out     0.462     5.268       -         
triger_level_cnt_4[2]               Net      -        -       0.000     -           1         
triger_level_cnt[2]                 DFFC     D        In      -         5.268       -         
==============================================================================================
Total path delay (propagation time + setup) of 5.329 is 2.788(52.3%) logic and 2.541(47.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      5.202
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.698

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[0] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
triger_level_cnt[0]        DFFC     Q        Out     0.243     0.243       -         
triger_level_cnt[0]        Net      -        -       0.535     -           5         
un1_match_final_3          LUT4     I2       In      -         0.778       -         
un1_match_final_3          LUT4     F        Out     0.462     1.240       -         
un1_match_final_3          Net      -        -       0.401     -           1         
un1_match_final            LUT3     I2       In      -         1.641       -         
un1_match_final            LUT3     F        Out     0.462     2.103       -         
un1_match_final            Net      -        -       0.535     -           3         
triger_level_cnt13         LUT3     I2       In      -         2.638       -         
triger_level_cnt13         LUT3     F        Out     0.462     3.100       -         
triger_level_cnt13         Net      -        -       0.535     -           4         
un1_triger_level_cnt12     LUT4     I2       In      -         3.635       -         
un1_triger_level_cnt12     LUT4     F        Out     0.462     4.097       -         
un1_triger_level_cnt12     Net      -        -       0.535     -           3         
triger_level_cnt_4[2]      LUT3     I1       In      -         4.632       -         
triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.202       -         
triger_level_cnt_4[2]      Net      -        -       0.000     -           1         
triger_level_cnt[2]        DFFC     D        In      -         5.202       -         
=====================================================================================
Total path delay (propagation time + setup) of 5.263 is 2.722(51.7%) logic and 2.541(48.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                   Arrival           
Instance                         Reference               Type      Pin     Net                              Time        Slack 
                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------
internal_register_select[0]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[0]      0.243       -1.004
internal_register_select[1]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[1]      0.243       -0.964
internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -0.888
internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -0.867
internal_register_select[4]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[4]      0.243       -0.821
internal_register_select[3]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[3]      0.243       -0.809
internal_register_select[2]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[2]      0.243       -0.788
internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.780
module_state_fast[0]             ao_top_0|control[0]     DFFP      Q       module_state_fast[0]             0.243       -0.767
internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -0.718
==============================================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                               Required           
Instance                   Reference               Type      Pin     Net                          Time         Slack 
                           Clock                                                                                     
---------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[4]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[4]      5.626        -1.004
data_out_shift_reg[8]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[8]      5.626        -1.004
data_out_shift_reg[10]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[10]     5.626        -1.004
data_out_shift_reg[14]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[14]     5.626        -1.004
data_out_shift_reg[1]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]      5.626        -0.900
data_out_shift_reg[2]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]      5.626        -0.888
data_out_shift_reg[3]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[3]      5.626        -0.888
data_out_shift_reg[5]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[5]      5.626        -0.888
data_out_shift_reg[7]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[7]      5.626        -0.888
data_out_shift_reg[11]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[11]     5.626        -0.888
=====================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      5.687
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.626

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.004

    Number of logic level(s):                6
    Starting point:                          internal_register_select[0] / Q
    Ending point:                            data_out_shift_reg[4] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[0]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[0]         Net       -        -       0.718     -           38        
data_from_internal_reg100_13_1      LUT2      I0       In      -         0.961       -         
data_from_internal_reg100_13_1      LUT2      F        Out     0.549     1.510       -         
data_from_internal_reg100_13_1      Net       -        -       0.535     -           4         
data_from_internal_reg100_13        LUT4      I1       In      -         2.045       -         
data_from_internal_reg100_13        LUT4      F        Out     0.570     2.615       -         
data_from_internal_reg100_13        Net       -        -       0.596     -           13        
data_out_shift_reg_4_1_a2_4[14]     LUT3      I1       In      -         3.211       -         
data_out_shift_reg_4_1_a2_4[14]     LUT3      F        Out     0.570     3.781       -         
N_137                               Net       -        -       0.535     -           4         
data_out_shift_reg_4_1_N_8L17       LUT4      I1       In      -         4.316       -         
data_out_shift_reg_4_1_N_8L17       LUT4      F        Out     0.570     4.886       -         
data_out_shift_reg_4_1_N_8L17       Net       -        -       0.401     -           1         
data_out_shift_reg_4_1_N_9L20       LUT4      I3       In      -         5.287       -         
data_out_shift_reg_4_1_N_9L20       LUT4      F        Out     0.371     5.658       -         
data_out_shift_reg_4_1_N_9L20       Net       -        -       0.401     -           1         
data_out_shift_reg_4_1[4]           LUT4      I1       In      -         6.059       -         
data_out_shift_reg_4_1[4]           LUT4      F        Out     0.570     6.629       -         
data_out_shift_reg_4[4]             Net       -        -       0.000     -           1         
data_out_shift_reg[4]               DFFCE     D        In      -         6.629       -         
===============================================================================================
Total path delay (propagation time + setup) of 6.690 is 3.504(52.4%) logic and 3.186(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.687
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.626

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.004

    Number of logic level(s):                6
    Starting point:                          internal_register_select[0] / Q
    Ending point:                            data_out_shift_reg[14] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[0]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[0]         Net       -        -       0.718     -           38        
data_from_internal_reg100_13_1      LUT2      I0       In      -         0.961       -         
data_from_internal_reg100_13_1      LUT2      F        Out     0.549     1.510       -         
data_from_internal_reg100_13_1      Net       -        -       0.535     -           4         
data_from_internal_reg100_13        LUT4      I1       In      -         2.045       -         
data_from_internal_reg100_13        LUT4      F        Out     0.570     2.615       -         
data_from_internal_reg100_13        Net       -        -       0.596     -           13        
data_out_shift_reg_4_1_a2_4[14]     LUT3      I1       In      -         3.211       -         
data_out_shift_reg_4_1_a2_4[14]     LUT3      F        Out     0.570     3.781       -         
N_137                               Net       -        -       0.535     -           4         
data_out_shift_reg_4_1_N_8L17_2     LUT4      I1       In      -         4.316       -         
data_out_shift_reg_4_1_N_8L17_2     LUT4      F        Out     0.570     4.886       -         
data_out_shift_reg_4_1_N_8L17_2     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1_N_9L20_2     LUT4      I3       In      -         5.287       -         
data_out_shift_reg_4_1_N_9L20_2     LUT4      F        Out     0.371     5.658       -         
data_out_shift_reg_4_1_N_9L20_2     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1[14]          LUT4      I1       In      -         6.059       -         
data_out_shift_reg_4_1[14]          LUT4      F        Out     0.570     6.629       -         
data_out_shift_reg_4[14]            Net       -        -       0.000     -           1         
data_out_shift_reg[14]              DFFCE     D        In      -         6.629       -         
===============================================================================================
Total path delay (propagation time + setup) of 6.690 is 3.504(52.4%) logic and 3.186(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.687
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.626

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.004

    Number of logic level(s):                6
    Starting point:                          internal_register_select[0] / Q
    Ending point:                            data_out_shift_reg[8] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[0]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[0]         Net       -        -       0.718     -           38        
data_from_internal_reg100_13_1      LUT2      I0       In      -         0.961       -         
data_from_internal_reg100_13_1      LUT2      F        Out     0.549     1.510       -         
data_from_internal_reg100_13_1      Net       -        -       0.535     -           4         
data_from_internal_reg100_13        LUT4      I1       In      -         2.045       -         
data_from_internal_reg100_13        LUT4      F        Out     0.570     2.615       -         
data_from_internal_reg100_13        Net       -        -       0.596     -           13        
data_out_shift_reg_4_1_a2_4[14]     LUT3      I1       In      -         3.211       -         
data_out_shift_reg_4_1_a2_4[14]     LUT3      F        Out     0.570     3.781       -         
N_137                               Net       -        -       0.535     -           4         
data_out_shift_reg_4_1_N_8L17_1     LUT4      I1       In      -         4.316       -         
data_out_shift_reg_4_1_N_8L17_1     LUT4      F        Out     0.570     4.886       -         
data_out_shift_reg_4_1_N_8L17_1     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1_N_9L20_1     LUT4      I3       In      -         5.287       -         
data_out_shift_reg_4_1_N_9L20_1     LUT4      F        Out     0.371     5.658       -         
data_out_shift_reg_4_1_N_9L20_1     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1[8]           LUT4      I1       In      -         6.059       -         
data_out_shift_reg_4_1[8]           LUT4      F        Out     0.570     6.629       -         
data_out_shift_reg_4[8]             Net       -        -       0.000     -           1         
data_out_shift_reg[8]               DFFCE     D        In      -         6.629       -         
===============================================================================================
Total path delay (propagation time + setup) of 6.690 is 3.504(52.4%) logic and 3.186(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.687
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.626

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.004

    Number of logic level(s):                6
    Starting point:                          internal_register_select[0] / Q
    Ending point:                            data_out_shift_reg[10] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[0]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[0]         Net       -        -       0.718     -           38        
data_from_internal_reg100_13_1      LUT2      I0       In      -         0.961       -         
data_from_internal_reg100_13_1      LUT2      F        Out     0.549     1.510       -         
data_from_internal_reg100_13_1      Net       -        -       0.535     -           4         
data_from_internal_reg100_13        LUT4      I1       In      -         2.045       -         
data_from_internal_reg100_13        LUT4      F        Out     0.570     2.615       -         
data_from_internal_reg100_13        Net       -        -       0.596     -           13        
data_out_shift_reg_4_1_a2_4[14]     LUT3      I1       In      -         3.211       -         
data_out_shift_reg_4_1_a2_4[14]     LUT3      F        Out     0.570     3.781       -         
N_137                               Net       -        -       0.535     -           4         
data_out_shift_reg_4_1_N_8L17_0     LUT4      I1       In      -         4.316       -         
data_out_shift_reg_4_1_N_8L17_0     LUT4      F        Out     0.570     4.886       -         
data_out_shift_reg_4_1_N_8L17_0     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1_N_9L20_0     LUT4      I3       In      -         5.287       -         
data_out_shift_reg_4_1_N_9L20_0     LUT4      F        Out     0.371     5.658       -         
data_out_shift_reg_4_1_N_9L20_0     Net       -        -       0.401     -           1         
data_out_shift_reg_4_1[10]          LUT4      I1       In      -         6.059       -         
data_out_shift_reg_4_1[10]          LUT4      F        Out     0.570     6.629       -         
data_out_shift_reg_4[10]            Net       -        -       0.000     -           1         
data_out_shift_reg[10]              DFFCE     D        In      -         6.629       -         
===============================================================================================
Total path delay (propagation time + setup) of 6.690 is 3.504(52.4%) logic and 3.186(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.687
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.626

    - Propagation time:                      6.589
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.964

    Number of logic level(s):                6
    Starting point:                          internal_register_select[1] / Q
    Ending point:                            data_out_shift_reg[4] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[1]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[1]         Net       -        -       0.657     -           21        
data_from_internal_reg100_13_1      LUT2      I1       In      -         0.900       -         
data_from_internal_reg100_13_1      LUT2      F        Out     0.570     1.470       -         
data_from_internal_reg100_13_1      Net       -        -       0.535     -           4         
data_from_internal_reg100_13        LUT4      I1       In      -         2.005       -         
data_from_internal_reg100_13        LUT4      F        Out     0.570     2.575       -         
data_from_internal_reg100_13        Net       -        -       0.596     -           13        
data_out_shift_reg_4_1_a2_4[14]     LUT3      I1       In      -         3.171       -         
data_out_shift_reg_4_1_a2_4[14]     LUT3      F        Out     0.570     3.741       -         
N_137                               Net       -        -       0.535     -           4         
data_out_shift_reg_4_1_N_8L17       LUT4      I1       In      -         4.276       -         
data_out_shift_reg_4_1_N_8L17       LUT4      F        Out     0.570     4.846       -         
data_out_shift_reg_4_1_N_8L17       Net       -        -       0.401     -           1         
data_out_shift_reg_4_1_N_9L20       LUT4      I3       In      -         5.247       -         
data_out_shift_reg_4_1_N_9L20       LUT4      F        Out     0.371     5.618       -         
data_out_shift_reg_4_1_N_9L20       Net       -        -       0.401     -           1         
data_out_shift_reg_4_1[4]           LUT4      I1       In      -         6.019       -         
data_out_shift_reg_4_1[4]           LUT4      F        Out     0.570     6.589       -         
data_out_shift_reg_4[4]             Net       -        -       0.000     -           1         
data_out_shift_reg[4]               DFFCE     D        In      -         6.589       -         
===============================================================================================
Total path delay (propagation time + setup) of 6.650 is 3.525(53.0%) logic and 3.125(47.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.424
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       3.771
=============================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.505        2.424
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.505        2.424
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.505        2.648
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.505        3.421
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.505        3.421
address_counter[9]            System        DFFCE     D       address_counter_s[9]            5.626        3.771
address_counter[8]            System        DFFCE     D       address_counter_s[8]            5.626        3.806
address_counter[7]            System        DFFCE     D       address_counter_s[7]            5.626        3.841
address_counter[6]            System        DFFCE     D       address_counter_s[6]            5.626        3.876
address_counter[5]            System        DFFCE     D       address_counter_s[5]            5.626        3.911
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.566
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.505

    - Propagation time:                      2.081
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.424

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       0.535     -           6         
un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -         
un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -         
un1_capture_window_sel_c2                Net      -        -       0.535     -           2         
capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -         
capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -         
capture_window_sel_3[2]                  Net      -        -       0.000     -           1         
capture_window_sel[2]                    DFFC     D        In      -         2.081       -         
===================================================================================================
Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 226MB)


Finished timing report (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 226MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw2a_18pbga256-8
Cell usage:
ALU             70 uses
DFF             38 uses
DFFC            45 uses
DFFCE           268 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       1 use
SDPX9           3 uses
LUT2            58 uses
LUT3            119 uses
LUT4            286 uses

I/O ports: 87
I/O primitives: 67
IBUF           65 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   390 of 15552 (2%)

RAM/ROM usage summary
Block Rams : 3 of 46 (6%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 313

@S |Mapping Summary:
Total  LUTs: 463 (2%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:07s; Memory used current: 44MB peak: 226MB)

Process took 0h:00m:13s realtime, 0h:00m:07s cputime
# Fri Aug 30 13:35:40 2019

###########################################################]
