<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device>gw2a18-002</Device>
    <FileList>
        <File path="src/project.gao" type="file.gao" enable="1"/>
        <File path="src/Reload_example.v" type="file.verilog" enable="1"/>
        <File path="src/Reload.cst" type="file.cst" enable="1"/>
        <File path="src/advanced_fir_filter/advanced_fir_filter.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rom_c.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rom_t.v" type="file.verilog" enable="1"/>
    </FileList>
</Project>
