`

    #Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
    #install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    #OS: Windows 8 6.2
    #Hostname: GW-SW-063

    # Thu Aug 29 14:22:11 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\gw_ao_expression.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
    @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
    @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
    @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
    @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
    @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
    @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
    @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
    @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
    @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
    @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
    @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
    @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
    @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
    @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
    @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
    @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
    @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
    @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
    @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
    @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
    @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top_0
    Running optimization stage 1 on ao_mem_ctrl_0_1024s_58s_10s .......
    Running optimization stage 1 on ao_crc32_0 .......
    Running optimization stage 1 on ao_match_0_0s_1s_58s_0_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_top_0 .......
    Running optimization stage 2 on ao_match_0_0s_1s_58s_0_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_top_0 .......
    Extracted state machine for register module_state
    State machine has 11 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1001
       1010
       1011
    Running optimization stage 2 on ao_crc32_0 .......
    Running optimization stage 2 on ao_mem_ctrl_0_1024s_58s_10s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Aug 29 14:22:12 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Aug 29 14:22:13 2019

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Aug 29 14:22:13 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Aug 29 14:22:14 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Thu Aug 29 14:22:15 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    @N:MF284 :  | Setting synthesis effort to medium for the design
    Linked File:  ao_0_scck.rpt
    Printing clock  summary report in "E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 103MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
    original code -> new code
       0000 -> 00000000001
       0001 -> 00000000010
       0010 -> 00000000100
       0011 -> 00000001000
       0100 -> 00000010000
       0101 -> 00000100000
       0110 -> 00001000000
       0111 -> 00010000000
       1001 -> 00100000000
       1010 -> 01000000000
       1011 -> 10000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Clock Summary
    ******************

              Start                   Requested     Requested     Clock        Clock                     Clock
    Level     Clock                   Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------------------
    0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     379

    0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     158
    ==========================================================================================================

    Clock Load Summary
    ***********************

                            Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|control[0]     379       control[0](port)     data_register[78:0].C                    -                 -

    ao_top_0|clk_i          158       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    ======================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 480 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ============================= Non-Gated/Non-Generated Clocks =============================
    Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
    ------------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           Unconstrained_port        101        ENCRYPTED
    ClockId_0_1       ENCRYPTED           Unconstrained_io_port     379        ENCRYPTED
    ==========================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Thu Aug 29 14:22:17 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Thu Aug 29 14:22:17 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1-1-Beta1
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

    Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)

    Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 199MB peak: 199MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 200MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 200MB)

    Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 200MB)

    Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:03s		    -2.44ns		 474 /       415
       2		0h:00m:03s		    -2.44ns		 479 /       415
       3		0h:00m:03s		    -2.58ns		 479 /       415
    Timing driven replication report
    Added 3 Registers via timing driven replication
    Added 3 LUTs via timing driven replication

       4		0h:00m:03s		    -2.30ns		 489 /       418
       5		0h:00m:03s		    -2.44ns		 489 /       418
       6		0h:00m:03s		    -2.16ns		 490 /       418

       7		0h:00m:03s		    -2.16ns		 490 /       418
       8		0h:00m:03s		    -2.30ns		 491 /       418
       9		0h:00m:03s		    -2.30ns		 492 /       418

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 217MB peak: 217MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 144MB peak: 218MB)

    Writing Analyst data base E:\W-File\Advanced_FIR_Fliter2\RefDesign\Default\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 216MB peak: 219MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 215MB peak: 219MB)

    Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 215MB peak: 219MB)

    @W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.57ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 5.53ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu Aug 29 14:22:25 2019
    #

    Top view:               ao_top_0
    Requested Frequency:    180.7 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.977

                            Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i          218.6 MHz     185.8 MHz     4.574         5.381         -0.807     inferred     Autoconstr_clkgroup_0
    ao_top_0|control[0]     180.7 MHz     153.6 MHz     5.535         6.511         -0.977     inferred     Autoconstr_clkgroup_1
    System                  150.0 MHz     236.2 MHz     6.667         4.234         2.432      system       system_clkgroup
    =============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------
    Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------
    System               ao_top_0|clk_i       |  4.574       2.432   |  No paths    -      |  No paths    -      |  No paths    -
    System               ao_top_0|control[0]  |  5.535       3.619   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       System               |  4.574       3.796   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       ao_top_0|clk_i       |  4.574       -0.807  |  4.574       3.735  |  No paths    -      |  2.287       1.448
    ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  System               |  5.535       4.757   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|control[0]  |  5.535       -0.977  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top_0|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                                                  Arrival
    Instance                             Reference          Type      Pin     Net                                  Time        Slack
                                         Clock
    ---------------------------------------------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep      ao_top_0|clk_i     DFFC      Q       match                                0.243       -0.807
    internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC      Q       internal_reg_force_triger_syn[1]     0.243       -0.786
    capture_window_sel[2]                ao_top_0|clk_i     DFFC      Q       capture_window_sel[2]                0.243       -0.750
    capture_window_sel[0]                ao_top_0|clk_i     DFFC      Q       capture_window_sel[0]                0.243       -0.729
    genblk2\.u_ao_match_1.match_sep      ao_top_0|clk_i     DFFC      Q       match                                0.243       -0.699
    triger_level_cnt[0]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[0]                  0.243       -0.608
    trigger_seq_start                    ao_top_0|clk_i     DFFCE     Q       trigger_seq_start                    0.243       -0.169
    u_ao_mem_ctrl.capture_loop           ao_top_0|clk_i     DFFCE     Q       capture_loop                         0.243       -0.148
    triger_level_cnt[1]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[1]                  0.243       0.009
    triger_level_cnt[2]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]                  0.243       0.026
    =================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                         Required
    Instance                              Reference          Type      Pin     Net                         Time         Slack
                                          Clock
    --------------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       4.513        -0.807
    u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      g0                          4.513        -0.750
    triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       4.513        -0.699
    triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       4.513        -0.608
    triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]       4.513        -0.608
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     4.513        -0.495
    trigger_seq_start                     ao_top_0|clk_i     DFFCE     CE      un2_start_reg               4.513        0.200
    u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6        4.513        0.223
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]      4.513        0.223
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]      4.513        0.223
    ==========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      5.320
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.807

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep          DFFC     Q        Out     0.243     0.243       -
    match                                    Net      -        -       0.535     -           2
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     I1       In      -         0.778       -
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     F        Out     0.570     1.348       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3_1     Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     I0       In      -         1.749       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     F        Out     0.549     2.298       -
    addr_ct_en_sn.triger_m2_0_a2_1_1         Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2             LUT4     I3       In      -         2.699       -
    addr_ct_en_sn.triger_m2_0_a2             LUT4     F        Out     0.371     3.070       -
    triger_level_cnt_0_sqmuxa                Net      -        -       0.596     -           15
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     I0       In      -         3.666       -
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     F        Out     0.549     4.215       -
    un1_triger_level_cnt12                   Net      -        -       0.535     -           4
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     I1       In      -         4.750       -
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.320       -
    triger_level_cnt_4[2]                    Net      -        -       0.000     -           1
    triger_level_cnt[2]                      DFFC     D        In      -         5.320       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 5.381 is 2.913(54.1%) logic and 2.468(45.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      5.299
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.786

        Number of logic level(s):                5
        Starting point:                          internal_reg_force_triger_syn[1] / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_reg_force_triger_syn[1]         DFFC     Q        Out     0.243     0.243       -
    internal_reg_force_triger_syn[1]         Net      -        -       0.535     -           2
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     I0       In      -         0.778       -
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     F        Out     0.549     1.327       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3_1     Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     I0       In      -         1.728       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     F        Out     0.549     2.277       -
    addr_ct_en_sn.triger_m2_0_a2_1_1         Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2             LUT4     I3       In      -         2.678       -
    addr_ct_en_sn.triger_m2_0_a2             LUT4     F        Out     0.371     3.049       -
    triger_level_cnt_0_sqmuxa                Net      -        -       0.596     -           15
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     I0       In      -         3.645       -
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     F        Out     0.549     4.194       -
    un1_triger_level_cnt12                   Net      -        -       0.535     -           4
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     I1       In      -         4.729       -
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.299       -
    triger_level_cnt_4[2]                    Net      -        -       0.000     -           1
    triger_level_cnt[2]                      DFFC     D        In      -         5.299       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 5.360 is 2.892(54.0%) logic and 2.468(46.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      5.263
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.750

        Number of logic level(s):                5
        Starting point:                          capture_window_sel[2] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    capture_window_sel[2]            DFFC      Q        Out     0.243     0.243       -
    capture_window_sel[2]            Net       -        -       0.535     -           5
    un6_start_reg_ac0_5_c_2          LUT4      I1       In      -         0.778       -
    un6_start_reg_ac0_5_c_2          LUT4      F        Out     0.570     1.348       -
    un6_start_reg_ac0_5_c_1          Net       -        -       0.535     -           2
    addr_ct_en_sn.start_reg_1        LUT3      I2       In      -         1.883       -
    addr_ct_en_sn.start_reg_1        LUT3      F        Out     0.462     2.345       -
    addr_ct_en_sn.start_reg_1        Net       -        -       0.401     -           1
    addr_ct_en_sn.start_reg          LUT4      I1       In      -         2.746       -
    addr_ct_en_sn.start_reg          LUT4      F        Out     0.570     3.316       -
    start_reg                        Net       -        -       0.535     -           4
    u_ao_mem_ctrl.g0_1               LUT4      I2       In      -         3.851       -
    u_ao_mem_ctrl.g0_1               LUT4      F        Out     0.462     4.313       -
    g0_1                             Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0                 LUT4      I0       In      -         4.714       -
    u_ao_mem_ctrl.g0                 LUT4      F        Out     0.549     5.263       -
    g0                               Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.263       -
    ============================================================================================
    Total path delay (propagation time + setup) of 5.324 is 2.917(54.8%) logic and 2.407(45.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      5.242
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.729

        Number of logic level(s):                5
        Starting point:                          capture_window_sel[0] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    capture_window_sel[0]            DFFC      Q        Out     0.243     0.243       -
    capture_window_sel[0]            Net       -        -       0.535     -           7
    un6_start_reg_ac0_5_c_2          LUT4      I0       In      -         0.778       -
    un6_start_reg_ac0_5_c_2          LUT4      F        Out     0.549     1.327       -
    un6_start_reg_ac0_5_c_1          Net       -        -       0.535     -           2
    addr_ct_en_sn.start_reg_1        LUT3      I2       In      -         1.862       -
    addr_ct_en_sn.start_reg_1        LUT3      F        Out     0.462     2.324       -
    addr_ct_en_sn.start_reg_1        Net       -        -       0.401     -           1
    addr_ct_en_sn.start_reg          LUT4      I1       In      -         2.725       -
    addr_ct_en_sn.start_reg          LUT4      F        Out     0.570     3.295       -
    start_reg                        Net       -        -       0.535     -           4
    u_ao_mem_ctrl.g0_1               LUT4      I2       In      -         3.830       -
    u_ao_mem_ctrl.g0_1               LUT4      F        Out     0.462     4.292       -
    g0_1                             Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0                 LUT4      I0       In      -         4.693       -
    u_ao_mem_ctrl.g0                 LUT4      F        Out     0.549     5.242       -
    g0                               Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.242       -
    ============================================================================================
    Total path delay (propagation time + setup) of 5.303 is 2.896(54.6%) logic and 2.407(45.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      5.212
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.699

        Number of logic level(s):                5
        Starting point:                          genblk2\.u_ao_match_1.match_sep / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    genblk2\.u_ao_match_1.match_sep          DFFC     Q        Out     0.243     0.243       -
    match                                    Net      -        -       0.535     -           2
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     I2       In      -         0.778       -
    addr_ct_en_sn.triger_m2_0_a2_N_2L1       LUT4     F        Out     0.462     1.240       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3_1     Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     I0       In      -         1.641       -
    addr_ct_en_sn.triger_m2_0_a2_N_3L3       LUT4     F        Out     0.549     2.190       -
    addr_ct_en_sn.triger_m2_0_a2_1_1         Net      -        -       0.401     -           1
    addr_ct_en_sn.triger_m2_0_a2             LUT4     I3       In      -         2.591       -
    addr_ct_en_sn.triger_m2_0_a2             LUT4     F        Out     0.371     2.962       -
    triger_level_cnt_0_sqmuxa                Net      -        -       0.596     -           15
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     I0       In      -         3.558       -
    addr_ct_en_sn.un1_triger_level_cnt12     LUT2     F        Out     0.549     4.107       -
    un1_triger_level_cnt12                   Net      -        -       0.535     -           4
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     I1       In      -         4.642       -
    addr_ct_en_sn.triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.212       -
    triger_level_cnt_4[2]                    Net      -        -       0.000     -           1
    triger_level_cnt[2]                      DFFC     D        In      -         5.212       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 5.273 is 2.805(53.2%) logic and 2.468(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top_0|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                   Arrival
    Instance                         Reference               Type      Pin     Net                              Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -0.977
    internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -0.956
    internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -0.956
    internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -0.935
    internal_register_select[14]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[14]     0.243       -0.869
    internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.848
    internal_register_select[15]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[15]     0.243       -0.778
    internal_register_select[11]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[11]     0.243       -0.757
    module_state[3]                  ao_top_0|control[0]     DFFC      Q       module_state[3]                  0.243       -0.602
    bit_count[1]                     ao_top_0|control[0]     DFFCE     Q       bit_count[1]                     0.243       -0.541
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                              Starting                                                              Required
    Instance                  Reference               Type      Pin     Net                         Time         Slack
                              Clock
    -------------------------------------------------------------------------------------------------------------------
    data_out_shift_reg[1]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]     5.474        -0.977
    data_out_shift_reg[2]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]     5.474        -0.977
    data_out_shift_reg[3]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[3]     5.474        -0.977
    data_out_shift_reg[0]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]     5.474        -0.753
    address_counter[0]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    address_counter[1]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    address_counter[2]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    address_counter[3]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    address_counter[4]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    address_counter[5]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.474        -0.602
    ===================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.535
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.474

        - Propagation time:                      6.450
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.977

        Number of logic level(s):                6
        Starting point:                          internal_register_select[13] / Q
        Ending point:                            data_out_shift_reg[3] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    internal_register_select[13]                       DFFCE     Q        Out     0.243     0.243       -
    internal_register_select[13]                       Net       -        -       0.535     -           1
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      I1       In      -         0.778       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      F        Out     0.570     1.348       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              Net       -        -       0.535     -           7
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      I1       In      -         1.883       -
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      F        Out     0.570     2.453       -
    internal_reg_start_m_14                            Net       -        -       0.535     -           8
    addr_ct_en_sn.data_from_internal_reg77             LUT4      I2       In      -         2.988       -
    addr_ct_en_sn.data_from_internal_reg77             LUT4      F        Out     0.462     3.450       -
    data_from_internal_reg77                           Net       -        -       0.596     -           16
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      I1       In      -         4.046       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      F        Out     0.570     4.616       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      I1       In      -         5.017       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      F        Out     0.570     5.587       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      I2       In      -         5.988       -
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      F        Out     0.462     6.450       -
    data_out_shift_reg_4[3]                            Net       -        -       0.000     -           1
    data_out_shift_reg[3]                              DFFCE     D        In      -         6.450       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 6.511 is 3.508(53.9%) logic and 3.003(46.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.535
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.474

        - Propagation time:                      6.450
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.977

        Number of logic level(s):                6
        Starting point:                          internal_register_select[13] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    internal_register_select[13]                       DFFCE     Q        Out     0.243     0.243       -
    internal_register_select[13]                       Net       -        -       0.535     -           1
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      I1       In      -         0.778       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      F        Out     0.570     1.348       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              Net       -        -       0.535     -           7
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      I1       In      -         1.883       -
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      F        Out     0.570     2.453       -
    internal_reg_start_m_14                            Net       -        -       0.535     -           8
    addr_ct_en_sn.data_from_internal_reg78             LUT4      I2       In      -         2.988       -
    addr_ct_en_sn.data_from_internal_reg78             LUT4      F        Out     0.462     3.450       -
    data_from_internal_reg78                           Net       -        -       0.596     -           16
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[1]     LUT4      I1       In      -         4.046       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[1]     LUT4      F        Out     0.570     4.616       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[1]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[1]     LUT2      I1       In      -         5.017       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[1]     LUT2      F        Out     0.570     5.587       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[1]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_out_shift_reg_4[1]              LUT4      I2       In      -         5.988       -
    addr_ct_en_sn.data_out_shift_reg_4[1]              LUT4      F        Out     0.462     6.450       -
    data_out_shift_reg_4[1]                            Net       -        -       0.000     -           1
    data_out_shift_reg[1]                              DFFCE     D        In      -         6.450       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 6.511 is 3.508(53.9%) logic and 3.003(46.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.535
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.474

        - Propagation time:                      6.450
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.977

        Number of logic level(s):                6
        Starting point:                          internal_register_select[13] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    internal_register_select[13]                       DFFCE     Q        Out     0.243     0.243       -
    internal_register_select[13]                       Net       -        -       0.535     -           1
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      I1       In      -         0.778       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      F        Out     0.570     1.348       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              Net       -        -       0.535     -           7
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      I1       In      -         1.883       -
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      F        Out     0.570     2.453       -
    internal_reg_start_m_14                            Net       -        -       0.535     -           8
    addr_ct_en_sn.data_from_internal_reg78             LUT4      I2       In      -         2.988       -
    addr_ct_en_sn.data_from_internal_reg78             LUT4      F        Out     0.462     3.450       -
    data_from_internal_reg78                           Net       -        -       0.596     -           16
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[2]     LUT4      I1       In      -         4.046       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[2]     LUT4      F        Out     0.570     4.616       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_2[2]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[2]     LUT2      I1       In      -         5.017       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[2]     LUT2      F        Out     0.570     5.587       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_4[2]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_out_shift_reg_4[2]              LUT4      I2       In      -         5.988       -
    addr_ct_en_sn.data_out_shift_reg_4[2]              LUT4      F        Out     0.462     6.450       -
    data_out_shift_reg_4[2]                            Net       -        -       0.000     -           1
    data_out_shift_reg[2]                              DFFCE     D        In      -         6.450       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 6.511 is 3.508(53.9%) logic and 3.003(46.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.535
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.474

        - Propagation time:                      6.429
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.956

        Number of logic level(s):                6
        Starting point:                          internal_register_select[9] / Q
        Ending point:                            data_out_shift_reg[3] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    internal_register_select[9]                        DFFCE     Q        Out     0.243     0.243       -
    internal_register_select[9]                        Net       -        -       0.535     -           1
    addr_ct_en_sn.match_unit_rd_en_2_4[0]              LUT4      I1       In      -         0.778       -
    addr_ct_en_sn.match_unit_rd_en_2_4[0]              LUT4      F        Out     0.570     1.348       -
    addr_ct_en_sn.match_unit_rd_en_2_4[0]              Net       -        -       0.535     -           7
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      I0       In      -         1.883       -
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      F        Out     0.549     2.432       -
    internal_reg_start_m_14                            Net       -        -       0.535     -           8
    addr_ct_en_sn.data_from_internal_reg77             LUT4      I2       In      -         2.967       -
    addr_ct_en_sn.data_from_internal_reg77             LUT4      F        Out     0.462     3.429       -
    data_from_internal_reg77                           Net       -        -       0.596     -           16
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      I1       In      -         4.025       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      F        Out     0.570     4.595       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      I1       In      -         4.996       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      F        Out     0.570     5.566       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      I2       In      -         5.967       -
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      F        Out     0.462     6.429       -
    data_out_shift_reg_4[3]                            Net       -        -       0.000     -           1
    data_out_shift_reg[3]                              DFFCE     D        In      -         6.429       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 6.490 is 3.487(53.7%) logic and 3.003(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.535
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.474

        - Propagation time:                      6.429
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.956

        Number of logic level(s):                6
        Starting point:                          internal_register_select[12] / Q
        Ending point:                            data_out_shift_reg[3] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    internal_register_select[12]                       DFFCE     Q        Out     0.243     0.243       -
    internal_register_select[12]                       Net       -        -       0.535     -           1
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      I0       In      -         0.778       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              LUT4      F        Out     0.549     1.327       -
    addr_ct_en_sn.match_unit_rd_en_2_5[0]              Net       -        -       0.535     -           7
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      I1       In      -         1.862       -
    addr_ct_en_sn.match_unit_rd_en_2[0]                LUT2      F        Out     0.570     2.432       -
    internal_reg_start_m_14                            Net       -        -       0.535     -           8
    addr_ct_en_sn.data_from_internal_reg77             LUT4      I2       In      -         2.967       -
    addr_ct_en_sn.data_from_internal_reg77             LUT4      F        Out     0.462     3.429       -
    data_from_internal_reg77                           Net       -        -       0.596     -           16
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      I1       In      -         4.025       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     LUT4      F        Out     0.570     4.595       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_1[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      I1       In      -         4.996       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     LUT3      F        Out     0.570     5.566       -
    addr_ct_en_sn.data_from_internal_reg_0_iv_3[3]     Net       -        -       0.401     -           1
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      I2       In      -         5.967       -
    addr_ct_en_sn.data_out_shift_reg_4[3]              LUT4      F        Out     0.462     6.429       -
    data_out_shift_reg_4[3]                            Net       -        -       0.000     -           1
    data_out_shift_reg[3]                              DFFCE     D        In      -         6.429       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 6.490 is 3.487(53.7%) logic and 3.003(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                             Starting                                           Arrival
    Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                             Clock
    -------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.432
    address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       3.619
    =============================================================================================================

    Ending Points with Worst Slack
    ******************************

                                  Starting                                                        Required
    Instance                      Reference     Type      Pin     Net                             Time         Slack
                                  Clock
    ----------------------------------------------------------------------------------------------------------------
    capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.513        2.432
    capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.513        2.432
    capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.513        2.657
    capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.513        3.429
    internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.513        3.429
    address_counter[9]            System        DFFCE     D       address_counter_s[9]            5.474        3.619
    address_counter[8]            System        DFFCE     D       address_counter_s[8]            5.474        3.654
    address_counter[7]            System        DFFCE     D       address_counter_s[7]            5.474        3.689
    address_counter[6]            System        DFFCE     D       address_counter_s[6]            5.474        3.724
    address_counter[5]            System        DFFCE     D       address_counter_s[5]            5.474        3.759
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.574
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.513

        - Propagation time:                      2.081
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 2.432

        Number of logic level(s):                2
        Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
        Ending point:                            capture_window_sel[2] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                     Pin      Pin               Arrival     No. of
    Name                                      Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6      INV      O        Out     0.000     0.000       -
    capture_end                               Net      -        -       0.535     -           6
    un1_capture_window_sel_ac0_1              LUT4     I0       In      -         0.535       -
    un1_capture_window_sel_ac0_1              LUT4     F        Out     0.549     1.084       -
    un1_capture_window_sel_c2                 Net      -        -       0.535     -           2
    addr_ct_en_sn.capture_window_sel_3[2]     LUT3     I2       In      -         1.619       -
    addr_ct_en_sn.capture_window_sel_3[2]     LUT3     F        Out     0.462     2.081       -
    capture_window_sel_3[2]                   Net      -        -       0.000     -           1
    capture_window_sel[2]                     DFFC     D        In      -         2.081       -
    ====================================================================================================
    Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)

    Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)

    ---------------------------------------
    Resource Usage Report for ao_top_0

    Mapping to part: gw2a_18pbga256-8
    Cell usage:
    ALU             70 uses
    DFF             57 uses
    DFFC            45 uses
    DFFCE           277 uses
    DFFNP           2 uses
    DFFP            5 uses
    DFFPE           32 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       5 uses
    MUX2_LUT6       2 uses
    SDPX9           4 uses
    LUT2            62 uses
    LUT3            96 uses
    LUT4            285 uses

    I/O ports: 125
    I/O primitives: 70
    IBUF           68 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   418 of 15552 (2%)

    RAM/ROM usage summary
    Block Rams : 4 of 46 (8%)

    Total load per clock:
       ao_top_0|clk_i: 1
       ao_top_0|control[0]: 322

    @S |Mapping Summary:
    Total  LUTs: 443 (2%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 44MB peak: 219MB)

    Process took 0h:00m:07s realtime, 0h:00m:07s cputime
    # Thu Aug 29 14:22:25 2019

    ###########################################################]

`