rtl_dir:=		../../project/src/advanced_fir_filter
tb_dir:=		../../tb
tb_file:=		$(tb_dir)/tb_vcs.v								


vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog 				\
	-v /gwsw/gowin_simlib/gw2a/prim_sim.v 				\
	$(tb_file)							\
	$(rtl_dir)/advanced_fir_filter.vo					\
    -cm line+cond+fsm+branch+tgl

vd:
	verdi -sverilog						\
	-v /gwsw/gowin_simlib/gw2a/prim_sim.v 				\
	$(tb_file)							\
	$(rtl_dir)/advanced_fir_filter.vo					\
	-ssf fir_tb.fsdb						\
	&
reVd:
	./repair.sh tb
	verdi -ssr wave.ses &
#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf csrc simv.daidir simv.vdb verdiLog cm.log novas.conf novas.rc novas_dump.log simv fir_tb.fsdb ucli.key wave.ses.png 	./repair.sh tb