`timescale 1ns/1ps
module Reload_tb(
);
//**********************************************************************
// --- Parameter
//**********************************************************************
    localparam NUM_CYCLE = 32;
	localparam MEM_DEPTH = 1024;
    parameter NUM_MUL = 4;
	parameter NUM_CHN    =4;
    parameter TAP_SIZES  = 32;
    parameter DIN_WIDTH  =18;
    parameter COEFF_WIDTH=18;
    parameter DOUT_WIDTH =18;
//**********************************************************************
// --- In/OUT Signal Declaration
//**********************************************************************	
    reg clk=0;
    reg ce=0;
    reg rstn=0;
    wire outvalid;
    wire obstart;
    wire [DOUT_WIDTH-1:0] dout;    
    wire						inpvalid;
    wire                        ibstart;
	wire signed [17:0]	din;
	
	wire recycle;
	reg pstart;
	reg [9:0] addr;
    reg [9:0] cnt_cycle;
	wire input_ready;
	reg [9:0] cnt_coeff;
	wire signed [17:0]	coeffin;
	reg [1:0] coeffset;

//**********************************************************************
// --- In/OUT Signal Declaration
//**********************************************************************	
    always #5 clk=~clk;
    initial begin
        #10 rstn=1;
        #10 ce=1;
    end

//**********************************************************************
// --- Module: fir_singlerate
// --- Description:	
//		1.
//		2.
//**********************************************************************
    assign inpvalid = (pstart && cnt_cycle == 0) ? 1'b1 : 1'b0;
	assign ibstart = (pstart && addr%NUM_CHN == 1 && cnt_cycle == 0)? 1'b1 : 1'b0;
	assign recycle = (addr == 0 && cnt_cycle == NUM_CYCLE-2) ? 1'b1 : 1'b0;
	
	GSR GSR(.GSRI(1'b1));

	Advanced_FIR_Filter_Top Advanced_FIR_Filter_Top(
		.clk(clk), 
		.rstn(rstn & ~recycle),
		.ce(ce),
		
		.coeffwe((cnt_coeff < TAP_SIZES*NUM_CHN-1 && cnt_coeff > 0)?1'b1:1'b0),
		.coeffin(coeffin),
		.coeffset(coeffset),

		.inpvalid(inpvalid),
		.ibstart(ibstart),
		.din(din),
	
		.input_ready(input_ready),
		
		.outvalid(outvalid),
		.obstart(obstart),
		.dout(dout)
	);
    
  
//**********************************************************************
// --- Module:
// --- Description:	
//		1.
//		2.
//**********************************************************************

    Gowin_ROM_t ROM_data(
        .dout(din), //output [17:0] dout
        .clk(clk), //input clk
        .oce(ce), //input oce
        .ce(ce), //input ce
        .reset(~rstn), //input reset
        .wre(1'b0), //input wre
        .ad(addr) //input [9:0] ad
    );
	
	 Gowin_ROM_c ROM_coeff(
        .dout(coeffin), //output [17:0] dout
        .clk(clk), //input clk
        .oce(ce), //input oce
        .ce(ce), //input ce
        .reset(~rstn), //input reset
        .wre(1'b0), //input wre
        .ad(cnt_coeff) //input [9:0] ad
    );
    
    always @(posedge clk or negedge rstn) begin
        if(!rstn) cnt_cycle <= NUM_CYCLE-1;
        else if(ce) begin
			if(cnt_cycle == NUM_CYCLE-1 && input_ready) cnt_cycle <= 0;
            else if(cnt_cycle == NUM_CYCLE-1) cnt_cycle <= cnt_cycle;
            else cnt_cycle <= cnt_cycle + 1;
        end
    end

    always @(posedge clk or negedge rstn) begin
        if(!rstn) addr <= 0;
        else if(ce & pstart & input_ready) begin
			if(cnt_cycle == NUM_CYCLE-1 && addr == MEM_DEPTH-1) addr <= 0;
            else if(cnt_cycle == NUM_CYCLE-1) addr <= addr + 1;
        end
    end

	always @(posedge clk or negedge rstn) begin
        if(!rstn) pstart <= 0;
        else if(ce) begin
            if(cnt_cycle == NUM_CYCLE-1) pstart <= 1'b1;
        end
    end



	always @(posedge clk or negedge rstn) begin
		if(!rstn) cnt_coeff <= 0;
		else if(ce) begin
			if(recycle) cnt_coeff <= 0;
			else if(cnt_coeff == TAP_SIZES*NUM_CHN-1) cnt_coeff <= cnt_coeff;
			else cnt_coeff <= cnt_coeff + 1;
		end
	end
	
	always @(posedge clk or negedge rstn) begin
		if(!rstn) coeffset <= 0;
		else if(ce) begin
			if(cnt_coeff == TAP_SIZES*NUM_CHN-2) coeffset <= {coeffset[0], 1'b1};
			else coeffset <= 0;
		end
	end

	
//**********************************************************************
// --- 
//**********************************************************************	

endmodule