#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-HW-023 # Mon Aug 5 17:24:47 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\LED_blink_test\src\LED_test.v" (library work) @W:CG921 : LED_test.v(14) | led is already declared in this scope. Verilog syntax check successful! Options changed - recompiling Selecting top level module LED_test @N:CG364 : LED_test.v(2) | Synthesizing module LED_test in library work. Running optimization stage 1 on LED_test ....... Running optimization stage 2 on LED_test ....... @N:CL189 : LED_test.v(19) | Register bit clk_cnt[26] is always 0. @N:CL189 : LED_test.v(19) | Register bit clk_cnt[27] is always 0. @N:CL189 : LED_test.v(19) | Register bit clk_cnt[28] is always 0. @N:CL189 : LED_test.v(19) | Register bit clk_cnt[29] is always 0. @N:CL189 : LED_test.v(19) | Register bit clk_cnt[30] is always 0. @N:CL189 : LED_test.v(19) | Register bit clk_cnt[31] is always 0. @W:CL279 : LED_test.v(19) | Pruning register bits 31 to 26 of clk_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Aug 5 17:24:48 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level @N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Aug 5 17:24:48 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Aug 5 17:24:48 2019 ###########################################################]