# Fri Aug 10 17:33:56 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G-Beta7 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-017 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1117R, Built Jun 28 2018 10:23:07 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A:MF827 : | No constraint file specified. Linked File: IO_test_scck.rpt Printing clock summary report in "E:\LED_test\impl\synthesize\rev_1\IO_test_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. syn_allowed_resources : blockrams=46 set on top level netlist IO_test Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------- 0 - IO_test|clk 381.1 MHz 2.624 inferred Autoconstr_clkgroup_0 30 ================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------- IO_test|clk 30 clk(port) led_1[0].C - - ======================================================================================= @W:MT529 : io_test.v(19) | Found inferred clock IO_test|clk which controls 30 sequential elements including clk_cnt[25:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 30 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk Unconstrained_port 30 clk_cnt[25:0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N: : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\LED_test\impl\synthesize\rev_1\IO_test.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 190MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Aug 10 17:33:58 2018 ###########################################################]