#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-023

# Tue Aug  6 11:25:15 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\src\LED_test.v" (library work)
@W:CG921 : LED_test.v(14) | led is already declared in this scope.
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module LED_test
@N:CG364 : LED_test.v(2) | Synthesizing module LED_test in library work.
Running optimization stage 1 on LED_test .......
Running optimization stage 2 on LED_test .......
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[26] is always 0.
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[27] is always 0.
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[28] is always 0.
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[29] is always 0.
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[30] is always 0.
@N:CL189 : LED_test.v(19) | Register bit clk_cnt[31] is always 0.
@W:CL279 : LED_test.v(19) | Pruning register bits 31 to 26 of clk_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 11:25:16 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level
@N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 11:25:16 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 11:25:16 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
File D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\LED_blink_test\impl\synthesize\rev_1\synwork\LED_test_comp.srs changed - recompiling
@N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level
@N:NF107 : led_test.v(2) | Selected library: work cell: LED_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 11:25:18 2019

###########################################################]


Premap Report



# Tue Aug  6 11:25:18 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  LED_test_scck.rpt
Printing clock  summary report in "D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\impl\synthesize\rev_1\LED_test_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)



Clock Summary
******************

          Start            Requested     Requested     Clock        Clock                     Clock
Level     Clock            Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------------
0 -       LED_test|clk     330.5 MHz     3.026         inferred     Autoconstr_clkgroup_0     30   
===================================================================================================



Clock Load Summary
***********************

                 Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
Clock            Load      Pin           Seq Example     Seq Example       Comb Example 
----------------------------------------------------------------------------------------
LED_test|clk     30        clk(port)     led_1[0].C      -                 -            
========================================================================================

@W:MT529 : led_test.v(19) | Found inferred clock LED_test|clk which controls 30 sequential elements including clk_cnt[25:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 30 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 Unconstrained_port     30         clk_cnt[25:0]  
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\impl\synthesize\rev_1\LED_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug  6 11:25:20 2019

###########################################################]


Map & Optimize Report



# Tue Aug  6 11:25:20 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@W:BN132 : led_test.v(57) | Removing sequential instance led_1[3] because it is equivalent to instance led_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : led_test.v(48) | Removing sequential instance led_1[2] because it is equivalent to instance led_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : led_test.v(62) | Removing user instance led_24[3] because it is equivalent to instance led_17[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : led_test.v(53) | Removing user instance led_17[2] because it is equivalent to instance led_3[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : led_test.v(48) | Boundary register led_1[2] (in view: work.LED_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : led_test.v(57) | Boundary register led_1[3] (in view: work.LED_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@W:BN132 : led_test.v(39) | Removing sequential instance led_1[1] because it is equivalent to instance led_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : led_test.v(39) | Boundary register led_1[1] (in view: work.LED_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 191MB)

@N:MO231 : led_test.v(19) | Found counter in view:work.LED_test(verilog) instance clk_cnt[25:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.37ns		  42 /        27

   2		0h:00m:01s		    -1.49ns		  66 /        27
   3		0h:00m:01s		    -1.37ns		  67 /        27
   4		0h:00m:01s		    -1.49ns		  68 /        27
   5		0h:00m:01s		    -1.74ns		  69 /        27
   6		0h:00m:01s		    -1.74ns		  69 /        27


   7		0h:00m:01s		    -1.49ns		  75 /        27
   8		0h:00m:01s		    -1.68ns		  77 /        27
   9		0h:00m:01s		    -1.68ns		  77 /        27
  10		0h:00m:01s		    -1.37ns		  77 /        27
  11		0h:00m:01s		    -1.68ns		  77 /        27
  12		0h:00m:01s		    -1.68ns		  77 /        27
  13		0h:00m:01s		    -1.74ns		  77 /        27
  14		0h:00m:01s		    -1.43ns		  77 /        27

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 192MB)

Writing Analyst data base D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\impl\synthesize\rev_1\synwork\LED_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 192MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 192MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 192MB)

@W:MT420 :  | Found inferred clock LED_test|clk with period 6.88ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug  6 11:25:24 2019
#


Top view:               LED_test
Requested Frequency:    145.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.215

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
LED_test|clk       145.3 MHz     123.5 MHz     6.883         8.098         -1.215     inferred     Autoconstr_clkgroup_0
System             100.0 MHz     234.1 MHz     10.000        4.271         5.729      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------
System        LED_test|clk  |  6.883       5.729   |  No paths    -      |  No paths    -      |  No paths    -    
LED_test|clk  LED_test|clk  |  6.883       -1.215  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: LED_test|clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                          Arrival           
Instance        Reference        Type     Pin     Net             Time        Slack 
                Clock                                                               
------------------------------------------------------------------------------------
clk_cnt[9]      LED_test|clk     DFF      Q       clk_cnt[9]      0.367       -1.215
clk_cnt[3]      LED_test|clk     DFF      Q       clk_cnt[3]      0.367       -1.148
clk_cnt[8]      LED_test|clk     DFF      Q       clk_cnt[8]      0.367       -1.148
clk_cnt[2]      LED_test|clk     DFF      Q       clk_cnt[2]      0.367       -1.081
clk_cnt[18]     LED_test|clk     DFFR     Q       clk_cnt[18]     0.367       -1.059
clk_cnt[13]     LED_test|clk     DFFR     Q       clk_cnt[13]     0.367       -0.992
clk_cnt[17]     LED_test|clk     DFFR     Q       clk_cnt[17]     0.367       -0.992
clk_cnt[16]     LED_test|clk     DFFR     Q       clk_cnt[16]     0.367       -0.938
clk_cnt[12]     LED_test|clk     DFF      Q       clk_cnt[12]     0.367       -0.925
clk_cnt[4]      LED_test|clk     DFF      Q       clk_cnt[4]      0.367       -0.871
====================================================================================


Ending Points with Worst Slack
******************************

                Starting                                                     Required           
Instance        Reference        Type      Pin       Net                     Time         Slack 
                Clock                                                                           
------------------------------------------------------------------------------------------------
led_1[0]        LED_test|clk     DFFRE     D         led_1e_0[0]             6.750        -1.215
clk_cnt[6]      LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[13]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[14]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[15]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[16]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[17]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[18]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[19]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
clk_cnt[20]     LED_test|clk     DFFR      RESET     clk_cnt11_0_N_3_mux     6.750        -1.059
================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      7.965
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.215

    Number of logic level(s):                4
    Starting point:                          clk_cnt[9] / Q
    Ending point:                            led_1[0] / D
    The start point is clocked by            LED_test|clk [rising] on pin CLK
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                              Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
clk_cnt[9]                        DFF           Q        Out     0.367     0.367       -         
clk_cnt[9]                        Net           -        -       1.021     -           2         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     LUT4          I1       In      -         1.388       -         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     LUT4          F        Out     1.099     2.487       -         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     Net           -        -       1.021     -           1         
clk_cnt11_0tt_m2_0_a2_3           MUX2_LUT5     S0       In      -         3.508       -         
clk_cnt11_0tt_m2_0_a2_3           MUX2_LUT5     O        Out     0.472     3.980       -         
clk_cnt11_0tt_m2_0_a2_3           Net           -        -       1.021     -           8         
led_1e_N_3L3                      LUT2          I1       In      -         5.001       -         
led_1e_N_3L3                      LUT2          F        Out     1.099     6.100       -         
clk_cntd_1[5]                     Net           -        -       0.766     -           1         
led_1e[0]                         LUT3          I1       In      -         6.866       -         
led_1e[0]                         LUT3          F        Out     1.099     7.965       -         
led_1e_0[0]                       Net           -        -       0.000     -           1         
led_1[0]                          DFFRE         D        In      -         7.965       -         
=================================================================================================
Total path delay (propagation time + setup) of 8.098 is 4.269(52.7%) logic and 3.829(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      7.898
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.148

    Number of logic level(s):                4
    Starting point:                          clk_cnt[3] / Q
    Ending point:                            led_1[0] / D
    The start point is clocked by            LED_test|clk [rising] on pin CLK
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[3]             DFF           Q        Out     0.367     0.367       -         
clk_cnt[3]             Net           -        -       1.021     -           2         
un1_clk_cntlto6_4      LUT4          I1       In      -         1.388       -         
un1_clk_cntlto6_4      LUT4          F        Out     1.099     2.487       -         
un1_clk_cntlto6_4      Net           -        -       1.021     -           9         
clk_cnt11_0tt_m1_e     MUX2_LUT5     S0       In      -         3.508       -         
clk_cnt11_0tt_m1_e     MUX2_LUT5     O        Out     0.472     3.980       -         
clk_cnt11_0tt_m1_e     Net           -        -       1.021     -           6         
led_1e_N_3L3           LUT2          I0       In      -         5.001       -         
led_1e_N_3L3           LUT2          F        Out     1.032     6.033       -         
clk_cntd_1[5]          Net           -        -       0.766     -           1         
led_1e[0]              LUT3          I1       In      -         6.799       -         
led_1e[0]              LUT3          F        Out     1.099     7.898       -         
led_1e_0[0]            Net           -        -       0.000     -           1         
led_1[0]               DFFRE         D        In      -         7.898       -         
======================================================================================
Total path delay (propagation time + setup) of 8.031 is 4.202(52.3%) logic and 3.829(47.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      7.898
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.148

    Number of logic level(s):                4
    Starting point:                          clk_cnt[8] / Q
    Ending point:                            led_1[0] / D
    The start point is clocked by            LED_test|clk [rising] on pin CLK
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                              Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
clk_cnt[8]                        DFF           Q        Out     0.367     0.367       -         
clk_cnt[8]                        Net           -        -       1.021     -           2         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     LUT4          I0       In      -         1.388       -         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     LUT4          F        Out     1.032     2.420       -         
clk_cnt11_0tt_m2_0_a2_3_N_2L1     Net           -        -       1.021     -           1         
clk_cnt11_0tt_m2_0_a2_3           MUX2_LUT5     S0       In      -         3.441       -         
clk_cnt11_0tt_m2_0_a2_3           MUX2_LUT5     O        Out     0.472     3.913       -         
clk_cnt11_0tt_m2_0_a2_3           Net           -        -       1.021     -           8         
led_1e_N_3L3                      LUT2          I1       In      -         4.934       -         
led_1e_N_3L3                      LUT2          F        Out     1.099     6.033       -         
clk_cntd_1[5]                     Net           -        -       0.766     -           1         
led_1e[0]                         LUT3          I1       In      -         6.799       -         
led_1e[0]                         LUT3          F        Out     1.099     7.898       -         
led_1e_0[0]                       Net           -        -       0.000     -           1         
led_1[0]                          DFFRE         D        In      -         7.898       -         
=================================================================================================
Total path delay (propagation time + setup) of 8.031 is 4.202(52.3%) logic and 3.829(47.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      7.830
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.080

    Number of logic level(s):                4
    Starting point:                          clk_cnt[2] / Q
    Ending point:                            led_1[0] / D
    The start point is clocked by            LED_test|clk [rising] on pin CLK
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[2]             DFF           Q        Out     0.367     0.367       -         
clk_cnt[2]             Net           -        -       1.021     -           2         
un1_clk_cntlto6_4      LUT4          I0       In      -         1.388       -         
un1_clk_cntlto6_4      LUT4          F        Out     1.032     2.420       -         
un1_clk_cntlto6_4      Net           -        -       1.021     -           9         
clk_cnt11_0tt_m1_e     MUX2_LUT5     S0       In      -         3.441       -         
clk_cnt11_0tt_m1_e     MUX2_LUT5     O        Out     0.472     3.913       -         
clk_cnt11_0tt_m1_e     Net           -        -       1.021     -           6         
led_1e_N_3L3           LUT2          I0       In      -         4.934       -         
led_1e_N_3L3           LUT2          F        Out     1.032     5.966       -         
clk_cntd_1[5]          Net           -        -       0.766     -           1         
led_1e[0]              LUT3          I1       In      -         6.731       -         
led_1e[0]              LUT3          F        Out     1.099     7.830       -         
led_1e_0[0]            Net           -        -       0.000     -           1         
led_1[0]               DFFRE         D        In      -         7.830       -         
======================================================================================
Total path delay (propagation time + setup) of 7.963 is 4.135(51.9%) logic and 3.829(48.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      7.809
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.059

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            clk_cnt[6] / RESET
    The start point is clocked by            LED_test|clk [rising] on pin CLK
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net                    Pin       Pin               Arrival     No. of    
Name                     Type     Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
clk_cnt[18]              DFFR     Q         Out     0.367     0.367       -         
clk_cnt[18]              Net      -         -       1.021     -           5         
clk_cnt11_0_m1_e_1_1     LUT4     I1        In      -         1.388       -         
clk_cnt11_0_m1_e_1_1     LUT4     F         Out     1.099     2.487       -         
led_1e_N_2L1_1_0         Net      -         -       1.021     -           4         
clk_cnt11_0_m1_e_sx      LUT4     I1        In      -         3.508       -         
clk_cnt11_0_m1_e_sx      LUT4     F         Out     1.099     4.607       -         
clk_cnt11_0_m1_e_sx      Net      -         -       1.021     -           8         
clk_cnt11_0_m1_e         LUT4     I1        In      -         5.628       -         
clk_cnt11_0_m1_e         LUT4     F         Out     1.099     6.727       -         
clk_cnt11_0_N_3_mux      Net      -         -       1.082     -           14        
clk_cnt[6]               DFFR     RESET     In      -         7.809       -         
====================================================================================
Total path delay (propagation time + setup) of 7.942 is 3.797(47.8%) logic and 4.145(52.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

              Starting                                     Arrival          
Instance      Reference     Type     Pin     Net           Time        Slack
              Clock                                                         
----------------------------------------------------------------------------
rst_n_c_i     System        INV      O       rst_n_c_i     0.000       5.729
============================================================================


Ending Points with Worst Slack
******************************

             Starting                                        Required          
Instance     Reference     Type      Pin       Net           Time         Slack
             Clock                                                             
-------------------------------------------------------------------------------
led_1[0]     System        DFFRE     RESET     rst_n_c_i     6.750        5.729
===============================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.883
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.750

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.729

    Number of logic level(s):                0
    Starting point:                          rst_n_c_i / O
    Ending point:                            led_1[0] / RESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            LED_test|clk [rising] on pin CLK

Instance / Net               Pin       Pin               Arrival     No. of    
Name               Type      Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_n_c_i          INV       O         Out     0.000     0.000       -         
rst_n_c_i          Net       -         -       1.021     -           1         
led_1[0]           DFFRE     RESET     In      -         1.021       -         
===============================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

---------------------------------------
Resource Usage Report for LED_test 

Mapping to part: gw1n_9lqfp144-6
Cell usage:
ALU             26 uses
DFF             12 uses
DFFR            14 uses
DFFRE           1 use
GSR             1 use
INV             1 use
MUX2_LUT5       8 uses
MUX2_LUT6       3 uses
LUT2            3 uses
LUT3            2 uses
LUT4            41 uses

I/O ports: 6
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   27 of 6480 (0%)
Total load per clock:
   LED_test|clk: 27

@S |Mapping Summary:
Total  LUTs: 46 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 192MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Aug  6 11:25:24 2019

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