Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\impl\synthesize\rev_1\LED_test.vm |
Physical Constraints File | D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N9_LED_blink\src\LED_test.cst |
Timing Constraint File | --- |
GOWIN version | V1.9.1Beta |
Part Number | GW1N-LV9LQ144C6/I5 |
Created Time | Tue Aug 06 11:25:29 2019 |
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 76 |
Numbers of Endpoints Analyzed | 47 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 2 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 98.395(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | -0.326 | 2 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -0.163 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[10] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.563 |
2 | -0.163 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.563 |
3 | 0.310 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.090 |
4 | 0.310 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.090 |
5 | 0.799 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.601 |
6 | 0.799 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.601 |
7 | 1.252 | \clk_cnt_Z[2] /Q | \led_1[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.148 |
8 | 1.678 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[14] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.079 |
9 | 1.678 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[13] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.079 |
10 | 1.678 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[15] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.079 |
11 | 1.747 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.653 |
12 | 1.747 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.653 |
13 | 1.765 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.635 |
14 | 1.765 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[6] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.991 |
15 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[17] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
16 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[20] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
17 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[18] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
18 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[19] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
19 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[21] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
20 | 2.043 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[16] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.714 |
21 | 2.047 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[24] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.709 |
22 | 2.047 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[23] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.709 |
23 | 2.047 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[22] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.709 |
24 | 2.047 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[25] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.709 |
25 | 2.067 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.333 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.853 | \clk_cnt_Z[25] /Q | \clk_cnt_Z[25] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
2 | 0.853 | \clk_cnt_Z[17] /Q | \clk_cnt_Z[17] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
3 | 0.853 | \clk_cnt_Z[13] /Q | \clk_cnt_Z[13] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
4 | 0.854 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[23] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.854 |
5 | 0.854 | \clk_cnt_Z[19] /Q | \clk_cnt_Z[19] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.854 |
6 | 0.895 | \led_1[0] /Q | \led_1[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.895 |
7 | 1.088 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[18] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.088 |
8 | 1.088 | \clk_cnt_Z[6] /Q | \clk_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.088 |
9 | 1.089 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[20] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.089 |
10 | 1.091 | \clk_cnt_Z[24] /Q | \clk_cnt_Z[24] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.091 |
11 | 1.092 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[16] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.092 |
12 | 1.094 | \clk_cnt_Z[22] /Q | \clk_cnt_Z[22] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.094 |
13 | 1.099 | \clk_cnt_Z[14] /Q | \clk_cnt_Z[14] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.099 |
14 | 1.116 | \clk_cnt_Z[21] /Q | \clk_cnt_Z[21] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.116 |
15 | 1.116 | \clk_cnt_Z[15] /Q | \clk_cnt_Z[15] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.116 |
16 | 2.027 | \clk_cnt_Z[24] /Q | \clk_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.027 |
17 | 2.162 | \clk_cnt_Z[0] /Q | \clk_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.162 |
18 | 2.162 | \clk_cnt_Z[0] /Q | \clk_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.162 |
19 | 2.247 | \clk_cnt_Z[5] /Q | \clk_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.247 |
20 | 2.387 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.387 |
21 | 2.409 | \clk_cnt_Z[1] /Q | \clk_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.409 |
22 | 2.429 | \clk_cnt_Z[0] /Q | \clk_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.429 |
23 | 2.429 | \clk_cnt_Z[0] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.429 |
24 | 2.432 | \clk_cnt_Z[5] /Q | \clk_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.432 |
25 | 2.492 | \clk_cnt_Z[1] /Q | \clk_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.492 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[12] |
2 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[10] |
3 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[5] |
4 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[14] |
5 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[13] |
6 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[7] |
7 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[6] |
8 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \led_1[0] |
9 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[25] |
10 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[0] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -0.163 |
Data Arrival Time | 13.885 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.786 | 1.487 | tNET | FF | 1 | R16C22[0][A] | \clk_cntd[10] /I3 |
13.885 | 1.099 | tINS | FF | 1 | R16C22[0][A] | \clk_cntd[10] /F |
13.885 | 0.000 | tNET | FF | 1 | R16C22[0][A] | \clk_cnt_Z[10] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C22[0][A] | \clk_cnt_Z[10] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[10] | |||
13.722 | -0.400 | tSu | 1 | R16C22[0][A] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.860, 29.906%; route: 6.245, 65.301%; tC2Q: 0.458, 4.793% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path2
Path Summary:
Slack | -0.163 |
Data Arrival Time | 13.885 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.786 | 1.487 | tNET | FF | 1 | R16C22[0][B] | \clk_cntd[12] /I3 |
13.885 | 1.099 | tINS | FF | 1 | R16C22[0][B] | \clk_cntd[12] /F |
13.885 | 0.000 | tNET | FF | 1 | R16C22[0][B] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C22[0][B] | \clk_cnt_Z[12] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[12] | |||
13.722 | -0.400 | tSu | 1 | R16C22[0][B] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.860, 29.906%; route: 6.245, 65.301%; tC2Q: 0.458, 4.793% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path3
Path Summary:
Slack | 0.310 |
Data Arrival Time | 13.412 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.786 | 1.487 | tNET | FF | 1 | R16C22[1][B] | \clk_cntd[7] /I3 |
13.412 | 0.626 | tINS | FF | 1 | R16C22[1][B] | \clk_cntd[7] /F |
13.412 | 0.000 | tNET | FF | 1 | R16C22[1][B] | \clk_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C22[1][B] | \clk_cnt_Z[7] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[7] | |||
13.722 | -0.400 | tSu | 1 | R16C22[1][B] | \clk_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.387, 26.259%; route: 6.245, 68.699%; tC2Q: 0.458, 5.042% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path4
Path Summary:
Slack | 0.310 |
Data Arrival Time | 13.412 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.786 | 1.487 | tNET | FF | 1 | R16C22[1][A] | \clk_cntd[11] /I3 |
13.412 | 0.626 | tINS | FF | 1 | R16C22[1][A] | \clk_cntd[11] /F |
13.412 | 0.000 | tNET | FF | 1 | R16C22[1][A] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C22[1][A] | \clk_cnt_Z[11] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[11] | |||
13.722 | -0.400 | tSu | 1 | R16C22[1][A] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.387, 26.259%; route: 6.245, 68.699%; tC2Q: 0.458, 5.042% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path5
Path Summary:
Slack | 0.799 |
Data Arrival Time | 12.923 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.297 | 0.998 | tNET | FF | 1 | R16C21[0][A] | \clk_cntd[3] /I3 |
12.923 | 0.626 | tINS | FF | 1 | R16C21[0][A] | \clk_cntd[3] /F |
12.923 | 0.000 | tNET | FF | 1 | R16C21[0][A] | \clk_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C21[0][A] | \clk_cnt_Z[3] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[3] | |||
13.722 | -0.400 | tSu | 1 | R16C21[0][A] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.387, 27.752%; route: 5.756, 66.919%; tC2Q: 0.458, 5.329% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path6
Path Summary:
Slack | 0.799 |
Data Arrival Time | 12.923 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.657 | 0.437 | tINS | FF | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.797 | 2.140 | tNET | FF | 1 | R16C17[2][B] | \clk_cntd_1[3] /S0 |
11.299 | 0.502 | tINS | FF | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
12.297 | 0.998 | tNET | FF | 1 | R16C21[1][A] | \clk_cntd[8] /I3 |
12.923 | 0.626 | tINS | FF | 1 | R16C21[1][A] | \clk_cntd[8] /F |
12.923 | 0.000 | tNET | FF | 1 | R16C21[1][A] | \clk_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C21[1][A] | \clk_cnt_Z[8] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[8] | |||
13.722 | -0.400 | tSu | 1 | R16C21[1][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.387, 27.752%; route: 5.756, 66.919%; tC2Q: 0.458, 5.329% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path7
Path Summary:
Slack | 1.252 |
Data Arrival Time | 12.470 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[2] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C15[0][B] | \clk_cnt_Z[2] /CLK |
4.780 | 0.458 | tC2Q | RF | 2 | R16C15[0][B] | \clk_cnt_Z[2] /Q |
6.573 | 1.793 | tNET | FF | 1 | R16C21[0][B] | un1_clk_cntlto6_4_cZ/I0 |
7.672 | 1.099 | tINS | FF | 9 | R16C21[0][B] | un1_clk_cntlto6_4_cZ/F |
8.824 | 1.152 | tNET | FF | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/S0 |
9.261 | 0.437 | tINS | FF | 6 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/O |
9.795 | 0.534 | tNET | FF | 1 | R16C20[0][B] | led_1e_N_3L3/I0 |
10.617 | 0.822 | tINS | FF | 1 | R16C20[0][B] | led_1e_N_3L3/F |
11.438 | 0.821 | tNET | FF | 1 | R16C22[2][A] | \led_1e[0] /I1 |
12.470 | 1.032 | tINS | FF | 1 | R16C22[2][A] | \led_1e[0] /F |
12.470 | 0.000 | tNET | FF | 1 | R16C22[2][A] | \led_1[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C22[2][A] | \led_1[0] /CLK |
14.122 | -0.200 | tUnc | \led_1[0] | |||
13.722 | -0.400 | tSu | 1 | R16C22[2][A] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.390, 41.606%; route: 4.300, 52.769%; tC2Q: 0.458, 5.625% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path8
Path Summary:
Slack | 1.678 |
Data Arrival Time | 12.401 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.401 | 1.542 | tNET | RR | 1 | R16C25[2][A] | \clk_cnt_Z[14] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C25[2][A] | \clk_cnt_Z[14] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[14] | |||
14.079 | -0.043 | tSu | 1 | R16C25[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 39.512%; route: 4.428, 54.815%; tC2Q: 0.458, 5.673% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path9
Path Summary:
Slack | 1.678 |
Data Arrival Time | 12.401 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.401 | 1.542 | tNET | RR | 1 | R16C25[1][B] | \clk_cnt_Z[13] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C25[1][B] | \clk_cnt_Z[13] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[13] | |||
14.079 | -0.043 | tSu | 1 | R16C25[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 39.512%; route: 4.428, 54.815%; tC2Q: 0.458, 5.673% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path10
Path Summary:
Slack | 1.678 |
Data Arrival Time | 12.401 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.401 | 1.542 | tNET | RR | 1 | R16C25[2][B] | \clk_cnt_Z[15] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C25[2][B] | \clk_cnt_Z[15] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[15] | |||
14.079 | -0.043 | tSu | 1 | R16C25[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 39.512%; route: 4.428, 54.815%; tC2Q: 0.458, 5.673% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path11
Path Summary:
Slack | 1.747 |
Data Arrival Time | 11.975 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C22[0][B] | \clk_cnt_Z[12] /CLK |
4.780 | 0.458 | tC2Q | RF | 3 | R16C22[0][B] | \clk_cnt_Z[12] /Q |
5.592 | 0.812 | tNET | FF | 1 | R16C25[3][A] | clk_cntd_1_1_0_N_2L1_cZ/I0 |
6.691 | 1.099 | tINS | FF | 1 | R16C25[3][A] | clk_cntd_1_1_0_N_2L1_cZ/F |
7.512 | 0.821 | tNET | FF | 1 | R16C23[3][B] | \clk_cntd_1_1_0[0] /I3 |
8.544 | 1.032 | tINS | FF | 1 | R16C23[3][B] | \clk_cntd_1_1_0[0] /F |
8.550 | 0.005 | tNET | FF | 1 | R16C23[3][A] | \clk_cntd_1_cZ[0] /I0 |
9.582 | 1.032 | tINS | FF | 2 | R16C23[3][A] | \clk_cntd_1_cZ[0] /F |
10.876 | 1.295 | tNET | FF | 1 | R16C15[0][A] | \clk_cntd[0] /I3 |
11.975 | 1.099 | tINS | FF | 1 | R16C15[0][A] | \clk_cntd[0] /F |
11.975 | 0.000 | tNET | FF | 1 | R16C15[0][A] | \clk_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[0] | |||
13.722 | -0.400 | tSu | 1 | R16C15[0][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 4.262, 55.689%; route: 2.933, 38.323%; tC2Q: 0.458, 5.989% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path12
Path Summary:
Slack | 1.747 |
Data Arrival Time | 11.975 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C22[0][B] | \clk_cnt_Z[12] /CLK |
4.780 | 0.458 | tC2Q | RF | 3 | R16C22[0][B] | \clk_cnt_Z[12] /Q |
5.592 | 0.812 | tNET | FF | 1 | R16C25[3][A] | clk_cntd_1_1_0_N_2L1_cZ/I0 |
6.691 | 1.099 | tINS | FF | 1 | R16C25[3][A] | clk_cntd_1_1_0_N_2L1_cZ/F |
7.512 | 0.821 | tNET | FF | 1 | R16C23[3][B] | \clk_cntd_1_1_0[0] /I3 |
8.544 | 1.032 | tINS | FF | 1 | R16C23[3][B] | \clk_cntd_1_1_0[0] /F |
8.550 | 0.005 | tNET | FF | 1 | R16C23[3][A] | \clk_cntd_1_cZ[0] /I0 |
9.582 | 1.032 | tINS | FF | 2 | R16C23[3][A] | \clk_cntd_1_cZ[0] /F |
10.876 | 1.295 | tNET | FF | 1 | R16C15[0][B] | \clk_cntd[2] /I3 |
11.975 | 1.099 | tINS | FF | 1 | R16C15[0][B] | \clk_cntd[2] /F |
11.975 | 0.000 | tNET | FF | 1 | R16C15[0][B] | \clk_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C15[0][B] | \clk_cnt_Z[2] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[2] | |||
13.722 | -0.400 | tSu | 1 | R16C15[0][B] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 4.262, 55.689%; route: 2.933, 38.323%; tC2Q: 0.458, 5.989% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path13
Path Summary:
Slack | 1.765 |
Data Arrival Time | 11.957 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
4.780 | 0.458 | tC2Q | RF | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
6.092 | 1.312 | tNET | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.914 | 0.822 | tINS | FF | 1 | R16C21[3][B] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
8.220 | 1.305 | tNET | FF | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
8.692 | 0.472 | tINS | FR | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
9.842 | 1.150 | tNET | RR | 1 | R16C20[2][B] | clk_cntd_N_2L1_1/S0 |
10.344 | 0.502 | tINS | RF | 2 | R16C20[2][B] | clk_cntd_N_2L1_1/O |
10.858 | 0.515 | tNET | FF | 1 | R16C20[0][A] | \clk_cntd[1] /I3 |
11.957 | 1.099 | tINS | FF | 1 | R16C20[0][A] | \clk_cntd[1] /F |
11.957 | 0.000 | tNET | FF | 1 | R16C20[0][A] | \clk_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C20[0][A] | \clk_cnt_Z[1] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[1] | |||
13.722 | -0.400 | tSu | 1 | R16C20[0][A] | \clk_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 2.895, 37.915%; route: 4.282, 56.082%; tC2Q: 0.458, 6.003% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path14
Path Summary:
Slack | 1.765 |
Data Arrival Time | 12.313 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.313 | 1.454 | tNET | RR | 1 | R16C24[1][A] | \clk_cnt_Z[6] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C24[1][A] | \clk_cnt_Z[6] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[6] | |||
14.079 | -0.043 | tSu | 1 | R16C24[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 39.943%; route: 4.341, 54.322%; tC2Q: 0.458, 5.735% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path15
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[0][B] | \clk_cnt_Z[17] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[0][B] | \clk_cnt_Z[17] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[17] | |||
14.079 | -0.043 | tSu | 1 | R16C26[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path16
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[20] | |||
14.079 | -0.043 | tSu | 1 | R16C26[2][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path17
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[18] | |||
14.079 | -0.043 | tSu | 1 | R16C26[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path18
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[1][B] | \clk_cnt_Z[19] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[1][B] | \clk_cnt_Z[19] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[19] | |||
14.079 | -0.043 | tSu | 1 | R16C26[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path19
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[2][B] | \clk_cnt_Z[21] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[2][B] | \clk_cnt_Z[21] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[21] | |||
14.079 | -0.043 | tSu | 1 | R16C26[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path20
Path Summary:
Slack | 2.043 |
Data Arrival Time | 12.036 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.036 | 1.177 | tNET | RR | 1 | R16C26[0][A] | \clk_cnt_Z[16] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C26[0][A] | \clk_cnt_Z[16] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[16] | |||
14.079 | -0.043 | tSu | 1 | R16C26[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.379%; route: 4.064, 52.680%; tC2Q: 0.458, 5.942% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path21
Path Summary:
Slack | 2.047 |
Data Arrival Time | 12.031 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.031 | 1.172 | tNET | RR | 1 | R16C27[1][A] | \clk_cnt_Z[24] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C27[1][A] | \clk_cnt_Z[24] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[24] | |||
14.079 | -0.043 | tSu | 1 | R16C27[1][A] | \clk_cnt_Z[24] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.404%; route: 4.059, 52.651%; tC2Q: 0.458, 5.945% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path22
Path Summary:
Slack | 2.047 |
Data Arrival Time | 12.031 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.031 | 1.172 | tNET | RR | 1 | R16C27[0][B] | \clk_cnt_Z[23] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C27[0][B] | \clk_cnt_Z[23] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[23] | |||
14.079 | -0.043 | tSu | 1 | R16C27[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.404%; route: 4.059, 52.651%; tC2Q: 0.458, 5.945% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path23
Path Summary:
Slack | 2.047 |
Data Arrival Time | 12.031 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.031 | 1.172 | tNET | RR | 1 | R16C27[0][A] | \clk_cnt_Z[22] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C27[0][A] | \clk_cnt_Z[22] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[22] | |||
14.079 | -0.043 | tSu | 1 | R16C27[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.404%; route: 4.059, 52.651%; tC2Q: 0.458, 5.945% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path24
Path Summary:
Slack | 2.047 |
Data Arrival Time | 12.031 |
Data Required Time | 14.079 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
4.780 | 0.458 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
5.202 | 0.422 | tNET | RR | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/I1 |
6.301 | 1.099 | tINS | RF | 1 | R16C27[2][B] | clk_cnt11_a3_N_2L1_0/F |
6.306 | 0.005 | tNET | FF | 1 | R16C27[2][A] | clk_cnt11_a3/I0 |
7.338 | 1.032 | tINS | FF | 12 | R16C27[2][A] | clk_cnt11_a3/F |
9.798 | 2.460 | tNET | FF | 1 | R16C20[1][A] | clk_cnt11_0_m1_e/I0 |
10.859 | 1.061 | tINS | FR | 14 | R16C20[1][A] | clk_cnt11_0_m1_e/F |
12.031 | 1.172 | tNET | RR | 1 | R16C27[1][B] | \clk_cnt_Z[25] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C27[1][B] | \clk_cnt_Z[25] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[25] | |||
14.079 | -0.043 | tSu | 1 | R16C27[1][B] | \clk_cnt_Z[25] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.192, 41.404%; route: 4.059, 52.651%; tC2Q: 0.458, 5.945% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Path25
Path Summary:
Slack | 2.067 |
Data Arrival Time | 11.655 |
Data Required Time | 13.722 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
4.322 | 3.340 | tNET | RR | 1 | R16C15[0][B] | \clk_cnt_Z[2] /CLK |
4.780 | 0.458 | tC2Q | RF | 2 | R16C15[0][B] | \clk_cnt_Z[2] /Q |
6.573 | 1.793 | tNET | FF | 1 | R16C21[0][B] | un1_clk_cntlto6_4_cZ/I0 |
7.672 | 1.099 | tINS | FF | 9 | R16C21[0][B] | un1_clk_cntlto6_4_cZ/F |
8.824 | 1.152 | tNET | FF | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/S0 |
9.261 | 0.437 | tINS | FF | 6 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/O |
9.795 | 0.534 | tNET | FF | 1 | R16C16[2][B] | clk_cntd_N_2L1/I0 |
10.617 | 0.822 | tINS | FF | 1 | R16C16[2][B] | clk_cntd_N_2L1/F |
10.623 | 0.005 | tNET | FF | 1 | R16C16[1][A] | \clk_cntd[5] /I3 |
11.655 | 1.032 | tINS | FF | 1 | R16C16[1][A] | \clk_cntd[5] /F |
11.655 | 0.000 | tNET | FF | 1 | R16C16[1][A] | \clk_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
14.322 | 3.340 | tNET | RR | 1 | R16C16[1][A] | \clk_cnt_Z[5] /CLK |
14.122 | -0.200 | tUnc | \clk_cnt_Z[5] | |||
13.722 | -0.400 | tSu | 1 | R16C16[1][A] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Arrival Data Path Delay | cell: 3.390, 46.232%; route: 3.484, 47.517%; tC2Q: 0.458, 6.251% |
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.193 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[25] |
To | \clk_cnt_Z[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[1][B] | \clk_cnt_Z[25] /CLK |
3.674 | 0.333 | tC2Q | RR | 2 | R16C27[1][B] | \clk_cnt_Z[25] /Q |
3.676 | 0.002 | tNET | RR | 2 | R16C27[1][B] | \clk_cnt_s_0[25] /I0 |
4.193 | 0.517 | tINS | RF | 1 | R16C27[1][B] | \clk_cnt_s_0[25] /SUM |
4.193 | 0.000 | tNET | FF | 1 | R16C27[1][B] | \clk_cnt_Z[25] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[1][B] | \clk_cnt_Z[25] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[25] | |||
3.340 | 0.000 | tHld | 1 | R16C27[1][B] | \clk_cnt_Z[25] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path2
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.193 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[17] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[0][B] | \clk_cnt_Z[17] /CLK |
3.674 | 0.333 | tC2Q | RR | 2 | R16C26[0][B] | \clk_cnt_Z[17] /Q |
3.676 | 0.002 | tNET | RR | 2 | R16C26[0][B] | \clk_cnt_cry_0[17] /I0 |
4.193 | 0.517 | tINS | RF | 1 | R16C26[0][B] | \clk_cnt_cry_0[17] /SUM |
4.193 | 0.000 | tNET | FF | 1 | R16C26[0][B] | \clk_cnt_Z[17] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[0][B] | \clk_cnt_Z[17] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[17] | |||
3.340 | 0.000 | tHld | 1 | R16C26[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path3
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.193 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[13] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[1][B] | \clk_cnt_Z[13] /CLK |
3.674 | 0.333 | tC2Q | RR | 3 | R16C25[1][B] | \clk_cnt_Z[13] /Q |
3.676 | 0.002 | tNET | RR | 2 | R16C25[1][B] | \clk_cnt_cry_0[13] /I0 |
4.193 | 0.517 | tINS | RF | 1 | R16C25[1][B] | \clk_cnt_cry_0[13] /SUM |
4.193 | 0.000 | tNET | FF | 1 | R16C25[1][B] | \clk_cnt_Z[13] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[1][B] | \clk_cnt_Z[13] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[13] | |||
3.340 | 0.000 | tHld | 1 | R16C25[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path4
Path Summary:
Slack | 0.854 |
Data Arrival Time | 4.194 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[0][B] | \clk_cnt_Z[23] /CLK |
3.674 | 0.333 | tC2Q | RR | 6 | R16C27[0][B] | \clk_cnt_Z[23] /Q |
3.677 | 0.004 | tNET | RR | 2 | R16C27[0][B] | \clk_cnt_cry_0[23] /I0 |
4.194 | 0.517 | tINS | RF | 1 | R16C27[0][B] | \clk_cnt_cry_0[23] /SUM |
4.194 | 0.000 | tNET | FF | 1 | R16C27[0][B] | \clk_cnt_Z[23] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[0][B] | \clk_cnt_Z[23] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[23] | |||
3.340 | 0.000 | tHld | 1 | R16C27[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 60.548%; route: 0.004, 0.415%; tC2Q: 0.333, 39.038% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path5
Path Summary:
Slack | 0.854 |
Data Arrival Time | 4.194 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[19] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[1][B] | \clk_cnt_Z[19] /CLK |
3.674 | 0.333 | tC2Q | RR | 3 | R16C26[1][B] | \clk_cnt_Z[19] /Q |
3.677 | 0.004 | tNET | RR | 2 | R16C26[1][B] | \clk_cnt_cry_0[19] /I0 |
4.194 | 0.517 | tINS | RF | 1 | R16C26[1][B] | \clk_cnt_cry_0[19] /SUM |
4.194 | 0.000 | tNET | FF | 1 | R16C26[1][B] | \clk_cnt_Z[19] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[1][B] | \clk_cnt_Z[19] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[19] | |||
3.340 | 0.000 | tHld | 1 | R16C26[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 60.548%; route: 0.004, 0.415%; tC2Q: 0.333, 39.038% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path6
Path Summary:
Slack | 0.895 |
Data Arrival Time | 4.236 |
Data Required Time | 3.340 |
From | \led_1[0] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[2][A] | \led_1[0] /CLK |
3.674 | 0.333 | tC2Q | RR | 5 | R16C22[2][A] | \led_1[0] /Q |
3.680 | 0.006 | tNET | RR | 1 | R16C22[2][A] | \led_1e[0] /I2 |
4.236 | 0.556 | tINS | RR | 1 | R16C22[2][A] | \led_1e[0] /F |
4.236 | 0.000 | tNET | RR | 1 | R16C22[2][A] | \led_1[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[2][A] | \led_1[0] /CLK |
3.340 | 0.000 | tUnc | \led_1[0] | |||
3.340 | 0.000 | tHld | 1 | R16C22[2][A] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path7
Path Summary:
Slack | 1.088 |
Data Arrival Time | 4.428 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
3.674 | 0.333 | tC2Q | RR | 5 | R16C26[1][A] | \clk_cnt_Z[18] /Q |
3.911 | 0.238 | tNET | RR | 2 | R16C26[1][A] | \clk_cnt_cry_0[18] /I0 |
4.428 | 0.517 | tINS | RF | 1 | R16C26[1][A] | \clk_cnt_cry_0[18] /SUM |
4.428 | 0.000 | tNET | FF | 1 | R16C26[1][A] | \clk_cnt_Z[18] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[1][A] | \clk_cnt_Z[18] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[18] | |||
3.340 | 0.000 | tHld | 1 | R16C26[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path8
Path Summary:
Slack | 1.088 |
Data Arrival Time | 4.428 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[6] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C24[1][A] | \clk_cnt_Z[6] /CLK |
3.674 | 0.333 | tC2Q | RR | 2 | R16C24[1][A] | \clk_cnt_Z[6] /Q |
3.911 | 0.238 | tNET | RR | 2 | R16C24[1][A] | \clk_cnt_cry_0[6] /I0 |
4.428 | 0.517 | tINS | RF | 1 | R16C24[1][A] | \clk_cnt_cry_0[6] /SUM |
4.428 | 0.000 | tNET | FF | 1 | R16C24[1][A] | \clk_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C24[1][A] | \clk_cnt_Z[6] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[6] | |||
3.340 | 0.000 | tHld | 1 | R16C24[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path9
Path Summary:
Slack | 1.089 |
Data Arrival Time | 4.429 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
3.674 | 0.333 | tC2Q | RR | 4 | R16C26[2][A] | \clk_cnt_Z[20] /Q |
3.912 | 0.239 | tNET | RR | 2 | R16C26[2][A] | \clk_cnt_cry_0[20] /I0 |
4.429 | 0.517 | tINS | RF | 1 | R16C26[2][A] | \clk_cnt_cry_0[20] /SUM |
4.429 | 0.000 | tNET | FF | 1 | R16C26[2][A] | \clk_cnt_Z[20] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[2][A] | \clk_cnt_Z[20] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[20] | |||
3.340 | 0.000 | tHld | 1 | R16C26[2][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.471%; route: 0.239, 21.922%; tC2Q: 0.333, 30.607% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path10
Path Summary:
Slack | 1.091 |
Data Arrival Time | 4.432 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[24] |
To | \clk_cnt_Z[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[1][A] | \clk_cnt_Z[24] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C27[1][A] | \clk_cnt_Z[24] /Q |
3.915 | 0.241 | tNET | RR | 2 | R16C27[1][A] | \clk_cnt_cry_0[24] /I0 |
4.432 | 0.517 | tINS | RF | 1 | R16C27[1][A] | \clk_cnt_cry_0[24] /SUM |
4.432 | 0.000 | tNET | FF | 1 | R16C27[1][A] | \clk_cnt_Z[24] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[1][A] | \clk_cnt_Z[24] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[24] | |||
3.340 | 0.000 | tHld | 1 | R16C27[1][A] | \clk_cnt_Z[24] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.368%; route: 0.241, 22.091%; tC2Q: 0.333, 30.540% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path11
Path Summary:
Slack | 1.092 |
Data Arrival Time | 4.432 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[0][A] | \clk_cnt_Z[16] /CLK |
3.674 | 0.333 | tC2Q | RF | 4 | R16C26[0][A] | \clk_cnt_Z[16] /Q |
3.915 | 0.242 | tNET | FF | 2 | R16C26[0][A] | \clk_cnt_cry_0[16] /I0 |
4.432 | 0.517 | tINS | FF | 1 | R16C26[0][A] | \clk_cnt_cry_0[16] /SUM |
4.432 | 0.000 | tNET | FF | 1 | R16C26[0][A] | \clk_cnt_Z[16] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[0][A] | \clk_cnt_Z[16] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[16] | |||
3.340 | 0.000 | tHld | 1 | R16C26[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.351%; route: 0.242, 22.119%; tC2Q: 0.333, 30.530% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path12
Path Summary:
Slack | 1.094 |
Data Arrival Time | 4.434 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[22] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[0][A] | \clk_cnt_Z[22] /CLK |
3.674 | 0.333 | tC2Q | RR | 6 | R16C27[0][A] | \clk_cnt_Z[22] /Q |
3.917 | 0.244 | tNET | RR | 2 | R16C27[0][A] | \clk_cnt_cry_0[22] /I0 |
4.434 | 0.517 | tINS | RF | 1 | R16C27[0][A] | \clk_cnt_cry_0[22] /SUM |
4.434 | 0.000 | tNET | FF | 1 | R16C27[0][A] | \clk_cnt_Z[22] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[0][A] | \clk_cnt_Z[22] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[22] | |||
3.340 | 0.000 | tHld | 1 | R16C27[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.253%; route: 0.244, 22.281%; tC2Q: 0.333, 30.466% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path13
Path Summary:
Slack | 1.099 |
Data Arrival Time | 4.439 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[14] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[2][A] | \clk_cnt_Z[14] /CLK |
3.674 | 0.333 | tC2Q | RR | 3 | R16C25[2][A] | \clk_cnt_Z[14] /Q |
3.922 | 0.249 | tNET | RR | 2 | R16C25[2][A] | \clk_cnt_cry_0[14] /I0 |
4.439 | 0.517 | tINS | RF | 1 | R16C25[2][A] | \clk_cnt_cry_0[14] /SUM |
4.439 | 0.000 | tNET | FF | 1 | R16C25[2][A] | \clk_cnt_Z[14] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[2][A] | \clk_cnt_Z[14] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[14] | |||
3.340 | 0.000 | tHld | 1 | R16C25[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 47.036%; route: 0.249, 22.637%; tC2Q: 0.333, 30.326% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path14
Path Summary:
Slack | 1.116 |
Data Arrival Time | 4.457 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[21] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[2][B] | \clk_cnt_Z[21] /CLK |
3.674 | 0.333 | tC2Q | RR | 6 | R16C26[2][B] | \clk_cnt_Z[21] /Q |
3.940 | 0.266 | tNET | RR | 2 | R16C26[2][B] | \clk_cnt_cry_0[21] /I0 |
4.457 | 0.517 | tINS | RF | 1 | R16C26[2][B] | \clk_cnt_cry_0[21] /SUM |
4.457 | 0.000 | tNET | FF | 1 | R16C26[2][B] | \clk_cnt_Z[21] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C26[2][B] | \clk_cnt_Z[21] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[21] | |||
3.340 | 0.000 | tHld | 1 | R16C26[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 46.308%; route: 0.266, 23.836%; tC2Q: 0.333, 29.857% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path15
Path Summary:
Slack | 1.116 |
Data Arrival Time | 4.457 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[15] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[2][B] | \clk_cnt_Z[15] /CLK |
3.674 | 0.333 | tC2Q | RR | 3 | R16C25[2][B] | \clk_cnt_Z[15] /Q |
3.940 | 0.266 | tNET | RR | 2 | R16C25[2][B] | \clk_cnt_cry_0[15] /I0 |
4.457 | 0.517 | tINS | RF | 1 | R16C25[2][B] | \clk_cnt_cry_0[15] /SUM |
4.457 | 0.000 | tNET | FF | 1 | R16C25[2][B] | \clk_cnt_Z[15] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C25[2][B] | \clk_cnt_Z[15] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[15] | |||
3.340 | 0.000 | tHld | 1 | R16C25[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.517, 46.308%; route: 0.266, 23.836%; tC2Q: 0.333, 29.857% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path16
Path Summary:
Slack | 2.027 |
Data Arrival Time | 5.367 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[24] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C27[1][A] | \clk_cnt_Z[24] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C27[1][A] | \clk_cnt_Z[24] /Q |
4.233 | 0.559 | tNET | RR | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_0_cZ/I2 |
4.618 | 0.385 | tINS | RR | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_0_cZ/F |
4.618 | 0.000 | tNET | RR | 1 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/I0 |
4.716 | 0.098 | tINS | RR | 8 | R16C17[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
4.995 | 0.280 | tNET | RR | 1 | R16C15[0][A] | \clk_cntd[0] /I1 |
5.367 | 0.372 | tINS | RF | 1 | R16C15[0][A] | \clk_cntd[0] /F |
5.367 | 0.000 | tNET | FF | 1 | R16C15[0][A] | \clk_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[0] | |||
3.340 | 0.000 | tHld | 1 | R16C15[0][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.855, 42.180%; route: 0.839, 41.375%; tC2Q: 0.333, 16.445% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path17
Path Summary:
Slack | 2.162 |
Data Arrival Time | 5.502 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[0] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
3.674 | 0.333 | tC2Q | RR | 7 | R16C15[0][A] | \clk_cnt_Z[0] /Q |
4.182 | 0.509 | tNET | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /S0 |
4.519 | 0.337 | tINS | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /O |
4.519 | 0.000 | tNET | RR | 1 | R16C17[2][B] | \clk_cntd_1[3] /I0 |
4.585 | 0.066 | tINS | RR | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
5.130 | 0.545 | tNET | RR | 1 | R16C21[0][A] | \clk_cntd[3] /I3 |
5.502 | 0.372 | tINS | RF | 1 | R16C21[0][A] | \clk_cntd[3] /F |
5.502 | 0.000 | tNET | FF | 1 | R16C21[0][A] | \clk_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C21[0][A] | \clk_cnt_Z[3] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[3] | |||
3.340 | 0.000 | tHld | 1 | R16C21[0][A] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.775, 35.849%; route: 1.054, 48.733%; tC2Q: 0.333, 15.419% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path18
Path Summary:
Slack | 2.162 |
Data Arrival Time | 5.502 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[0] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
3.674 | 0.333 | tC2Q | RR | 7 | R16C15[0][A] | \clk_cnt_Z[0] /Q |
4.182 | 0.509 | tNET | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /S0 |
4.519 | 0.337 | tINS | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /O |
4.519 | 0.000 | tNET | RR | 1 | R16C17[2][B] | \clk_cntd_1[3] /I0 |
4.585 | 0.066 | tINS | RR | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
5.130 | 0.545 | tNET | RR | 1 | R16C21[1][A] | \clk_cntd[8] /I3 |
5.502 | 0.372 | tINS | RF | 1 | R16C21[1][A] | \clk_cntd[8] /F |
5.502 | 0.000 | tNET | FF | 1 | R16C21[1][A] | \clk_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C21[1][A] | \clk_cnt_Z[8] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[8] | |||
3.340 | 0.000 | tHld | 1 | R16C21[1][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.775, 35.849%; route: 1.054, 48.733%; tC2Q: 0.333, 15.419% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path19
Path Summary:
Slack | 2.247 |
Data Arrival Time | 5.587 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[5] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C16[1][A] | \clk_cnt_Z[5] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C16[1][A] | \clk_cnt_Z[5] /Q |
4.223 | 0.550 | tNET | RR | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_0_cZ/I1 |
4.595 | 0.372 | tINS | RF | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_0_cZ/F |
4.595 | 0.000 | tNET | FF | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_cZ/I0 |
4.684 | 0.089 | tINS | FF | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_cZ/O |
4.684 | 0.000 | tNET | FF | 1 | R16C20[2][B] | clk_cntd_N_2L1_1/I0 |
4.778 | 0.094 | tINS | FF | 2 | R16C20[2][B] | clk_cntd_N_2L1_1/O |
5.031 | 0.253 | tNET | FF | 1 | R16C21[1][B] | \clk_cntd[9] /I3 |
5.587 | 0.556 | tINS | FR | 1 | R16C21[1][B] | \clk_cntd[9] /F |
5.587 | 0.000 | tNET | RR | 1 | R16C21[1][B] | \clk_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C21[1][B] | \clk_cnt_Z[9] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[9] | |||
3.340 | 0.000 | tHld | 1 | R16C21[1][B] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 1.111, 49.446%; route: 0.803, 35.719%; tC2Q: 0.333, 14.835% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path20
Path Summary:
Slack | 2.387 |
Data Arrival Time | 5.728 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[0][B] | \clk_cnt_Z[12] /CLK |
3.674 | 0.333 | tC2Q | RR | 3 | R16C22[0][B] | \clk_cnt_Z[12] /Q |
4.251 | 0.578 | tNET | RR | 2 | R16C25[1][A] | \clk_cnt_cry_0[12] /I0 |
4.768 | 0.517 | tINS | RF | 1 | R16C25[1][A] | \clk_cnt_cry_0[12] /SUM |
5.356 | 0.587 | tNET | FF | 1 | R16C22[0][B] | \clk_cntd[12] /I2 |
5.728 | 0.372 | tINS | FF | 1 | R16C22[0][B] | \clk_cntd[12] /F |
5.728 | 0.000 | tNET | FF | 1 | R16C22[0][B] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[0][B] | \clk_cnt_Z[12] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[12] | |||
3.340 | 0.000 | tHld | 1 | R16C22[0][B] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.889, 37.238%; route: 1.165, 48.799%; tC2Q: 0.333, 13.963% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path21
Path Summary:
Slack | 2.409 |
Data Arrival Time | 5.750 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[1] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C20[0][A] | \clk_cnt_Z[1] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C20[0][A] | \clk_cnt_Z[1] /Q |
3.950 | 0.276 | tNET | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_0_cZ/I1 |
4.335 | 0.385 | tINS | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_0_cZ/F |
4.335 | 0.000 | tNET | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/I0 |
4.433 | 0.098 | tINS | RR | 6 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/O |
5.024 | 0.591 | tNET | RR | 1 | R16C15[0][B] | \clk_cntd[2] /I0 |
5.750 | 0.726 | tINS | RR | 1 | R16C15[0][B] | \clk_cntd[2] /F |
5.750 | 0.000 | tNET | RR | 1 | R16C15[0][B] | \clk_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][B] | \clk_cnt_Z[2] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[2] | |||
3.340 | 0.000 | tHld | 1 | R16C15[0][B] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 1.209, 50.177%; route: 0.867, 35.989%; tC2Q: 0.333, 13.834% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path22
Path Summary:
Slack | 2.429 |
Data Arrival Time | 5.770 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[0] |
To | \clk_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
3.674 | 0.333 | tC2Q | RR | 7 | R16C15[0][A] | \clk_cnt_Z[0] /Q |
4.182 | 0.509 | tNET | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /S0 |
4.519 | 0.337 | tINS | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /O |
4.519 | 0.000 | tNET | RR | 1 | R16C17[2][B] | \clk_cntd_1[3] /I0 |
4.585 | 0.066 | tINS | RR | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
5.398 | 0.812 | tNET | RR | 1 | R16C22[1][B] | \clk_cntd[7] /I3 |
5.770 | 0.372 | tINS | RF | 1 | R16C22[1][B] | \clk_cntd[7] /F |
5.770 | 0.000 | tNET | FF | 1 | R16C22[1][B] | \clk_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[1][B] | \clk_cnt_Z[7] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[7] | |||
3.340 | 0.000 | tHld | 1 | R16C22[1][B] | \clk_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.775, 31.901%; route: 1.321, 54.378%; tC2Q: 0.333, 13.721% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path23
Path Summary:
Slack | 2.429 |
Data Arrival Time | 5.770 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[0] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C15[0][A] | \clk_cnt_Z[0] /CLK |
3.674 | 0.333 | tC2Q | RR | 7 | R16C15[0][A] | \clk_cnt_Z[0] /Q |
4.182 | 0.509 | tNET | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /S0 |
4.519 | 0.337 | tINS | RR | 1 | R16C17[3][A] | \clk_cntd_1_0_cZ[3] /O |
4.519 | 0.000 | tNET | RR | 1 | R16C17[2][B] | \clk_cntd_1[3] /I0 |
4.585 | 0.066 | tINS | RR | 6 | R16C17[2][B] | \clk_cntd_1[3] /O |
5.398 | 0.812 | tNET | RR | 1 | R16C22[1][A] | \clk_cntd[11] /I3 |
5.770 | 0.372 | tINS | RF | 1 | R16C22[1][A] | \clk_cntd[11] /F |
5.770 | 0.000 | tNET | FF | 1 | R16C22[1][A] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C22[1][A] | \clk_cnt_Z[11] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[11] | |||
3.340 | 0.000 | tHld | 1 | R16C22[1][A] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 0.775, 31.901%; route: 1.321, 54.378%; tC2Q: 0.333, 13.721% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path24
Path Summary:
Slack | 2.432 |
Data Arrival Time | 5.772 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[5] |
To | \clk_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C16[1][A] | \clk_cnt_Z[5] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C16[1][A] | \clk_cnt_Z[5] /Q |
4.223 | 0.550 | tNET | RR | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_0_cZ/I1 |
4.608 | 0.385 | tINS | RR | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_0_cZ/F |
4.608 | 0.000 | tNET | RR | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_cZ/I0 |
4.706 | 0.098 | tINS | RR | 1 | R16C20[3][A] | clk_cntd_N_2L1_1_0_cZ/O |
4.706 | 0.000 | tNET | RR | 1 | R16C20[2][B] | clk_cntd_N_2L1_1/I0 |
4.772 | 0.066 | tINS | RR | 2 | R16C20[2][B] | clk_cntd_N_2L1_1/O |
5.048 | 0.276 | tNET | RR | 1 | R16C20[0][A] | \clk_cntd[1] /I3 |
5.772 | 0.724 | tINS | RR | 1 | R16C20[0][A] | \clk_cntd[1] /F |
5.772 | 0.000 | tNET | RR | 1 | R16C20[0][A] | \clk_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C20[0][A] | \clk_cnt_Z[1] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[1] | |||
3.340 | 0.000 | tHld | 1 | R16C20[0][A] | \clk_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 1.273, 52.343%; route: 0.826, 33.951%; tC2Q: 0.333, 13.706% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Path25
Path Summary:
Slack | 2.492 |
Data Arrival Time | 5.832 |
Data Required Time | 3.340 |
From | \clk_cnt_Z[1] |
To | \clk_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C20[0][A] | \clk_cnt_Z[1] /CLK |
3.674 | 0.333 | tC2Q | RR | 11 | R16C20[0][A] | \clk_cnt_Z[1] /Q |
3.950 | 0.276 | tNET | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_0_cZ/I1 |
4.335 | 0.385 | tINS | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_0_cZ/F |
4.335 | 0.000 | tNET | RR | 1 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/I0 |
4.433 | 0.098 | tINS | RR | 6 | R16C18[3][A] | clk_cnt11_0tt_m1_e_cZ/O |
4.718 | 0.286 | tNET | RR | 1 | R16C16[2][A] | clk_cntd_N_2L1_0/I0 |
5.274 | 0.556 | tINS | RR | 1 | R16C16[2][A] | clk_cntd_N_2L1_0/F |
5.276 | 0.002 | tNET | RR | 1 | R16C16[0][B] | \clk_cntd[4] /I3 |
5.832 | 0.556 | tINS | RR | 1 | R16C16[0][B] | \clk_cntd[4] /F |
5.832 | 0.000 | tNET | RR | 1 | R16C16[0][B] | \clk_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL6[B] | clk_ibuf/O |
3.340 | 2.496 | tNET | RR | 1 | R16C16[0][B] | \clk_cnt_Z[4] /CLK |
3.340 | 0.000 | tUnc | \clk_cnt_Z[4] | |||
3.340 | 0.000 | tHld | 1 | R16C16[0][B] | \clk_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Arrival Data Path Delay | cell: 1.595, 64.015%; route: 0.563, 22.607%; tC2Q: 0.333, 13.378% |
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[12] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[12] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[12] /CLK |
MPW2
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[10] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[10] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[10] /CLK |
MPW3
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[5] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[5] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[5] /CLK |
MPW4
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[14] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[14] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[14] /CLK |
MPW5
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[13] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[13] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[13] /CLK |
MPW6
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[7] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[7] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[7] /CLK |
MPW7
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[6] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[6] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[6] /CLK |
MPW8
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \led_1[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \led_1[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \led_1[0] /CLK |
MPW9
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[25] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[25] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[25] /CLK |
MPW10
MPW Summary:
Slack: | 2.475 |
Actual Width: | 3.725 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.615 | 3.631 | tNET | FF | \clk_cnt_Z[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.340 | 2.496 | tNET | RR | \clk_cnt_Z[0] /CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
27 | clk_c | -0.163 | 3.631 |
14 | clk_cnt11_0_N_3_mux | 1.678 | 1.684 |
12 | clk_cnt11_0_m1_e_1_0 | 1.678 | 3.093 |
11 | clk_cnt[1] | 3.555 | 1.300 |
11 | clk_cnt[5] | 3.775 | 1.290 |
11 | clk_cnt[7] | 2.915 | 1.636 |
11 | clk_cnt[24] | 1.773 | 1.491 |
9 | un1_clk_cntlto6_4 | 0.769 | 1.351 |
8 | clk_cnt11_0tt_m2_0_a2_3 | -0.163 | 2.140 |
8 | clk_cnt11_0_m1_e_sx | 2.817 | 0.437 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R16C21 | 0.403 |
R16C23 | 0.347 |
R16C22 | 0.292 |
R16C20 | 0.278 |
R16C26 | 0.264 |
R16C25 | 0.250 |
R16C24 | 0.236 |
R16C18 | 0.167 |
R16C27 | 0.167 |
R16C17 | 0.153 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|