#Build: Synplify Pro (R) N-2018.03G, Build 224R, Jul 26 2018 #install: E:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-HW-026 # Fri Nov 9 13:45:58 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G Install: E:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-026 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q1p1, Build 224R, Built Jul 26 2018 09:18:13 @N: : | Running in 64-bit mode Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G Install: E:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-026 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q1p1, Build 224R, Built Jul 26 2018 09:18:13 @N: : | Running in 64-bit mode @N: : | : Running Verilog Compiler in System Verilog mode @N: : | : Running Verilog Compiler in Multiple File Compilation Unit mode @I::"E:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"E:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"E:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"E:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"E:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"F:\code\LED_blink_test\src\IO_test.v" (library work) @W:CG921 : IO_test.v(14) | led is already declared in this scope. Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module IO_test @N:CG364 : IO_test.v(2) | Synthesizing module IO_test in library work. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[26] is always 0. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[27] is always 0. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[28] is always 0. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[29] is always 0. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[30] is always 0. @N:CL189 : IO_test.v(19) | Register bit clk_cnt[31] is always 0. @W:CL279 : IO_test.v(19) | Pruning register bits 31 to 26 of clk_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Nov 9 13:45:58 2018 ###########################################################] Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G Install: E:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-026 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 224R, Built Jul 26 2018 09:18:13 @N: : | Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Nov 9 13:45:58 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Nov 9 13:45:58 2018 ###########################################################]