Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\impl\synthesize\rev_1\IO_test.vm
Physical Constraints File E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\src\LED_test.cst
Timing Constraint File ---
GOWIN version V1.9.1Beta
Part Number GW1N-LV9LQ144C6/I5
Created Time Tue Aug 06 14:24:18 2019
Legal Announcement Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C
Hold Delay Model Fast 1.26V 0C
Numbers of Paths Analyzed 99
Numbers of Endpoints Analyzed 87
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
DEFAULT_CLK Base 10.000 100.000 0.000 5.000

Max Frequency Summary:

NO. Clock Name Fmax Entity
1 DEFAULT_CLK 140.191(MHz) TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
DEFAULT_CLK Setup 0.000 0
DEFAULT_CLK Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.867 \delay_1s_cnt[0] /Q \pwm_on[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.533
2 3.114 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[0] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.643
3 3.114 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[5] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.643
4 3.114 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[6] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.643
5 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[1] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
6 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[8] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
7 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[7] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
8 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[2] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
9 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[3] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
10 3.393 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[4] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.363
11 3.402 \delay_1ms_cnt_Z[5] /Q \delay_1s_cnt[9] /CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.354
12 3.445 \delay_1ms_cnt_Z[9] /Q display_mode_Z/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 6.311
13 3.896 \delay_1s_cnt[4] /Q \delay_1s_cnt[6] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.504
14 3.957 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[2] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.443
15 3.957 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[4] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.443
16 3.961 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[9] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.439
17 4.079 \delay_1ms_cnt_Z[5] /Q \delay_1ms_cnt_Z[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.321
18 4.119 \delay_1ms_cnt_Z[5] /Q \delay_1ms_cnt_Z[8] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.281
19 4.234 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[7] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.166
20 4.316 \delay_1s_cnt[4] /Q \delay_1s_cnt[9] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.084
21 4.324 \delay_1s_cnt[4] /Q \delay_1s_cnt[7] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.076
22 4.363 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[5] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.037
23 4.363 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[6] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 5.037
24 4.425 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[1] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 4.975
25 4.425 \delay_1ms_cnt_Z[8] /Q \delay_1ms_cnt_Z[3] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 4.975

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 display_mode_Z/Q display_mode_Z/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.708
2 0.709 \delay_1us_cnt_Z[5] /Q \delay_1us_cnt_Z[5] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.709
3 0.709 \delay_1us_cnt_Z[6] /Q \delay_1us_cnt_Z[6] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.709
4 0.710 \delay_1us_cnt_Z[4] /Q \delay_1us_cnt_Z[4] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.710
5 0.710 \delay_1us_cnt_Z[0] /Q \delay_1us_cnt_Z[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.710
6 0.711 \delay_1us_cnt_Z[3] /Q \delay_1us_cnt_Z[3] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.711
7 0.898 \delay_1ms_cnt_Z[4] /Q \delay_1ms_cnt_Z[4] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.898
8 0.953 \delay_1us_cnt_Z[4] /Q \delay_1us_cnt_fast_Z[5] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.953
9 0.956 \delay_1s_cnt[8] /Q \delay_1s_cnt[2] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.956
10 0.967 \delay_1s_cnt[8] /Q \delay_1s_cnt[1] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.967
11 0.967 \delay_1s_cnt[8] /Q \delay_1s_cnt[7] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.967
12 0.975 \delay_1us_cnt_Z[3] /Q \delay_1us_cnt_fast_Z[4] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.975
13 1.061 \delay_1us_cnt_Z[2] /Q \delay_1us_cnt_Z[2] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.061
14 1.061 \delay_1us_cnt_Z[1] /Q \delay_1us_cnt_Z[1] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.061
15 1.066 \delay_1s_cnt[8] /Q \delay_1s_cnt[8] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.066
16 1.151 \delay_1s_cnt[8] /Q \delay_1s_cnt[3] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.151
17 1.151 \delay_1s_cnt[8] /Q \delay_1s_cnt[4] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.151
18 1.283 \delay_1s_cnt[8] /Q \delay_1s_cnt[9] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.283
19 1.295 display_mode_Z/Q \pwm_on[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.295
20 1.310 \delay_1ms_cnt_Z[4] /Q \delay_1ms_cnt_Z[2] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.310
21 1.317 \delay_1ms_cnt_Z[4] /Q \delay_1ms_cnt_Z[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.317
22 1.317 \delay_1ms_cnt_Z[4] /Q \delay_1ms_cnt_Z[1] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.317
23 1.329 \delay_1ms_cnt_Z[4] /Q \delay_1ms_cnt_Z[3] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.329
24 1.331 \delay_1s_cnt[8] /Q \delay_1s_cnt[0] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.331
25 1.331 \delay_1s_cnt[8] /Q \delay_1s_cnt[5] /D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.331

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1us_cnt_fast_Z[5]
2 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1s_cnt[9]
3 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1s_cnt[5]
4 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1ms_cnt_Z[7]
5 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK display_mode_Z
6 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1us_cnt_Z[2]
7 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1ms_cnt_Z[8]
8 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1us_cnt_Z[3]
9 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1us_cnt_Z[4]
10 2.561 3.811 1.250 Low Pulse Width DEFAULT_CLK \delay_1s_cnt[6]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.867
Data Arrival Time 10.938
Data Required Time 13.805
From \delay_1s_cnt[0]
To \pwm_on[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R15C20[2][A] \delay_1s_cnt[0] /CLK
4.863 0.458 tC2Q RF 3 R15C20[2][A] \delay_1s_cnt[0] /Q
7.139 2.276 tNET FF 2 R15C32[1][A] un2_pwm_on_cry_0_0/I0
8.097 0.958 tINS FF 1 R15C32[1][A] un2_pwm_on_cry_0_0/COUT
8.097 0.000 tNET FF 2 R15C32[1][B] un2_pwm_on_cry_1_0/CIN
8.154 0.057 tINS FF 1 R15C32[1][B] un2_pwm_on_cry_1_0/COUT
8.154 0.000 tNET FF 2 R15C32[2][A] un2_pwm_on_cry_2_0/CIN
8.211 0.057 tINS FF 1 R15C32[2][A] un2_pwm_on_cry_2_0/COUT
8.211 0.000 tNET FF 2 R15C32[2][B] un2_pwm_on_cry_3_0/CIN
8.268 0.057 tINS FF 1 R15C32[2][B] un2_pwm_on_cry_3_0/COUT
8.268 0.000 tNET FF 2 R15C33[0][A] un2_pwm_on_cry_4_0/CIN
8.325 0.057 tINS FF 1 R15C33[0][A] un2_pwm_on_cry_4_0/COUT
8.325 0.000 tNET FF 2 R15C33[0][B] un2_pwm_on_cry_5_0/CIN
8.382 0.057 tINS FF 1 R15C33[0][B] un2_pwm_on_cry_5_0/COUT
8.382 0.000 tNET FF 2 R15C33[1][A] un2_pwm_on_cry_6_0/CIN
8.439 0.057 tINS FF 1 R15C33[1][A] un2_pwm_on_cry_6_0/COUT
8.439 0.000 tNET FF 2 R15C33[1][B] un2_pwm_on_cry_7_0/CIN
8.496 0.057 tINS FF 1 R15C33[1][B] un2_pwm_on_cry_7_0/COUT
8.496 0.000 tNET FF 2 R15C33[2][A] un2_pwm_on_cry_8_0/CIN
8.553 0.057 tINS FF 1 R15C33[2][A] un2_pwm_on_cry_8_0/COUT
8.553 0.000 tNET FF 2 R15C33[2][B] un2_pwm_on_cry_9_0/CIN
8.610 0.057 tINS FF 1 R15C33[2][B] un2_pwm_on_cry_9_0/COUT
10.312 1.702 tNET FF 1 R15C24[1][B] N_26_i_cZ/I1
10.938 0.626 tINS FF 1 R15C24[1][B] N_26_i_cZ/F
10.938 0.000 tNET FF 1 R15C24[1][B] \pwm_on[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C24[1][B] \pwm_on[0] /CLK
14.205 -0.200 tUnc \pwm_on[0]
13.805 -0.400 tSu 1 R15C24[1][B] \pwm_on[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.097, 32.098%; route: 3.978, 60.886%; tC2Q: 0.458, 7.016%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path2

Path Summary:

Slack 3.114
Data Arrival Time 11.047
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
11.047 1.460 tNET RR 1 R15C20[2][A] \delay_1s_cnt[0] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C20[2][A] \delay_1s_cnt[0] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[0]
14.162 -0.043 tSu 1 R15C20[2][A] \delay_1s_cnt[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 24.448%; route: 4.560, 68.652%; tC2Q: 0.458, 6.900%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path3

Path Summary:

Slack 3.114
Data Arrival Time 11.047
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
11.047 1.460 tNET RR 1 R15C20[0][A] \delay_1s_cnt[5] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C20[0][A] \delay_1s_cnt[5] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[5]
14.162 -0.043 tSu 1 R15C20[0][A] \delay_1s_cnt[5]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 24.448%; route: 4.560, 68.652%; tC2Q: 0.458, 6.900%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path4

Path Summary:

Slack 3.114
Data Arrival Time 11.047
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
11.047 1.460 tNET RR 1 R15C20[0][B] \delay_1s_cnt[6] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C20[0][B] \delay_1s_cnt[6] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[6]
14.162 -0.043 tSu 1 R15C20[0][B] \delay_1s_cnt[6]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 24.448%; route: 4.560, 68.652%; tC2Q: 0.458, 6.900%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path5

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[1][A] \delay_1s_cnt[1] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[1][A] \delay_1s_cnt[1] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[1]
14.162 -0.043 tSu 1 R15C21[1][A] \delay_1s_cnt[1]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path6

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[8]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[8]
14.162 -0.043 tSu 1 R15C21[0][B] \delay_1s_cnt[8]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path7

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[0][A] \delay_1s_cnt[7] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[0][A] \delay_1s_cnt[7] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[7]
14.162 -0.043 tSu 1 R15C21[0][A] \delay_1s_cnt[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path8

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[1][B] \delay_1s_cnt[2] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[1][B] \delay_1s_cnt[2] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[2]
14.162 -0.043 tSu 1 R15C21[1][B] \delay_1s_cnt[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path9

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[2][A] \delay_1s_cnt[3] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[2][A] \delay_1s_cnt[3] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[3]
14.162 -0.043 tSu 1 R15C21[2][A] \delay_1s_cnt[3]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path10

Path Summary:

Slack 3.393
Data Arrival Time 10.768
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.768 1.181 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[4]
14.162 -0.043 tSu 1 R15C21[2][B] \delay_1s_cnt[4]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.521%; route: 4.281, 67.276%; tC2Q: 0.458, 7.203%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path11

Path Summary:

Slack 3.402
Data Arrival Time 10.759
Data Required Time 14.162
From \delay_1ms_cnt_Z[5]
To \delay_1s_cnt[9]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
6.658 1.795 tNET FF 1 R15C20[2][B] m8_N_4L5_cZ/I0
7.480 0.822 tINS FF 1 R15C20[2][B] m8_N_4L5_cZ/F
8.786 1.305 tNET FF 1 R15C24[3][B] m8/I3
9.588 0.802 tINS FR 10 R15C24[3][B] m8/F
10.759 1.171 tNET RR 1 R14C23[0][A] \delay_1s_cnt[9] /CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C23[0][A] \delay_1s_cnt[9] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[9]
14.162 -0.043 tSu 1 R14C23[0][A] \delay_1s_cnt[9]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 1.624, 25.558%; route: 4.272, 67.229%; tC2Q: 0.458, 7.213%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path12

Path Summary:

Slack 3.445
Data Arrival Time 10.716
Data Required Time 14.162
From \delay_1ms_cnt_Z[9]
To display_mode_Z
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C31[0][A] \delay_1ms_cnt_Z[9] /CLK
4.863 0.458 tC2Q RF 6 R14C31[0][A] \delay_1ms_cnt_Z[9] /Q
6.163 1.300 tNET FF 1 R15C28[0][A] G_7_N_2L1_0/I2
7.262 1.099 tINS FF 1 R15C28[0][A] G_7_N_2L1_0/F
7.268 0.005 tNET FF 1 R15C28[1][A] m17_sx_cZ/I3
7.894 0.626 tINS FF 1 R15C28[1][A] m17_sx_cZ/F
9.199 1.305 tNET FF 1 R15C24[3][A] m17/I3
10.001 0.802 tINS FR 1 R15C24[3][A] m17/F
10.716 0.715 tNET RR 1 R15C24[0][A] display_mode_Z/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C24[0][A] display_mode_Z/CLK
14.205 -0.200 tUnc display_mode_Z
14.162 -0.043 tSu 1 R15C24[0][A] display_mode_Z

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.527, 40.039%; route: 3.326, 52.699%; tC2Q: 0.458, 7.262%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path13

Path Summary:

Slack 3.896
Data Arrival Time 9.909
Data Required Time 13.805
From \delay_1s_cnt[4]
To \delay_1s_cnt[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CLK
4.863 0.458 tC2Q RF 4 R15C21[2][B] \delay_1s_cnt[4] /Q
6.170 1.307 tNET FF 2 R15C23[0][A] \delay_1s_cnt_cry_0[4] /I0
7.215 1.045 tINS FF 1 R15C23[0][A] \delay_1s_cnt_cry_0[4] /COUT
7.215 0.000 tNET FF 2 R15C23[0][B] \delay_1s_cnt_cry_0[5] /CIN
7.272 0.057 tINS FF 1 R15C23[0][B] \delay_1s_cnt_cry_0[5] /COUT
7.272 0.000 tNET FF 2 R15C23[1][A] \delay_1s_cnt_cry_0[6] /CIN
7.835 0.563 tINS FF 1 R15C23[1][A] \delay_1s_cnt_cry_0[6] /SUM
8.810 0.975 tNET FF 1 R15C20[0][B] \delay_1s_cnt_lm_0[6] /I1
9.909 1.099 tINS FF 1 R15C20[0][B] \delay_1s_cnt_lm_0[6] /F
9.909 0.000 tNET FF 1 R15C20[0][B] \delay_1s_cnt[6] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C20[0][B] \delay_1s_cnt[6] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[6]
13.805 -0.400 tSu 1 R15C20[0][B] \delay_1s_cnt[6]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.764, 50.218%; route: 2.282, 41.454%; tC2Q: 0.458, 8.327%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path14

Path Summary:

Slack 3.957
Data Arrival Time 9.848
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.749 0.831 tNET FF 1 R15C29[1][A] \delay_1ms_cnt_lm_0[2] /I1
9.848 1.099 tINS FF 1 R15C29[1][A] \delay_1ms_cnt_lm_0[2] /F
9.848 0.000 tNET FF 1 R15C29[1][A] \delay_1ms_cnt_Z[2] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C29[1][A] \delay_1ms_cnt_Z[2] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[2]
13.805 -0.400 tSu 1 R15C29[1][A] \delay_1ms_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.163, 58.110%; route: 1.822, 33.470%; tC2Q: 0.458, 8.420%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path15

Path Summary:

Slack 3.957
Data Arrival Time 9.848
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.749 0.831 tNET FF 1 R15C29[2][A] \delay_1ms_cnt_lm_0[4] /I1
9.848 1.099 tINS FF 1 R15C29[2][A] \delay_1ms_cnt_lm_0[4] /F
9.848 0.000 tNET FF 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[4]
13.805 -0.400 tSu 1 R15C29[2][A] \delay_1ms_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.163, 58.110%; route: 1.822, 33.470%; tC2Q: 0.458, 8.420%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path16

Path Summary:

Slack 3.961
Data Arrival Time 9.844
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[9]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.745 0.826 tNET FF 1 R14C31[0][A] \delay_1ms_cnt_lm_0[9] /I1
9.844 1.099 tINS FF 1 R14C31[0][A] \delay_1ms_cnt_lm_0[9] /F
9.844 0.000 tNET FF 1 R14C31[0][A] \delay_1ms_cnt_Z[9] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C31[0][A] \delay_1ms_cnt_Z[9] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[9]
13.805 -0.400 tSu 1 R14C31[0][A] \delay_1ms_cnt_Z[9]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.163, 58.158%; route: 1.817, 33.414%; tC2Q: 0.458, 8.427%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path17

Path Summary:

Slack 4.079
Data Arrival Time 9.726
Data Required Time 13.805
From \delay_1ms_cnt_Z[5]
To \delay_1ms_cnt_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
5.697 0.834 tNET FF 1 R15C31[3][B] G_7_sx_cZ/I1
6.729 1.032 tINS FF 1 R15C31[3][B] G_7_sx_cZ/F
6.735 0.005 tNET FF 1 R15C31[3][A] G_7/I0
7.767 1.032 tINS FF 10 R15C31[3][A] G_7/F
8.627 0.861 tNET FF 1 R15C29[0][A] \delay_1ms_cnt_lm_0[0] /I0
9.726 1.099 tINS FF 1 R15C29[0][A] \delay_1ms_cnt_lm_0[0] /F
9.726 0.000 tNET FF 1 R15C29[0][A] \delay_1ms_cnt_Z[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C29[0][A] \delay_1ms_cnt_Z[0] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[0]
13.805 -0.400 tSu 1 R15C29[0][A] \delay_1ms_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.163, 59.439%; route: 1.700, 31.947%; tC2Q: 0.458, 8.613%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path18

Path Summary:

Slack 4.119
Data Arrival Time 9.686
Data Required Time 13.805
From \delay_1ms_cnt_Z[5]
To \delay_1ms_cnt_Z[8]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
4.863 0.458 tC2Q RF 6 R14C32[0][A] \delay_1ms_cnt_Z[5] /Q
5.697 0.834 tNET FF 1 R15C31[3][B] G_7_sx_cZ/I1
6.729 1.032 tINS FF 1 R15C31[3][B] G_7_sx_cZ/F
6.735 0.005 tNET FF 1 R15C31[3][A] G_7/I0
7.767 1.032 tINS FF 10 R15C31[3][A] G_7/F
8.587 0.821 tNET FF 1 R14C30[0][B] \delay_1ms_cnt_lm_0[8] /I0
9.686 1.099 tINS FF 1 R14C30[0][B] \delay_1ms_cnt_lm_0[8] /F
9.686 0.000 tNET FF 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[8]
13.805 -0.400 tSu 1 R14C30[0][B] \delay_1ms_cnt_Z[8]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.163, 59.889%; route: 1.660, 31.432%; tC2Q: 0.458, 8.678%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path19

Path Summary:

Slack 4.234
Data Arrival Time 9.571
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.749 0.831 tNET FF 1 R14C30[0][A] \delay_1ms_cnt_lm_0[7] /I1
9.571 0.822 tINS FF 1 R14C30[0][A] \delay_1ms_cnt_lm_0[7] /F
9.571 0.000 tNET FF 1 R14C30[0][A] \delay_1ms_cnt_Z[7] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C30[0][A] \delay_1ms_cnt_Z[7] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[7]
13.805 -0.400 tSu 1 R14C30[0][A] \delay_1ms_cnt_Z[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.886, 55.863%; route: 1.822, 35.265%; tC2Q: 0.458, 8.872%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path20

Path Summary:

Slack 4.316
Data Arrival Time 9.489
Data Required Time 13.805
From \delay_1s_cnt[4]
To \delay_1s_cnt[9]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CLK
4.863 0.458 tC2Q RF 4 R15C21[2][B] \delay_1s_cnt[4] /Q
6.170 1.307 tNET FF 2 R15C23[0][A] \delay_1s_cnt_cry_0[4] /I0
7.215 1.045 tINS FF 1 R15C23[0][A] \delay_1s_cnt_cry_0[4] /COUT
7.215 0.000 tNET FF 2 R15C23[0][B] \delay_1s_cnt_cry_0[5] /CIN
7.272 0.057 tINS FF 1 R15C23[0][B] \delay_1s_cnt_cry_0[5] /COUT
7.272 0.000 tNET FF 2 R15C23[1][A] \delay_1s_cnt_cry_0[6] /CIN
7.329 0.057 tINS FF 1 R15C23[1][A] \delay_1s_cnt_cry_0[6] /COUT
7.329 0.000 tNET FF 2 R15C23[1][B] \delay_1s_cnt_cry_0[7] /CIN
7.386 0.057 tINS FF 1 R15C23[1][B] \delay_1s_cnt_cry_0[7] /COUT
7.386 0.000 tNET FF 2 R15C23[2][A] \delay_1s_cnt_cry_0[8] /CIN
7.443 0.057 tINS FF 1 R15C23[2][A] \delay_1s_cnt_cry_0[8] /COUT
7.443 0.000 tNET FF 2 R15C23[2][B] \delay_1s_cnt_s_0[9] /CIN
7.971 0.528 tINS FR 1 R15C23[2][B] \delay_1s_cnt_s_0[9] /SUM
8.390 0.419 tNET RR 1 R14C23[0][A] \delay_1s_cnt_lm_0[9] /I1
9.489 1.099 tINS RF 1 R14C23[0][A] \delay_1s_cnt_lm_0[9] /F
9.489 0.000 tNET FF 1 R14C23[0][A] \delay_1s_cnt[9] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C23[0][A] \delay_1s_cnt[9] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[9]
13.805 -0.400 tSu 1 R14C23[0][A] \delay_1s_cnt[9]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.900, 57.039%; route: 1.726, 33.946%; tC2Q: 0.458, 9.015%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path21

Path Summary:

Slack 4.324
Data Arrival Time 9.481
Data Required Time 13.805
From \delay_1s_cnt[4]
To \delay_1s_cnt[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CLK
4.863 0.458 tC2Q RF 4 R15C21[2][B] \delay_1s_cnt[4] /Q
6.170 1.307 tNET FF 2 R15C23[0][A] \delay_1s_cnt_cry_0[4] /I0
7.215 1.045 tINS FF 1 R15C23[0][A] \delay_1s_cnt_cry_0[4] /COUT
7.215 0.000 tNET FF 2 R15C23[0][B] \delay_1s_cnt_cry_0[5] /CIN
7.272 0.057 tINS FF 1 R15C23[0][B] \delay_1s_cnt_cry_0[5] /COUT
7.272 0.000 tNET FF 2 R15C23[1][A] \delay_1s_cnt_cry_0[6] /CIN
7.329 0.057 tINS FF 1 R15C23[1][A] \delay_1s_cnt_cry_0[6] /COUT
7.329 0.000 tNET FF 2 R15C23[1][B] \delay_1s_cnt_cry_0[7] /CIN
7.892 0.563 tINS FF 1 R15C23[1][B] \delay_1s_cnt_cry_0[7] /SUM
8.382 0.490 tNET FF 1 R15C21[0][A] \delay_1s_cnt_lm_0[7] /I1
9.481 1.099 tINS FF 1 R15C21[0][A] \delay_1s_cnt_lm_0[7] /F
9.481 0.000 tNET FF 1 R15C21[0][A] \delay_1s_cnt[7] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C21[0][A] \delay_1s_cnt[7] /CLK
14.205 -0.200 tUnc \delay_1s_cnt[7]
13.805 -0.400 tSu 1 R15C21[0][A] \delay_1s_cnt[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.821, 55.571%; route: 1.797, 35.400%; tC2Q: 0.458, 9.029%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path22

Path Summary:

Slack 4.363
Data Arrival Time 9.442
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.912 1.026 tINS FR 10 R15C32[3][A] m4_e/F
8.343 0.431 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_lm_0[5] /I1
9.442 1.099 tINS RF 1 R14C32[0][A] \delay_1ms_cnt_lm_0[5] /F
9.442 0.000 tNET FF 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C32[0][A] \delay_1ms_cnt_Z[5] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[5]
13.805 -0.400 tSu 1 R14C32[0][A] \delay_1ms_cnt_Z[5]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.157, 62.677%; route: 1.422, 28.223%; tC2Q: 0.458, 9.099%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path23

Path Summary:

Slack 4.363
Data Arrival Time 9.442
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.912 1.026 tINS FR 10 R15C32[3][A] m4_e/F
8.343 0.431 tNET RR 1 R14C32[0][B] \delay_1ms_cnt_lm_0[6] /I1
9.442 1.099 tINS RF 1 R14C32[0][B] \delay_1ms_cnt_lm_0[6] /F
9.442 0.000 tNET FF 1 R14C32[0][B] \delay_1ms_cnt_Z[6] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R14C32[0][B] \delay_1ms_cnt_Z[6] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[6]
13.805 -0.400 tSu 1 R14C32[0][B] \delay_1ms_cnt_Z[6]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 3.157, 62.677%; route: 1.422, 28.223%; tC2Q: 0.458, 9.099%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path24

Path Summary:

Slack 4.425
Data Arrival Time 9.380
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.754 0.835 tNET FF 1 R15C29[0][B] \delay_1ms_cnt_lm_0[1] /I1
9.380 0.626 tINS FF 1 R15C29[0][B] \delay_1ms_cnt_lm_0[1] /F
9.380 0.000 tNET FF 1 R15C29[0][B] \delay_1ms_cnt_Z[1] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C29[0][B] \delay_1ms_cnt_Z[1] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[1]
13.805 -0.400 tSu 1 R15C29[0][B] \delay_1ms_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.690, 54.073%; route: 1.826, 36.713%; tC2Q: 0.458, 9.213%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Path25

Path Summary:

Slack 4.425
Data Arrival Time 9.380
Data Required Time 13.805
From \delay_1ms_cnt_Z[8]
To \delay_1ms_cnt_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
4.405 3.423 tNET RR 1 R14C30[0][B] \delay_1ms_cnt_Z[8] /CLK
4.863 0.458 tC2Q RF 6 R14C30[0][B] \delay_1ms_cnt_Z[8] /Q
5.849 0.986 tNET FF 1 R15C32[3][B] m4_e_2_0_cZ/I0
6.881 1.032 tINS FF 1 R15C32[3][B] m4_e_2_0_cZ/F
6.886 0.005 tNET FF 1 R15C32[3][A] m4_e/I3
7.918 1.032 tINS FF 10 R15C32[3][A] m4_e/F
8.754 0.835 tNET FF 1 R15C29[1][B] \delay_1ms_cnt_lm_0[3] /I1
9.380 0.626 tINS FF 1 R15C29[1][B] \delay_1ms_cnt_lm_0[3] /F
9.380 0.000 tNET FF 1 R15C29[1][B] \delay_1ms_cnt_Z[3] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
10.982 0.982 tINS RR 31 IOR5[A] clk_ibuf/O
14.405 3.423 tNET RR 1 R15C29[1][B] \delay_1ms_cnt_Z[3] /CLK
14.205 -0.200 tUnc \delay_1ms_cnt_Z[3]
13.805 -0.400 tSu 1 R15C29[1][B] \delay_1ms_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%
Arrival Data Path Delay cell: 2.690, 54.073%; route: 1.826, 36.713%; tC2Q: 0.458, 9.213%
Required Clock Path Delay cell: 0.982, 22.290%; route: 3.423, 77.710%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 4.119
Data Required Time 3.411
From display_mode_Z
To display_mode_Z
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C24[0][A] display_mode_Z/CLK
3.744 0.333 tC2Q RR 2 R15C24[0][A] display_mode_Z/Q
3.747 0.002 tNET RR 1 R15C24[0][A] display_mode_i_cZ/I0
4.119 0.372 tINS RF 1 R15C24[0][A] display_mode_i_cZ/F
4.119 0.000 tNET FF 1 R15C24[0][A] display_mode_Z/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C24[0][A] display_mode_Z/CLK
3.411 0.000 tUnc display_mode_Z
3.411 0.000 tHld 1 R15C24[0][A] display_mode_Z

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path2

Path Summary:

Slack 0.709
Data Arrival Time 4.120
Data Required Time 3.411
From \delay_1us_cnt_Z[5]
To \delay_1us_cnt_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[0][A] \delay_1us_cnt_Z[5] /CLK
3.744 0.333 tC2Q RR 4 R15C18[0][A] \delay_1us_cnt_Z[5] /Q
3.748 0.004 tNET RR 1 R15C18[0][A] un2_delay_1us_cnt_axbxc5_cZ/I2
4.120 0.372 tINS RF 1 R15C18[0][A] un2_delay_1us_cnt_axbxc5_cZ/F
4.120 0.000 tNET FF 1 R15C18[0][A] \delay_1us_cnt_Z[5] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[0][A] \delay_1us_cnt_Z[5] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[5]
3.411 0.000 tHld 1 R15C18[0][A] \delay_1us_cnt_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path3

Path Summary:

Slack 0.709
Data Arrival Time 4.120
Data Required Time 3.411
From \delay_1us_cnt_Z[6]
To \delay_1us_cnt_Z[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C20[1][A] \delay_1us_cnt_Z[6] /CLK
3.744 0.333 tC2Q RR 5 R15C20[1][A] \delay_1us_cnt_Z[6] /Q
3.748 0.004 tNET RR 1 R15C20[1][A] \delay_1us_cnt_0[6] /I3
4.120 0.372 tINS RF 1 R15C20[1][A] \delay_1us_cnt_0[6] /F
4.120 0.000 tNET FF 1 R15C20[1][A] \delay_1us_cnt_Z[6] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C20[1][A] \delay_1us_cnt_Z[6] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[6]
3.411 0.000 tHld 1 R15C20[1][A] \delay_1us_cnt_Z[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path4

Path Summary:

Slack 0.710
Data Arrival Time 4.121
Data Required Time 3.411
From \delay_1us_cnt_Z[4]
To \delay_1us_cnt_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[1][A] \delay_1us_cnt_Z[4] /CLK
3.744 0.333 tC2Q RR 6 R15C18[1][A] \delay_1us_cnt_Z[4] /Q
3.749 0.005 tNET RR 1 R15C18[1][A] \delay_1us_cnt_3_cZ[4] /I1
4.121 0.372 tINS RF 1 R15C18[1][A] \delay_1us_cnt_3_cZ[4] /F
4.121 0.000 tNET FF 1 R15C18[1][A] \delay_1us_cnt_Z[4] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[1][A] \delay_1us_cnt_Z[4] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[4]
3.411 0.000 tHld 1 R15C18[1][A] \delay_1us_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path5

Path Summary:

Slack 0.710
Data Arrival Time 4.121
Data Required Time 3.411
From \delay_1us_cnt_Z[0]
To \delay_1us_cnt_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[1][A] \delay_1us_cnt_Z[0] /CLK
3.744 0.333 tC2Q RR 6 R15C19[1][A] \delay_1us_cnt_Z[0] /Q
3.749 0.005 tNET RR 1 R15C19[1][A] N_53_i_i_cZ/I0
4.121 0.372 tINS RF 1 R15C19[1][A] N_53_i_i_cZ/F
4.121 0.000 tNET FF 1 R15C19[1][A] \delay_1us_cnt_Z[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[1][A] \delay_1us_cnt_Z[0] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[0]
3.411 0.000 tHld 1 R15C19[1][A] \delay_1us_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path6

Path Summary:

Slack 0.711
Data Arrival Time 4.122
Data Required Time 3.411
From \delay_1us_cnt_Z[3]
To \delay_1us_cnt_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[0][A] \delay_1us_cnt_Z[3] /CLK
3.744 0.333 tC2Q RR 6 R15C19[0][A] \delay_1us_cnt_Z[3] /Q
3.750 0.006 tNET RR 1 R15C19[0][A] un2_delay_1us_cnt_axbxc3_cZ/I3
4.122 0.372 tINS RF 1 R15C19[0][A] un2_delay_1us_cnt_axbxc3_cZ/F
4.122 0.000 tNET FF 1 R15C19[0][A] \delay_1us_cnt_Z[3] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[0][A] \delay_1us_cnt_Z[3] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[3]
3.411 0.000 tHld 1 R15C19[0][A] \delay_1us_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path7

Path Summary:

Slack 0.898
Data Arrival Time 4.309
Data Required Time 3.411
From \delay_1ms_cnt_Z[4]
To \delay_1ms_cnt_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.744 0.333 tC2Q RR 14 R15C29[2][A] \delay_1ms_cnt_Z[4] /Q
3.753 0.008 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_lm_0[4] /I2
4.309 0.556 tINS RR 1 R15C29[2][A] \delay_1ms_cnt_lm_0[4] /F
4.309 0.000 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.411 0.000 tUnc \delay_1ms_cnt_Z[4]
3.411 0.000 tHld 1 R15C29[2][A] \delay_1ms_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.556, 61.943%; route: 0.008, 0.921%; tC2Q: 0.333, 37.136%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path8

Path Summary:

Slack 0.953
Data Arrival Time 4.364
Data Required Time 3.411
From \delay_1us_cnt_Z[4]
To \delay_1us_cnt_fast_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[1][A] \delay_1us_cnt_Z[4] /CLK
3.744 0.333 tC2Q RF 6 R15C18[1][A] \delay_1us_cnt_Z[4] /Q
3.992 0.248 tNET FF 1 R15C19[0][B] un2_delay_1us_cnt_axbxc5_fast/I1
4.364 0.372 tINS FF 1 R15C19[0][B] un2_delay_1us_cnt_axbxc5_fast/F
4.364 0.000 tNET FF 1 R15C19[0][B] \delay_1us_cnt_fast_Z[5] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[0][B] \delay_1us_cnt_fast_Z[5] /CLK
3.411 0.000 tUnc \delay_1us_cnt_fast_Z[5]
3.411 0.000 tHld 1 R15C19[0][B] \delay_1us_cnt_fast_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 39.022%; route: 0.248, 26.011%; tC2Q: 0.333, 34.966%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path9

Path Summary:

Slack 0.956
Data Arrival Time 4.367
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RF 13 R15C21[0][B] \delay_1s_cnt[8] /Q
3.995 0.251 tNET FF 1 R15C21[1][B] \delay_1s_cnt_lm_0[2] /I3
4.367 0.372 tINS FF 1 R15C21[1][B] \delay_1s_cnt_lm_0[2] /F
4.367 0.000 tNET FF 1 R15C21[1][B] \delay_1s_cnt[2] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[1][B] \delay_1s_cnt[2] /CLK
3.411 0.000 tUnc \delay_1s_cnt[2]
3.411 0.000 tHld 1 R15C21[1][B] \delay_1s_cnt[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 38.914%; route: 0.251, 26.217%; tC2Q: 0.333, 34.869%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path10

Path Summary:

Slack 0.967
Data Arrival Time 4.378
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.006 0.262 tNET RR 1 R15C21[1][A] \delay_1s_cnt_lm_0[1] /I3
4.378 0.372 tINS RF 1 R15C21[1][A] \delay_1s_cnt_lm_0[1] /F
4.378 0.000 tNET FF 1 R15C21[1][A] \delay_1s_cnt[1] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[1][A] \delay_1s_cnt[1] /CLK
3.411 0.000 tUnc \delay_1s_cnt[1]
3.411 0.000 tHld 1 R15C21[1][A] \delay_1s_cnt[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 38.452%; route: 0.262, 27.093%; tC2Q: 0.333, 34.455%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path11

Path Summary:

Slack 0.967
Data Arrival Time 4.378
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.006 0.262 tNET RR 1 R15C21[0][A] \delay_1s_cnt_lm_0[7] /I3
4.378 0.372 tINS RF 1 R15C21[0][A] \delay_1s_cnt_lm_0[7] /F
4.378 0.000 tNET FF 1 R15C21[0][A] \delay_1s_cnt[7] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][A] \delay_1s_cnt[7] /CLK
3.411 0.000 tUnc \delay_1s_cnt[7]
3.411 0.000 tHld 1 R15C21[0][A] \delay_1s_cnt[7]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 38.452%; route: 0.262, 27.093%; tC2Q: 0.333, 34.455%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path12

Path Summary:

Slack 0.975
Data Arrival Time 4.386
Data Required Time 3.411
From \delay_1us_cnt_Z[3]
To \delay_1us_cnt_fast_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[0][A] \delay_1us_cnt_Z[3] /CLK
3.744 0.333 tC2Q RR 6 R15C19[0][A] \delay_1us_cnt_Z[3] /Q
4.014 0.270 tNET RR 1 R15C18[1][B] \delay_1us_cnt_3_fast_cZ[4] /I0
4.386 0.372 tINS RF 1 R15C18[1][B] \delay_1us_cnt_3_fast_cZ[4] /F
4.386 0.000 tNET FF 1 R15C18[1][B] \delay_1us_cnt_fast_Z[4] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[1][B] \delay_1us_cnt_fast_Z[4] /CLK
3.411 0.000 tUnc \delay_1us_cnt_fast_Z[4]
3.411 0.000 tHld 1 R15C18[1][B] \delay_1us_cnt_fast_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 38.154%; route: 0.270, 27.657%; tC2Q: 0.333, 34.189%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path13

Path Summary:

Slack 1.061
Data Arrival Time 4.472
Data Required Time 3.411
From \delay_1us_cnt_Z[2]
To \delay_1us_cnt_Z[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[0][B] \delay_1us_cnt_Z[2] /CLK
3.744 0.333 tC2Q RR 4 R15C18[0][B] \delay_1us_cnt_Z[2] /Q
3.748 0.004 tNET RR 1 R15C18[0][B] un2_delay_1us_cnt_axbxc2_cZ/I2
4.472 0.724 tINS RR 1 R15C18[0][B] un2_delay_1us_cnt_axbxc2_cZ/F
4.472 0.000 tNET RR 1 R15C18[0][B] \delay_1us_cnt_Z[2] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C18[0][B] \delay_1us_cnt_Z[2] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[2]
3.411 0.000 tHld 1 R15C18[0][B] \delay_1us_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path14

Path Summary:

Slack 1.061
Data Arrival Time 4.472
Data Required Time 3.411
From \delay_1us_cnt_Z[1]
To \delay_1us_cnt_Z[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[1][B] \delay_1us_cnt_Z[1] /CLK
3.744 0.333 tC2Q RR 5 R15C19[1][B] \delay_1us_cnt_Z[1] /Q
3.748 0.004 tNET RR 1 R15C19[1][B] un2_delay_1us_cnt_axbxc1_cZ/I1
4.472 0.724 tINS RR 1 R15C19[1][B] un2_delay_1us_cnt_axbxc1_cZ/F
4.472 0.000 tNET RR 1 R15C19[1][B] \delay_1us_cnt_Z[1] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C19[1][B] \delay_1us_cnt_Z[1] /CLK
3.411 0.000 tUnc \delay_1us_cnt_Z[1]
3.411 0.000 tHld 1 R15C19[1][B] \delay_1us_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path15

Path Summary:

Slack 1.066
Data Arrival Time 4.477
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[8]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
3.753 0.008 tNET RR 1 R15C21[0][B] \delay_1s_cnt_lm_0[8] /I3
4.477 0.724 tINS RR 1 R15C21[0][B] \delay_1s_cnt_lm_0[8] /F
4.477 0.000 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.411 0.000 tUnc \delay_1s_cnt[8]
3.411 0.000 tHld 1 R15C21[0][B] \delay_1s_cnt[8]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.724, 67.943%; route: 0.008, 0.776%; tC2Q: 0.333, 31.281%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path16

Path Summary:

Slack 1.151
Data Arrival Time 4.562
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.006 0.262 tNET RR 1 R15C21[2][A] \delay_1s_cnt_lm_0[3] /I3
4.562 0.556 tINS RR 1 R15C21[2][A] \delay_1s_cnt_lm_0[3] /F
4.562 0.000 tNET RR 1 R15C21[2][A] \delay_1s_cnt[3] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[2][A] \delay_1s_cnt[3] /CLK
3.411 0.000 tUnc \delay_1s_cnt[3]
3.411 0.000 tHld 1 R15C21[2][A] \delay_1s_cnt[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.556, 48.287%; route: 0.262, 22.764%; tC2Q: 0.333, 28.949%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path17

Path Summary:

Slack 1.151
Data Arrival Time 4.562
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.006 0.262 tNET RR 1 R15C21[2][B] \delay_1s_cnt_lm_0[4] /I3
4.562 0.556 tINS RR 1 R15C21[2][B] \delay_1s_cnt_lm_0[4] /F
4.562 0.000 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[2][B] \delay_1s_cnt[4] /CLK
3.411 0.000 tUnc \delay_1s_cnt[4]
3.411 0.000 tHld 1 R15C21[2][B] \delay_1s_cnt[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.556, 48.287%; route: 0.262, 22.764%; tC2Q: 0.333, 28.949%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path18

Path Summary:

Slack 1.283
Data Arrival Time 4.694
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[9]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RR 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.322 0.577 tNET RR 1 R14C23[0][A] \delay_1s_cnt_lm_0[9] /I3
4.694 0.372 tINS RF 1 R14C23[0][A] \delay_1s_cnt_lm_0[9] /F
4.694 0.000 tNET FF 1 R14C23[0][A] \delay_1s_cnt[9] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R14C23[0][A] \delay_1s_cnt[9] /CLK
3.411 0.000 tUnc \delay_1s_cnt[9]
3.411 0.000 tHld 1 R14C23[0][A] \delay_1s_cnt[9]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.372, 28.999%; route: 0.577, 45.016%; tC2Q: 0.333, 25.985%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path19

Path Summary:

Slack 1.295
Data Arrival Time 4.706
Data Required Time 3.411
From display_mode_Z
To \pwm_on[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C24[0][A] display_mode_Z/CLK
3.744 0.333 tC2Q RR 2 R15C24[0][A] display_mode_Z/Q
3.982 0.238 tNET RR 1 R15C24[1][B] N_26_i_cZ/I0
4.706 0.724 tINS RR 1 R15C24[1][B] N_26_i_cZ/F
4.706 0.000 tNET RR 1 R15C24[1][B] \pwm_on[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C24[1][B] \pwm_on[0] /CLK
3.411 0.000 tUnc \pwm_on[0]
3.411 0.000 tHld 1 R15C24[1][B] \pwm_on[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.724, 55.911%; route: 0.238, 18.347%; tC2Q: 0.333, 25.742%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path20

Path Summary:

Slack 1.310
Data Arrival Time 4.721
Data Required Time 3.411
From \delay_1ms_cnt_Z[4]
To \delay_1ms_cnt_Z[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.744 0.333 tC2Q RF 14 R15C29[2][A] \delay_1ms_cnt_Z[4] /Q
3.995 0.251 tNET FF 1 R15C29[1][A] \delay_1ms_cnt_lm_0[2] /I2
4.721 0.726 tINS FR 1 R15C29[1][A] \delay_1ms_cnt_lm_0[2] /F
4.721 0.000 tNET RR 1 R15C29[1][A] \delay_1ms_cnt_Z[2] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[1][A] \delay_1ms_cnt_Z[2] /CLK
3.411 0.000 tUnc \delay_1ms_cnt_Z[2]
3.411 0.000 tHld 1 R15C29[1][A] \delay_1ms_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.726, 55.421%; route: 0.251, 19.132%; tC2Q: 0.333, 25.446%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path21

Path Summary:

Slack 1.317
Data Arrival Time 4.728
Data Required Time 3.411
From \delay_1ms_cnt_Z[4]
To \delay_1ms_cnt_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.744 0.333 tC2Q RF 14 R15C29[2][A] \delay_1ms_cnt_Z[4] /Q
4.002 0.258 tNET FF 1 R15C29[0][A] \delay_1ms_cnt_lm_0[0] /I2
4.728 0.726 tINS FR 1 R15C29[0][A] \delay_1ms_cnt_lm_0[0] /F
4.728 0.000 tNET RR 1 R15C29[0][A] \delay_1ms_cnt_Z[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[0][A] \delay_1ms_cnt_Z[0] /CLK
3.411 0.000 tUnc \delay_1ms_cnt_Z[0]
3.411 0.000 tHld 1 R15C29[0][A] \delay_1ms_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.726, 55.126%; route: 0.258, 19.564%; tC2Q: 0.333, 25.310%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path22

Path Summary:

Slack 1.317
Data Arrival Time 4.728
Data Required Time 3.411
From \delay_1ms_cnt_Z[4]
To \delay_1ms_cnt_Z[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.744 0.333 tC2Q RF 14 R15C29[2][A] \delay_1ms_cnt_Z[4] /Q
4.002 0.258 tNET FF 1 R15C29[0][B] \delay_1ms_cnt_lm_0[1] /I2
4.728 0.726 tINS FR 1 R15C29[0][B] \delay_1ms_cnt_lm_0[1] /F
4.728 0.000 tNET RR 1 R15C29[0][B] \delay_1ms_cnt_Z[1] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[0][B] \delay_1ms_cnt_Z[1] /CLK
3.411 0.000 tUnc \delay_1ms_cnt_Z[1]
3.411 0.000 tHld 1 R15C29[0][B] \delay_1ms_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.726, 55.126%; route: 0.258, 19.564%; tC2Q: 0.333, 25.310%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path23

Path Summary:

Slack 1.329
Data Arrival Time 4.740
Data Required Time 3.411
From \delay_1ms_cnt_Z[4]
To \delay_1ms_cnt_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[2][A] \delay_1ms_cnt_Z[4] /CLK
3.744 0.333 tC2Q RR 14 R15C29[2][A] \delay_1ms_cnt_Z[4] /Q
4.016 0.272 tNET RR 1 R15C29[1][B] \delay_1ms_cnt_lm_0[3] /I2
4.740 0.724 tINS RR 1 R15C29[1][B] \delay_1ms_cnt_lm_0[3] /F
4.740 0.000 tNET RR 1 R15C29[1][B] \delay_1ms_cnt_Z[3] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C29[1][B] \delay_1ms_cnt_Z[3] /CLK
3.411 0.000 tUnc \delay_1ms_cnt_Z[3]
3.411 0.000 tHld 1 R15C29[1][B] \delay_1ms_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.724, 54.463%; route: 0.272, 20.462%; tC2Q: 0.333, 25.075%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path24

Path Summary:

Slack 1.331
Data Arrival Time 4.742
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RF 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.016 0.272 tNET FF 1 R15C20[2][A] \delay_1s_cnt_lm_0[0] /I3
4.742 0.726 tINS FR 1 R15C20[2][A] \delay_1s_cnt_lm_0[0] /F
4.742 0.000 tNET RR 1 R15C20[2][A] \delay_1s_cnt[0] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C20[2][A] \delay_1s_cnt[0] /CLK
3.411 0.000 tUnc \delay_1s_cnt[0]
3.411 0.000 tHld 1 R15C20[2][A] \delay_1s_cnt[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.726, 54.544%; route: 0.272, 20.413%; tC2Q: 0.333, 25.043%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Path25

Path Summary:

Slack 1.331
Data Arrival Time 4.742
Data Required Time 3.411
From \delay_1s_cnt[8]
To \delay_1s_cnt[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C21[0][B] \delay_1s_cnt[8] /CLK
3.744 0.333 tC2Q RF 13 R15C21[0][B] \delay_1s_cnt[8] /Q
4.016 0.272 tNET FF 1 R15C20[0][A] \delay_1s_cnt_lm_0[5] /I3
4.742 0.726 tINS FR 1 R15C20[0][A] \delay_1s_cnt_lm_0[5] /F
4.742 0.000 tNET RR 1 R15C20[0][A] \delay_1s_cnt[5] /D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
0.844 0.844 tINS RR 31 IOR5[A] clk_ibuf/O
3.411 2.567 tNET RR 1 R15C20[0][A] \delay_1s_cnt[5] /CLK
3.411 0.000 tUnc \delay_1s_cnt[5]
3.411 0.000 tHld 1 R15C20[0][A] \delay_1s_cnt[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%
Arrival Data Path Delay cell: 0.726, 54.544%; route: 0.272, 20.413%; tC2Q: 0.333, 25.043%
Required Clock Path Delay cell: 0.844, 24.755%; route: 2.567, 75.245%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1us_cnt_fast_Z[5]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1us_cnt_fast_Z[5] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1us_cnt_fast_Z[5] /CLK

MPW2

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1s_cnt[9]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1s_cnt[9] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1s_cnt[9] /CLK

MPW3

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1s_cnt[5]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1s_cnt[5] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1s_cnt[5] /CLK

MPW4

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1ms_cnt_Z[7]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1ms_cnt_Z[7] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1ms_cnt_Z[7] /CLK

MPW5

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: display_mode_Z

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF display_mode_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR display_mode_Z/CLK

MPW6

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1us_cnt_Z[2]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1us_cnt_Z[2] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1us_cnt_Z[2] /CLK

MPW7

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1ms_cnt_Z[8]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1ms_cnt_Z[8] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1ms_cnt_Z[8] /CLK

MPW8

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1us_cnt_Z[3]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1us_cnt_Z[3] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1us_cnt_Z[3] /CLK

MPW9

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1us_cnt_Z[4]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1us_cnt_Z[4] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1us_cnt_Z[4] /CLK

MPW10

MPW Summary:

Slack: 2.561
Actual Width: 3.811
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: \delay_1s_cnt[6]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
9.600 3.616 tNET FF \delay_1s_cnt[6] /CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
13.411 2.567 tNET RR \delay_1s_cnt[6] /CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
31 clk_c 2.867 3.616
14 delay_1ms_cnt[4] 4.302 1.491
13 un2_pwm_on_8 3.621 1.978
10 N_6_0 4.079 0.861
10 N_33_mux 3.957 0.835
10 N_28 5.616 0.843
10 delay_1ms 3.114 1.689
10 delay_1us_cnt9_i 5.433 2.173
10 m25_2 4.886 0.876
6 delay_1ms_cnt[8] 3.957 1.476

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R15C23 0.361
R15C31 0.347
R15C21 0.306
R15C29 0.306
R15C22 0.292
R15C20 0.292
R15C30 0.278
R15C32 0.250
R14C31 0.222
R15C19 0.194

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command