#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-023

# Tue Aug  6 14:24:05 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\src\LED_test.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module led_breath
@N:CG364 : LED_test.v(1) | Synthesizing module led_breath in library work.
@N:CG179 : LED_test.v(42) | Removing redundant assignment.
@N:CG179 : LED_test.v(58) | Removing redundant assignment.
@N:CG179 : LED_test.v(78) | Removing redundant assignment.
Running optimization stage 1 on led_breath .......
@W:CL271 : LED_test.v(85) | Pruning unused bits 3 to 2 of pwm_on[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : LED_test.v(85) | Pruning register bit 1 of pwm_on[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on led_breath .......
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : LED_test.v(51) | Pruning register bits 15 to 10 of delay_1s_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : LED_test.v(35) | Pruning register bits 15 to 10 of delay_1ms_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : LED_test.v(19) | Pruning register bits 15 to 7 of delay_1us_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:24:05 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : led_test.v(1) | Selected library: work cell: led_breath view verilog as top level
@N:NF107 : led_test.v(1) | Selected library: work cell: led_breath view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:24:05 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:24:05 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
File D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
File E:\Demo_program\DK-START-GW1NR9\LED_breath_test\impl\synthesize\rev_1\synwork\IO_test_comp.srs changed - recompiling
@N:NF107 : led_test.v(1) | Selected library: work cell: led_breath view verilog as top level
@N:NF107 : led_test.v(1) | Selected library: work cell: led_breath view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:24:07 2019

###########################################################]


Premap Report



# Tue Aug  6 14:24:07 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  IO_test_scck.rpt
Printing clock  summary report in "E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\impl\synthesize\rev_1\IO_test_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)



Clock Summary
******************

          Start              Requested     Requested     Clock        Clock                     Clock
Level     Clock              Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------
0 -       led_breath|clk     213.6 MHz     4.682         inferred     Autoconstr_clkgroup_0     29   
=====================================================================================================



Clock Load Summary
***********************

                   Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
Clock              Load      Pin           Seq Example     Seq Example       Comb Example 
------------------------------------------------------------------------------------------
led_breath|clk     29        clk(port)     pwm_on[0].C     -                 -            
==========================================================================================

@W:MT529 : led_test.v(71) | Found inferred clock led_breath|clk which controls 29 sequential elements including display_mode. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 29 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 Unconstrained_port     29         display_mode   
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\impl\synthesize\rev_1\IO_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug  6 14:24:09 2019

###########################################################]


Map & Optimize Report



# Tue Aug  6 14:24:09 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

@N:MO231 : led_test.v(35) | Found counter in view:work.led_breath(verilog) instance delay_1ms_cnt[9:0] 
@N:MO231 : led_test.v(51) | Found counter in view:work.led_breath(verilog) instance delay_1s_cnt[9:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 190MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 190MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 190MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.25ns		  75 /        29
   2		0h:00m:00s		    -2.25ns		  75 /        29

   3		0h:00m:01s		    -2.00ns		  76 /        29
   4		0h:00m:01s		    -1.68ns		  77 /        29
   5		0h:00m:01s		    -1.04ns		  77 /        29
   6		0h:00m:01s		    -1.04ns		  77 /        29
   7		0h:00m:01s		    -1.04ns		  77 /        29
   8		0h:00m:01s		    -1.04ns		  77 /        29
   9		0h:00m:01s		    -1.04ns		  77 /        29
@N:FX271 : led_test.v(19) | Replicating instance delay_1us_cnt[4] (in view: work.led_breath(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : led_test.v(19) | Replicating instance delay_1us_cnt[5] (in view: work.led_breath(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication


  10		0h:00m:01s		    -0.76ns		  82 /        31
  11		0h:00m:01s		    -0.53ns		  82 /        31
  12		0h:00m:01s		    -0.73ns		  82 /        31

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 191MB)

Writing Analyst data base E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NR9\DK-START-GW1NR9-LED_Blink\impl\synthesize\rev_1\synwork\IO_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)

@W:MT420 :  | Found inferred clock led_breath|clk with period 5.50ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug  6 14:24:13 2019
#


Top view:               led_breath
Requested Frequency:    181.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.971

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
led_breath|clk     181.8 MHz     154.5 MHz     5.500         6.471         -0.971     inferred     Autoconstr_clkgroup_0
System             100.0 MHz     176.9 MHz     10.000        5.654         4.346      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------
Starting        Ending          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------
System          led_breath|clk  |  5.500       4.346   |  No paths    -      |  No paths    -      |  No paths    -    
led_breath|clk  System          |  5.500       4.112   |  No paths    -      |  No paths    -      |  No paths    -    
led_breath|clk  led_breath|clk  |  5.500       -0.971  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: led_breath|clk
====================================



Starting Points with Worst Slack
********************************

                     Starting                                                  Arrival           
Instance             Reference          Type      Pin     Net                  Time        Slack 
                     Clock                                                                       
-------------------------------------------------------------------------------------------------
delay_1ms_cnt[5]     led_breath|clk     DFFCE     Q       delay_1ms_cnt[5]     0.367       -0.971
delay_1ms_cnt[3]     led_breath|clk     DFFCE     Q       delay_1ms_cnt[3]     0.367       -0.903
delay_1ms_cnt[7]     led_breath|clk     DFFCE     Q       delay_1ms_cnt[7]     0.367       -0.694
delay_1ms_cnt[9]     led_breath|clk     DFFCE     Q       delay_1ms_cnt[9]     0.367       -0.632
delay_1s_cnt[4]      led_breath|clk     DFFCE     Q       un2_pwm_on_4         0.367       -0.573
delay_1ms_cnt[8]     led_breath|clk     DFFCE     Q       delay_1ms_cnt[8]     0.367       -0.565
delay_1s_cnt[1]      led_breath|clk     DFFCE     Q       un2_pwm_on_1         0.367       -0.505
delay_1s_cnt[3]      led_breath|clk     DFFCE     Q       un2_pwm_on_3         0.367       -0.505
delay_1s_cnt[0]      led_breath|clk     DFFCE     Q       un2_pwm_on_0         0.367       -0.438
delay_1s_cnt[8]      led_breath|clk     DFFCE     Q       un2_pwm_on_8         0.367       -0.356
=================================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                                     Required           
Instance             Reference          Type      Pin     Net                     Time         Slack 
                     Clock                                                                           
-----------------------------------------------------------------------------------------------------
delay_1ms_cnt[0]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[0]     5.367        -0.971
delay_1ms_cnt[1]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[1]     5.367        -0.971
delay_1ms_cnt[2]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[2]     5.367        -0.971
delay_1ms_cnt[3]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[3]     5.367        -0.971
delay_1ms_cnt[4]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[4]     5.367        -0.971
delay_1ms_cnt[5]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[5]     5.367        -0.971
delay_1ms_cnt[6]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[6]     5.367        -0.971
delay_1ms_cnt[7]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[7]     5.367        -0.971
delay_1ms_cnt[8]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[8]     5.367        -0.971
delay_1ms_cnt[9]     led_breath|clk     DFFCE     D       delay_1ms_cnt_lm[9]     5.367        -0.971
=====================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      6.338
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.971

    Number of logic level(s):                3
    Starting point:                          delay_1ms_cnt[5] / Q
    Ending point:                            delay_1ms_cnt[0] / D
    The start point is clocked by            led_breath|clk [rising] on pin CLK
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                      Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
delay_1ms_cnt[5]          DFFCE     Q        Out     0.367     0.367       -         
delay_1ms_cnt[5]          Net       -        -       1.021     -           6         
G_7_sx                    LUT4      I1       In      -         1.388       -         
G_7_sx                    LUT4      F        Out     1.099     2.487       -         
G_7_sx                    Net       -        -       0.766     -           1         
G_7                       LUT3      I0       In      -         3.253       -         
G_7                       LUT3      F        Out     1.032     4.285       -         
N_6_0                     Net       -        -       1.021     -           10        
delay_1ms_cnt_lm_0[0]     LUT4      I0       In      -         5.306       -         
delay_1ms_cnt_lm_0[0]     LUT4      F        Out     1.032     6.338       -         
delay_1ms_cnt_lm[0]       Net       -        -       0.000     -           1         
delay_1ms_cnt[0]          DFFCE     D        In      -         6.338       -         
=====================================================================================
Total path delay (propagation time + setup) of 6.471 is 3.663(56.6%) logic and 2.808(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      6.338
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.971

    Number of logic level(s):                3
    Starting point:                          delay_1ms_cnt[5] / Q
    Ending point:                            delay_1ms_cnt[9] / D
    The start point is clocked by            led_breath|clk [rising] on pin CLK
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                      Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
delay_1ms_cnt[5]          DFFCE     Q        Out     0.367     0.367       -         
delay_1ms_cnt[5]          Net       -        -       1.021     -           6         
G_7_sx                    LUT4      I1       In      -         1.388       -         
G_7_sx                    LUT4      F        Out     1.099     2.487       -         
G_7_sx                    Net       -        -       0.766     -           1         
G_7                       LUT3      I0       In      -         3.253       -         
G_7                       LUT3      F        Out     1.032     4.285       -         
N_6_0                     Net       -        -       1.021     -           10        
delay_1ms_cnt_lm_0[9]     LUT4      I0       In      -         5.306       -         
delay_1ms_cnt_lm_0[9]     LUT4      F        Out     1.032     6.338       -         
delay_1ms_cnt_lm[9]       Net       -        -       0.000     -           1         
delay_1ms_cnt[9]          DFFCE     D        In      -         6.338       -         
=====================================================================================
Total path delay (propagation time + setup) of 6.471 is 3.663(56.6%) logic and 2.808(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      6.338
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.971

    Number of logic level(s):                3
    Starting point:                          delay_1ms_cnt[5] / Q
    Ending point:                            delay_1ms_cnt[8] / D
    The start point is clocked by            led_breath|clk [rising] on pin CLK
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                      Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
delay_1ms_cnt[5]          DFFCE     Q        Out     0.367     0.367       -         
delay_1ms_cnt[5]          Net       -        -       1.021     -           6         
G_7_sx                    LUT4      I1       In      -         1.388       -         
G_7_sx                    LUT4      F        Out     1.099     2.487       -         
G_7_sx                    Net       -        -       0.766     -           1         
G_7                       LUT3      I0       In      -         3.253       -         
G_7                       LUT3      F        Out     1.032     4.285       -         
N_6_0                     Net       -        -       1.021     -           10        
delay_1ms_cnt_lm_0[8]     LUT4      I0       In      -         5.306       -         
delay_1ms_cnt_lm_0[8]     LUT4      F        Out     1.032     6.338       -         
delay_1ms_cnt_lm[8]       Net       -        -       0.000     -           1         
delay_1ms_cnt[8]          DFFCE     D        In      -         6.338       -         
=====================================================================================
Total path delay (propagation time + setup) of 6.471 is 3.663(56.6%) logic and 2.808(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      6.338
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.971

    Number of logic level(s):                3
    Starting point:                          delay_1ms_cnt[5] / Q
    Ending point:                            delay_1ms_cnt[7] / D
    The start point is clocked by            led_breath|clk [rising] on pin CLK
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                      Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
delay_1ms_cnt[5]          DFFCE     Q        Out     0.367     0.367       -         
delay_1ms_cnt[5]          Net       -        -       1.021     -           6         
G_7_sx                    LUT4      I1       In      -         1.388       -         
G_7_sx                    LUT4      F        Out     1.099     2.487       -         
G_7_sx                    Net       -        -       0.766     -           1         
G_7                       LUT3      I0       In      -         3.253       -         
G_7                       LUT3      F        Out     1.032     4.285       -         
N_6_0                     Net       -        -       1.021     -           10        
delay_1ms_cnt_lm_0[7]     LUT4      I0       In      -         5.306       -         
delay_1ms_cnt_lm_0[7]     LUT4      F        Out     1.032     6.338       -         
delay_1ms_cnt_lm[7]       Net       -        -       0.000     -           1         
delay_1ms_cnt[7]          DFFCE     D        In      -         6.338       -         
=====================================================================================
Total path delay (propagation time + setup) of 6.471 is 3.663(56.6%) logic and 2.808(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      6.338
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.971

    Number of logic level(s):                3
    Starting point:                          delay_1ms_cnt[5] / Q
    Ending point:                            delay_1ms_cnt[6] / D
    The start point is clocked by            led_breath|clk [rising] on pin CLK
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                      Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
delay_1ms_cnt[5]          DFFCE     Q        Out     0.367     0.367       -         
delay_1ms_cnt[5]          Net       -        -       1.021     -           6         
G_7_sx                    LUT4      I1       In      -         1.388       -         
G_7_sx                    LUT4      F        Out     1.099     2.487       -         
G_7_sx                    Net       -        -       0.766     -           1         
G_7                       LUT3      I0       In      -         3.253       -         
G_7                       LUT3      F        Out     1.032     4.285       -         
N_6_0                     Net       -        -       1.021     -           10        
delay_1ms_cnt_lm_0[6]     LUT4      I0       In      -         5.306       -         
delay_1ms_cnt_lm_0[6]     LUT4      F        Out     1.032     6.338       -         
delay_1ms_cnt_lm[6]       Net       -        -       0.000     -           1         
delay_1ms_cnt[6]          DFFCE     D        In      -         6.338       -         
=====================================================================================
Total path delay (propagation time + setup) of 6.471 is 3.663(56.6%) logic and 2.808(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                   Starting                                          Arrival          
Instance           Reference     Type     Pin     Net                Time        Slack
                   Clock                                                              
--------------------------------------------------------------------------------------
N_53_i_i           System        INV      O       N_53_i_i           0.000       4.346
display_mode_i     System        INV      O       display_mode_i     0.000       4.346
======================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                           Required          
Instance             Reference     Type      Pin     Net                Time         Slack
                     Clock                                                                
------------------------------------------------------------------------------------------
delay_1us_cnt[0]     System        DFFC      D       N_53_i_i           5.367        4.346
display_mode         System        DFFCE     D       display_mode_i     5.367        4.346
==========================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.500
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.367

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.346

    Number of logic level(s):                0
    Starting point:                          N_53_i_i / O
    Ending point:                            delay_1us_cnt[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            led_breath|clk [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
N_53_i_i             INV      O        Out     0.000     0.000       -         
N_53_i_i             Net      -        -       1.021     -           1         
delay_1us_cnt[0]     DFFC     D        In      -         1.021       -         
===============================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)

---------------------------------------
Resource Usage Report for led_breath 

Mapping to part: gw1n_9lqfp144-6
Cell usage:
ALU             30 uses
DFFC            10 uses
DFFCE           21 uses
GSR             1 use
INV             3 uses
LUT2            4 uses
LUT3            6 uses
LUT4            41 uses

I/O ports: 6
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   31 of 6480 (0%)
Total load per clock:
   led_breath|clk: 31

@S |Mapping Summary:
Total  LUTs: 51 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 191MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue Aug  6 14:24:13 2019

###########################################################]