#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-023

# Tue Aug  6 14:29:07 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw1ns.v" (library work)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\src\gowin_empu\gowin_empu.v" (library work)
@I::"E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\src\ledtest_top.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module ledtest_top
@N:CG364 : gw1ns.v(1547) | Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
@N:CG364 : gw1ns.v(365) | Synthesizing module IBUF in library work.
Running optimization stage 1 on IBUF .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MCU .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on GW_CLKDIV .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on GW_GPIO .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DQCE .......
Running optimization stage 1 on FLASH128K .......
Running optimization stage 1 on gw_rom_flash_15s_32s .......
Running optimization stage 1 on GW_FLASH .......
Running optimization stage 1 on SP .......
Running optimization stage 1 on GW_SRAM .......
Running optimization stage 1 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on ADC .......
Running optimization stage 1 on gw_cmsdk_apb2_adc .......
Running optimization stage 1 on DLC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on DFFNCE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on SPI_Z2 .......
Running optimization stage 1 on gw_cmsdk_apb2_spi .......
Running optimization stage 1 on gw_peripherals_interconnect_12s .......
Running optimization stage 1 on \~Gowin_EMPU.Gowin_EMPU_  .......
@N:CG364 : gowin_empu.v(4175) | Synthesizing module Gowin_EMPU in library work.
Running optimization stage 1 on Gowin_EMPU .......
@W:CL168 : gowin_empu.v(4209) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : ledtest_top.v(1) | Synthesizing module ledtest_top in library work.
Running optimization stage 1 on ledtest_top .......
Running optimization stage 2 on ledtest_top .......
Running optimization stage 2 on Gowin_EMPU .......
Running optimization stage 2 on \~Gowin_EMPU.Gowin_EMPU_  .......
Running optimization stage 2 on gw_peripherals_interconnect_12s .......
Running optimization stage 2 on gw_cmsdk_apb2_spi .......
Running optimization stage 2 on SPI_Z2 .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFNCE .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DLC .......
Running optimization stage 2 on gw_cmsdk_apb2_adc .......
Running optimization stage 2 on ADC .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 2 on GW_SRAM .......
Running optimization stage 2 on SP .......
Running optimization stage 2 on GW_FLASH .......
Running optimization stage 2 on gw_rom_flash_15s_32s .......
Running optimization stage 2 on FLASH128K .......
Running optimization stage 2 on DQCE .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on GW_GPIO .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on GW_CLKDIV .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on MCU .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on IBUF .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:29:07 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:29:08 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:29:08 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
File D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
File E:\Demo_program\DK-START-GW1NS2\DK-START-GW1NS2-ledtest\DK-START-GW1NS2-ledtest\impl\synthesize\rev_1\synwork\DK-START-GW1NS2-ledtest_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:29:09 2019

###########################################################]


Premap Report



# Tue Aug  6 14:29:10 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  DK-START-GW1NS2-ledtest_scck.rpt
Printing clock  summary report in "E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\impl\synthesize\rev_1\DK-START-GW1NS2-ledtest_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 118MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)



Clock Summary
******************

          Start                             Requested     Requested     Clock        Clock                     Clock
Level     Clock                             Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------------------
0 -       System                            328.2 MHz     3.047         system       system_clkgroup           0    
                                                                                                                    
0 -       GW_CLKDIV|fclk_inferred_clock     100.0 MHz     10.000        inferred     Autoconstr_clkgroup_0     147  
                                                                                                                    
0 -       SPI_Z2|N_88_i_inferred_clock      100.0 MHz     10.000        inferred     Autoconstr_clkgroup_1     3    
====================================================================================================================



Clock Load Summary
***********************

                                  Clock     Source                                                                                                        Clock Pin                                                                                                                     Non-clock Pin                                                                                                                   Non-clock Pin
Clock                             Load      Pin                                                                                                           Seq Example                                                                                                                   Seq Example                                                                                                                     Comb Example 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                            0         -                                                                                                             -                                                                                                                             -                                                                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                                                                     
GW_CLKDIV|fclk_inferred_clock     147       Gowin_EMPU_inst.Gowin_EMPU_inst.sysclk.clkdiv_inst.CLKOUT(CLKDIV)                                             Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[2\].CLK     -                                                                                                                               -            
                                                                                                                                                                                                                                                                                                                                                                                                                                     
SPI_Z2|N_88_i_inferred_clock      3         Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.N_88_i_cZ.F(LUT2)     Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.SCLK_MASTER_2.G            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.SCLK_MASTER_1_fast.CLEAR     -            
=====================================================================================================================================================================================================================================================================================================================================================================================================================================


@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\impl\synthesize\rev_1\DK-START-GW1NS2-ledtest.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 108MB peak: 194MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Tue Aug  6 14:29:12 2019

###########################################################]


Map & Optimize Report



# Tue Aug  6 14:29:12 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -4.52ns		 192 /         0
   2		0h:00m:01s		    -4.52ns		 192 /         0

   3		0h:00m:01s		    -4.52ns		 192 /         0

   4		0h:00m:01s		    -4.52ns		 192 /         0

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 148 clock pin(s) of sequential element(s)
0 instances converted, 148 sequential instances remain driven by gated/generated clocks

================================================================================================================================================================================== Gated/Generated Clocks ===================================================================================================================================================================================
Clock Tree ID     Driving Element                                                                                       Drive Element Type     Fanout     Sample Instance                                                                                                      Explanation                                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        Gowin_EMPU_inst.Gowin_EMPU_inst.sysclk.clkdiv_inst                                                    CLKDIV                 147        Gowin_EMPU_inst.Gowin_EMPU_inst.u_flash_wrap.\\rom_haddr_test_Z\[11\]                                                Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
ClockId0002        Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.N_88_i_cZ     LUT2                   1          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.SCLK_MASTER_2     Asynchronous set/reset mismatch prevents generated clock conversion                                           
=============================================================================================================================================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 194MB)

Writing Analyst data base E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\impl\synthesize\rev_1\synwork\DK-START-GW1NS2-ledtest_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 194MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 194MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 194MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 194MB)

@W:MT246 : gowin_empu.v(3996) | Blackbox MCU is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(1380) | Blackbox ADC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(359) | Blackbox DQCE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(206) | Blackbox FLASH128K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(34) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock GW_CLKDIV|fclk_inferred_clock with period 8.87ns. Please declare a user-defined clock on net Gowin_EMPU_inst.Gowin_EMPU_inst.sysclk.fclk. 
@W:MT420 :  | Found inferred clock SPI_Z2|N_88_i_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.N_88_i. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug  6 14:29:16 2019
#


Top view:               ledtest_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -4.156

                                  Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                    Frequency     Frequency     Period        Period        Slack      Type         Group                
---------------------------------------------------------------------------------------------------------------------------------------
GW_CLKDIV|fclk_inferred_clock     112.8 MHz     58.2 MHz      8.868         17.180        -4.156     inferred     Autoconstr_clkgroup_0
SPI_Z2|N_88_i_inferred_clock      100.0 MHz     NA            10.000        NA            NA         inferred     Autoconstr_clkgroup_1
System                            165.4 MHz     140.6 MHz     6.046         7.114         -1.067     system       system_clkgroup      
=======================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise  
-------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                       Ending                         |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack 
-------------------------------------------------------------------------------------------------------------------------------------------------------
System                         System                         |  6.046       -1.067  |  No paths    -      |  No paths    -       |  No paths    -     
System                         GW_CLKDIV|fclk_inferred_clock  |  8.868       0.712   |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV|fclk_inferred_clock  System                         |  8.868       1.975   |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV|fclk_inferred_clock  GW_CLKDIV|fclk_inferred_clock  |  8.868       -1.565  |  No paths    -      |  4.434       -4.156  |  4.434       -0.239
SPI_Z2|N_88_i_inferred_clock   GW_CLKDIV|fclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  Diff grp    -       |  No paths    -     
=======================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_CLKDIV|fclk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                                          Starting                                                                  Arrival           
Instance                                                                                                                  Reference                         Type      Pin     Net                   Time        Slack 
                                                                                                                          Clock                                                                                       
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[1\]     GW_CLKDIV|fclk_inferred_clock     DFFC      Q       c_status_fast[1]      0.367       -4.156
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_0_rep1        GW_CLKDIV|fclk_inferred_clock     DFFC      Q       c_status_0_rep1       0.367       -4.089
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[0\]     GW_CLKDIV|fclk_inferred_clock     DFFC      Q       c_status_fast[0]      0.367       -4.089
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\clock_sel_fast_Z\[1\]           GW_CLKDIV|fclk_inferred_clock     DFFCE     Q       clock_sel_fast[1]     0.367       -4.021
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.clock_cnt\[0\]         GW_CLKDIV|fclk_inferred_clock     DFFC      Q       clock_cnt[0]          0.367       -3.901
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[2\]     GW_CLKDIV|fclk_inferred_clock     DFFC      Q       c_status_fast[2]      0.367       -3.879
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\clock_sel_fast_Z\[0\]           GW_CLKDIV|fclk_inferred_clock     DFFCE     Q       clock_sel_fast[0]     0.367       -3.834
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.clock_cnt\[1\]         GW_CLKDIV|fclk_inferred_clock     DFFC      Q       clock_cnt[1]          0.367       -3.812
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.pending_data           GW_CLKDIV|fclk_inferred_clock     DFFCE     Q       pending_data          0.367       -3.683
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.clock_cnt\[2\]         GW_CLKDIV|fclk_inferred_clock     DFFC      Q       clock_cnt[2]          0.367       -3.624
======================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                          Starting                                                                    Required           
Instance                                                                                                                  Reference                         Type       Pin     Net                    Time         Slack 
                                                                                                                          Clock                                                                                          
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]          GW_CLKDIV|fclk_inferred_clock     DFFNCE     D       n_status_7[0]          4.301        -4.156
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[2\]          GW_CLKDIV|fclk_inferred_clock     DFFNCE     D       n_status_7[2]          4.301        -3.428
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[1\]          GW_CLKDIV|fclk_inferred_clock     DFFNCE     D       N_106_i                4.301        -2.426
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.data_cnt\[2\]          GW_CLKDIV|fclk_inferred_clock     DFFC       D       data_cnt_3[2]          8.735        -1.565
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.data_cnt_fast\[2\]     GW_CLKDIV|fclk_inferred_clock     DFFC       D       data_cnt_3_fast[2]     8.735        -1.565
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.data_cnt\[3\]          GW_CLKDIV|fclk_inferred_clock     DFFC       D       data_cnt_3[3]          8.735        -1.092
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.data_cnt\[4\]          GW_CLKDIV|fclk_inferred_clock     DFFC       D       data_cnt_1_axbxc4      8.735        -1.092
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.data_cnt_fast\[3\]     GW_CLKDIV|fclk_inferred_clock     DFFC       D       data_cnt_3_fast[3]     8.735        -1.092
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.clock_cnt\[0\]         GW_CLKDIV|fclk_inferred_clock     DFFC       D       clock_cnt_lm[0]        4.301        -0.239
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.clock_cnt\[1\]         GW_CLKDIV|fclk_inferred_clock     DFFC       D       clock_cnt_lm[1]        4.301        -0.239
=========================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.434
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.301

    - Propagation time:                      8.457
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.156

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[1\] / Q
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\] / D
    The start point is clocked by            GW_CLKDIV|fclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|fclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                                Pin      Pin               Arrival     No. of    
Name                                                                                                                            Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[1\]           DFFC          Q        Out     0.367     0.367       -         
c_status_fast[1]                                                                                                                Net           -        -       1.021     -           3         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          I1       In      -         1.388       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          F        Out     1.099     2.487       -         
G_8_0_sn_sx                                                                                                                     Net           -        -       1.021     -           2         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          I1       In      -         3.508       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          F        Out     1.099     4.607       -         
G_8_0_mb_N_4L5_1_0                                                                                                              Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     I0       In      -         4.607       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     O        Out     0.150     4.757       -         
G_8_0_mb_1                                                                                                                      Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          I0       In      -         5.778       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          F        Out     1.032     6.810       -         
G_8_0_mb                                                                                                                        Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          I3       In      -         7.831       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          F        Out     0.626     8.457       -         
n_status_7[0]                                                                                                                   Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]                DFFNCE        D        In      -         8.457       -         
===============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.590 is 4.506(52.5%) logic and 4.084(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.434
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.301

    - Propagation time:                      8.457
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.156

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[1\] / Q
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\] / D
    The start point is clocked by            GW_CLKDIV|fclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|fclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                                Pin      Pin               Arrival     No. of    
Name                                                                                                                            Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[1\]           DFFC          Q        Out     0.367     0.367       -         
c_status_fast[1]                                                                                                                Net           -        -       1.021     -           3         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          I1       In      -         1.388       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          F        Out     1.099     2.487       -         
G_8_0_sn_sx                                                                                                                     Net           -        -       1.021     -           2         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_1_cZ                                                                           LUT4          I1       In      -         3.508       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_1_cZ                                                                           LUT4          F        Out     1.099     4.607       -         
G_8_0_mb_N_4L5_1_1                                                                                                              Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     I1       In      -         4.607       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     O        Out     0.150     4.757       -         
G_8_0_mb_1                                                                                                                      Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          I0       In      -         5.778       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          F        Out     1.032     6.810       -         
G_8_0_mb                                                                                                                        Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          I3       In      -         7.831       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          F        Out     0.626     8.457       -         
n_status_7[0]                                                                                                                   Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]                DFFNCE        D        In      -         8.457       -         
===============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.590 is 4.506(52.5%) logic and 4.084(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.434
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.301

    - Propagation time:                      8.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.089

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_0_rep1 / Q
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\] / D
    The start point is clocked by            GW_CLKDIV|fclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|fclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                                Pin      Pin               Arrival     No. of    
Name                                                                                                                            Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_0_rep1              DFFC          Q        Out     0.367     0.367       -         
c_status_0_rep1                                                                                                                 Net           -        -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          I0       In      -         1.388       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          F        Out     1.032     2.420       -         
G_8_0_sn_sx                                                                                                                     Net           -        -       1.021     -           2         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          I1       In      -         3.441       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          F        Out     1.099     4.540       -         
G_8_0_mb_N_4L5_1_0                                                                                                              Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     I0       In      -         4.540       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     O        Out     0.150     4.690       -         
G_8_0_mb_1                                                                                                                      Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          I0       In      -         5.711       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          F        Out     1.032     6.743       -         
G_8_0_mb                                                                                                                        Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          I3       In      -         7.764       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          F        Out     0.626     8.390       -         
n_status_7[0]                                                                                                                   Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]                DFFNCE        D        In      -         8.390       -         
===============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.523 is 4.439(52.1%) logic and 4.084(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.434
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.301

    - Propagation time:                      8.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.089

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[0\] / Q
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\] / D
    The start point is clocked by            GW_CLKDIV|fclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|fclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                                Pin      Pin               Arrival     No. of    
Name                                                                                                                            Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_fast\[0\]           DFFC          Q        Out     0.367     0.367       -         
c_status_fast[0]                                                                                                                Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_2L1_1_cZ                                                                             LUT4          I1       In      -         1.388       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_2L1_1_cZ                                                                             LUT4          F        Out     1.099     2.487       -         
G_8_0_mb_N_2L1_1                                                                                                                Net           -        -       1.021     -           2         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          I0       In      -         3.508       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_0_cZ                                                                           LUT4          F        Out     1.032     4.540       -         
G_8_0_mb_N_4L5_1_0                                                                                                              Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     I0       In      -         4.540       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     O        Out     0.150     4.690       -         
G_8_0_mb_1                                                                                                                      Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          I0       In      -         5.711       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          F        Out     1.032     6.743       -         
G_8_0_mb                                                                                                                        Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          I3       In      -         7.764       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          F        Out     0.626     8.390       -         
n_status_7[0]                                                                                                                   Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]                DFFNCE        D        In      -         8.390       -         
===============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.523 is 4.439(52.1%) logic and 4.084(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.434
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.301

    - Propagation time:                      8.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.089

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_0_rep1 / Q
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\] / D
    The start point is clocked by            GW_CLKDIV|fclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|fclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                                Pin      Pin               Arrival     No. of    
Name                                                                                                                            Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.c_status_0_rep1              DFFC          Q        Out     0.367     0.367       -         
c_status_0_rep1                                                                                                                 Net           -        -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          I0       In      -         1.388       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_sn_sx_cZ                                                                                  LUT4          F        Out     1.032     2.420       -         
G_8_0_sn_sx                                                                                                                     Net           -        -       1.021     -           2         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_1_cZ                                                                           LUT4          I1       In      -         3.441       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1_1_cZ                                                                           LUT4          F        Out     1.099     4.540       -         
G_8_0_mb_N_4L5_1_1                                                                                                              Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     I1       In      -         4.540       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_N_4L5_1                                                                                MUX2_LUT5     O        Out     0.150     4.690       -         
G_8_0_mb_1                                                                                                                      Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          I0       In      -         5.711       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_8_0_mb_cZ                                                                                     LUT4          F        Out     1.032     6.743       -         
G_8_0_mb                                                                                                                        Net           -        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          I3       In      -         7.764       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status_7_2_0_\.m12_0_0     LUT4          F        Out     0.626     8.390       -         
n_status_7[0]                                                                                                                   Net           -        -       0.000     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.\\genblk1\.n_status\[0\]                DFFNCE        D        In      -         8.390       -         
===============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.523 is 4.439(52.1%) logic and 4.084(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                              Starting                                                                  Arrival           
Instance                                      Reference     Type     Pin                      Net                       Time        Slack 
                                              Clock                                                                                       
------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[11]     apbtargexp2_paddr[11]     0.000       -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[8]      apbtargexp2_paddr[8]      0.000       -1.000
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PWRITE        apbtargexp2_pwrite        0.000       -0.945
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PENABLE       apbtargexp2_penable       0.000       -0.878
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[10]     apbtargexp2_paddr[10]     0.000       -0.794
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PSEL          apbtargexp2_psel          0.000       -0.790
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[2]      apbtargexp2_paddr[2]      0.000       -0.751
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[9]      apbtargexp2_paddr[9]      0.000       0.709 
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[5]      apbtargexp2_paddr[5]      0.000       0.724 
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[4]      apbtargexp2_paddr[4]      0.000       0.791 
==========================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                 Starting                                                                    Required           
Instance                                                                                         Reference     Type     Pin                       Net                        Time         Slack 
                                                                                                 Clock                                                                                          
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[8]      apbtargexp2_prdata[8]      6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[9]      apbtargexp2_prdata[9]      6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[10]     apbtargexp2_prdata[10]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[11]     apbtargexp2_prdata[11]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[12]     apbtargexp2_prdata[12]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[13]     apbtargexp2_prdata[13]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[14]     apbtargexp2_prdata[14]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[15]     apbtargexp2_prdata[15]     6.046        -1.067
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.N_247_i_cZ     System        INV      I                         N_247                      6.046        -0.945
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                        System        MCU      APBTARGEXP2PRDATA[0]      apbtargexp2_prdata[0]      6.046        -0.862
================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.046
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.046

    - Propagation time:                      7.114
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.067

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[8]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                 Pin                      Pin               Arrival     No. of    
Name                                                                                                  Type     Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                             MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                 Net      -                        -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                             LUT3     I1                       In      -         1.021       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                             LUT3     F                        Out     1.099     2.120       -         
G_11_1                                                                                                Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                  LUT4     I0                       In      -         2.886       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                  LUT4     F                        Out     1.032     3.918       -         
\\u_gw_peripherals_interconnect\.u_gw_cmsdk_apb2_adc\.read_enable                                     Net      -                        -       1.143     -           25        
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[8\]     LUT2     I0                       In      -         5.061       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[8\]     LUT2     F                        Out     1.032     6.093       -         
apbtargexp2_prdata[8]                                                                                 Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                             MCU      APBTARGEXP2PRDATA[8]     In      -         7.114       -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 7.114 is 3.163(44.5%) logic and 3.951(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.046
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.046

    - Propagation time:                      7.114
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.067

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[9]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                 Pin                      Pin               Arrival     No. of    
Name                                                                                                  Type     Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                             MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                 Net      -                        -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                             LUT3     I1                       In      -         1.021       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                             LUT3     F                        Out     1.099     2.120       -         
G_11_1                                                                                                Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                  LUT4     I0                       In      -         2.886       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                  LUT4     F                        Out     1.032     3.918       -         
\\u_gw_peripherals_interconnect\.u_gw_cmsdk_apb2_adc\.read_enable                                     Net      -                        -       1.143     -           25        
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[9\]     LUT2     I0                       In      -         5.061       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[9\]     LUT2     F                        Out     1.032     6.093       -         
apbtargexp2_prdata[9]                                                                                 Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                             MCU      APBTARGEXP2PRDATA[9]     In      -         7.114       -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 7.114 is 3.163(44.5%) logic and 3.951(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.046
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.046

    - Propagation time:                      7.114
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.067

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[10]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                  Pin                       Pin               Arrival     No. of    
Name                                                                                                   Type     Name                      Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PADDR[11]      Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                  Net      -                         -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     I1                        In      -         1.021       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     F                         Out     1.099     2.120       -         
G_11_1                                                                                                 Net      -                         -       0.766     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     I0                        In      -         2.886       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     F                         Out     1.032     3.918       -         
\\u_gw_peripherals_interconnect\.u_gw_cmsdk_apb2_adc\.read_enable                                      Net      -                         -       1.143     -           25        
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[10\]     LUT2     I0                        In      -         5.061       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[10\]     LUT2     F                         Out     1.032     6.093       -         
apbtargexp2_prdata[10]                                                                                 Net      -                         -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PRDATA[10]     In      -         7.114       -         
==================================================================================================================================================================================
Total path delay (propagation time + setup) of 7.114 is 3.163(44.5%) logic and 3.951(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.046
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.046

    - Propagation time:                      7.114
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.067

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[11]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                  Pin                       Pin               Arrival     No. of    
Name                                                                                                   Type     Name                      Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PADDR[11]      Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                  Net      -                         -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     I1                        In      -         1.021       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     F                         Out     1.099     2.120       -         
G_11_1                                                                                                 Net      -                         -       0.766     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     I0                        In      -         2.886       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     F                         Out     1.032     3.918       -         
\\u_gw_peripherals_interconnect\.u_gw_cmsdk_apb2_adc\.read_enable                                      Net      -                         -       1.143     -           25        
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[11\]     LUT2     I0                        In      -         5.061       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[11\]     LUT2     F                         Out     1.032     6.093       -         
apbtargexp2_prdata[11]                                                                                 Net      -                         -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PRDATA[11]     In      -         7.114       -         
==================================================================================================================================================================================
Total path delay (propagation time + setup) of 7.114 is 3.163(44.5%) logic and 3.951(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.046
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.046

    - Propagation time:                      7.114
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.067

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[12]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                  Pin                       Pin               Arrival     No. of    
Name                                                                                                   Type     Name                      Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PADDR[11]      Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                  Net      -                         -       1.021     -           4         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     I1                        In      -         1.021       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11_1_cZ                                                              LUT3     F                         Out     1.099     2.120       -         
G_11_1                                                                                                 Net      -                         -       0.766     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     I0                        In      -         2.886       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.G_11                                                                   LUT4     F                         Out     1.032     3.918       -         
\\u_gw_peripherals_interconnect\.u_gw_cmsdk_apb2_adc\.read_enable                                      Net      -                         -       1.143     -           25        
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[12\]     LUT2     I0                        In      -         5.061       -         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.\\PRDATA_1\[12\]     LUT2     F                         Out     1.032     6.093       -         
apbtargexp2_prdata[12]                                                                                 Net      -                         -       1.021     -           1         
Gowin_EMPU_inst.Gowin_EMPU_inst.u_mcu_top                                                              MCU      APBTARGEXP2PRDATA[12]     In      -         7.114       -         
==================================================================================================================================================================================
Total path delay (propagation time + setup) of 7.114 is 3.163(44.5%) logic and 3.951(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 194MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 194MB)

---------------------------------------
Resource Usage Report for ledtest_top 

Mapping to part: gw1ns_2clqfp144-6
Cell usage:
ADC             1 use
ALU             5 uses
CLKDIV          1 use
DFFC            60 uses
DFFCE           78 uses
DFFNCE          3 uses
DFFP            1 use
DFFPE           1 use
DLC             1 use
DQCE            1 use
FLASH128K       1 use
GSR             2 uses
INV             23 uses
MCU             1 use
MUX2_LUT5       2 uses
SP              4 uses
LUT2            45 uses
LUT3            43 uses
LUT4            104 uses

I/O ports: 18
I/O primitives: 18
IBUF           2 uses
IOBUF          16 uses

I/O Register bits:                  0
Register bits not including I/Os:   143 of 1296 (11%)

RAM/ROM usage summary
Block Rams : 4 of 4 (100%)

Total load per clock:

@S |Mapping Summary:
Total  LUTs: 192 (11%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 194MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Aug  6 14:29:17 2019

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