#Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018 #install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-HW-023 # Wed Dec 12 18:09:51 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\generic\gw1ns.v" (library work) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v" (library work) @I:"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v":"E:\Demo_program\DK-START-GW1NS2\DK-START-GW1NS2-ledtest\DK-START-GW1NS2-ledtest\src\gowin_empu\temp\gw_empu\config.v" (library work) @I:"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v":"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_name.v" (library work) @W:CG1337 : gowin_empu.v(1329) | Net master_pse11 is not declared. @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v" (library work) Verilog syntax check successful! Selecting top level module Gowin_EMPU Running optimization stage 1 on GSR ....... Running optimization stage 1 on CLKDIV ....... Running optimization stage 1 on GW_CLKDIV ....... Running optimization stage 1 on MCU ....... Running optimization stage 1 on IOBUF ....... Running optimization stage 1 on GW_GPIO ....... Running optimization stage 1 on DQCE ....... Running optimization stage 1 on FLASH128K ....... Running optimization stage 1 on gw_rom_flash_15s_32s ....... Running optimization stage 1 on GW_FLASH ....... Running optimization stage 1 on SP ....... Running optimization stage 1 on GW_SRAM ....... Running optimization stage 1 on gw_cmsdk_apb2_slave_mux_Z1 ....... Running optimization stage 1 on gw_int_apb2_decoder_8s ....... Running optimization stage 1 on ADC ....... Running optimization stage 1 on gw_cmsdk_apb2_adc ....... Running optimization stage 1 on SPI_Z2 ....... Running optimization stage 1 on gw_cmsdk_apb2_spi ....... Running optimization stage 1 on gw_peripherals_interconnect_12s ....... Running optimization stage 1 on \~Gowin_EMPU.Gowin_EMPU ....... @N:CG364 : gowin_empu_top.v(5) | Synthesizing module Gowin_EMPU in library work. Running optimization stage 1 on Gowin_EMPU ....... Running optimization stage 2 on Gowin_EMPU ....... Running optimization stage 2 on \~Gowin_EMPU.Gowin_EMPU ....... Running optimization stage 2 on gw_peripherals_interconnect_12s ....... Running optimization stage 2 on gw_cmsdk_apb2_spi ....... Running optimization stage 2 on SPI_Z2 ....... Running optimization stage 2 on gw_cmsdk_apb2_adc ....... Running optimization stage 2 on ADC ....... Running optimization stage 2 on gw_int_apb2_decoder_8s ....... Running optimization stage 2 on gw_cmsdk_apb2_slave_mux_Z1 ....... Running optimization stage 2 on GW_SRAM ....... Running optimization stage 2 on SP ....... Running optimization stage 2 on GW_FLASH ....... Running optimization stage 2 on gw_rom_flash_15s_32s ....... Running optimization stage 2 on FLASH128K ....... Running optimization stage 2 on DQCE ....... Running optimization stage 2 on GW_GPIO ....... Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on MCU ....... Running optimization stage 2 on GW_CLKDIV ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on GSR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Dec 12 18:09:53 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode @N:NF107 : gowin_empu_top.v(5) | Selected library: work cell: Gowin_EMPU view verilog as top level @N:NF107 : gowin_empu_top.v(5) | Selected library: work cell: Gowin_EMPU view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Dec 12 18:09:53 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Dec 12 18:09:53 2018 ###########################################################]