Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\impl\synthesize\rev_1\DK-START-GW1NS2-ledtest.vm
Physical Constraints File E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW1NS2\DK-START-GW1NS2-ledtest-demo\DK-START-GW1NS2-LED-Blink\src\ledtest.cst
Timing Constraint File ---
GOWIN version V1.9.1Beta
Part Number GW1NS-UX2CLQ144C6/I5
Created Time Tue Aug 06 14:29:23 2019
Legal Announcement Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C
Hold Delay Model Fast 1.26V 0C
Numbers of Paths Analyzed 479
Numbers of Endpoints Analyzed 597
Numbers of Falling Endpoints 6
Numbers of Setup Violated Endpoints 6
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
DEFAULT_CLK Base 10.000 100.000 0.000 5.000

Max Frequency Summary:

NO. Clock Name Fmax Entity
1 DEFAULT_CLK 55.985(MHz) TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
DEFAULT_CLK Setup -11.067 6
DEFAULT_CLK Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -3.931 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 8.469
2 -2.107 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/D DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 6.645
3 -1.336 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 5.874
4 -1.231 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 6.126
5 -1.231 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 6.126
6 -1.231 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[F] 5.000 -0.138 6.126
7 0.399 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CE DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 4.219
8 0.519 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.881
9 0.519 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.881
10 0.706 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.694
11 0.712 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.688
12 0.712 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.688
13 0.736 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.526
14 0.736 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.526
15 0.828 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.434
16 0.895 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.367
17 1.052 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.210
18 1.225 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 3.037
19 1.565 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 7.835
20 1.591 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 7.809
21 1.591 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 7.809
22 1.676 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.081
23 1.676 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 8.081
24 1.764 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 7.636
25 1.878 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/D DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.138 2.384

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.570 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.570
2 0.570 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.570
3 0.571 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.571
4 0.576 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_eoc_Z/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.576
5 0.708 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.708
6 0.710 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.710
7 0.833 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.833
8 0.833 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.833
9 0.833 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[3]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.833
10 0.835 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.835
11 0.868 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.883
12 0.875 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.890
13 0.875 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]/CE DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.890
14 0.892 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.892
15 0.894 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.894
16 0.895 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.895
17 0.905 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.905
18 0.906 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.906
19 0.906 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.906
20 0.937 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.937
21 0.937 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[12]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.937
22 0.937 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[3]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.937
23 0.940 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.940
24 0.942 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[14]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.942
25 0.942 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[13]/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.942

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 6.097 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 3.660
2 6.978 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 2.778
3 6.978 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 2.778
4 7.050 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 10.000 0.000 2.707

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.836 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.851
2 1.839 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.854
3 1.839 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 1.854
4 2.434 Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 2.449

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]
2 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]
3 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]
4 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]
5 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]
6 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]
7 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z
8 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z
9 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]
10 2.378 3.628 1.250 Low Pulse Width DEFAULT_CLK Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -3.931
Data Arrival Time 14.056
Data Required Time 10.126
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK
6.046 0.458 tC2Q RF 6 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q
7.835 1.789 tNET FF 1 R5C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_2L1_1_cZ/I2
8.460 0.625 tINS FR 2 R5C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_2L1_1_cZ/F
8.883 0.423 tNET RR 1 R5C8[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1_0_cZ/I0
9.982 1.099 tINS RF 1 R5C8[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1_0_cZ/F
9.982 0.000 tNET FF 1 R5C8[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1/I0
10.131 0.149 tINS FF 1 R5C8[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1/O
11.594 1.463 tNET FF 1 R5C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_cZ/I0
12.626 1.032 tINS FF 1 R5C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_cZ/F
13.430 0.804 tNET FF 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_0/I3
14.056 0.626 tINS FF 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_0/F
14.056 0.000 tNET FF 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]
10.126 -0.400 tSu 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.531, 41.693%; route: 4.480, 52.895%; tC2Q: 0.458, 5.412%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path2

Path Summary:

Slack -2.107
Data Arrival Time 12.233
Data Required Time 10.126
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
10.975 1.001 tNET FF 1 R7C7[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0_1/I0
11.601 0.626 tINS FF 1 R7C7[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0_1/F
11.607 0.005 tNET FF 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0/I3
12.233 0.626 tINS FF 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0/F
12.233 0.000 tNET FF 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]
10.126 -0.400 tSu 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.383, 50.907%; route: 2.804, 42.196%; tC2Q: 0.458, 6.897%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path3

Path Summary:

Slack -1.336
Data Arrival Time 11.461
Data Required Time 10.126
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/CLK
6.046 0.458 tC2Q RF 3 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q
6.853 0.807 tNET FF 1 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/I0
7.952 1.099 tINS FF 2 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/F
8.298 0.346 tNET FF 1 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I0
9.330 1.032 tINS FF 4 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F
10.639 1.309 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.N_106_i/I1
11.461 0.822 tINS FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.N_106_i/F
11.461 0.000 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
10.126 -0.400 tSu 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 2.953, 50.274%; route: 2.462, 41.923%; tC2Q: 0.458, 7.803%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path4

Path Summary:

Slack -1.231
Data Arrival Time 11.713
Data Required Time 10.482
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK
6.046 0.458 tC2Q RF 6 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q
7.826 1.780 tNET FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/I1
8.858 1.032 tINS FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/F
9.194 0.336 tNET FF 1 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I1
10.255 1.061 tINS FR 3 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F
11.713 1.458 tNET RR 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]
10.482 -0.043 tSu 1 R7C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 2.093, 34.168%; route: 3.574, 58.350%; tC2Q: 0.458, 7.482%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path5

Path Summary:

Slack -1.231
Data Arrival Time 11.713
Data Required Time 10.482
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK
6.046 0.458 tC2Q RF 6 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q
7.826 1.780 tNET FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/I1
8.858 1.032 tINS FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/F
9.194 0.336 tNET FF 1 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I1
10.255 1.061 tINS FR 3 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F
11.713 1.458 tNET RR 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
10.482 -0.043 tSu 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 2.093, 34.168%; route: 3.574, 58.350%; tC2Q: 0.458, 7.482%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path6

Path Summary:

Slack -1.231
Data Arrival Time 11.713
Data Required Time 10.482
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK
6.046 0.458 tC2Q RF 6 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/Q
7.826 1.780 tNET FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/I1
8.858 1.032 tINS FF 1 R5C9[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_1_cZ/F
9.194 0.336 tNET FF 1 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I1
10.255 1.061 tINS FR 3 R5C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F
11.713 1.458 tNET RR 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK
10.526 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]
10.482 -0.043 tSu 1 R7C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]

Path Statistics:

Clock Skew 0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 2.093, 34.168%; route: 3.574, 58.350%; tC2Q: 0.458, 7.482%
Required Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%

Path7

Path Summary:

Slack 0.399
Data Arrival Time 14.945
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FF 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
12.011 0.827 tNET FF 1 R8C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/I2
13.110 1.099 tINS FF 2 R8C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/F
13.604 0.495 tNET FF 1 R8C10[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_reg_trdy9_0/I2
14.229 0.625 tINS FR 1 R8C10[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_reg_trdy9_0/F
14.945 0.715 tNET RR 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy
15.344 -0.043 tSu 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 1.724, 40.860%; route: 2.037, 48.277%; tC2Q: 0.458, 10.863%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path8

Path Summary:

Slack 0.519
Data Arrival Time 14.468
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.195 0.429 tNET RR 1 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0
13.221 1.026 tINS RR 5 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F
13.646 0.425 tNET RR 1 R8C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_axbxc4/I3
14.468 0.822 tINS RF 1 R8C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_axbxc4/F
14.468 0.000 tNET FF 1 R8C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]
14.987 -0.400 tSu 1 R8C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.604, 51.844%; route: 3.818, 42.995%; tC2Q: 0.458, 5.161%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path9

Path Summary:

Slack 0.519
Data Arrival Time 14.468
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.195 0.429 tNET RR 1 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0
13.221 1.026 tINS RR 5 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F
13.646 0.425 tNET RR 1 R9C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[2]/I1
14.468 0.822 tINS RF 1 R9C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[2]/F
14.468 0.000 tNET FF 1 R9C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R9C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]
14.987 -0.400 tSu 1 R9C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.604, 51.844%; route: 3.818, 42.995%; tC2Q: 0.458, 5.161%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path10

Path Summary:

Slack 0.706
Data Arrival Time 14.281
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.195 0.429 tNET RR 1 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0
13.227 1.032 tINS RF 5 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F
13.249 0.022 tNET FF 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/I3
14.281 1.032 tINS FF 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/F
14.281 0.000 tNET FF 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]
14.987 -0.400 tSu 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.820, 55.442%; route: 3.415, 39.286%; tC2Q: 0.458, 5.272%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path11

Path Summary:

Slack 0.712
Data Arrival Time 14.276
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.195 0.429 tNET RR 1 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0
13.221 1.026 tINS RR 5 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F
13.650 0.429 tNET RR 1 R8C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[2]/I1
14.276 0.626 tINS RF 1 R8C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[2]/F
14.276 0.000 tNET FF 1 R8C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]
14.987 -0.400 tSu 1 R8C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.408, 50.734%; route: 3.822, 43.991%; tC2Q: 0.458, 5.275%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path12

Path Summary:

Slack 0.712
Data Arrival Time 14.276
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.195 0.429 tNET RR 1 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0
13.221 1.026 tINS RR 5 R8C8[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F
13.650 0.429 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/I3
14.276 0.626 tINS RF 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/F
14.276 0.000 tNET FF 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]
14.987 -0.400 tSu 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.408, 50.734%; route: 3.822, 43.991%; tC2Q: 0.458, 5.275%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path13

Path Summary:

Slack 0.736
Data Arrival Time 14.252
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FR 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
11.609 0.426 tNET RR 1 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I2
12.641 1.032 tINS RF 5 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F
13.153 0.511 tNET FF 1 R10C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[4]/I0
14.252 1.099 tINS FF 1 R10C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[4]/F
14.252 0.000 tNET FF 1 R10C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R10C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]
14.987 -0.400 tSu 1 R10C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 2.131, 60.437%; route: 0.937, 26.564%; tC2Q: 0.458, 12.999%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path14

Path Summary:

Slack 0.736
Data Arrival Time 14.252
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FR 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
11.609 0.426 tNET RR 1 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I2
12.641 1.032 tINS RF 5 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F
13.153 0.511 tNET FF 1 R10C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[2]/I0
14.252 1.099 tINS FF 1 R10C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[2]/F
14.252 0.000 tNET FF 1 R10C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R10C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]
14.987 -0.400 tSu 1 R10C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 2.131, 60.437%; route: 0.937, 26.564%; tC2Q: 0.458, 12.999%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path15

Path Summary:

Slack 0.828
Data Arrival Time 14.159
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FR 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
11.609 0.426 tNET RR 1 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I2
12.635 1.026 tINS RR 5 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F
13.060 0.425 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[0]/I0
14.159 1.099 tINS RF 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[0]/F
14.159 0.000 tNET FF 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
14.987 -0.400 tSu 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 2.125, 61.888%; route: 0.850, 24.764%; tC2Q: 0.458, 13.348%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path16

Path Summary:

Slack 0.895
Data Arrival Time 14.092
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FR 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
11.609 0.426 tNET RR 1 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I2
12.635 1.026 tINS RR 5 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F
13.060 0.425 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[1]/I0
14.092 1.032 tINS RF 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[1]/F
14.092 0.000 tNET FF 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]
14.987 -0.400 tSu 1 R8C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 2.058, 61.129%; route: 0.850, 25.257%; tC2Q: 0.458, 13.614%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path17

Path Summary:

Slack 1.052
Data Arrival Time 13.935
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FF 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
12.011 0.827 tNET FF 1 R8C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/I2
13.110 1.099 tINS FF 2 R8C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/F
13.935 0.825 tNET FF 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy
14.987 -0.400 tSu 1 R8C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 1.099, 34.239%; route: 1.652, 51.481%; tC2Q: 0.458, 14.279%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path18

Path Summary:

Slack 1.225
Data Arrival Time 13.762
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FR 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
11.609 0.426 tNET RR 1 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I2
12.641 1.032 tINS RF 5 R8C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F
12.663 0.022 tNET FF 1 R8C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[3]/I0
13.762 1.099 tINS FF 1 R8C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[3]/F
13.762 0.000 tNET FF 1 R8C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]
14.987 -0.400 tSu 1 R8C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 2.131, 70.171%; route: 0.448, 14.737%; tC2Q: 0.458, 15.092%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path19

Path Summary:

Slack 1.565
Data Arrival Time 13.422
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.768 0.626 tINS FF 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.600 0.832 tNET FF 1 R8C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/I0
13.422 0.822 tINS FF 1 R8C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/F
13.422 0.000 tNET FF 1 R8C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]
14.987 -0.400 tSu 1 R8C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.579, 45.682%; route: 3.797, 48.467%; tC2Q: 0.458, 5.850%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path20

Path Summary:

Slack 1.591
Data Arrival Time 13.396
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/CLK
6.046 0.458 tC2Q RF 3 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q
6.853 0.807 tNET FF 1 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/I0
7.952 1.099 tINS FF 2 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/F
8.298 0.346 tNET FF 1 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I0
9.330 1.032 tINS FF 4 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F
10.639 1.309 tNET FF 1 R7C7[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1
11.461 0.822 tINS FF 6 R7C7[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F
12.297 0.836 tNET FF 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/I3
13.396 1.099 tINS FF 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/F
13.396 0.000 tNET FF 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]
14.987 -0.400 tSu 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.052, 51.892%; route: 3.298, 42.239%; tC2Q: 0.458, 5.870%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path21

Path Summary:

Slack 1.591
Data Arrival Time 13.396
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/CLK
6.046 0.458 tC2Q RF 3 R7C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[1]/Q
6.853 0.807 tNET FF 1 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/I0
7.952 1.099 tINS FF 2 R7C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_x2_0/F
8.298 0.346 tNET FF 1 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I0
9.330 1.032 tINS FF 4 R7C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F
10.639 1.309 tNET FF 1 R7C7[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1
11.461 0.822 tINS FF 6 R7C7[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F
12.297 0.836 tNET FF 1 R8C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[1]/I3
13.396 1.099 tINS FF 1 R8C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[1]/F
13.396 0.000 tNET FF 1 R8C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]
14.987 -0.400 tSu 1 R8C8[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 4.052, 51.892%; route: 3.298, 42.239%; tC2Q: 0.458, 5.870%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path22

Path Summary:

Slack 1.676
Data Arrival Time 13.668
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.290 1.315 tNET FF 1 R7C6[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/I0
11.916 0.626 tINS FF 2 R7C6[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/F
11.927 0.011 tNET FF 1 R7C6[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_n_status_0_sqmuxa_2_i_0/I1
12.953 1.026 tINS FR 1 R7C6[3][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_n_status_0_sqmuxa_2_i_0/F
13.668 0.715 tNET RR 1 R7C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R7C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy
15.344 -0.043 tSu 1 R7C6[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_rrdy

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.783, 46.816%; route: 3.839, 47.512%; tC2Q: 0.458, 5.672%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path23

Path Summary:

Slack 1.676
Data Arrival Time 13.668
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.290 1.315 tNET FF 1 R7C6[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/I0
11.916 0.626 tINS FF 2 R7C6[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/F
11.927 0.011 tNET FF 1 R7C6[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_reg_roe9_i_0/I1
12.953 1.026 tINS FR 1 R7C6[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_reg_roe9_i_0/F
13.668 0.715 tNET RR 1 R7C6[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R7C6[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe
15.344 -0.043 tSu 1 R7C6[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.783, 46.816%; route: 3.839, 47.512%; tC2Q: 0.458, 5.672%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path24

Path Summary:

Slack 1.764
Data Arrival Time 13.223
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK
6.046 0.458 tC2Q RF 5 R8C6[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q
7.838 1.792 tNET FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I1
8.870 1.032 tINS FF 1 R5C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F
8.875 0.005 tNET FF 1 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0
9.974 1.099 tINS FF 8 R5C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F
11.142 1.167 tNET FF 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2
11.767 0.625 tINS FR 5 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F
12.191 0.425 tNET RR 1 R8C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[0]/I0
13.223 1.032 tINS RF 1 R8C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[0]/F
13.223 0.000 tNET FF 1 R8C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]
14.987 -0.400 tSu 1 R8C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 3.788, 49.608%; route: 3.390, 44.389%; tC2Q: 0.458, 6.002%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path25

Path Summary:

Slack 1.878
Data Arrival Time 13.110
Data Required Time 14.987
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF 1 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK
11.184 0.458 tC2Q FF 5 R7C7[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/Q
12.011 0.827 tNET FF 1 R8C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_92_i_cZ/I2
13.110 1.099 tINS FF 1 R8C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_92_i_cZ/F
13.110 0.000 tNET FF 1 R8C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R8C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag
14.987 -0.400 tSu 1 R8C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag

Path Statistics:

Clock Skew -0.138
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 1.296, 22.636%; route: 4.429, 77.364%
Arrival Data Path Delay cell: 1.099, 46.092%; route: 0.827, 34.685%; tC2Q: 0.458, 19.222%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.570
Data Arrival Time 4.923
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/CLK
4.686 0.333 tC2Q RR 1 R9C9[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/Q
4.923 0.236 tNET RR 1 R9C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]
4.353 0.000 tHld 1 R9C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path2

Path Summary:

Slack 0.570
Data Arrival Time 4.923
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C10[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/CLK
4.686 0.333 tC2Q RR 1 R10C10[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/Q
4.923 0.236 tNET RR 1 R10C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]
4.353 0.000 tHld 1 R10C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path3

Path Summary:

Slack 0.571
Data Arrival Time 4.924
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/CLK
4.686 0.333 tC2Q RR 2 R9C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q
4.924 0.238 tNET RR 1 R9C12[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C12[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]
4.353 0.000 tHld 1 R9C12[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path4

Path Summary:

Slack 0.576
Data Arrival Time 4.929
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_eoc_Z
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C13[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_eoc_Z/CLK
4.686 0.333 tC2Q RR 2 R8C13[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_eoc_Z/Q
4.929 0.243 tNET RR 1 R8C13[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C13[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z
4.353 0.000 tHld 1 R8C13[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg2_eoc_Z

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path5

Path Summary:

Slack 0.708
Data Arrival Time 5.061
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/CLK
4.686 0.333 tC2Q RR 4 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/Q
4.689 0.002 tNET RR 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_m6_cZ_cZ/I2
5.061 0.372 tINS RF 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_m6_cZ_cZ/F
5.061 0.000 tNET FF 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]
4.353 0.000 tHld 1 R9C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path6

Path Summary:

Slack 0.710
Data Arrival Time 5.063
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/CLK
4.686 0.333 tC2Q RR 5 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/Q
4.691 0.005 tNET RR 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/I1
5.063 0.372 tINS RF 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/F
5.063 0.000 tNET FF 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]
4.353 0.000 tHld 1 R8C8[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path7

Path Summary:

Slack 0.833
Data Arrival Time 5.187
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/CLK
4.686 0.333 tC2Q RR 1 R9C8[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/Q
5.187 0.500 tNET RR 1 R9C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]
4.353 0.000 tHld 1 R9C9[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path8

Path Summary:

Slack 0.833
Data Arrival Time 5.187
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/CLK
4.686 0.333 tC2Q RR 1 R9C8[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/Q
5.187 0.500 tNET RR 1 R9C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]
4.353 0.000 tHld 1 R9C9[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path9

Path Summary:

Slack 0.833
Data Arrival Time 5.187
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[3]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C11[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[3]/CLK
4.686 0.333 tC2Q RR 1 R8C11[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[3]/Q
5.187 0.500 tNET RR 1 R8C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]
4.353 0.000 tHld 1 R8C10[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path10

Path Summary:

Slack 0.835
Data Arrival Time 5.188
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/CLK
4.686 0.333 tC2Q RR 2 R9C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q
5.188 0.501 tNET RR 1 R8C12[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C12[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]
4.353 0.000 tHld 1 R8C12[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path11

Path Summary:

Slack 0.868
Data Arrival Time 5.236
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/CLK
4.686 0.333 tC2Q RR 9 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q
5.236 0.549 tNET RR 1 R10C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]
4.368 0.015 tHld 1 R10C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.549, 62.242%; tC2Q: 0.333, 37.758%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path12

Path Summary:

Slack 0.875
Data Arrival Time 5.243
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/CLK
4.686 0.333 tC2Q RR 9 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q
5.243 0.557 tNET RR 1 R8C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]
4.368 0.015 tHld 1 R8C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.557, 62.560%; tC2Q: 0.333, 37.440%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path13

Path Summary:

Slack 0.875
Data Arrival Time 5.243
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/CLK
4.686 0.333 tC2Q RR 9 R10C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rd_Z/Q
5.243 0.557 tNET RR 1 R8C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]
4.368 0.015 tHld 1 R8C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.557, 62.560%; tC2Q: 0.333, 37.440%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path14

Path Summary:

Slack 0.892
Data Arrival Time 5.245
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK
4.686 0.333 tC2Q RR 3 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/Q
4.689 0.002 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0_fast/I3
5.245 0.556 tINS RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0_fast/F
5.245 0.000 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
4.353 0.000 tHld 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path15

Path Summary:

Slack 0.894
Data Arrival Time 5.247
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK
4.686 0.333 tC2Q RR 5 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/Q
4.691 0.005 tNET RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/I2
5.247 0.556 tINS RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/F
5.247 0.000 tNET RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]
4.353 0.000 tHld 1 R8C8[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path16

Path Summary:

Slack 0.895
Data Arrival Time 5.248
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK
4.686 0.333 tC2Q RR 7 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/Q
4.692 0.006 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/I1
5.248 0.556 tINS RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/F
5.248 0.000 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]
4.353 0.000 tHld 1 R8C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path17

Path Summary:

Slack 0.905
Data Arrival Time 5.258
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/CLK
4.686 0.333 tC2Q RR 2 R7C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/Q
5.258 0.572 tNET RR 1 R8C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]
4.353 0.000 tHld 1 R8C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.572, 63.164%; tC2Q: 0.333, 36.836%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path18

Path Summary:

Slack 0.906
Data Arrival Time 5.259
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C11[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/CLK
4.686 0.333 tC2Q RR 3 R7C11[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/Q
5.259 0.573 tNET RR 1 R9C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R9C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]
4.353 0.000 tHld 1 R9C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.573, 63.212%; tC2Q: 0.333, 36.788%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path19

Path Summary:

Slack 0.906
Data Arrival Time 5.259
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C11[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/CLK
4.686 0.333 tC2Q RR 3 R7C11[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/Q
5.259 0.573 tNET RR 1 R8C13[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C13[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]
4.353 0.000 tHld 1 R8C13[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.573, 63.212%; tC2Q: 0.333, 36.788%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path20

Path Summary:

Slack 0.937
Data Arrival Time 5.290
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/CLK
4.686 0.333 tC2Q RF 3 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q
4.918 0.231 tNET FF 1 R7C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_0_a2[7]/I0
5.290 0.372 tINS FF 1 R7C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_0_a2[7]/F
5.290 0.000 tNET FF 1 R7C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]
4.353 0.000 tHld 1 R7C12[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path21

Path Summary:

Slack 0.937
Data Arrival Time 5.290
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[12]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[12]/CLK
4.686 0.333 tC2Q RF 1 R8C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[12]/Q
4.918 0.231 tNET FF 1 R8C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[12]/I3
5.290 0.372 tINS FF 1 R8C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[12]/F
5.290 0.000 tNET FF 1 R8C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R8C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]
4.353 0.000 tHld 1 R8C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[12]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path22

Path Summary:

Slack 0.937
Data Arrival Time 5.290
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[3]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R5C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[3]/CLK
4.686 0.333 tC2Q RF 1 R5C12[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[3]/Q
4.918 0.231 tNET FF 1 R5C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_0_iv_0[3]/I1
5.290 0.372 tINS FF 1 R5C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_0_iv_0[3]/F
5.290 0.000 tNET FF 1 R5C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R5C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]
4.353 0.000 tHld 1 R5C13[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path23

Path Summary:

Slack 0.940
Data Arrival Time 5.293
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C11[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/CLK
4.686 0.333 tC2Q RF 3 R7C11[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/Q
4.921 0.234 tNET FF 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[6]/I0
5.293 0.372 tINS FF 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[6]/F
5.293 0.000 tNET FF 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]
4.353 0.000 tHld 1 R7C12[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.582%; route: 0.234, 24.950%; tC2Q: 0.333, 35.468%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path24

Path Summary:

Slack 0.942
Data Arrival Time 5.295
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[14]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C14[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[14]/CLK
4.686 0.333 tC2Q RR 1 R7C14[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[14]/Q
4.923 0.236 tNET RR 1 R7C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[14]/I3
5.295 0.372 tINS RF 1 R7C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[14]/F
5.295 0.000 tNET FF 1 R7C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]
4.353 0.000 tHld 1 R7C14[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[14]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path25

Path Summary:

Slack 0.942
Data Arrival Time 5.295
Data Required Time 4.353
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[13]
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C14[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[13]/CLK
4.686 0.333 tC2Q RR 1 R7C14[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[13]/Q
4.923 0.236 tNET RR 1 R7C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[13]/I3
5.295 0.372 tINS RF 1 R7C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_cZ[13]/F
5.295 0.000 tNET FF 1 R7C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]
4.353 0.000 tHld 1 R7C14[1][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[13]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 6.097
Data Arrival Time 9.247
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
6.046 0.458 tC2Q RF 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
6.547 0.501 tNET FF 1 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1
7.579 1.032 tINS FF 3 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F
9.247 1.668 tNET FF 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1
15.344 -0.043 tSu 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 1.032, 28.200%; route: 2.169, 59.276%; tC2Q: 0.458, 12.524%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path2

Path Summary:

Slack 6.978
Data Arrival Time 8.366
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
6.046 0.458 tC2Q RF 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
6.547 0.501 tNET FF 1 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1
7.646 1.099 tINS FF 3 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F
8.366 0.720 tNET FF 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
15.344 -0.043 tSu 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 1.099, 39.556%; route: 1.221, 43.947%; tC2Q: 0.458, 16.497%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path3

Path Summary:

Slack 6.978
Data Arrival Time 8.366
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
6.046 0.458 tC2Q RF 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
6.547 0.501 tNET FF 1 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1
7.646 1.099 tINS FF 3 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F
8.366 0.720 tNET FF 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER
15.344 -0.043 tSu 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 1.099, 39.556%; route: 1.221, 43.947%; tC2Q: 0.458, 16.497%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Path4

Path Summary:

Slack 7.050
Data Arrival Time 8.294
Data Required Time 15.344
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
3.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
3.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
5.587 1.909 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
6.046 0.458 tC2Q RF 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
6.547 0.501 tNET FF 1 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1
7.579 1.032 tINS FF 3 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F
8.294 0.715 tNET FF 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
10.982 0.982 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
13.377 2.395 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
13.678 0.302 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
15.587 1.909 tNET RR 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLK
15.387 -0.200 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast
15.344 -0.043 tSu 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%
Arrival Data Path Delay cell: 1.032, 38.123%; route: 1.217, 44.945%; tC2Q: 0.458, 16.931%
Required Clock Path Delay cell: 1.284, 22.972%; route: 4.304, 77.028%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.836
Data Arrival Time 6.204
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
4.686 0.333 tC2Q RR 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
4.958 0.271 tNET RR 1 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1
5.684 0.726 tINS RR 3 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F
6.204 0.521 tNET RR 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast
4.368 0.015 tHld 1 R5C7[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.726, 39.215%; route: 0.792, 42.780%; tC2Q: 0.333, 18.005%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path2

Path Summary:

Slack 1.839
Data Arrival Time 6.207
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
4.686 0.333 tC2Q RR 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
4.958 0.271 tNET RR 1 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1
5.682 0.724 tINS RR 3 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F
6.207 0.526 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast
4.368 0.015 tHld 1 R7C9[2][A] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.724, 39.051%; route: 0.797, 42.969%; tC2Q: 0.333, 17.979%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path3

Path Summary:

Slack 1.839
Data Arrival Time 6.207
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
4.686 0.333 tC2Q RR 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
4.958 0.271 tNET RR 1 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1
5.682 0.724 tINS RR 3 R7C9[3][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F
6.207 0.526 tNET RR 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER
4.368 0.015 tHld 1 R7C9[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.724, 39.051%; route: 0.797, 42.969%; tC2Q: 0.333, 17.979%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Path4

Path Summary:

Slack 2.434
Data Arrival Time 6.802
Data Required Time 4.368
From Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity
To Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK
4.686 0.333 tC2Q RR 6 R7C7[1][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q
4.958 0.271 tNET RR 1 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1
5.684 0.726 tINS RR 3 R5C7[2][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F
6.802 1.119 tNET RR 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/I
0.844 0.844 tINS RR 1 IOL5[A] Gowin_EMPU_inst/sys_clk_ibuf/O
2.660 1.816 tNET RR 5 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
2.919 0.259 tINS RR 150 RIGHTSIDE[0] Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
4.353 1.434 tNET RR 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLK
4.353 0.000 tUnc Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1
4.368 0.015 tHld 1 R7C10[0][B] Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%
Arrival Data Path Delay cell: 0.726, 29.644%; route: 1.390, 56.746%; tC2Q: 0.333, 13.610%
Required Clock Path Delay cell: 1.104, 25.351%; route: 3.250, 74.649%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]/CLK

MPW2

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]/CLK

MPW3

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]/CLK

MPW4

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]/CLK

MPW5

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]/CLK

MPW6

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]/CLK

MPW7

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z/CLK

MPW8

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/CLK

MPW9

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]/CLK

MPW10

MPW Summary:

Slack: 2.378
Actual Width: 3.628
Required Width: 1.250
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF Gowin_EMPU_inst/sys_clk_ibuf/I
5.984 0.984 tINS FF Gowin_EMPU_inst/sys_clk_ibuf/O
8.461 2.476 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
8.773 0.312 tINS FF Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
10.726 1.953 tNET FF Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR Gowin_EMPU_inst/sys_clk_ibuf/I
10.844 0.844 tINS RR Gowin_EMPU_inst/sys_clk_ibuf/O
12.660 1.816 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN
12.919 0.259 tINS RR Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
14.353 1.434 tNET RR Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
150 fclk -3.931 1.953
12 dw08_cs 4.417 1.318
12 dw04_cs 3.368 1.309
12 c_status[1] -0.414 1.965
11 u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1.c_status[2] -0.091 1.639
10 c_status[0] -0.709 1.327
9 reg_rd 4.686 1.325
9 shift_direction 6.614 1.296
9 dw10_cs 4.628 1.312
9 N_328 4.843 0.852

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R7C8 0.583
R15C2 0.583
R14C1 0.528
R7C7 0.514
R12C1 0.514
R15C3 0.486
R8C7 0.458
R7C9 0.458
R9C9 0.417
R8C9 0.403

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command