Project Settings
Project Name DK-START-GW1NS2-ledtest Device Name rev_1: GOWIN-GW1NSR : GW1NSR_2C
Implementation Name rev_1 Top Module ledtest_top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 9 1 0 - 00m:00s - 2018/12/20
16:39:07
Premap Up-to-date
Map & Optimize Up-to-date

Area Summary
I/O ports (io_port) 18 Non I/O Register bits (non_io_reg) 143 (11%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 4 (4)
LUTs (total_luts) 192 (11%)

Timing Summary
Clock NameReq FreqEst FreqSlack
GW_CLKDIV|fclk_inferred_clock112.8 MHz58.2 MHz-4.156
SPI_Z2|N_88_i_inferred_clock100.0 MHzNANA
System165.4 MHz140.6 MHz-1.067

Optimizations Summary
Combined Clock Conversion 0 / 2