Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\Demo_program\DK-START-GW1NSR2\DK-START-GW1NSR2-ledtest\DK-START-GW1NSR2-ledtest\impl\synthesize\rev_1\DK-START-GW1NS2-ledtest.vm |
Physical Constraints File | E:\Demo_program\DK-START-GW1NSR2\DK-START-GW1NSR2-ledtest\DK-START-GW1NSR2-ledtest\src\DK-START-GW1NS2-ledtest.cst |
Timing Constraint File | --- |
Command Line | D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\Pnr\bin\gowin.exe -do E:\Demo_program\DK-START-GW1NSR2\DK-START-GW1NSR2-ledtest\DK-START-GW1NSR2-ledtest\impl\pnr\cmd.do |
GOWIN version | v1.8.3.01Beta |
Part Number | GW1NSR-LX2CQN48PES |
Created Time | Thu Dec 20 16:40:12 2018 |
Legal Announcement | Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 479 |
Numbers of Endpoints Analyzed | 597 |
Numbers of Falling Endpoints | 6 |
Numbers of Setup Violated Endpoints | 8 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 59.358(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | -9.412 | 8 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -3.423 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 7.918 |
2 | -2.300 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 6.794 |
3 | -1.230 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 5.724 |
4 | -0.972 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 5.278 |
5 | -0.946 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CE | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 5.609 |
6 | -0.364 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 4.670 |
7 | -0.136 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 4.442 |
8 | -0.039 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 4.345 |
9 | 0.270 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 4.036 |
10 | 0.324 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 4.526 |
11 | 0.522 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 3.784 |
12 | 0.692 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 4.159 |
13 | 0.692 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[F] | 5.000 | -0.094 | 4.159 |
14 | 0.806 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.594 |
15 | 1.009 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.391 |
16 | 1.025 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.375 |
17 | 1.316 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.084 |
18 | 1.411 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.989 |
19 | 1.411 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.989 |
20 | 1.495 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 2.811 |
21 | 1.495 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 2.811 |
22 | 1.499 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.901 |
23 | 1.504 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2]/D | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.094 | 2.801 |
24 | 1.800 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.600 |
25 | 2.068 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.688 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.570 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
2 | 0.570 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
3 | 0.570 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[4]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
4 | 0.570 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
5 | 0.709 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709 |
6 | 0.710 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710 |
7 | 0.833 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.833 |
8 | 0.835 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.835 |
9 | 0.840 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.840 |
10 | 0.840 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.840 |
11 | 0.894 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.894 |
12 | 0.905 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.905 |
13 | 0.940 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.pending_data/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.940 |
14 | 0.940 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[2]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.940 |
15 | 0.943 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.943 |
16 | 0.943 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.943 |
17 | 0.944 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.944 |
18 | 0.946 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw10_cs_Z/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.946 |
19 | 0.949 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.949 |
20 | 0.949 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.949 |
21 | 0.964 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.964 |
22 | 1.060 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.060 |
23 | 1.061 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.061 |
24 | 1.062 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.062 |
25 | 1.062 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.062 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.819 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.938 |
2 | 6.618 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.139 |
3 | 6.978 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.779 |
4 | 6.978 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.779 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.828 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.843 |
2 | 1.828 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.843 |
3 | 1.957 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.972 |
4 | 2.526 | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.541 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12] |
2 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14] |
3 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3] |
4 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11] |
5 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11] |
6 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3] |
7 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z |
8 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z |
9 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2] |
10 | 2.897 | 4.147 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -3.423 |
Data Arrival Time | 11.596 |
Data Required Time | 8.173 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK |
4.137 | 0.458 | tC2Q | RF | 4 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/Q |
5.438 | 1.301 | tNET | FF | 1 | R7C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_o2_2/I1 |
6.260 | 0.822 | tINS | FF | 3 | R7C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER4_i_o2_2/F |
7.075 | 0.815 | tNET | FF | 1 | R8C6[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1/S0 |
7.512 | 0.437 | tINS | FF | 1 | R8C6[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_N_4L5_1/O |
8.975 | 1.463 | tNET | FF | 1 | R8C6[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_cZ/I0 |
10.007 | 1.032 | tINS | FF | 1 | R8C6[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_8_0_mb_cZ/F |
10.497 | 0.490 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_0/I3 |
11.596 | 1.099 | tINS | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_0/F |
11.596 | 0.000 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] | |||
8.173 | -0.400 | tSu | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.390, 42.816%; route: 4.069, 51.395%; tC2Q: 0.458, 5.789% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path2
Path Summary:
Slack | -2.300 |
Data Arrival Time | 10.473 |
Data Required Time | 8.173 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/Q |
4.956 | 0.819 | tNET | FF | 1 | R7C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_a2_2_d_0_sn_sx/I0 |
6.055 | 1.099 | tINS | FF | 1 | R7C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_a2_2_d_0_sn_sx/F |
6.876 | 0.821 | tNET | FF | 1 | R7C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_a2_2_d_0_sn/I3 |
7.902 | 1.026 | tINS | FR | 2 | R7C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_a2_2_d_0_sn/F |
8.325 | 0.423 | tNET | RR | 1 | R7C8[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0_1/I2 |
9.357 | 1.032 | tINS | RF | 1 | R7C8[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0_1/F |
9.847 | 0.490 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0/I3 |
10.473 | 0.626 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m17_0_0/F |
10.473 | 0.000 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] | |||
8.173 | -0.400 | tSu | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.783, 55.678%; route: 2.553, 37.576%; tC2Q: 0.458, 6.746% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path3
Path Summary:
Slack | -1.230 |
Data Arrival Time | 9.402 |
Data Required Time | 8.173 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
8.776 | 1.475 | tNET | FF | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.N_106_i/I1 |
9.402 | 0.626 | tINS | FF | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.N_106_i/F |
9.402 | 0.000 | tNET | FF | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] | |||
8.173 | -0.400 | tSu | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 2.480, 43.328%; route: 2.785, 48.665%; tC2Q: 0.458, 8.008% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path4
Path Summary:
Slack | -0.972 |
Data Arrival Time | 14.051 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
10.695 | 1.464 | tNET | FF | 1 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I3 |
11.794 | 1.099 | tINS | FF | 5 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F |
12.952 | 1.157 | tNET | FF | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[0]/I0 |
14.051 | 1.099 | tINS | FF | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[0]/F |
14.051 | 0.000 | tNET | FF | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0] | |||
13.078 | -0.400 | tSu | 1 | R10C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[0] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 2.198, 41.643%; route: 2.622, 49.673%; tC2Q: 0.458, 8.684% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path5
Path Summary:
Slack | -0.946 |
Data Arrival Time | 14.381 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
11.030 | 1.799 | tNET | FF | 1 | R7C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/I3 |
12.062 | 1.032 | tINS | FF | 2 | R7C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/F |
13.041 | 0.979 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_reg_trdy9_0/I2 |
13.666 | 0.625 | tINS | FR | 1 | R7C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_reg_trdy9_0/F |
14.381 | 0.715 | tNET | RR | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy | |||
13.435 | -0.043 | tSu | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.657, 29.542%; route: 3.494, 62.286%; tC2Q: 0.458, 8.171% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path6
Path Summary:
Slack | -0.364 |
Data Arrival Time | 13.443 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
10.695 | 1.464 | tNET | FF | 1 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I3 |
11.794 | 1.099 | tINS | FF | 5 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F |
12.621 | 0.827 | tNET | FF | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[3]/I0 |
13.443 | 0.822 | tINS | FF | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[3]/F |
13.443 | 0.000 | tNET | FF | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] | |||
13.078 | -0.400 | tSu | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.921, 41.132%; route: 2.291, 49.054%; tC2Q: 0.458, 9.814% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path7
Path Summary:
Slack | -0.136 |
Data Arrival Time | 13.215 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
10.695 | 1.464 | tNET | FF | 1 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I3 |
11.756 | 1.061 | tINS | FR | 5 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F |
12.183 | 0.427 | tNET | RR | 1 | R9C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[4]/I0 |
13.215 | 1.032 | tINS | RF | 1 | R9C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[4]/F |
13.215 | 0.000 | tNET | FF | 1 | R9C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4] | |||
13.078 | -0.400 | tSu | 1 | R9C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[4] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 2.093, 47.114%; route: 1.891, 42.569%; tC2Q: 0.458, 10.317% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path8
Path Summary:
Slack | -0.039 |
Data Arrival Time | 13.117 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
10.695 | 1.464 | tNET | FF | 1 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I3 |
11.794 | 1.099 | tINS | FF | 5 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F |
12.295 | 0.501 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[2]/I0 |
13.117 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[2]/F |
13.117 | 0.000 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R8C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2] | |||
13.078 | -0.400 | tSu | 1 | R8C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[2] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.921, 44.215%; route: 1.965, 45.236%; tC2Q: 0.458, 10.549% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path9
Path Summary:
Slack | 0.270 |
Data Arrival Time | 12.809 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
10.695 | 1.464 | tNET | FF | 1 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/I3 |
11.756 | 1.061 | tINS | FR | 5 | R8C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt14_0/F |
12.183 | 0.427 | tNET | RR | 1 | R8C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[1]/I0 |
12.809 | 0.626 | tINS | RF | 1 | R8C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt_lm_0[1]/F |
12.809 | 0.000 | tNET | FF | 1 | R8C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R8C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1] | |||
13.078 | -0.400 | tSu | 1 | R8C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[1] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.687, 41.794%; route: 1.891, 46.851%; tC2Q: 0.458, 11.355% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path10
Path Summary:
Slack | 0.324 |
Data Arrival Time | 8.205 |
Data Required Time | 8.529 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/CLK |
4.137 | 0.458 | tC2Q | RF | 2 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q |
4.956 | 0.819 | tNET | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/I0 |
6.055 | 1.099 | tINS | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/F |
6.061 | 0.005 | tNET | FF | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I2 |
7.087 | 1.026 | tINS | FR | 3 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F |
8.205 | 1.118 | tNET | RR | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] | |||
8.529 | -0.043 | tSu | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 2.125, 46.948%; route: 1.943, 42.926%; tC2Q: 0.458, 10.126% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path11
Path Summary:
Slack | 0.522 |
Data Arrival Time | 12.557 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
11.030 | 1.799 | tNET | FF | 1 | R7C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/I3 |
12.062 | 1.032 | tINS | FF | 2 | R7C7[3][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy9_0_a2/F |
12.557 | 0.495 | tNET | FF | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy | |||
13.078 | -0.400 | tSu | 1 | R7C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_trdy |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.032, 27.272%; route: 2.294, 60.616%; tC2Q: 0.458, 12.112% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path12
Path Summary:
Slack | 0.692 |
Data Arrival Time | 7.837 |
Data Required Time | 8.529 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/CLK |
4.137 | 0.458 | tC2Q | RF | 2 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q |
4.956 | 0.819 | tNET | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/I0 |
6.055 | 1.099 | tINS | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/F |
6.061 | 0.005 | tNET | FF | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I2 |
7.087 | 1.026 | tINS | FR | 3 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F |
7.837 | 0.750 | tNET | RR | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] | |||
8.529 | -0.043 | tSu | 1 | R8C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[1] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 2.125, 51.097%; route: 1.575, 37.882%; tC2Q: 0.458, 11.021% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path13
Path Summary:
Slack | 0.692 |
Data Arrival Time | 7.837 |
Data Required Time | 8.529 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/CLK |
4.137 | 0.458 | tC2Q | RF | 2 | R8C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_Z[0]/Q |
4.956 | 0.819 | tNET | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/I0 |
6.055 | 1.099 | tINS | FF | 1 | R9C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0_a3_2_cZ/F |
6.061 | 0.005 | tNET | FF | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/I2 |
7.087 | 1.026 | tINS | FR | 3 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/m14_i_0/F |
7.837 | 0.750 | tNET | RR | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK |
8.573 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] | |||
8.529 | -0.043 | tSu | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
Path Statistics:
Clock Skew | 0.094 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 2.125, 51.097%; route: 1.575, 37.882%; tC2Q: 0.458, 11.021% |
Required Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Path14
Path Summary:
Slack | 0.806 |
Data Arrival Time | 12.273 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
9.587 | 2.285 | tNET | FF | 1 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1 |
10.619 | 1.032 | tINS | FF | 6 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F |
11.451 | 0.832 | tNET | FF | 1 | R8C9[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[1]/I3 |
12.273 | 0.822 | tINS | FF | 1 | R8C9[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[1]/F |
12.273 | 0.000 | tNET | FF | 1 | R8C9[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R8C9[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1] | |||
13.078 | -0.400 | tSu | 1 | R8C9[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.708, 43.144%; route: 4.428, 51.523%; tC2Q: 0.458, 5.333% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path15
Path Summary:
Slack | 1.009 |
Data Arrival Time | 12.070 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q |
5.127 | 0.990 | tNET | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I3 |
6.226 | 1.099 | tINS | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F |
6.231 | 0.005 | tNET | FF | 1 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0 |
7.330 | 1.099 | tINS | FF | 8 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F |
8.173 | 0.842 | tNET | FF | 1 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2 |
8.799 | 0.626 | tINS | FF | 5 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F |
9.300 | 0.501 | tNET | FF | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0 |
9.926 | 0.626 | tINS | FF | 5 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F |
11.248 | 1.322 | tNET | FF | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_axbxc4/I3 |
12.070 | 0.822 | tINS | FF | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_axbxc4/F |
12.070 | 0.000 | tNET | FF | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] | |||
13.078 | -0.400 | tSu | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 4.272, 50.910%; route: 3.661, 43.628%; tC2Q: 0.458, 5.462% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path16
Path Summary:
Slack | 1.025 |
Data Arrival Time | 12.053 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q |
5.127 | 0.990 | tNET | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I3 |
6.226 | 1.099 | tINS | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F |
6.231 | 0.005 | tNET | FF | 1 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0 |
7.330 | 1.099 | tINS | FF | 8 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F |
8.173 | 0.842 | tNET | FF | 1 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2 |
8.799 | 0.626 | tINS | FF | 5 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F |
9.300 | 0.501 | tNET | FF | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0 |
9.926 | 0.626 | tINS | FF | 5 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F |
11.231 | 1.305 | tNET | FF | 1 | R7C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/I3 |
12.053 | 0.822 | tINS | FF | 1 | R7C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[3]/F |
12.053 | 0.000 | tNET | FF | 1 | R7C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3] | |||
13.078 | -0.400 | tSu | 1 | R7C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 4.272, 51.011%; route: 3.644, 43.517%; tC2Q: 0.458, 5.473% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path17
Path Summary:
Slack | 1.316 |
Data Arrival Time | 11.763 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
9.587 | 2.285 | tNET | FF | 1 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1 |
10.619 | 1.032 | tINS | FF | 6 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F |
11.137 | 0.517 | tNET | FF | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/I2 |
11.763 | 0.626 | tINS | FF | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/F |
11.763 | 0.000 | tNET | FF | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] | |||
13.078 | -0.400 | tSu | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.512, 43.443%; route: 4.114, 50.887%; tC2Q: 0.458, 5.670% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path18
Path Summary:
Slack | 1.411 |
Data Arrival Time | 11.668 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
9.587 | 2.285 | tNET | FF | 1 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1 |
10.613 | 1.026 | tINS | FR | 6 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F |
11.042 | 0.429 | tNET | RR | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[0]/I2 |
11.668 | 0.626 | tINS | RF | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[0]/F |
11.668 | 0.000 | tNET | FF | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0] | |||
13.078 | -0.400 | tSu | 1 | R8C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.506, 43.884%; route: 4.025, 50.379%; tC2Q: 0.458, 5.737% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path19
Path Summary:
Slack | 1.411 |
Data Arrival Time | 11.668 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
9.587 | 2.285 | tNET | FF | 1 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1 |
10.613 | 1.026 | tINS | FR | 6 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F |
11.042 | 0.429 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/I3 |
11.668 | 0.626 | tINS | RF | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/F |
11.668 | 0.000 | tNET | FF | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] | |||
13.078 | -0.400 | tSu | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.506, 43.884%; route: 4.025, 50.379%; tC2Q: 0.458, 5.737% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path20
Path Summary:
Slack | 1.495 |
Data Arrival Time | 11.583 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1 |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK |
9.231 | 0.458 | tC2Q | FF | 6 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/Q |
11.583 | 2.352 | tNET | FF | 1 | R7C6[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C6[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1 | |||
13.078 | -0.400 | tSu | 1 | R7C6[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_0_rep1 |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.352, 83.694%; tC2Q: 0.458, 16.306% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path21
Path Summary:
Slack | 1.495 |
Data Arrival Time | 11.583 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/CLK |
9.231 | 0.458 | tC2Q | FF | 6 | R8C8[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[0]/Q |
10.551 | 1.320 | tNET | FF | 1 | R7C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_92_i_cZ/I1 |
11.583 | 1.032 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_92_i_cZ/F |
11.583 | 0.000 | tNET | FF | 1 | R7C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag | |||
13.078 | -0.400 | tSu | 1 | R7C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_latch_flag |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 1.032, 36.716%; route: 1.320, 46.977%; tC2Q: 0.458, 16.306% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path22
Path Summary:
Slack | 1.499 |
Data Arrival Time | 11.580 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q |
5.127 | 0.990 | tNET | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I3 |
6.226 | 1.099 | tINS | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F |
6.231 | 0.005 | tNET | FF | 1 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0 |
7.330 | 1.099 | tINS | FF | 8 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F |
8.173 | 0.842 | tNET | FF | 1 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/I2 |
8.799 | 0.626 | tINS | FF | 5 | R8C9[0][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_n_status23_3_i/F |
9.300 | 0.501 | tNET | FF | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/I0 |
9.926 | 0.626 | tINS | FF | 5 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_genblk1.data_cnt_1_ac0_1/F |
10.758 | 0.832 | tNET | FF | 1 | R5C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[2]/I1 |
11.580 | 0.822 | tINS | FF | 1 | R5C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[2]/F |
11.580 | 0.000 | tNET | FF | 1 | R5C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R5C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2] | |||
13.078 | -0.400 | tSu | 1 | R5C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 4.272, 54.066%; route: 3.171, 40.134%; tC2Q: 0.458, 5.801% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path23
Path Summary:
Slack | 1.504 |
Data Arrival Time | 11.574 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | 1 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/CLK |
9.231 | 0.458 | tC2Q | FF | 5 | R7C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status[2]/Q |
11.574 | 2.343 | tNET | FF | 1 | R9C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2] | |||
13.078 | -0.400 | tSu | 1 | R9C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.c_status_fast[2] |
Path Statistics:
Clock Skew | -0.094 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.296, 34.355%; route: 2.476, 65.645% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.343, 83.639%; tC2Q: 0.458, 16.361% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path24
Path Summary:
Slack | 1.800 |
Data Arrival Time | 11.278 |
Data Required Time | 13.078 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/CLK |
4.137 | 0.458 | tC2Q | RF | 5 | R5C10[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[4]/Q |
5.437 | 1.300 | tNET | FF | 1 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/I0 |
6.259 | 0.822 | tINS | FF | 3 | R7C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1_0/F |
6.270 | 0.011 | tNET | FF | 1 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/I3 |
7.302 | 1.032 | tINS | FF | 4 | R7C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.n_status_7_2_0_.m12_0_o2_1/F |
9.587 | 2.285 | tNET | FF | 1 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/I1 |
10.619 | 1.032 | tINS | FF | 6 | R7C10[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.un1_data_cnt16_0/F |
10.652 | 0.033 | tNET | FF | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/I2 |
11.278 | 0.626 | tINS | FF | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/F |
11.278 | 0.000 | tNET | FF | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] | |||
13.078 | -0.400 | tSu | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.512, 46.214%; route: 3.629, 47.755%; tC2Q: 0.458, 6.031% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path25
Path Summary:
Slack | 2.068 |
Data Arrival Time | 11.367 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R9C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.clock_cnt[3]/Q |
5.127 | 0.990 | tNET | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/I3 |
6.226 | 1.099 | tINS | FF | 1 | R7C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10_1_1_cZ/F |
6.231 | 0.005 | tNET | FF | 1 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/I0 |
7.330 | 1.099 | tINS | FF | 8 | R7C7[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/G_10/F |
8.155 | 0.824 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/I0 |
8.781 | 0.626 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_sqmuxa_1_i_0_o2/F |
9.591 | 0.810 | tNET | FF | 1 | R7C9[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_reg_roe9_i_0/I1 |
10.652 | 1.061 | tINS | FR | 1 | R7C9[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_reg_roe9_i_0/F |
11.367 | 0.715 | tNET | RR | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe | |||
13.435 | -0.043 | tSu | 1 | R7C9[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_roe |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 3.885, 50.530%; route: 3.345, 43.508%; tC2Q: 0.458, 5.961% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.570 |
Data Arrival Time | 3.489 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C11[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/CLK |
3.252 | 0.333 | tC2Q | RR | 1 | R9C11[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[6]/Q |
3.489 | 0.236 | tNET | RR | 1 | R9C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6] | |||
2.919 | 0.000 | tHld | 1 | R9C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path2
Path Summary:
Slack | 0.570 |
Data Arrival Time | 3.489 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/CLK |
3.252 | 0.333 | tC2Q | RR | 1 | R7C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[5]/Q |
3.489 | 0.236 | tNET | RR | 1 | R7C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5] | |||
2.919 | 0.000 | tHld | 1 | R7C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path3
Path Summary:
Slack | 0.570 |
Data Arrival Time | 3.489 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[4] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C12[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[4]/CLK |
3.252 | 0.333 | tC2Q | RR | 1 | R8C12[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[4]/Q |
3.489 | 0.236 | tNET | RR | 1 | R8C12[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C12[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4] | |||
2.919 | 0.000 | tHld | 1 | R8C12[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path4
Path Summary:
Slack | 0.570 |
Data Arrival Time | 3.489 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/CLK |
3.252 | 0.333 | tC2Q | RR | 1 | R9C10[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[2]/Q |
3.489 | 0.236 | tNET | RR | 1 | R9C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2] | |||
2.919 | 0.000 | tHld | 1 | R9C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path5
Path Summary:
Slack | 0.709 |
Data Arrival Time | 3.628 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/CLK |
3.252 | 0.333 | tC2Q | RR | 7 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/Q |
3.256 | 0.004 | tNET | RR | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O5_0_a2/I2 |
3.628 | 0.372 | tINS | RF | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O5_0_a2/F |
3.628 | 0.000 | tNET | FF | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z | |||
2.919 | 0.000 | tHld | 1 | R9C13[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/SPI_ACK_O_Z |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path6
Path Summary:
Slack | 0.710 |
Data Arrival Time | 3.629 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK |
3.252 | 0.333 | tC2Q | RR | 4 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/Q |
3.257 | 0.005 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0/I2 |
3.629 | 0.372 | tINS | RF | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0/F |
3.629 | 0.000 | tNET | FF | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER | |||
2.919 | 0.000 | tHld | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path7
Path Summary:
Slack | 0.833 |
Data Arrival Time | 3.753 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C12[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/CLK |
3.252 | 0.333 | tC2Q | RR | 1 | R8C12[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[7]/Q |
3.753 | 0.500 | tNET | RR | 1 | R8C11[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C11[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7] | |||
2.919 | 0.000 | tHld | 1 | R8C11[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path8
Path Summary:
Slack | 0.835 |
Data Arrival Time | 3.754 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[2]/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R10C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[2]/Q |
3.754 | 0.501 | tNET | RR | 1 | R10C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2] | |||
2.919 | 0.000 | tHld | 1 | R10C9[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path9
Path Summary:
Slack | 0.840 |
Data Arrival Time | 3.759 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/CLK |
3.252 | 0.333 | tC2Q | RR | 2 | R8C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q |
3.759 | 0.506 | tNET | RR | 1 | R8C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0] | |||
2.919 | 0.000 | tHld | 1 | R8C11[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_txdata_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.506, 60.303%; tC2Q: 0.333, 39.697% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path10
Path Summary:
Slack | 0.840 |
Data Arrival Time | 3.759 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/CLK |
3.252 | 0.333 | tC2Q | RR | 2 | R8C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/latch_s_data_Z[0]/Q |
3.759 | 0.506 | tNET | RR | 1 | R8C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0] | |||
2.919 | 0.000 | tHld | 1 | R8C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_ssmask[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.506, 60.303%; tC2Q: 0.333, 39.697% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path11
Path Summary:
Slack | 0.894 |
Data Arrival Time | 3.813 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK |
3.252 | 0.333 | tC2Q | RR | 5 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/Q |
3.257 | 0.005 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/I2 |
3.813 | 0.556 | tINS | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_fast_cZ[1]/F |
3.813 | 0.000 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] | |||
2.919 | 0.000 | tHld | 1 | R7C9[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt_fast[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path12
Path Summary:
Slack | 0.905 |
Data Arrival Time | 3.824 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R10C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/Q |
3.824 | 0.572 | tNET | RR | 1 | R9C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3] | |||
2.919 | 0.000 | tHld | 1 | R9C8[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/reg_rxdata_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.572, 63.164%; tC2Q: 0.333, 36.836% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path13
Path Summary:
Slack | 0.940 |
Data Arrival Time | 3.859 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.pending_data |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C6[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.pending_data/CLK |
3.252 | 0.333 | tC2Q | RF | 3 | R9C6[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.pending_data/Q |
3.487 | 0.234 | tNET | FF | 1 | R9C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_sqmuxa_0_a2/I3 |
3.859 | 0.372 | tINS | FF | 1 | R9C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_sqmuxa_0_a2/F |
3.859 | 0.000 | tNET | FF | 1 | R9C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt | |||
2.919 | 0.000 | tHld | 1 | R9C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.reg_tmt |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.582%; route: 0.234, 24.950%; tC2Q: 0.333, 35.468% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path14
Path Summary:
Slack | 0.940 |
Data Arrival Time | 3.859 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[2] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C12[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[2]/CLK |
3.252 | 0.333 | tC2Q | RF | 2 | R10C12[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/reg_ctrl_Z[2]/Q |
3.487 | 0.234 | tNET | FF | 1 | R10C13[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_0_iv_0[2]/I2 |
3.859 | 0.372 | tINS | FF | 1 | R10C13[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_0_iv_0[2]/F |
3.859 | 0.000 | tNET | FF | 1 | R10C13[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C13[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2] | |||
2.919 | 0.000 | tHld | 1 | R10C13[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.582%; route: 0.234, 24.950%; tC2Q: 0.333, 35.468% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path15
Path Summary:
Slack | 0.943 |
Data Arrival Time | 3.862 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/CLK |
3.252 | 0.333 | tC2Q | RR | 2 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/Q |
3.490 | 0.238 | tNET | RR | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[1]/I0 |
3.862 | 0.372 | tINS | RF | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[1]/F |
3.862 | 0.000 | tNET | FF | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1] | |||
2.919 | 0.000 | tHld | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.452%; route: 0.238, 25.196%; tC2Q: 0.333, 35.352% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path16
Path Summary:
Slack | 0.943 |
Data Arrival Time | 3.862 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/CLK |
3.252 | 0.333 | tC2Q | RF | 3 | R8C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q |
3.490 | 0.238 | tNET | FF | 1 | R8C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_0_a2[7]/I0 |
3.862 | 0.372 | tINS | FF | 1 | R8C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_0_a2[7]/F |
3.862 | 0.000 | tNET | FF | 1 | R8C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7] | |||
2.919 | 0.000 | tHld | 1 | R8C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path17
Path Summary:
Slack | 0.944 |
Data Arrival Time | 3.863 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R8C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[6]/Q |
3.491 | 0.239 | tNET | RR | 1 | R8C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[5]/I1 |
3.863 | 0.372 | tINS | RF | 1 | R8C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[5]/F |
3.863 | 0.000 | tNET | FF | 1 | R8C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5] | |||
2.919 | 0.000 | tHld | 1 | R8C7[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.403%; route: 0.239, 25.289%; tC2Q: 0.333, 35.307% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path18
Path Summary:
Slack | 0.946 |
Data Arrival Time | 3.866 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw10_cs_Z |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw10_cs_Z/CLK |
3.252 | 0.333 | tC2Q | RR | 9 | R10C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw10_cs_Z/Q |
3.494 | 0.241 | tNET | RR | 1 | R10C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_60_i_cZ/I3 |
3.866 | 0.372 | tINS | RF | 1 | R10C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_60_i_cZ/F |
3.866 | 0.000 | tNET | FF | 1 | R10C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1] | |||
2.919 | 0.000 | tHld | 1 | R10C10[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.305%; route: 0.241, 25.476%; tC2Q: 0.333, 35.219% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path19
Path Summary:
Slack | 0.949 |
Data Arrival Time | 3.868 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R10C7[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[3]/Q |
3.496 | 0.244 | tNET | RR | 1 | R10C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[4]/I0 |
3.868 | 0.372 | tINS | RF | 1 | R10C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data_4_i_m2[4]/F |
3.868 | 0.000 | tNET | FF | 1 | R10C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4] | |||
2.919 | 0.000 | tHld | 1 | R10C7[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.194%; route: 0.244, 25.685%; tC2Q: 0.333, 35.120% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path20
Path Summary:
Slack | 0.949 |
Data Arrival Time | 3.868 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R10C7[2][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[1]/Q |
3.496 | 0.244 | tNET | RR | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_56_i_cZ/I0 |
3.868 | 0.372 | tINS | RF | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_56_i_cZ/F |
3.868 | 0.000 | tNET | FF | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0] | |||
2.919 | 0.000 | tHld | 1 | R10C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.rx_shift_data[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 39.194%; route: 0.244, 25.685%; tC2Q: 0.333, 35.120% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path21
Path Summary:
Slack | 0.964 |
Data Arrival Time | 3.883 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C12[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/CLK |
3.252 | 0.333 | tC2Q | RF | 12 | R10C12[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/Q |
3.511 | 0.258 | tNET | FF | 1 | R10C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_117_i_cZ/I2 |
3.883 | 0.372 | tINS | FF | 1 | R10C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_117_i_cZ/F |
3.883 | 0.000 | tNET | FF | 1 | R10C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R10C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7] | |||
2.919 | 0.000 | tHld | 1 | R10C11[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.372, 38.607%; route: 0.258, 26.799%; tC2Q: 0.333, 34.594% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path22
Path Summary:
Slack | 1.060 |
Data Arrival Time | 3.979 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK |
3.252 | 0.333 | tC2Q | RR | 3 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/Q |
3.255 | 0.002 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0_fast/I3 |
3.979 | 0.724 | tINS | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_0_fast/F |
3.979 | 0.000 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast | |||
2.919 | 0.000 | tHld | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path23
Path Summary:
Slack | 1.061 |
Data Arrival Time | 3.980 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/CLK |
3.252 | 0.333 | tC2Q | RR | 4 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/Q |
3.256 | 0.004 | tNET | RR | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_m6_cZ_cZ/I2 |
3.980 | 0.724 | tINS | RR | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_m6_cZ_cZ/F |
3.980 | 0.000 | tNET | RR | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5] | |||
2.919 | 0.000 | tHld | 1 | R8C9[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path24
Path Summary:
Slack | 1.062 |
Data Arrival Time | 3.981 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK |
3.252 | 0.333 | tC2Q | RR | 7 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/Q |
3.257 | 0.005 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/I1 |
3.981 | 0.724 | tINS | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[3]/F |
3.981 | 0.000 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] | |||
2.919 | 0.000 | tHld | 1 | R7C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path25
Path Summary:
Slack | 1.062 |
Data Arrival Time | 3.981 |
Data Required Time | 2.919 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/CLK |
3.252 | 0.333 | tC2Q | RR | 8 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/Q |
3.257 | 0.005 | tNET | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/I1 |
3.981 | 0.724 | tINS | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/data_cnt_3_cZ[0]/F |
3.981 | 0.000 | tNET | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0]/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] | |||
2.919 | 0.000 | tHld | 1 | R7C10[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.data_cnt[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.819 |
Data Arrival Time | 7.616 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
5.126 | 0.990 | tNET | FF | 1 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1 |
5.948 | 0.822 | tINS | FF | 3 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F |
7.616 | 1.668 | tNET | FF | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast | |||
13.435 | -0.043 | tSu | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 0.822, 20.875%; route: 2.657, 67.486%; tC2Q: 0.458, 11.639% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path2
Path Summary:
Slack | 6.618 |
Data Arrival Time | 6.817 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
5.126 | 0.990 | tNET | FF | 1 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1 |
5.948 | 0.822 | tINS | FF | 3 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F |
6.817 | 0.869 | tNET | FF | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 | |||
13.435 | -0.043 | tSu | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 0.822, 26.187%; route: 1.859, 59.211%; tC2Q: 0.458, 14.602% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path3
Path Summary:
Slack | 6.978 |
Data Arrival Time | 6.457 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
4.967 | 0.831 | tNET | FF | 1 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1 |
5.593 | 0.626 | tINS | FF | 3 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F |
6.457 | 0.864 | tNET | FF | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast | |||
13.435 | -0.043 | tSu | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 0.626, 22.530%; route: 1.694, 60.974%; tC2Q: 0.458, 16.496% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Path4
Path Summary:
Slack | 6.978 |
Data Arrival Time | 6.457 |
Data Required Time | 13.435 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
3.678 | 1.909 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
4.137 | 0.458 | tC2Q | RF | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
4.967 | 0.831 | tNET | FF | 1 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1 |
5.593 | 0.626 | tINS | FF | 3 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F |
6.457 | 0.864 | tNET | FF | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.468 | 0.486 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.769 | 0.302 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
13.678 | 1.909 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK |
13.478 | -0.200 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER | |||
13.435 | -0.043 | tSu | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Arrival Data Path Delay | cell: 0.626, 22.530%; route: 1.694, 60.974%; tC2Q: 0.458, 16.496% |
Required Clock Path Delay | cell: 1.284, 34.893%; route: 2.395, 65.107% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.828 |
Data Arrival Time | 4.762 |
Data Required Time | 2.934 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
3.252 | 0.333 | tC2Q | RR | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
3.829 | 0.577 | tNET | RR | 1 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1 |
4.214 | 0.385 | tINS | RR | 3 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F |
4.762 | 0.548 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast | |||
2.934 | 0.015 | tHld | 1 | R9C8[1][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_fast |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.385, 20.892%; route: 1.124, 61.020%; tC2Q: 0.333, 18.088% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path2
Path Summary:
Slack | 1.828 |
Data Arrival Time | 4.762 |
Data Required Time | 2.934 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
3.252 | 0.333 | tC2Q | RR | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
3.829 | 0.577 | tNET | RR | 1 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/I1 |
4.214 | 0.385 | tINS | RR | 3 | R9C7[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/un1_RST_I_1_0_a2_cZ_cZ/F |
4.762 | 0.548 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER | |||
2.934 | 0.015 | tHld | 1 | R9C8[1][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.385, 20.892%; route: 1.124, 61.020%; tC2Q: 0.333, 18.088% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path3
Path Summary:
Slack | 1.957 |
Data Arrival Time | 4.891 |
Data Required Time | 2.934 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
3.252 | 0.333 | tC2Q | RR | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
3.786 | 0.533 | tNET | RR | 1 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1 |
4.342 | 0.556 | tINS | RR | 3 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F |
4.891 | 0.550 | tNET | RR | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 | |||
2.934 | 0.015 | tHld | 1 | R9C8[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.556, 28.191%; route: 1.083, 54.908%; tC2Q: 0.333, 16.901% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Path4
Path Summary:
Slack | 2.526 |
Data Arrival Time | 5.461 |
Data Required Time | 2.934 |
From | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity |
To | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/CLK |
3.252 | 0.333 | tC2Q | RR | 6 | R8C6[2][A] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_polarity/Q |
3.786 | 0.533 | tNET | RR | 1 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/I1 |
4.342 | 0.556 | tINS | RR | 3 | R10C8[3][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/N_88_i_cZ/F |
5.461 | 1.119 | tNET | RR | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 1 | IOR3[A] | Gowin_EMPU_inst/sys_clk_ibuf/O |
1.226 | 0.382 | tNET | RR | 5 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
1.485 | 0.259 | tINS | RR | 150 | RIGHTSIDE[1] | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
2.919 | 1.434 | tNET | RR | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast/CLK |
2.919 | 0.000 | tUnc | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast | |||
2.934 | 0.015 | tHld | 1 | R8C5[0][B] | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SCLK_MASTER_1_fast |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Arrival Data Path Delay | cell: 0.556, 21.877%; route: 1.652, 65.007%; tC2Q: 0.333, 13.116% |
Required Clock Path Delay | cell: 1.104, 37.804%; route: 1.816, 62.196% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[12]/CLK |
MPW2
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[14]/CLK |
MPW3
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[3]/CLK |
MPW4
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_flash_wrap/rom_haddr_test_Z[11]/CLK |
MPW5
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_adc/read_mux_byte0_reg[11]/CLK |
MPW6
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[3]/CLK |
MPW7
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw0c_cs_Z/CLK |
MPW8
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw08_cs_Z/CLK |
MPW9
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/genblk1.SPI_DATA_O[2]/CLK |
MPW10
MPW Summary:
Slack: | 2.897 |
Actual Width: | 4.147 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | Gowin_EMPU_inst/sys_clk_ibuf/I |
5.984 | 0.984 | tINS | FF | Gowin_EMPU_inst/sys_clk_ibuf/O |
6.508 | 0.523 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
6.820 | 0.312 | tINS | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
8.773 | 1.953 | tNET | FF | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | Gowin_EMPU_inst/sys_clk_ibuf/I |
10.844 | 0.844 | tINS | RR | Gowin_EMPU_inst/sys_clk_ibuf/O |
11.226 | 0.382 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/HCLKIN |
11.485 | 0.259 | tINS | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
12.919 | 1.434 | tNET | RR | Gowin_EMPU_inst/Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/dw04_cs_Z/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
150 | fclk | -3.423 | 1.953 |
12 | dw08_cs | 5.522 | 1.804 |
12 | dw04_cs | 3.342 | 1.501 |
12 | c_status[1] | -0.974 | 1.315 |
11 | u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1.c_status[2] | -1.254 | 1.329 |
10 | c_status[0] | -0.093 | 1.316 |
9 | reg_rd | 5.348 | 1.200 |
9 | shift_direction | 6.491 | 1.351 |
9 | dw10_cs | 5.436 | 0.840 |
9 | N_328 | 4.891 | 0.846 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R15C2 | 0.625 |
R7C9 | 0.556 |
R8C7 | 0.556 |
R8C9 | 0.514 |
R8C10 | 0.514 |
R14C1 | 0.514 |
R9C11 | 0.486 |
R8C8 | 0.486 |
R15C3 | 0.472 |
R7C10 | 0.472 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|