#Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018
#install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-023

# Thu Dec 20 16:39:07 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\generic\gw1ns.v" (library work)
@I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\Demo_program\DK-START-GW1NSR2\DK-START-GW1NSR2-ledtest\DK-START-GW1NSR2-ledtest\src\gowin_empu\gowin_empu.v" (library work)
@I::"E:\Demo_program\DK-START-GW1NSR2\DK-START-GW1NSR2-ledtest\DK-START-GW1NSR2-ledtest\src\ledtest_top.v" (library work)
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module ledtest_top
@N:CG364 : gw1ns.v(1547) | Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
@N:CG364 : gw1ns.v(365) | Synthesizing module IBUF in library work.
Running optimization stage 1 on IBUF .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MCU .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on GW_CLKDIV .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on GW_GPIO .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DQCE .......
Running optimization stage 1 on FLASH128K .......
Running optimization stage 1 on gw_rom_flash_15s_32s .......
Running optimization stage 1 on GW_FLASH .......
Running optimization stage 1 on SP .......
Running optimization stage 1 on GW_SRAM .......
Running optimization stage 1 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on ADC .......
Running optimization stage 1 on gw_cmsdk_apb2_adc .......
Running optimization stage 1 on DLC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on DFFNCE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on SPI_Z2 .......
Running optimization stage 1 on gw_cmsdk_apb2_spi .......
Running optimization stage 1 on gw_peripherals_interconnect_12s .......
Running optimization stage 1 on \~Gowin_EMPU.Gowin_EMPU_  .......
@N:CG364 : gowin_empu.v(4175) | Synthesizing module Gowin_EMPU in library work.
Running optimization stage 1 on Gowin_EMPU .......
@W:CL168 : gowin_empu.v(4209) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : ledtest_top.v(1) | Synthesizing module ledtest_top in library work.
Running optimization stage 1 on ledtest_top .......
Running optimization stage 2 on ledtest_top .......
Running optimization stage 2 on Gowin_EMPU .......
Running optimization stage 2 on \~Gowin_EMPU.Gowin_EMPU_  .......
Running optimization stage 2 on gw_peripherals_interconnect_12s .......
Running optimization stage 2 on gw_cmsdk_apb2_spi .......
Running optimization stage 2 on SPI_Z2 .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFNCE .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DLC .......
Running optimization stage 2 on gw_cmsdk_apb2_adc .......
Running optimization stage 2 on ADC .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 2 on GW_SRAM .......
Running optimization stage 2 on SP .......
Running optimization stage 2 on GW_FLASH .......
Running optimization stage 2 on gw_rom_flash_15s_32s .......
Running optimization stage 2 on FLASH128K .......
Running optimization stage 2 on DQCE .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on GW_GPIO .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on GW_CLKDIV .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on MCU .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on IBUF .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 20 16:39:07 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27

@N: :  | Running in 64-bit mode 

Linker output is up to date. No re-linking necessary


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 20 16:39:07 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 20 16:39:07 2018

###########################################################]



@A: :  | multi_srs_gen output is up to date. No run necessary. 
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Multi-srs Generator Report
Linked File:  DK-START-GW1NS2-ledtest_multi_srs_gen.srr



@A: :  | premap output is up to date. No run necessary. 
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Premap Report
Linked File:  DK-START-GW1NS2-ledtest_premap.srr



@A: :  | fpga_mapper output is up to date. No run necessary. 
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Map & Optimize Report
Linked File:  DK-START-GW1NS2-ledtest_fpga_mapper.srr