Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\impl\synthesize\rev_1\IO_test.vm |
Physical Constraints File | E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\src\IO_test.cst |
Timing Constraint File | --- |
GOWIN version | V1.9.1Beta |
Part Number | GW2A-LV18PG256C8/I7 |
Created Time | Tue Aug 06 14:43:02 2019 |
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C |
Hold Delay Model | Fast 1.05V 0C |
Numbers of Paths Analyzed | 96 |
Numbers of Endpoints Analyzed | 59 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 281.893(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.453 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[2] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.312 |
2 | 6.453 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[3] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.312 |
3 | 6.453 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[0] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.312 |
4 | 6.453 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[1] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.312 |
5 | 6.479 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[7] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.286 |
6 | 6.479 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[5] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.286 |
7 | 6.479 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[4] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.286 |
8 | 6.479 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[6] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.286 |
9 | 6.481 | \clk_cnt_Z[8] /Q | \led_1[0] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.284 |
10 | 6.633 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[23] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.132 |
11 | 6.633 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[20] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.132 |
12 | 6.633 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[19] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.132 |
13 | 6.633 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[22] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.132 |
14 | 6.633 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[21] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.132 |
15 | 6.636 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[18] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.129 |
16 | 6.636 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[17] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.129 |
17 | 6.636 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[16] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.129 |
18 | 6.640 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[9] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.125 |
19 | 6.640 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[8] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.125 |
20 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[15] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
21 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[10] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
22 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[13] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
23 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[11] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
24 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[12] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
25 | 6.653 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[14] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.112 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.557 | \clk_cnt_Z[21] /Q | \clk_cnt_Z[21] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
2 | 0.557 | \clk_cnt_Z[19] /Q | \clk_cnt_Z[19] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
3 | 0.557 | \clk_cnt_Z[17] /Q | \clk_cnt_Z[17] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
4 | 0.557 | \clk_cnt_Z[13] /Q | \clk_cnt_Z[13] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
5 | 0.557 | \clk_cnt_Z[11] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
6 | 0.557 | \clk_cnt_Z[7] /Q | \clk_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
7 | 0.559 | \clk_cnt_Z[25] /Q | \clk_cnt_Z[25] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
8 | 0.559 | \clk_cnt_Z[1] /Q | \clk_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
9 | 0.559 | \clk_cnt_Z[5] /Q | \clk_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
10 | 0.560 | \led_1[0] /Q | \led_1[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.571 |
11 | 0.674 | \clk_cnt_Z[24] /Q | \clk_cnt_Z[24] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
12 | 0.674 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[18] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
13 | 0.674 | \clk_cnt_Z[14] /Q | \clk_cnt_Z[14] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
14 | 0.674 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[16] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
15 | 0.674 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
16 | 0.674 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
17 | 0.674 | \clk_cnt_Z[22] /Q | \clk_cnt_Z[22] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
18 | 0.678 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.689 |
19 | 0.678 | \clk_cnt_Z[0] /Q | \clk_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.689 |
20 | 0.678 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[20] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.689 |
21 | 0.679 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[23] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.690 |
22 | 0.679 | \clk_cnt_Z[15] /Q | \clk_cnt_Z[15] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.690 |
23 | 0.679 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.690 |
24 | 0.679 | \clk_cnt_Z[3] /Q | \clk_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.690 |
25 | 0.684 | \clk_cnt_Z[10] /Q | \clk_cnt_Z[10] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.695 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[0] |
2 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[2] |
3 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[6] |
4 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[14] |
5 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[13] |
6 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[5] |
7 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[12] |
8 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \led_1[0] |
9 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[25] |
10 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[11] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.453 |
Data Arrival Time | 5.196 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.196 | 0.687 | tNET | RR | 1 | R18C26[2][A] | \clk_cnt_Z[2] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C26[2][A] | \clk_cnt_Z[2] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R18C26[2][A] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.529%; route: 1.605, 48.467%; tC2Q: 0.232, 7.004% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path2
Path Summary:
Slack | 6.453 |
Data Arrival Time | 5.196 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.196 | 0.687 | tNET | RR | 1 | R18C26[2][B] | \clk_cnt_Z[3] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C26[2][B] | \clk_cnt_Z[3] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R18C26[2][B] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.529%; route: 1.605, 48.467%; tC2Q: 0.232, 7.004% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path3
Path Summary:
Slack | 6.453 |
Data Arrival Time | 5.196 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.196 | 0.687 | tNET | RR | 1 | R18C26[1][A] | \clk_cnt_Z[0] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C26[1][A] | \clk_cnt_Z[0] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R18C26[1][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.529%; route: 1.605, 48.467%; tC2Q: 0.232, 7.004% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path4
Path Summary:
Slack | 6.453 |
Data Arrival Time | 5.196 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.196 | 0.687 | tNET | RR | 1 | R18C26[1][B] | \clk_cnt_Z[1] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C26[1][B] | \clk_cnt_Z[1] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R18C26[1][B] | \clk_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.529%; route: 1.605, 48.467%; tC2Q: 0.232, 7.004% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path5
Path Summary:
Slack | 6.479 |
Data Arrival Time | 5.170 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.170 | 0.661 | tNET | RR | 1 | R18C27[1][B] | \clk_cnt_Z[7] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C27[1][B] | \clk_cnt_Z[7] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[7] | |||
11.648 | -0.035 | tSu | 1 | R18C27[1][B] | \clk_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.882%; route: 1.579, 48.058%; tC2Q: 0.232, 7.059% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path6
Path Summary:
Slack | 6.479 |
Data Arrival Time | 5.170 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.170 | 0.661 | tNET | RR | 1 | R18C27[0][B] | \clk_cnt_Z[5] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C27[0][B] | \clk_cnt_Z[5] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[5] | |||
11.648 | -0.035 | tSu | 1 | R18C27[0][B] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.882%; route: 1.579, 48.058%; tC2Q: 0.232, 7.059% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path7
Path Summary:
Slack | 6.479 |
Data Arrival Time | 5.170 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.170 | 0.661 | tNET | RR | 1 | R18C27[0][A] | \clk_cnt_Z[4] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C27[0][A] | \clk_cnt_Z[4] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[4] | |||
11.648 | -0.035 | tSu | 1 | R18C27[0][A] | \clk_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.882%; route: 1.579, 48.058%; tC2Q: 0.232, 7.059% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path8
Path Summary:
Slack | 6.479 |
Data Arrival Time | 5.170 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.170 | 0.661 | tNET | RR | 1 | R18C27[1][A] | \clk_cnt_Z[6] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C27[1][A] | \clk_cnt_Z[6] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R18C27[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.882%; route: 1.579, 48.058%; tC2Q: 0.232, 7.059% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path9
Path Summary:
Slack | 6.481 |
Data Arrival Time | 5.167 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.167 | 0.659 | tNET | RR | 1 | R18C35[0][B] | \led_1[0] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C35[0][B] | \led_1[0] /CLK |
11.683 | -0.200 | tUnc | \led_1[0] | |||
11.648 | -0.035 | tSu | 1 | R18C35[0][B] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 44.913%; route: 1.577, 48.023%; tC2Q: 0.232, 7.064% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path10
Path Summary:
Slack | 6.633 |
Data Arrival Time | 5.016 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.016 | 0.507 | tNET | RR | 1 | R18C29[2][B] | \clk_cnt_Z[23] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C29[2][B] | \clk_cnt_Z[23] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[23] | |||
11.648 | -0.035 | tSu | 1 | R18C29[2][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.088%; route: 1.425, 45.506%; tC2Q: 0.232, 7.406% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path11
Path Summary:
Slack | 6.633 |
Data Arrival Time | 5.016 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.016 | 0.507 | tNET | RR | 1 | R18C29[1][A] | \clk_cnt_Z[20] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C29[1][A] | \clk_cnt_Z[20] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[20] | |||
11.648 | -0.035 | tSu | 1 | R18C29[1][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.088%; route: 1.425, 45.506%; tC2Q: 0.232, 7.406% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path12
Path Summary:
Slack | 6.633 |
Data Arrival Time | 5.016 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.016 | 0.507 | tNET | RR | 1 | R18C29[0][B] | \clk_cnt_Z[19] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C29[0][B] | \clk_cnt_Z[19] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[19] | |||
11.648 | -0.035 | tSu | 1 | R18C29[0][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.088%; route: 1.425, 45.506%; tC2Q: 0.232, 7.406% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path13
Path Summary:
Slack | 6.633 |
Data Arrival Time | 5.016 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.016 | 0.507 | tNET | RR | 1 | R18C29[2][A] | \clk_cnt_Z[22] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C29[2][A] | \clk_cnt_Z[22] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[22] | |||
11.648 | -0.035 | tSu | 1 | R18C29[2][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.088%; route: 1.425, 45.506%; tC2Q: 0.232, 7.406% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path14
Path Summary:
Slack | 6.633 |
Data Arrival Time | 5.016 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.016 | 0.507 | tNET | RR | 1 | R18C29[1][B] | \clk_cnt_Z[21] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C29[1][B] | \clk_cnt_Z[21] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[21] | |||
11.648 | -0.035 | tSu | 1 | R18C29[1][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.088%; route: 1.425, 45.506%; tC2Q: 0.232, 7.406% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path15
Path Summary:
Slack | 6.636 |
Data Arrival Time | 5.012 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.012 | 0.503 | tNET | RR | 1 | R18C34[1][A] | \clk_cnt_Z[18] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C34[1][A] | \clk_cnt_Z[18] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[18] | |||
11.648 | -0.035 | tSu | 1 | R18C34[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.143%; route: 1.422, 45.442%; tC2Q: 0.232, 7.415% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path16
Path Summary:
Slack | 6.636 |
Data Arrival Time | 5.012 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.012 | 0.503 | tNET | RR | 1 | R18C34[0][B] | \clk_cnt_Z[17] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C34[0][B] | \clk_cnt_Z[17] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[17] | |||
11.648 | -0.035 | tSu | 1 | R18C34[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.143%; route: 1.422, 45.442%; tC2Q: 0.232, 7.415% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path17
Path Summary:
Slack | 6.636 |
Data Arrival Time | 5.012 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.012 | 0.503 | tNET | RR | 1 | R18C34[0][A] | \clk_cnt_Z[16] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C34[0][A] | \clk_cnt_Z[16] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[16] | |||
11.648 | -0.035 | tSu | 1 | R18C34[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.143%; route: 1.422, 45.442%; tC2Q: 0.232, 7.415% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path18
Path Summary:
Slack | 6.640 |
Data Arrival Time | 5.008 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.008 | 0.499 | tNET | RR | 1 | R18C32[2][B] | \clk_cnt_Z[9] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C32[2][B] | \clk_cnt_Z[9] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[9] | |||
11.648 | -0.035 | tSu | 1 | R18C32[2][B] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.198%; route: 1.418, 45.378%; tC2Q: 0.232, 7.424% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path19
Path Summary:
Slack | 6.640 |
Data Arrival Time | 5.008 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
5.008 | 0.499 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[8] | |||
11.648 | -0.035 | tSu | 1 | R18C32[2][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.198%; route: 1.418, 45.378%; tC2Q: 0.232, 7.424% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path20
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[2][B] | \clk_cnt_Z[15] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[2][B] | \clk_cnt_Z[15] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[15] | |||
11.648 | -0.035 | tSu | 1 | R18C33[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path21
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[0][A] | \clk_cnt_Z[10] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[0][A] | \clk_cnt_Z[10] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[10] | |||
11.648 | -0.035 | tSu | 1 | R18C33[0][A] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path22
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[1][B] | \clk_cnt_Z[13] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[1][B] | \clk_cnt_Z[13] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[13] | |||
11.648 | -0.035 | tSu | 1 | R18C33[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path23
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[0][B] | \clk_cnt_Z[11] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[0][B] | \clk_cnt_Z[11] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[11] | |||
11.648 | -0.035 | tSu | 1 | R18C33[0][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path24
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[1][A] | \clk_cnt_Z[12] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[1][A] | \clk_cnt_Z[12] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[12] | |||
11.648 | -0.035 | tSu | 1 | R18C33[1][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path25
Path Summary:
Slack | 6.653 |
Data Arrival Time | 4.995 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
2.297 | 0.182 | tNET | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/I0 |
2.852 | 0.555 | tINS | FF | 1 | R18C33[3][B] | clk_cnt11_0tt_m2_0_a2_2_cZ/F |
3.342 | 0.490 | tNET | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/I1 |
3.713 | 0.371 | tINS | FF | 1 | R18C29[3][B] | clk_cnt11_0_m1_e_N_5L7_cZ/F |
3.960 | 0.247 | tNET | FF | 1 | R18C31[2][B] | clk_cnt11_0_m1_e/I2 |
4.509 | 0.549 | tINS | FR | 27 | R18C31[2][B] | clk_cnt11_0_m1_e/F |
4.995 | 0.487 | tNET | RR | 1 | R18C33[2][A] | \clk_cnt_Z[14] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R18C33[2][A] | \clk_cnt_Z[14] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[14] | |||
11.648 | -0.035 | tSu | 1 | R18C33[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.475, 47.393%; route: 1.405, 45.152%; tC2Q: 0.232, 7.454% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[21] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[1][B] | \clk_cnt_Z[21] /CLK |
1.779 | 0.202 | tC2Q | RR | 2 | R18C29[1][B] | \clk_cnt_Z[21] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C29[1][B] | \clk_cnt_cry_0[21] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C29[1][B] | \clk_cnt_cry_0[21] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C29[1][B] | \clk_cnt_Z[21] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[1][B] | \clk_cnt_Z[21] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[21] | |||
1.588 | 0.011 | tHld | 1 | R18C29[1][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path2
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[19] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[0][B] | \clk_cnt_Z[19] /CLK |
1.779 | 0.202 | tC2Q | RR | 2 | R18C29[0][B] | \clk_cnt_Z[19] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C29[0][B] | \clk_cnt_cry_0[19] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C29[0][B] | \clk_cnt_cry_0[19] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C29[0][B] | \clk_cnt_Z[19] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[0][B] | \clk_cnt_Z[19] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[19] | |||
1.588 | 0.011 | tHld | 1 | R18C29[0][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path3
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[17] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[0][B] | \clk_cnt_Z[17] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R18C34[0][B] | \clk_cnt_Z[17] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C34[0][B] | \clk_cnt_cry_0[17] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C34[0][B] | \clk_cnt_cry_0[17] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C34[0][B] | \clk_cnt_Z[17] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[0][B] | \clk_cnt_Z[17] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[17] | |||
1.588 | 0.011 | tHld | 1 | R18C34[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path4
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[13] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[1][B] | \clk_cnt_Z[13] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R18C33[1][B] | \clk_cnt_Z[13] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C33[1][B] | \clk_cnt_cry_0[13] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C33[1][B] | \clk_cnt_cry_0[13] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C33[1][B] | \clk_cnt_Z[13] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[1][B] | \clk_cnt_Z[13] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[13] | |||
1.588 | 0.011 | tHld | 1 | R18C33[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path5
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[11] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[0][B] | \clk_cnt_Z[11] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R18C33[0][B] | \clk_cnt_Z[11] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C33[0][B] | \clk_cnt_cry_0[11] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C33[0][B] | \clk_cnt_cry_0[11] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C33[0][B] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[0][B] | \clk_cnt_Z[11] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[11] | |||
1.588 | 0.011 | tHld | 1 | R18C33[0][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path6
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[7] |
To | \clk_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C27[1][B] | \clk_cnt_Z[7] /CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R18C27[1][B] | \clk_cnt_Z[7] /Q |
1.782 | 0.002 | tNET | RR | 2 | R18C27[1][B] | \clk_cnt_s_0[7] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R18C27[1][B] | \clk_cnt_s_0[7] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R18C27[1][B] | \clk_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C27[1][B] | \clk_cnt_Z[7] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[7] | |||
1.588 | 0.011 | tHld | 1 | R18C27[1][B] | \clk_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path7
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.147 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[25] |
To | \clk_cnt_Z[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C30[0][B] | \clk_cnt_Z[25] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R18C30[0][B] | \clk_cnt_Z[25] /Q |
1.783 | 0.004 | tNET | RR | 2 | R18C30[0][B] | \clk_cnt_s_0[25] /I0 |
2.147 | 0.364 | tINS | RF | 1 | R18C30[0][B] | \clk_cnt_s_0[25] /SUM |
2.147 | 0.000 | tNET | FF | 1 | R18C30[0][B] | \clk_cnt_Z[25] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C30[0][B] | \clk_cnt_Z[25] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[25] | |||
1.588 | 0.011 | tHld | 1 | R18C30[0][B] | \clk_cnt_Z[25] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path8
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.147 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[1] |
To | \clk_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[1][B] | \clk_cnt_Z[1] /CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R18C26[1][B] | \clk_cnt_Z[1] /Q |
1.783 | 0.004 | tNET | RR | 2 | R18C26[1][B] | \clk_cnt_cry_0[1] /I0 |
2.147 | 0.364 | tINS | RF | 1 | R18C26[1][B] | \clk_cnt_cry_0[1] /SUM |
2.147 | 0.000 | tNET | FF | 1 | R18C26[1][B] | \clk_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[1][B] | \clk_cnt_Z[1] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[1] | |||
1.588 | 0.011 | tHld | 1 | R18C26[1][B] | \clk_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path9
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.147 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[5] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C27[0][B] | \clk_cnt_Z[5] /CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R18C27[0][B] | \clk_cnt_Z[5] /Q |
1.783 | 0.004 | tNET | RR | 2 | R18C27[0][B] | \clk_cnt_cry_0[5] /I0 |
2.147 | 0.364 | tINS | RF | 1 | R18C27[0][B] | \clk_cnt_cry_0[5] /SUM |
2.147 | 0.000 | tNET | FF | 1 | R18C27[0][B] | \clk_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C27[0][B] | \clk_cnt_Z[5] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[5] | |||
1.588 | 0.011 | tHld | 1 | R18C27[0][B] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path10
Path Summary:
Slack | 0.560 |
Data Arrival Time | 2.148 |
Data Required Time | 1.588 |
From | \led_1[0] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C35[0][B] | \led_1[0] /CLK |
1.779 | 0.202 | tC2Q | RR | 5 | R18C35[0][B] | \led_1[0] /Q |
1.784 | 0.005 | tNET | RR | 1 | R18C35[0][B] | \led_1e[0] /I0 |
2.148 | 0.364 | tINS | RF | 1 | R18C35[0][B] | \led_1e[0] /F |
2.148 | 0.000 | tNET | FF | 1 | R18C35[0][B] | \led_1[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C35[0][B] | \led_1[0] /CLK |
1.577 | 0.000 | tUnc | \led_1[0] | |||
1.588 | 0.011 | tHld | 1 | R18C35[0][B] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 63.760%; route: 0.005, 0.856%; tC2Q: 0.202, 35.383% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path11
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[24] |
To | \clk_cnt_Z[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C30[0][A] | \clk_cnt_Z[24] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C30[0][A] | \clk_cnt_Z[24] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C30[0][A] | \clk_cnt_cry_0[24] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C30[0][A] | \clk_cnt_cry_0[24] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C30[0][A] | \clk_cnt_Z[24] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C30[0][A] | \clk_cnt_Z[24] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[24] | |||
1.588 | 0.011 | tHld | 1 | R18C30[0][A] | \clk_cnt_Z[24] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path12
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[1][A] | \clk_cnt_Z[18] /CLK |
1.778 | 0.201 | tC2Q | RF | 4 | R18C34[1][A] | \clk_cnt_Z[18] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C34[1][A] | \clk_cnt_s_0[18] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C34[1][A] | \clk_cnt_s_0[18] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C34[1][A] | \clk_cnt_Z[18] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[1][A] | \clk_cnt_Z[18] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[18] | |||
1.588 | 0.011 | tHld | 1 | R18C34[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path13
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[14] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[2][A] | \clk_cnt_Z[14] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C33[2][A] | \clk_cnt_Z[14] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C33[2][A] | \clk_cnt_cry_0[14] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C33[2][A] | \clk_cnt_cry_0[14] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C33[2][A] | \clk_cnt_Z[14] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[2][A] | \clk_cnt_Z[14] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[14] | |||
1.588 | 0.011 | tHld | 1 | R18C33[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path14
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[0][A] | \clk_cnt_Z[16] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C34[0][A] | \clk_cnt_Z[16] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C34[0][A] | \clk_cnt_cry_0[16] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C34[0][A] | \clk_cnt_cry_0[16] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C34[0][A] | \clk_cnt_Z[16] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C34[0][A] | \clk_cnt_Z[16] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[16] | |||
1.588 | 0.011 | tHld | 1 | R18C34[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path15
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C32[2][A] | \clk_cnt_Z[8] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C32[2][A] | \clk_cnt_cry_0[8] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C32[2][A] | \clk_cnt_cry_0[8] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C32[2][A] | \clk_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C32[2][A] | \clk_cnt_Z[8] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[8] | |||
1.588 | 0.011 | tHld | 1 | R18C32[2][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path16
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[1][A] | \clk_cnt_Z[12] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C33[1][A] | \clk_cnt_Z[12] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C33[1][A] | \clk_cnt_cry_0[12] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C33[1][A] | \clk_cnt_cry_0[12] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C33[1][A] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[1][A] | \clk_cnt_Z[12] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[12] | |||
1.588 | 0.011 | tHld | 1 | R18C33[1][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path17
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[22] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[2][A] | \clk_cnt_Z[22] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R18C29[2][A] | \clk_cnt_Z[22] /Q |
1.899 | 0.120 | tNET | FF | 2 | R18C29[2][A] | \clk_cnt_cry_0[22] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R18C29[2][A] | \clk_cnt_cry_0[22] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R18C29[2][A] | \clk_cnt_Z[22] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[2][A] | \clk_cnt_Z[22] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[22] | |||
1.588 | 0.011 | tHld | 1 | R18C29[2][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path18
Path Summary:
Slack | 0.678 |
Data Arrival Time | 2.266 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[2][A] | \clk_cnt_Z[2] /CLK |
1.778 | 0.201 | tC2Q | RF | 4 | R18C26[2][A] | \clk_cnt_Z[2] /Q |
1.902 | 0.124 | tNET | FF | 2 | R18C26[2][A] | \clk_cnt_cry_0[2] /I0 |
2.266 | 0.364 | tINS | FF | 1 | R18C26[2][A] | \clk_cnt_cry_0[2] /SUM |
2.266 | 0.000 | tNET | FF | 1 | R18C26[2][A] | \clk_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[2][A] | \clk_cnt_Z[2] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[2] | |||
1.588 | 0.011 | tHld | 1 | R18C26[2][A] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.866%; route: 0.124, 17.941%; tC2Q: 0.201, 29.193% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path19
Path Summary:
Slack | 0.678 |
Data Arrival Time | 2.266 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[0] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[1][A] | \clk_cnt_Z[0] /CLK |
1.778 | 0.201 | tC2Q | RF | 4 | R18C26[1][A] | \clk_cnt_Z[0] /Q |
1.902 | 0.124 | tNET | FF | 2 | R18C26[1][A] | \clk_cnt_cry_0[0] /I0 |
2.266 | 0.364 | tINS | FF | 1 | R18C26[1][A] | \clk_cnt_cry_0[0] /SUM |
2.266 | 0.000 | tNET | FF | 1 | R18C26[1][A] | \clk_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[1][A] | \clk_cnt_Z[0] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[0] | |||
1.588 | 0.011 | tHld | 1 | R18C26[1][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.866%; route: 0.124, 17.941%; tC2Q: 0.201, 29.193% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path20
Path Summary:
Slack | 0.678 |
Data Arrival Time | 2.266 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[1][A] | \clk_cnt_Z[20] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R18C29[1][A] | \clk_cnt_Z[20] /Q |
1.902 | 0.124 | tNET | FF | 2 | R18C29[1][A] | \clk_cnt_cry_0[20] /I0 |
2.266 | 0.364 | tINS | FF | 1 | R18C29[1][A] | \clk_cnt_cry_0[20] /SUM |
2.266 | 0.000 | tNET | FF | 1 | R18C29[1][A] | \clk_cnt_Z[20] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[1][A] | \clk_cnt_Z[20] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[20] | |||
1.588 | 0.011 | tHld | 1 | R18C29[1][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.855%; route: 0.124, 17.958%; tC2Q: 0.201, 29.187% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path21
Path Summary:
Slack | 0.679 |
Data Arrival Time | 2.268 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[2][B] | \clk_cnt_Z[23] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R18C29[2][B] | \clk_cnt_Z[23] /Q |
1.904 | 0.125 | tNET | FF | 2 | R18C29[2][B] | \clk_cnt_cry_0[23] /I0 |
2.268 | 0.364 | tINS | FF | 1 | R18C29[2][B] | \clk_cnt_cry_0[23] /SUM |
2.268 | 0.000 | tNET | FF | 1 | R18C29[2][B] | \clk_cnt_Z[23] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C29[2][B] | \clk_cnt_Z[23] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[23] | |||
1.588 | 0.011 | tHld | 1 | R18C29[2][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.740%; route: 0.125, 18.137%; tC2Q: 0.201, 29.123% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path22
Path Summary:
Slack | 0.679 |
Data Arrival Time | 2.268 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[15] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[2][B] | \clk_cnt_Z[15] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C33[2][B] | \clk_cnt_Z[15] /Q |
1.904 | 0.125 | tNET | FF | 2 | R18C33[2][B] | \clk_cnt_cry_0[15] /I0 |
2.268 | 0.364 | tINS | FF | 1 | R18C33[2][B] | \clk_cnt_cry_0[15] /SUM |
2.268 | 0.000 | tNET | FF | 1 | R18C33[2][B] | \clk_cnt_Z[15] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[2][B] | \clk_cnt_Z[15] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[15] | |||
1.588 | 0.011 | tHld | 1 | R18C33[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.740%; route: 0.125, 18.137%; tC2Q: 0.201, 29.123% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path23
Path Summary:
Slack | 0.679 |
Data Arrival Time | 2.268 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C32[2][B] | \clk_cnt_Z[9] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R18C32[2][B] | \clk_cnt_Z[9] /Q |
1.904 | 0.124 | tNET | RR | 2 | R18C32[2][B] | \clk_cnt_cry_0[9] /I0 |
2.268 | 0.364 | tINS | RF | 1 | R18C32[2][B] | \clk_cnt_cry_0[9] /SUM |
2.268 | 0.000 | tNET | FF | 1 | R18C32[2][B] | \clk_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C32[2][B] | \clk_cnt_Z[9] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[9] | |||
1.588 | 0.011 | tHld | 1 | R18C32[2][B] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.720%; route: 0.124, 18.024%; tC2Q: 0.202, 29.257% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path24
Path Summary:
Slack | 0.679 |
Data Arrival Time | 2.268 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[3] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[2][B] | \clk_cnt_Z[3] /CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R18C26[2][B] | \clk_cnt_Z[3] /Q |
1.904 | 0.124 | tNET | RR | 2 | R18C26[2][B] | \clk_cnt_cry_0[3] /I0 |
2.268 | 0.364 | tINS | RF | 1 | R18C26[2][B] | \clk_cnt_cry_0[3] /SUM |
2.268 | 0.000 | tNET | FF | 1 | R18C26[2][B] | \clk_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C26[2][B] | \clk_cnt_Z[3] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[3] | |||
1.588 | 0.011 | tHld | 1 | R18C26[2][B] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.720%; route: 0.124, 18.024%; tC2Q: 0.202, 29.257% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path25
Path Summary:
Slack | 0.684 |
Data Arrival Time | 2.273 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[10] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[0][A] | \clk_cnt_Z[10] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R18C33[0][A] | \clk_cnt_Z[10] /Q |
1.909 | 0.130 | tNET | FF | 2 | R18C33[0][A] | \clk_cnt_cry_0[10] /I0 |
2.273 | 0.364 | tINS | FF | 1 | R18C33[0][A] | \clk_cnt_cry_0[10] /SUM |
2.273 | 0.000 | tNET | FF | 1 | R18C33[0][A] | \clk_cnt_Z[10] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 27 | IOT27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R18C33[0][A] | \clk_cnt_Z[10] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[10] | |||
1.588 | 0.011 | tHld | 1 | R18C33[0][A] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.346%; route: 0.130, 18.748%; tC2Q: 0.201, 28.906% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[0] /CLK |
MPW2
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[2] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[2] /CLK |
MPW3
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[6] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[6] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[6] /CLK |
MPW4
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[14] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[14] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[14] /CLK |
MPW5
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[13] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[13] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[13] /CLK |
MPW6
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[5] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[5] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[5] /CLK |
MPW7
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[12] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[12] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[12] /CLK |
MPW8
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \led_1[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \led_1[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \led_1[0] /CLK |
MPW9
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[25] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[25] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[25] /CLK |
MPW10
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[11] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[11] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[11] /CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
27 | clk_c | 6.453 | 1.228 |
27 | clk_cnt11_0_N_3_mux | 6.453 | 0.821 |
5 | led_c[0] | 8.950 | 1.947 |
4 | clk_cnt[7] | 6.777 | 0.261 |
4 | clk_cnt[5] | 6.657 | 0.176 |
4 | clk_cnt[6] | 6.758 | 0.174 |
4 | clk_cnt[18] | 6.684 | 0.579 |
4 | clk_cnt[0] | 6.739 | 0.258 |
4 | clk_cnt[3] | 6.688 | 0.261 |
4 | clk_cnt[4] | 6.618 | 0.177 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R18C33 | 0.292 |
R18C26 | 0.167 |
R18C27 | 0.167 |
R18C29 | 0.167 |
R18C30 | 0.153 |
R18C31 | 0.153 |
R18C32 | 0.139 |
R18C34 | 0.111 |
R18C28 | 0.097 |
R18C35 | 0.056 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|