#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-023

# Tue Aug  6 14:42:47 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\src\IO_test.v" (library work)
@W:CG921 : IO_test.v(14) | led is already declared in this scope.
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module IO_test
@N:CG364 : IO_test.v(2) | Synthesizing module IO_test in library work.
Running optimization stage 1 on IO_test .......
Running optimization stage 2 on IO_test .......
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[26] is always 0.
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[27] is always 0.
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[28] is always 0.
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[29] is always 0.
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[30] is always 0.
@N:CL189 : IO_test.v(19) | Register bit clk_cnt[31] is always 0.
@W:CL279 : IO_test.v(19) | Pruning register bits 31 to 26 of clk_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:42:47 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : io_test.v(2) | Selected library: work cell: IO_test view verilog as top level
@N:NF107 : io_test.v(2) | Selected library: work cell: IO_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:42:47 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:42:47 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
File C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
File D:\TEST\LED_test\impl\synthesize\rev_1\synwork\IO_test_comp.srs changed - recompiling
@N:NF107 : io_test.v(2) | Selected library: work cell: IO_test view verilog as top level
@N:NF107 : io_test.v(2) | Selected library: work cell: IO_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug  6 14:42:49 2019

###########################################################]


Premap Report



# Tue Aug  6 14:42:49 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  IO_test_scck.rpt
Printing clock  summary report in "E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\impl\synthesize\rev_1\IO_test_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)



Clock Summary
******************

          Start           Requested     Requested     Clock        Clock                     Clock
Level     Clock           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------
0 -       IO_test|clk     381.1 MHz     2.624         inferred     Autoconstr_clkgroup_0     30   
==================================================================================================



Clock Load Summary
***********************

                Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
Clock           Load      Pin           Seq Example     Seq Example       Comb Example 
---------------------------------------------------------------------------------------
IO_test|clk     30        clk(port)     led_1[0].C      -                 -            
=======================================================================================

@W:MT529 : io_test.v(19) | Found inferred clock IO_test|clk which controls 30 sequential elements including clk_cnt[25:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 30 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 Unconstrained_port     30         clk_cnt[25:0]  
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\impl\synthesize\rev_1\IO_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 191MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug  6 14:42:51 2019

###########################################################]


Map & Optimize Report



# Tue Aug  6 14:42:51 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\Program Files\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@W:BN132 : io_test.v(57) | Removing sequential instance led_1[3] because it is equivalent to instance led_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : io_test.v(48) | Removing sequential instance led_1[2] because it is equivalent to instance led_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : io_test.v(62) | Removing user instance led_24[3] because it is equivalent to instance led_17[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : io_test.v(53) | Removing user instance led_17[2] because it is equivalent to instance led_3[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : io_test.v(48) | Boundary register led_1[2] (in view: work.IO_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : io_test.v(57) | Boundary register led_1[3] (in view: work.IO_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@W:BN132 : io_test.v(39) | Removing sequential instance led_1[1] because it is equivalent to instance led_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : io_test.v(39) | Boundary register led_1[1] (in view: work.IO_test(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

@N:MO231 : io_test.v(19) | Found counter in view:work.IO_test(verilog) instance clk_cnt[25:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -1.97ns		  40 /        27

   2		0h:00m:01s		    -1.09ns		  64 /        27
   3		0h:00m:01s		    -0.75ns		  64 /        27


   4		0h:00m:01s		    -0.75ns		  64 /        27

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 191MB)

Writing Analyst data base E:\GWTW_stable\00_TechPub\51_DevBoard\DK-START-GW2A18\DK-START-GW2A18_LED_Blink\impl\synthesize\rev_1\synwork\IO_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)

@W:MT420 :  | Found inferred clock IO_test|clk with period 3.41ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug  6 14:42:55 2019
#


Top view:               IO_test
Requested Frequency:    293.5 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.601

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
IO_test|clk        293.5 MHz     249.5 MHz     3.407         4.008         -0.601     inferred     Autoconstr_clkgroup_0
System             150.0 MHz     259.4 MHz     6.667         3.855         2.811      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------
System       IO_test|clk  |  3.407       2.811   |  No paths    -      |  No paths    -      |  No paths    -    
IO_test|clk  System       |  3.407       2.629   |  No paths    -      |  No paths    -      |  No paths    -    
IO_test|clk  IO_test|clk  |  3.407       -0.601  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: IO_test|clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                         Arrival           
Instance        Reference       Type     Pin     Net             Time        Slack 
                Clock                                                              
-----------------------------------------------------------------------------------
clk_cnt[18]     IO_test|clk     DFFR     Q       clk_cnt[18]     0.243       -0.601
clk_cnt[17]     IO_test|clk     DFFR     Q       clk_cnt[17]     0.243       -0.580
clk_cnt[25]     IO_test|clk     DFFR     Q       clk_cnt[25]     0.243       -0.580
clk_cnt[24]     IO_test|clk     DFFR     Q       clk_cnt[24]     0.243       -0.559
clk_cnt[9]      IO_test|clk     DFFR     Q       clk_cnt[9]      0.243       -0.493
clk_cnt[20]     IO_test|clk     DFFR     Q       clk_cnt[20]     0.243       -0.493
clk_cnt[23]     IO_test|clk     DFFR     Q       clk_cnt[23]     0.243       -0.493
clk_cnt[1]      IO_test|clk     DFFR     Q       clk_cnt[1]      0.243       -0.476
clk_cnt[8]      IO_test|clk     DFFR     Q       clk_cnt[8]      0.243       -0.472
clk_cnt[19]     IO_test|clk     DFFR     Q       clk_cnt[19]     0.243       -0.472
===================================================================================


Ending Points with Worst Slack
******************************

               Starting                                                   Required           
Instance       Reference       Type     Pin       Net                     Time         Slack 
               Clock                                                                         
---------------------------------------------------------------------------------------------
clk_cnt[0]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[1]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[2]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[3]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[4]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[5]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[6]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[7]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[8]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
clk_cnt[9]     IO_test|clk     DFFR     RESET     clk_cnt11_0_N_3_mux     3.346        -0.601
=============================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      3.947
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.601

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            clk_cnt[0] / RESET
    The start point is clocked by            IO_test|clk [rising] on pin CLK
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net                      Pin       Pin               Arrival     No. of    
Name                       Type     Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[18]                DFFR     Q         Out     0.243     0.243       -         
clk_cnt[18]                Net      -         -       0.535     -           4         
G_14_0_a4_0_1              LUT4     I1        In      -         0.778       -         
G_14_0_a4_0_1              LUT4     F         Out     0.570     1.348       -         
G_14_0_a4_0_1              Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e_N_4L5     LUT3     I1        In      -         1.749       -         
clk_cnt11_0_m1_e_N_4L5     LUT3     F         Out     0.570     2.319       -         
clk_cnt11_0_m1_e_N_4L5     Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e           LUT4     I1        In      -         2.720       -         
clk_cnt11_0_m1_e           LUT4     F         Out     0.570     3.290       -         
clk_cnt11_0_N_3_mux        Net      -         -       0.657     -           27        
clk_cnt[0]                 DFFR     RESET     In      -         3.947       -         
======================================================================================
Total path delay (propagation time + setup) of 4.008 is 2.014(50.2%) logic and 1.994(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      3.947
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.601

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            led_1[0] / CE
    The start point is clocked by            IO_test|clk [rising] on pin CLK
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                       Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[18]                DFFR      Q        Out     0.243     0.243       -         
clk_cnt[18]                Net       -        -       0.535     -           4         
G_14_0_a4_0_1              LUT4      I1       In      -         0.778       -         
G_14_0_a4_0_1              LUT4      F        Out     0.570     1.348       -         
G_14_0_a4_0_1              Net       -        -       0.401     -           1         
clk_cnt11_0_m1_e_N_4L5     LUT3      I1       In      -         1.749       -         
clk_cnt11_0_m1_e_N_4L5     LUT3      F        Out     0.570     2.319       -         
clk_cnt11_0_m1_e_N_4L5     Net       -        -       0.401     -           1         
clk_cnt11_0_m1_e           LUT4      I1       In      -         2.720       -         
clk_cnt11_0_m1_e           LUT4      F        Out     0.570     3.290       -         
clk_cnt11_0_N_3_mux        Net       -        -       0.657     -           27        
led_1[0]                   DFFRE     CE       In      -         3.947       -         
======================================================================================
Total path delay (propagation time + setup) of 4.008 is 2.014(50.2%) logic and 1.994(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      3.947
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.601

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            clk_cnt[25] / RESET
    The start point is clocked by            IO_test|clk [rising] on pin CLK
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net                      Pin       Pin               Arrival     No. of    
Name                       Type     Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[18]                DFFR     Q         Out     0.243     0.243       -         
clk_cnt[18]                Net      -         -       0.535     -           4         
G_14_0_a4_0_1              LUT4     I1        In      -         0.778       -         
G_14_0_a4_0_1              LUT4     F         Out     0.570     1.348       -         
G_14_0_a4_0_1              Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e_N_4L5     LUT3     I1        In      -         1.749       -         
clk_cnt11_0_m1_e_N_4L5     LUT3     F         Out     0.570     2.319       -         
clk_cnt11_0_m1_e_N_4L5     Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e           LUT4     I1        In      -         2.720       -         
clk_cnt11_0_m1_e           LUT4     F         Out     0.570     3.290       -         
clk_cnt11_0_N_3_mux        Net      -         -       0.657     -           27        
clk_cnt[25]                DFFR     RESET     In      -         3.947       -         
======================================================================================
Total path delay (propagation time + setup) of 4.008 is 2.014(50.2%) logic and 1.994(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      3.947
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.601

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            clk_cnt[24] / RESET
    The start point is clocked by            IO_test|clk [rising] on pin CLK
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net                      Pin       Pin               Arrival     No. of    
Name                       Type     Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[18]                DFFR     Q         Out     0.243     0.243       -         
clk_cnt[18]                Net      -         -       0.535     -           4         
G_14_0_a4_0_1              LUT4     I1        In      -         0.778       -         
G_14_0_a4_0_1              LUT4     F         Out     0.570     1.348       -         
G_14_0_a4_0_1              Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e_N_4L5     LUT3     I1        In      -         1.749       -         
clk_cnt11_0_m1_e_N_4L5     LUT3     F         Out     0.570     2.319       -         
clk_cnt11_0_m1_e_N_4L5     Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e           LUT4     I1        In      -         2.720       -         
clk_cnt11_0_m1_e           LUT4     F         Out     0.570     3.290       -         
clk_cnt11_0_N_3_mux        Net      -         -       0.657     -           27        
clk_cnt[24]                DFFR     RESET     In      -         3.947       -         
======================================================================================
Total path delay (propagation time + setup) of 4.008 is 2.014(50.2%) logic and 1.994(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      3.947
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.601

    Number of logic level(s):                3
    Starting point:                          clk_cnt[18] / Q
    Ending point:                            clk_cnt[23] / RESET
    The start point is clocked by            IO_test|clk [rising] on pin CLK
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net                      Pin       Pin               Arrival     No. of    
Name                       Type     Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
clk_cnt[18]                DFFR     Q         Out     0.243     0.243       -         
clk_cnt[18]                Net      -         -       0.535     -           4         
G_14_0_a4_0_1              LUT4     I1        In      -         0.778       -         
G_14_0_a4_0_1              LUT4     F         Out     0.570     1.348       -         
G_14_0_a4_0_1              Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e_N_4L5     LUT3     I1        In      -         1.749       -         
clk_cnt11_0_m1_e_N_4L5     LUT3     F         Out     0.570     2.319       -         
clk_cnt11_0_m1_e_N_4L5     Net      -         -       0.401     -           1         
clk_cnt11_0_m1_e           LUT4     I1        In      -         2.720       -         
clk_cnt11_0_m1_e           LUT4     F         Out     0.570     3.290       -         
clk_cnt11_0_N_3_mux        Net      -         -       0.657     -           27        
clk_cnt[23]                DFFR     RESET     In      -         3.947       -         
======================================================================================
Total path delay (propagation time + setup) of 4.008 is 2.014(50.2%) logic and 1.994(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                 Starting                                       Arrival          
Instance         Reference     Type     Pin     Net             Time        Slack
                 Clock                                                           
---------------------------------------------------------------------------------
led_1_RNO[0]     System        INV      O       rst_n_c_i       0.000       2.811
led_1e[0]        System        INV      O       led_1e_0[0]     0.000       2.811
=================================================================================


Ending Points with Worst Slack
******************************

             Starting                                          Required          
Instance     Reference     Type      Pin       Net             Time         Slack
             Clock                                                               
---------------------------------------------------------------------------------
led_1[0]     System        DFFRE     D         led_1e_0[0]     3.346        2.811
led_1[0]     System        DFFRE     RESET     rst_n_c_i       3.346        2.811
=================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.407
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.346

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.811

    Number of logic level(s):                0
    Starting point:                          led_1_RNO[0] / O
    Ending point:                            led_1[0] / RESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            IO_test|clk [rising] on pin CLK

Instance / Net               Pin       Pin               Arrival     No. of    
Name               Type      Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
led_1_RNO[0]       INV       O         Out     0.000     0.000       -         
rst_n_c_i          Net       -         -       0.535     -           1         
led_1[0]           DFFRE     RESET     In      -         0.535       -         
===============================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB)

---------------------------------------
Resource Usage Report for IO_test 

Mapping to part: gw2a_18pbga256-8
Cell usage:
ALU             33 uses
DFFR            26 uses
DFFRE           1 use
GSR             1 use
INV             2 uses
LUT3            4 uses
LUT4            14 uses

I/O ports: 6
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   27 of 15552 (0%)
Total load per clock:
   IO_test|clk: 27

@S |Mapping Summary:
Total  LUTs: 18 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 191MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue Aug  6 14:42:55 2019

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