#Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018 #install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-HW-023 # Tue Jan 15 15:09:53 2019 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\user-bak\gqg\Desktop\LED_breath_test\src\LED_test.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module led_breath @N:CG364 : LED_test.v(1) | Synthesizing module led_breath in library work. @N:CG179 : LED_test.v(42) | Removing redundant assignment. @N:CG179 : LED_test.v(58) | Removing redundant assignment. @N:CG179 : LED_test.v(78) | Removing redundant assignment. Running optimization stage 1 on led_breath ....... @W:CL271 : LED_test.v(85) | Pruning unused bits 3 to 2 of pwm_on[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : LED_test.v(85) | Pruning register bit 1 of pwm_on[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on led_breath ....... @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(19) | Optimizing register bit delay_1us_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(35) | Optimizing register bit delay_1ms_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : LED_test.v(51) | Optimizing register bit delay_1s_cnt[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : LED_test.v(51) | Pruning register bits 15 to 10 of delay_1s_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : LED_test.v(35) | Pruning register bits 15 to 10 of delay_1ms_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : LED_test.v(19) | Pruning register bits 15 to 7 of delay_1us_cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 15 15:09:54 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta3 Install: D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-HW-023 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:43:27 @N: : | Running in 64-bit mode File E:\Demo_program\DK-START-GW1NR9\LED_breath_test\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling @N:NF107 : LED_test.v(1) | Selected library: work cell: led_breath view verilog as top level @N:NF107 : LED_test.v(1) | Selected library: work cell: led_breath view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 15 15:09:54 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 15 15:09:54 2019 ###########################################################]