Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | D:\user-bak\gqg\Desktop\LED_breath_test\impl\synthesize\rev_1\IO_test.vm |
Physical Constraints File | D:\user-bak\gqg\Desktop\LED_breath_test\src\LED_test.cst |
Timing Constraint File | --- |
Command Line | D:\Program Files\Gowin\Gowin_YunYuan_V1.8.3Beta\Pnr\bin\gowin.exe -do D:\user-bak\gqg\Desktop\LED_breath_test\impl\pnr\cmd.do |
GOWIN version | v1.8.3.01Beta |
Part Number | GW2AR-LV18EQ144C8/I7 |
Created Time | Tue Jan 15 15:11:20 2019 |
Legal Announcement | Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C |
Hold Delay Model | Fast 1.05V 0C |
Numbers of Paths Analyzed | 101 |
Numbers of Endpoints Analyzed | 89 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 264.216(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.215 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[0] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.550 |
2 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[2] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
3 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[5] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
4 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[8] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
5 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[1] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
6 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[4] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
7 | 6.240 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[3] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.525 |
8 | 6.247 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[6] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.518 |
9 | 6.247 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[9] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.518 |
10 | 6.247 | \delay_1ms_cnt_Z[0] /Q | \delay_1s_cnt[7] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.518 |
11 | 6.341 | \delay_1s_cnt[5] /Q | \pwm_on[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.424 |
12 | 6.343 | \delay_1s_cnt[4] /Q | display_mode_Z/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.422 |
13 | 6.359 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.406 |
14 | 6.471 | \delay_1s_cnt[0] /Q | \delay_1s_cnt[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.294 |
15 | 6.530 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.235 |
16 | 6.539 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.226 |
17 | 6.570 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.195 |
18 | 6.595 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.170 |
19 | 6.680 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.085 |
20 | 6.715 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.050 |
21 | 6.781 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.984 |
22 | 6.798 | \delay_1s_cnt[0] /Q | \delay_1s_cnt[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.967 |
23 | 6.904 | \delay_1ms_cnt_Z[6] /Q | \delay_1ms_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.861 |
24 | 6.931 | \delay_1s_cnt[0] /Q | \delay_1s_cnt[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.834 |
25 | 6.949 | \delay_1ms_cnt_Z[0] /Q | \delay_1ms_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.816 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.425 | \delay_1us_cnt_fast_Z[4] /Q | \delay_1us_cnt_fast_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436 |
2 | 0.425 | \delay_1us_cnt_fast_Z[6] /Q | \delay_1us_cnt_fast_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436 |
3 | 0.427 | \delay_1us_cnt_Z[1] /Q | \delay_1us_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
4 | 0.428 | \delay_1us_cnt_Z[0] /Q | \delay_1us_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.439 |
5 | 0.429 | \delay_1s_cnt[9] /Q | \delay_1s_cnt[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.440 |
6 | 0.432 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.443 |
7 | 0.485 | \delay_1us_cnt_Z[2] /Q | \delay_1us_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496 |
8 | 0.486 | \delay_1us_cnt_Z[6] /Q | \delay_1us_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.497 |
9 | 0.537 | display_mode_Z/Q | display_mode_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.548 |
10 | 0.537 | \delay_1us_cnt_fast_Z[5] /Q | \delay_1us_cnt_fast_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.548 |
11 | 0.552 | \delay_1us_cnt_Z[1] /Q | \delay_1us_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.563 |
12 | 0.559 | \delay_1us_cnt_Z[4] /Q | \delay_1us_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
13 | 0.559 | \delay_1us_cnt_Z[5] /Q | \delay_1us_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.570 |
14 | 0.569 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.580 |
15 | 0.630 | \delay_1s_cnt[9] /Q | \delay_1s_cnt[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.641 |
16 | 0.630 | \delay_1s_cnt[9] /Q | \delay_1s_cnt[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.641 |
17 | 0.674 | display_mode_Z/Q | \pwm_on[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
18 | 0.691 | \delay_1s_cnt[9] /Q | \delay_1s_cnt[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.702 |
19 | 0.703 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714 |
20 | 0.703 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714 |
21 | 0.703 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714 |
22 | 0.703 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714 |
23 | 0.703 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714 |
24 | 0.749 | \delay_1s_cnt[9] /Q | \delay_1s_cnt[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.760 |
25 | 0.750 | \delay_1ms_cnt_Z[4] /Q | \delay_1ms_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.761 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_fast_Z[6] |
2 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_fast_Z[4] |
3 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1s_cnt[6] |
4 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1ms_cnt_Z[8] |
5 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_Z[2] |
6 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_Z[3] |
7 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1ms_cnt_Z[9] |
8 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_Z[4] |
9 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1us_cnt_Z[5] |
10 | 3.120 | 4.120 | 1.000 | Low Pulse Width | DEFAULT_CLK | \delay_1s_cnt[7] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.215 |
Data Arrival Time | 6.570 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.570 | 0.714 | tNET | RR | 1 | R5C12[2][A] | \delay_1s_cnt[0] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C12[2][A] | \delay_1s_cnt[0] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[0] | |||
12.785 | -0.035 | tSu | 1 | R5C12[2][A] | \delay_1s_cnt[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 38.763%; route: 1.942, 54.702%; tC2Q: 0.232, 6.536% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path2
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[1][B] | \delay_1s_cnt[2] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[1][B] | \delay_1s_cnt[2] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[2] | |||
12.785 | -0.035 | tSu | 1 | R4C12[1][B] | \delay_1s_cnt[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path3
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[5] | |||
12.785 | -0.035 | tSu | 1 | R4C12[0][B] | \delay_1s_cnt[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path4
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[0][A] | \delay_1s_cnt[8] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[0][A] | \delay_1s_cnt[8] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[8] | |||
12.785 | -0.035 | tSu | 1 | R4C12[0][A] | \delay_1s_cnt[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path5
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[1][A] | \delay_1s_cnt[1] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[1][A] | \delay_1s_cnt[1] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[1] | |||
12.785 | -0.035 | tSu | 1 | R4C12[1][A] | \delay_1s_cnt[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path6
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[2][B] | \delay_1s_cnt[4] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[2][B] | \delay_1s_cnt[4] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[4] | |||
12.785 | -0.035 | tSu | 1 | R4C12[2][B] | \delay_1s_cnt[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path7
Path Summary:
Slack | 6.240 |
Data Arrival Time | 6.545 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.545 | 0.690 | tNET | RR | 1 | R4C12[2][A] | \delay_1s_cnt[3] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[2][A] | \delay_1s_cnt[3] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[3] | |||
12.785 | -0.035 | tSu | 1 | R4C12[2][A] | \delay_1s_cnt[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.035%; route: 1.917, 54.384%; tC2Q: 0.232, 6.581% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path8
Path Summary:
Slack | 6.247 |
Data Arrival Time | 6.538 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.538 | 0.683 | tNET | RR | 1 | R5C11[2][A] | \delay_1s_cnt[6] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C11[2][A] | \delay_1s_cnt[6] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[6] | |||
12.785 | -0.035 | tSu | 1 | R5C11[2][A] | \delay_1s_cnt[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.109%; route: 1.910, 54.297%; tC2Q: 0.232, 6.594% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path9
Path Summary:
Slack | 6.247 |
Data Arrival Time | 6.538 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.538 | 0.683 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[9] | |||
12.785 | -0.035 | tSu | 1 | R4C13[0][A] | \delay_1s_cnt[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.109%; route: 1.910, 54.297%; tC2Q: 0.232, 6.594% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path10
Path Summary:
Slack | 6.247 |
Data Arrival Time | 6.538 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1s_cnt[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.679 | 0.428 | tNET | FF | 1 | R4C9[0][B] | m3_e/I0 |
4.234 | 0.555 | tINS | FF | 1 | R4C9[0][B] | m3_e/F |
4.631 | 0.397 | tNET | FF | 1 | R4C8[0][A] | G_15_1_cZ/S0 |
4.882 | 0.251 | tINS | FF | 1 | R4C8[0][A] | G_15_1_cZ/O |
5.285 | 0.403 | tNET | FF | 1 | R4C7[3][B] | G_15/I0 |
5.855 | 0.570 | tINS | FR | 10 | R4C7[3][B] | G_15/F |
6.538 | 0.683 | tNET | RR | 1 | R5C11[2][B] | \delay_1s_cnt[7] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C11[2][B] | \delay_1s_cnt[7] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[7] | |||
12.785 | -0.035 | tSu | 1 | R5C11[2][B] | \delay_1s_cnt[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.376, 39.109%; route: 1.910, 54.297%; tC2Q: 0.232, 6.594% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path11
Path Summary:
Slack | 6.341 |
Data Arrival Time | 6.444 |
Data Required Time | 12.785 |
From | \delay_1s_cnt[5] |
To | \pwm_on[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R4C12[0][B] | \delay_1s_cnt[5] /Q |
4.153 | 0.901 | tNET | FF | 2 | R4C6[0][A] | un2_pwm_on_cry_5_0/I0 |
4.702 | 0.549 | tINS | FR | 1 | R4C6[0][A] | un2_pwm_on_cry_5_0/COUT |
4.702 | 0.000 | tNET | RR | 2 | R4C6[0][B] | un2_pwm_on_cry_6_0/CIN |
4.737 | 0.035 | tINS | RF | 1 | R4C6[0][B] | un2_pwm_on_cry_6_0/COUT |
4.737 | 0.000 | tNET | FF | 2 | R4C6[1][A] | un2_pwm_on_cry_7_0/CIN |
4.772 | 0.035 | tINS | FF | 1 | R4C6[1][A] | un2_pwm_on_cry_7_0/COUT |
4.772 | 0.000 | tNET | FF | 2 | R4C6[1][B] | un2_pwm_on_cry_8_0/CIN |
4.807 | 0.035 | tINS | FF | 1 | R4C6[1][B] | un2_pwm_on_cry_8_0/COUT |
4.807 | 0.000 | tNET | FF | 2 | R4C6[2][A] | un2_pwm_on_cry_9_0/CIN |
4.842 | 0.035 | tINS | FF | 1 | R4C6[2][A] | un2_pwm_on_cry_9_0/COUT |
6.073 | 1.231 | tNET | FF | 1 | R4C18[0][A] | \pwm_on_RNO[0] /I1 |
6.444 | 0.371 | tINS | FF | 1 | R4C18[0][A] | \pwm_on_RNO[0] /F |
6.444 | 0.000 | tNET | FF | 1 | R4C18[0][A] | \pwm_on[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C18[0][A] | \pwm_on[0] /CLK |
12.820 | -0.200 | tUnc | \pwm_on[0] | |||
12.785 | -0.035 | tSu | 1 | R4C18[0][A] | \pwm_on[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.061, 30.978%; route: 2.132, 62.247%; tC2Q: 0.232, 6.775% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path12
Path Summary:
Slack | 6.343 |
Data Arrival Time | 6.442 |
Data Required Time | 12.785 |
From | \delay_1s_cnt[4] |
To | display_mode_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R4C12[2][B] | \delay_1s_cnt[4] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R4C12[2][B] | \delay_1s_cnt[4] /Q |
3.919 | 0.667 | tNET | FF | 1 | R4C10[3][B] | m17_m5_0_a2_5_cZ/I1 |
4.474 | 0.555 | tINS | FF | 1 | R4C10[3][B] | m17_m5_0_a2_5_cZ/F |
4.887 | 0.413 | tNET | FF | 1 | R4C13[1][A] | m17_m5_0_a2_10_cZ/I3 |
5.436 | 0.549 | tINS | FR | 1 | R4C13[1][A] | m17_m5_0_a2_10_cZ/F |
5.437 | 0.001 | tNET | RR | 1 | R4C13[0][B] | m17_m5_0_a2/I3 |
5.764 | 0.327 | tINS | RR | 1 | R4C13[0][B] | m17_m5_0_a2/F |
6.442 | 0.678 | tNET | RR | 1 | R4C18[2][B] | display_mode_Z/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C18[2][B] | display_mode_Z/CLK |
12.820 | -0.200 | tUnc | display_mode_Z | |||
12.785 | -0.035 | tSu | 1 | R4C18[2][B] | display_mode_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.431, 41.813%; route: 1.759, 51.408%; tC2Q: 0.232, 6.779% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path13
Path Summary:
Slack | 6.359 |
Data Arrival Time | 6.426 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
4.652 | 0.035 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /COUT |
4.652 | 0.000 | tNET | FF | 2 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /CIN |
4.687 | 0.035 | tINS | FF | 1 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /COUT |
4.687 | 0.000 | tNET | FF | 2 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /CIN |
4.722 | 0.035 | tINS | FF | 1 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /COUT |
4.722 | 0.000 | tNET | FF | 2 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /CIN |
5.192 | 0.470 | tINS | FF | 1 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /SUM |
5.877 | 0.684 | tNET | FF | 1 | R4C7[1][B] | \delay_1ms_cnt_lm_0[7] /I3 |
6.426 | 0.549 | tINS | FR | 1 | R4C7[1][B] | \delay_1ms_cnt_lm_0[7] /F |
6.426 | 0.000 | tNET | RR | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[7] | |||
12.785 | -0.035 | tSu | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.800, 52.858%; route: 1.374, 40.330%; tC2Q: 0.232, 6.812% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path14
Path Summary:
Slack | 6.471 |
Data Arrival Time | 6.314 |
Data Required Time | 12.785 |
From | \delay_1s_cnt[0] |
To | \delay_1s_cnt[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C12[2][A] | \delay_1s_cnt[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 3 | R5C12[2][A] | \delay_1s_cnt[0] /Q |
3.823 | 0.571 | tNET | FF | 2 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /I0 |
4.393 | 0.570 | tINS | FR | 1 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /COUT |
4.393 | 0.000 | tNET | RR | 2 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /CIN |
4.428 | 0.035 | tINS | RF | 1 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /COUT |
4.428 | 0.000 | tNET | FF | 2 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /CIN |
4.463 | 0.035 | tINS | FF | 1 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /COUT |
4.463 | 0.000 | tNET | FF | 2 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /CIN |
4.498 | 0.035 | tINS | FF | 1 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /COUT |
4.498 | 0.000 | tNET | FF | 2 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /CIN |
4.534 | 0.035 | tINS | FF | 1 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /COUT |
4.534 | 0.000 | tNET | FF | 2 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /CIN |
4.569 | 0.035 | tINS | FF | 1 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /COUT |
4.569 | 0.000 | tNET | FF | 2 | R4C11[0][B] | \delay_1s_cnt_cry_0[6] /CIN |
4.604 | 0.035 | tINS | FF | 1 | R4C11[0][B] | \delay_1s_cnt_cry_0[6] /COUT |
4.604 | 0.000 | tNET | FF | 2 | R4C11[1][A] | \delay_1s_cnt_cry_0[7] /CIN |
4.639 | 0.035 | tINS | FF | 1 | R4C11[1][A] | \delay_1s_cnt_cry_0[7] /COUT |
4.639 | 0.000 | tNET | FF | 2 | R4C11[1][B] | \delay_1s_cnt_cry_0[8] /CIN |
5.109 | 0.470 | tINS | FF | 1 | R4C11[1][B] | \delay_1s_cnt_cry_0[8] /SUM |
5.765 | 0.656 | tNET | FF | 1 | R4C12[0][A] | \delay_1s_cnt_lm_0[8] /I1 |
6.314 | 0.549 | tINS | FR | 1 | R4C12[0][A] | \delay_1s_cnt_lm_0[8] /F |
6.314 | 0.000 | tNET | RR | 1 | R4C12[0][A] | \delay_1s_cnt[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[0][A] | \delay_1s_cnt[8] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[8] | |||
12.785 | -0.035 | tSu | 1 | R4C12[0][A] | \delay_1s_cnt[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.835, 55.716%; route: 1.227, 37.241%; tC2Q: 0.232, 7.043% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path15
Path Summary:
Slack | 6.530 |
Data Arrival Time | 6.255 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
4.652 | 0.035 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /COUT |
4.652 | 0.000 | tNET | FF | 2 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /CIN |
5.122 | 0.470 | tINS | FF | 1 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /SUM |
5.685 | 0.563 | tNET | FF | 1 | R4C7[1][A] | \delay_1ms_cnt_lm_0[5] /I3 |
6.255 | 0.570 | tINS | FR | 1 | R4C7[1][A] | \delay_1ms_cnt_lm_0[5] /F |
6.255 | 0.000 | tNET | RR | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[5] | |||
12.785 | -0.035 | tSu | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.751, 54.115%; route: 1.253, 38.714%; tC2Q: 0.232, 7.171% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path16
Path Summary:
Slack | 6.539 |
Data Arrival Time | 6.245 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
4.652 | 0.035 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /COUT |
4.652 | 0.000 | tNET | FF | 2 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /CIN |
4.687 | 0.035 | tINS | FF | 1 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /COUT |
4.687 | 0.000 | tNET | FF | 2 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /CIN |
5.157 | 0.470 | tINS | FF | 1 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /SUM |
5.675 | 0.518 | tNET | FF | 1 | R4C7[0][A] | \delay_1ms_cnt_lm_0[6] /I3 |
6.245 | 0.570 | tINS | FR | 1 | R4C7[0][A] | \delay_1ms_cnt_lm_0[6] /F |
6.245 | 0.000 | tNET | RR | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[6] | |||
12.785 | -0.035 | tSu | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.786, 55.371%; route: 1.208, 37.436%; tC2Q: 0.232, 7.193% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path17
Path Summary:
Slack | 6.570 |
Data Arrival Time | 6.214 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.981 | 0.470 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /SUM |
5.665 | 0.684 | tNET | FF | 1 | R5C10[2][B] | \delay_1ms_cnt_lm_0[1] /I3 |
6.214 | 0.549 | tINS | FR | 1 | R5C10[2][B] | \delay_1ms_cnt_lm_0[1] /F |
6.214 | 0.000 | tNET | RR | 1 | R5C10[2][B] | \delay_1ms_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C10[2][B] | \delay_1ms_cnt_Z[1] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[1] | |||
12.785 | -0.035 | tSu | 1 | R5C10[2][B] | \delay_1ms_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.589, 49.741%; route: 1.374, 42.997%; tC2Q: 0.232, 7.262% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path18
Path Summary:
Slack | 6.595 |
Data Arrival Time | 6.190 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
4.652 | 0.035 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /COUT |
4.652 | 0.000 | tNET | FF | 2 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /CIN |
4.687 | 0.035 | tINS | FF | 1 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /COUT |
4.687 | 0.000 | tNET | FF | 2 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /CIN |
4.722 | 0.035 | tINS | FF | 1 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /COUT |
4.722 | 0.000 | tNET | FF | 2 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /CIN |
4.758 | 0.035 | tINS | FF | 1 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /COUT |
4.758 | 0.000 | tNET | FF | 2 | R4C4[1][B] | \delay_1ms_cnt_cry_0[8] /CIN |
5.228 | 0.470 | tINS | FF | 1 | R4C4[1][B] | \delay_1ms_cnt_cry_0[8] /SUM |
5.641 | 0.413 | tNET | FF | 1 | R4C7[0][B] | \delay_1ms_cnt_lm_0[8] /I3 |
6.190 | 0.549 | tINS | FR | 1 | R4C7[0][B] | \delay_1ms_cnt_lm_0[8] /F |
6.190 | 0.000 | tNET | RR | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[8] | |||
12.785 | -0.035 | tSu | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.835, 57.898%; route: 1.103, 34.784%; tC2Q: 0.232, 7.318% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path19
Path Summary:
Slack | 6.680 |
Data Arrival Time | 6.104 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
5.016 | 0.470 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /SUM |
5.534 | 0.518 | tNET | FF | 1 | R4C9[0][A] | \delay_1ms_cnt_lm_0[2] /I3 |
6.104 | 0.570 | tINS | FR | 1 | R4C9[0][A] | \delay_1ms_cnt_lm_0[2] /F |
6.104 | 0.000 | tNET | RR | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[2] | |||
12.785 | -0.035 | tSu | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.645, 53.334%; route: 1.208, 39.145%; tC2Q: 0.232, 7.521% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path20
Path Summary:
Slack | 6.715 |
Data Arrival Time | 6.070 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
5.087 | 0.470 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /SUM |
5.500 | 0.413 | tNET | FF | 1 | R3C5[0][A] | \delay_1ms_cnt_lm_0[4] /I3 |
6.070 | 0.570 | tINS | FR | 1 | R3C5[0][A] | \delay_1ms_cnt_lm_0[4] /F |
6.070 | 0.000 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[4] | |||
12.785 | -0.035 | tSu | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.716, 56.244%; route: 1.103, 36.150%; tC2Q: 0.232, 7.606% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path21
Path Summary:
Slack | 6.781 |
Data Arrival Time | 6.003 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
4.617 | 0.035 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /COUT |
4.617 | 0.000 | tNET | FF | 2 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /CIN |
4.652 | 0.035 | tINS | FF | 1 | R4C3[2][B] | \delay_1ms_cnt_cry_0[4] /COUT |
4.652 | 0.000 | tNET | FF | 2 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /CIN |
4.687 | 0.035 | tINS | FF | 1 | R4C4[0][A] | \delay_1ms_cnt_cry_0[5] /COUT |
4.687 | 0.000 | tNET | FF | 2 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /CIN |
4.722 | 0.035 | tINS | FF | 1 | R4C4[0][B] | \delay_1ms_cnt_cry_0[6] /COUT |
4.722 | 0.000 | tNET | FF | 2 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /CIN |
4.758 | 0.035 | tINS | FF | 1 | R4C4[1][A] | \delay_1ms_cnt_cry_0[7] /COUT |
4.758 | 0.000 | tNET | FF | 2 | R4C4[1][B] | \delay_1ms_cnt_cry_0[8] /CIN |
4.793 | 0.035 | tINS | FF | 1 | R4C4[1][B] | \delay_1ms_cnt_cry_0[8] /COUT |
4.793 | 0.000 | tNET | FF | 2 | R4C4[2][A] | \delay_1ms_cnt_s_0[9] /CIN |
5.263 | 0.470 | tINS | FF | 1 | R4C4[2][A] | \delay_1ms_cnt_s_0[9] /SUM |
5.433 | 0.170 | tNET | FF | 1 | R3C4[0][A] | \delay_1ms_cnt_lm_0[9] /I3 |
6.003 | 0.570 | tINS | FR | 1 | R3C4[0][A] | \delay_1ms_cnt_lm_0[9] /F |
6.003 | 0.000 | tNET | RR | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[9] | |||
12.785 | -0.035 | tSu | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.892, 63.401%; route: 0.860, 28.823%; tC2Q: 0.232, 7.776% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path22
Path Summary:
Slack | 6.798 |
Data Arrival Time | 5.987 |
Data Required Time | 12.785 |
From | \delay_1s_cnt[0] |
To | \delay_1s_cnt[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C12[2][A] | \delay_1s_cnt[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 3 | R5C12[2][A] | \delay_1s_cnt[0] /Q |
3.823 | 0.571 | tNET | FF | 2 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /I0 |
4.393 | 0.570 | tINS | FR | 1 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /COUT |
4.393 | 0.000 | tNET | RR | 2 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /CIN |
4.428 | 0.035 | tINS | RF | 1 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /COUT |
4.428 | 0.000 | tNET | FF | 2 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /CIN |
4.463 | 0.035 | tINS | FF | 1 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /COUT |
4.463 | 0.000 | tNET | FF | 2 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /CIN |
4.498 | 0.035 | tINS | FF | 1 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /COUT |
4.498 | 0.000 | tNET | FF | 2 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /CIN |
4.534 | 0.035 | tINS | FF | 1 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /COUT |
4.534 | 0.000 | tNET | FF | 2 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /CIN |
5.004 | 0.470 | tINS | FF | 1 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /SUM |
5.417 | 0.413 | tNET | FF | 1 | R4C12[0][B] | \delay_1s_cnt_lm_0[5] /I1 |
5.987 | 0.570 | tINS | FR | 1 | R4C12[0][B] | \delay_1s_cnt_lm_0[5] /F |
5.987 | 0.000 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[5] | |||
12.785 | -0.035 | tSu | 1 | R4C12[0][B] | \delay_1s_cnt[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.751, 59.012%; route: 0.984, 33.169%; tC2Q: 0.232, 7.820% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path23
Path Summary:
Slack | 6.904 |
Data Arrival Time | 5.880 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[6] |
To | \delay_1ms_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /Q |
3.778 | 0.526 | tNET | FF | 1 | R4C4[3][A] | m4_e_RNO/I0 |
4.348 | 0.570 | tINS | FR | 1 | R4C4[3][A] | m4_e_RNO/F |
4.349 | 0.001 | tNET | RR | 1 | R4C4[3][B] | m4_e/I3 |
4.802 | 0.453 | tINS | RF | 10 | R4C4[3][B] | m4_e/F |
5.509 | 0.707 | tNET | FF | 1 | R5C10[2][A] | \delay_1ms_cnt_lm_0[0] /I1 |
5.880 | 0.371 | tINS | FF | 1 | R5C10[2][A] | \delay_1ms_cnt_lm_0[0] /F |
5.880 | 0.000 | tNET | FF | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[0] | |||
12.785 | -0.035 | tSu | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.394, 48.732%; route: 1.235, 43.158%; tC2Q: 0.232, 8.110% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path24
Path Summary:
Slack | 6.931 |
Data Arrival Time | 5.853 |
Data Required Time | 12.785 |
From | \delay_1s_cnt[0] |
To | \delay_1s_cnt[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C12[2][A] | \delay_1s_cnt[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 3 | R5C12[2][A] | \delay_1s_cnt[0] /Q |
3.823 | 0.571 | tNET | FF | 2 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /I0 |
4.393 | 0.570 | tINS | FR | 1 | R4C10[0][B] | \delay_1s_cnt_cry_0[0] /COUT |
4.393 | 0.000 | tNET | RR | 2 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /CIN |
4.428 | 0.035 | tINS | RF | 1 | R4C10[1][A] | \delay_1s_cnt_cry_0[1] /COUT |
4.428 | 0.000 | tNET | FF | 2 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /CIN |
4.463 | 0.035 | tINS | FF | 1 | R4C10[1][B] | \delay_1s_cnt_cry_0[2] /COUT |
4.463 | 0.000 | tNET | FF | 2 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /CIN |
4.498 | 0.035 | tINS | FF | 1 | R4C10[2][A] | \delay_1s_cnt_cry_0[3] /COUT |
4.498 | 0.000 | tNET | FF | 2 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /CIN |
4.534 | 0.035 | tINS | FF | 1 | R4C10[2][B] | \delay_1s_cnt_cry_0[4] /COUT |
4.534 | 0.000 | tNET | FF | 2 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /CIN |
4.569 | 0.035 | tINS | FF | 1 | R4C11[0][A] | \delay_1s_cnt_cry_0[5] /COUT |
4.569 | 0.000 | tNET | FF | 2 | R4C11[0][B] | \delay_1s_cnt_cry_0[6] /CIN |
4.604 | 0.035 | tINS | FF | 1 | R4C11[0][B] | \delay_1s_cnt_cry_0[6] /COUT |
4.604 | 0.000 | tNET | FF | 2 | R4C11[1][A] | \delay_1s_cnt_cry_0[7] /CIN |
4.639 | 0.035 | tINS | FF | 1 | R4C11[1][A] | \delay_1s_cnt_cry_0[7] /COUT |
4.639 | 0.000 | tNET | FF | 2 | R4C11[1][B] | \delay_1s_cnt_cry_0[8] /CIN |
4.674 | 0.035 | tINS | FF | 1 | R4C11[1][B] | \delay_1s_cnt_cry_0[8] /COUT |
4.674 | 0.000 | tNET | FF | 2 | R4C11[2][A] | \delay_1s_cnt_s_0[9] /CIN |
5.144 | 0.470 | tINS | FF | 1 | R4C11[2][A] | \delay_1s_cnt_s_0[9] /SUM |
5.391 | 0.247 | tNET | FF | 1 | R4C13[0][A] | \delay_1s_cnt_lm_0[9] /I1 |
5.853 | 0.462 | tINS | FR | 1 | R4C13[0][A] | \delay_1s_cnt_lm_0[9] /F |
5.853 | 0.000 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
12.820 | -0.200 | tUnc | \delay_1s_cnt[9] | |||
12.785 | -0.035 | tSu | 1 | R4C13[0][A] | \delay_1s_cnt[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.784, 62.944%; route: 0.818, 28.869%; tC2Q: 0.232, 8.187% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Path25
Path Summary:
Slack | 6.949 |
Data Arrival Time | 5.836 |
Data Required Time | 12.785 |
From | \delay_1ms_cnt_Z[0] |
To | \delay_1ms_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
3.020 | 2.337 | tNET | RR | 1 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /CLK |
3.252 | 0.232 | tC2Q | RF | 4 | R5C10[2][A] | \delay_1ms_cnt_Z[0] /Q |
3.941 | 0.689 | tNET | FF | 2 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /I0 |
4.511 | 0.570 | tINS | FR | 1 | R4C3[0][B] | \delay_1ms_cnt_cry_0[0] /COUT |
4.511 | 0.000 | tNET | RR | 2 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /CIN |
4.546 | 0.035 | tINS | RF | 1 | R4C3[1][A] | \delay_1ms_cnt_cry_0[1] /COUT |
4.546 | 0.000 | tNET | FF | 2 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /CIN |
4.582 | 0.035 | tINS | FF | 1 | R4C3[1][B] | \delay_1ms_cnt_cry_0[2] /COUT |
4.582 | 0.000 | tNET | FF | 2 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /CIN |
5.052 | 0.470 | tINS | FF | 1 | R4C3[2][A] | \delay_1ms_cnt_cry_0[3] /SUM |
5.465 | 0.413 | tNET | FF | 1 | R5C4[2][A] | \delay_1ms_cnt_lm_0[3] /I3 |
5.836 | 0.371 | tINS | FF | 1 | R5C4[2][A] | \delay_1ms_cnt_lm_0[3] /F |
5.836 | 0.000 | tNET | FF | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
13.020 | 2.337 | tNET | RR | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] /CLK |
12.820 | -0.200 | tUnc | \delay_1ms_cnt_Z[3] | |||
12.785 | -0.035 | tSu | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Arrival Data Path Delay | cell: 1.481, 52.605%; route: 1.103, 39.156%; tC2Q: 0.232, 8.238% |
Required Clock Path Delay | cell: 0.683, 22.601%; route: 2.337, 77.399% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.837 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_fast_Z[4] |
To | \delay_1us_cnt_fast_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[1][A] | \delay_1us_cnt_fast_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 3 | R4C18[1][A] | \delay_1us_cnt_fast_Z[4] /Q |
2.605 | 0.002 | tNET | RR | 1 | R4C18[1][A] | \delay_1us_cnt_3_fast_cZ[4] /I2 |
2.837 | 0.232 | tINS | RF | 1 | R4C18[1][A] | \delay_1us_cnt_3_fast_cZ[4] /F |
2.837 | 0.000 | tNET | FF | 1 | R4C18[1][A] | \delay_1us_cnt_fast_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[1][A] | \delay_1us_cnt_fast_Z[4] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_fast_Z[4] | |||
2.411 | 0.011 | tHld | 1 | R4C18[1][A] | \delay_1us_cnt_fast_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path2
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.837 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_fast_Z[6] |
To | \delay_1us_cnt_fast_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[0][A] | \delay_1us_cnt_fast_Z[6] /CLK |
2.602 | 0.202 | tC2Q | RR | 2 | R4C17[0][A] | \delay_1us_cnt_fast_Z[6] /Q |
2.605 | 0.002 | tNET | RR | 1 | R4C17[0][A] | \delay_1us_cnt_3_fast_cZ[6] /I2 |
2.837 | 0.232 | tINS | RF | 1 | R4C17[0][A] | \delay_1us_cnt_3_fast_cZ[6] /F |
2.837 | 0.000 | tNET | FF | 1 | R4C17[0][A] | \delay_1us_cnt_fast_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[0][A] | \delay_1us_cnt_fast_Z[6] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_fast_Z[6] | |||
2.411 | 0.011 | tHld | 1 | R4C17[0][A] | \delay_1us_cnt_fast_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path3
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.838 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[1] |
To | \delay_1us_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[1][A] | \delay_1us_cnt_Z[1] /CLK |
2.602 | 0.202 | tC2Q | RR | 4 | R4C17[1][A] | \delay_1us_cnt_Z[1] /Q |
2.606 | 0.004 | tNET | RR | 1 | R4C17[1][A] | un2_delay_1us_cnt_axbxc1_cZ/I1 |
2.838 | 0.232 | tINS | RF | 1 | R4C17[1][A] | un2_delay_1us_cnt_axbxc1_cZ/F |
2.838 | 0.000 | tNET | FF | 1 | R4C17[1][A] | \delay_1us_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[1][A] | \delay_1us_cnt_Z[1] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[1] | |||
2.411 | 0.011 | tHld | 1 | R4C17[1][A] | \delay_1us_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path4
Path Summary:
Slack | 0.428 |
Data Arrival Time | 2.839 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[0] |
To | \delay_1us_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C19[0][A] | \delay_1us_cnt_Z[0] /CLK |
2.602 | 0.202 | tC2Q | RR | 5 | R4C19[0][A] | \delay_1us_cnt_Z[0] /Q |
2.607 | 0.005 | tNET | RR | 1 | R4C19[0][A] | \delay_1us_cnt_RNO[0] /I0 |
2.839 | 0.232 | tINS | RF | 1 | R4C19[0][A] | \delay_1us_cnt_RNO[0] /F |
2.839 | 0.000 | tNET | FF | 1 | R4C19[0][A] | \delay_1us_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C19[0][A] | \delay_1us_cnt_Z[0] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[0] | |||
2.411 | 0.011 | tHld | 1 | R4C19[0][A] | \delay_1us_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path5
Path Summary:
Slack | 0.429 |
Data Arrival Time | 2.841 |
Data Required Time | 2.411 |
From | \delay_1s_cnt[9] |
To | \delay_1s_cnt[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.602 | 0.202 | tC2Q | RR | 13 | R4C13[0][A] | \delay_1s_cnt[9] /Q |
2.609 | 0.006 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt_lm_0[9] /I3 |
2.841 | 0.232 | tINS | RF | 1 | R4C13[0][A] | \delay_1s_cnt_lm_0[9] /F |
2.841 | 0.000 | tNET | FF | 1 | R4C13[0][A] | \delay_1s_cnt[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.400 | 0.000 | tUnc | \delay_1s_cnt[9] | |||
2.411 | 0.011 | tHld | 1 | R4C13[0][A] | \delay_1s_cnt[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path6
Path Summary:
Slack | 0.432 |
Data Arrival Time | 2.843 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.611 | 0.009 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_lm_0[4] /I2 |
2.843 | 0.232 | tINS | RF | 1 | R3C5[0][A] | \delay_1ms_cnt_lm_0[4] /F |
2.843 | 0.000 | tNET | FF | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[4] | |||
2.411 | 0.011 | tHld | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 52.423%; route: 0.009, 1.933%; tC2Q: 0.202, 45.644% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path7
Path Summary:
Slack | 0.485 |
Data Arrival Time | 2.896 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[2] |
To | \delay_1us_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C17[2][A] | \delay_1us_cnt_Z[2] /CLK |
2.602 | 0.202 | tC2Q | RR | 4 | R5C17[2][A] | \delay_1us_cnt_Z[2] /Q |
2.606 | 0.004 | tNET | RR | 1 | R5C17[2][A] | un2_delay_1us_cnt_axbxc2_cZ/I0 |
2.896 | 0.290 | tINS | RF | 1 | R5C17[2][A] | un2_delay_1us_cnt_axbxc2_cZ/F |
2.896 | 0.000 | tNET | FF | 1 | R5C17[2][A] | \delay_1us_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C17[2][A] | \delay_1us_cnt_Z[2] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[2] | |||
2.411 | 0.011 | tHld | 1 | R5C17[2][A] | \delay_1us_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path8
Path Summary:
Slack | 0.486 |
Data Arrival Time | 2.897 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[6] |
To | \delay_1us_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[2][A] | \delay_1us_cnt_Z[6] /CLK |
2.602 | 0.202 | tC2Q | RR | 4 | R4C17[2][A] | \delay_1us_cnt_Z[6] /Q |
2.607 | 0.005 | tNET | RR | 1 | R4C17[2][A] | \delay_1us_cnt_3_cZ[6] /I2 |
2.897 | 0.290 | tINS | RF | 1 | R4C17[2][A] | \delay_1us_cnt_3_cZ[6] /F |
2.897 | 0.000 | tNET | FF | 1 | R4C17[2][A] | \delay_1us_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[2][A] | \delay_1us_cnt_Z[6] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[6] | |||
2.411 | 0.011 | tHld | 1 | R4C17[2][A] | \delay_1us_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 58.363%; route: 0.005, 0.984%; tC2Q: 0.202, 40.653% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path9
Path Summary:
Slack | 0.537 |
Data Arrival Time | 2.949 |
Data Required Time | 2.411 |
From | display_mode_Z |
To | display_mode_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[2][B] | display_mode_Z/CLK |
2.602 | 0.202 | tC2Q | RR | 2 | R4C18[2][B] | display_mode_Z/Q |
2.605 | 0.002 | tNET | RR | 1 | R4C18[2][B] | display_mode_i_cZ/I0 |
2.949 | 0.344 | tINS | RF | 1 | R4C18[2][B] | display_mode_i_cZ/F |
2.949 | 0.000 | tNET | FF | 1 | R4C18[2][B] | display_mode_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[2][B] | display_mode_Z/CLK |
2.400 | 0.000 | tUnc | display_mode_Z | |||
2.411 | 0.011 | tHld | 1 | R4C18[2][B] | display_mode_Z |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.344, 62.723%; route: 0.002, 0.446%; tC2Q: 0.202, 36.831% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path10
Path Summary:
Slack | 0.537 |
Data Arrival Time | 2.949 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_fast_Z[5] |
To | \delay_1us_cnt_fast_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C17[2][B] | \delay_1us_cnt_fast_Z[5] /CLK |
2.602 | 0.202 | tC2Q | RR | 3 | R5C17[2][B] | \delay_1us_cnt_fast_Z[5] /Q |
2.605 | 0.002 | tNET | RR | 1 | R5C17[2][B] | un2_delay_1us_cnt_axbxc5_fast/I0 |
2.949 | 0.344 | tINS | RF | 1 | R5C17[2][B] | un2_delay_1us_cnt_axbxc5_fast/F |
2.949 | 0.000 | tNET | FF | 1 | R5C17[2][B] | \delay_1us_cnt_fast_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C17[2][B] | \delay_1us_cnt_fast_Z[5] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_fast_Z[5] | |||
2.411 | 0.011 | tHld | 1 | R5C17[2][B] | \delay_1us_cnt_fast_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.344, 62.723%; route: 0.002, 0.446%; tC2Q: 0.202, 36.831% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path11
Path Summary:
Slack | 0.552 |
Data Arrival Time | 2.963 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[1] |
To | \delay_1us_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[1][A] | \delay_1us_cnt_Z[1] /CLK |
2.602 | 0.202 | tC2Q | RR | 4 | R4C17[1][A] | \delay_1us_cnt_Z[1] /Q |
2.731 | 0.129 | tNET | RR | 1 | R4C18[1][B] | un2_delay_1us_cnt_axbxc3_cZ/I1 |
2.963 | 0.232 | tINS | RF | 1 | R4C18[1][B] | un2_delay_1us_cnt_axbxc3_cZ/F |
2.963 | 0.000 | tNET | FF | 1 | R4C18[1][B] | \delay_1us_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[1][B] | \delay_1us_cnt_Z[3] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[3] | |||
2.411 | 0.011 | tHld | 1 | R4C18[1][B] | \delay_1us_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 41.232%; route: 0.129, 22.867%; tC2Q: 0.202, 35.900% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path12
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.970 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[4] |
To | \delay_1us_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[0][B] | \delay_1us_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 5 | R4C18[0][B] | \delay_1us_cnt_Z[4] /Q |
2.606 | 0.004 | tNET | RR | 1 | R4C18[0][B] | \delay_1us_cnt_3_cZ[4] /I2 |
2.970 | 0.364 | tINS | RF | 1 | R4C18[0][B] | \delay_1us_cnt_3_cZ[4] /F |
2.970 | 0.000 | tNET | FF | 1 | R4C18[0][B] | \delay_1us_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[0][B] | \delay_1us_cnt_Z[4] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[4] | |||
2.411 | 0.011 | tHld | 1 | R4C18[0][B] | \delay_1us_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path13
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.970 |
Data Required Time | 2.411 |
From | \delay_1us_cnt_Z[5] |
To | \delay_1us_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[1][B] | \delay_1us_cnt_Z[5] /CLK |
2.602 | 0.202 | tC2Q | RR | 6 | R4C17[1][B] | \delay_1us_cnt_Z[5] /Q |
2.606 | 0.004 | tNET | RR | 1 | R4C17[1][B] | un2_delay_1us_cnt_axbxc5_cZ/I0 |
2.970 | 0.364 | tINS | RF | 1 | R4C17[1][B] | un2_delay_1us_cnt_axbxc5_cZ/F |
2.970 | 0.000 | tNET | FF | 1 | R4C17[1][B] | \delay_1us_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C17[1][B] | \delay_1us_cnt_Z[5] /CLK |
2.400 | 0.000 | tUnc | \delay_1us_cnt_Z[5] | |||
2.411 | 0.011 | tHld | 1 | R4C17[1][B] | \delay_1us_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path14
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.981 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.601 | 0.201 | tC2Q | RF | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.749 | 0.147 | tNET | FF | 1 | R3C4[0][A] | \delay_1ms_cnt_lm_0[9] /I2 |
2.981 | 0.232 | tINS | FF | 1 | R3C4[0][A] | \delay_1ms_cnt_lm_0[9] /F |
2.981 | 0.000 | tNET | FF | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[9] | |||
2.411 | 0.011 | tHld | 1 | R3C4[0][A] | \delay_1ms_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 39.987%; route: 0.147, 25.368%; tC2Q: 0.201, 34.644% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path15
Path Summary:
Slack | 0.630 |
Data Arrival Time | 3.042 |
Data Required Time | 2.411 |
From | \delay_1s_cnt[9] |
To | \delay_1s_cnt[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.602 | 0.202 | tC2Q | RR | 13 | R4C13[0][A] | \delay_1s_cnt[9] /Q |
2.752 | 0.149 | tNET | RR | 1 | R4C12[1][B] | \delay_1s_cnt_lm_0[2] /I3 |
3.042 | 0.290 | tINS | RF | 1 | R4C12[1][B] | \delay_1s_cnt_lm_0[2] /F |
3.042 | 0.000 | tNET | FF | 1 | R4C12[1][B] | \delay_1s_cnt[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C12[1][B] | \delay_1s_cnt[2] /CLK |
2.400 | 0.000 | tUnc | \delay_1s_cnt[2] | |||
2.411 | 0.011 | tHld | 1 | R4C12[1][B] | \delay_1s_cnt[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 45.234%; route: 0.149, 23.258%; tC2Q: 0.202, 31.508% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path16
Path Summary:
Slack | 0.630 |
Data Arrival Time | 3.042 |
Data Required Time | 2.411 |
From | \delay_1s_cnt[9] |
To | \delay_1s_cnt[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.602 | 0.202 | tC2Q | RR | 13 | R4C13[0][A] | \delay_1s_cnt[9] /Q |
2.752 | 0.149 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt_lm_0[5] /I3 |
3.042 | 0.290 | tINS | RF | 1 | R4C12[0][B] | \delay_1s_cnt_lm_0[5] /F |
3.042 | 0.000 | tNET | FF | 1 | R4C12[0][B] | \delay_1s_cnt[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C12[0][B] | \delay_1s_cnt[5] /CLK |
2.400 | 0.000 | tUnc | \delay_1s_cnt[5] | |||
2.411 | 0.011 | tHld | 1 | R4C12[0][B] | \delay_1s_cnt[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 45.234%; route: 0.149, 23.258%; tC2Q: 0.202, 31.508% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path17
Path Summary:
Slack | 0.674 |
Data Arrival Time | 3.086 |
Data Required Time | 2.411 |
From | display_mode_Z |
To | \pwm_on[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[2][B] | display_mode_Z/CLK |
2.601 | 0.201 | tC2Q | RF | 2 | R4C18[2][B] | display_mode_Z/Q |
2.722 | 0.120 | tNET | FF | 1 | R4C18[0][A] | \pwm_on_RNO[0] /I0 |
3.086 | 0.364 | tINS | FF | 1 | R4C18[0][A] | \pwm_on_RNO[0] /F |
3.086 | 0.000 | tNET | FF | 1 | R4C18[0][A] | \pwm_on[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C18[0][A] | \pwm_on[0] /CLK |
2.400 | 0.000 | tUnc | \pwm_on[0] | |||
2.411 | 0.011 | tHld | 1 | R4C18[0][A] | \pwm_on[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path18
Path Summary:
Slack | 0.691 |
Data Arrival Time | 3.102 |
Data Required Time | 2.411 |
From | \delay_1s_cnt[9] |
To | \delay_1s_cnt[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.602 | 0.202 | tC2Q | RR | 13 | R4C13[0][A] | \delay_1s_cnt[9] /Q |
2.870 | 0.268 | tNET | RR | 1 | R5C11[2][A] | \delay_1s_cnt_lm_0[6] /I3 |
3.102 | 0.232 | tINS | RF | 1 | R5C11[2][A] | \delay_1s_cnt_lm_0[6] /F |
3.102 | 0.000 | tNET | FF | 1 | R5C11[2][A] | \delay_1s_cnt[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C11[2][A] | \delay_1s_cnt[6] /CLK |
2.400 | 0.000 | tUnc | \delay_1s_cnt[6] | |||
2.411 | 0.011 | tHld | 1 | R5C11[2][A] | \delay_1s_cnt[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 33.067%; route: 0.268, 38.142%; tC2Q: 0.202, 28.791% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path19
Path Summary:
Slack | 0.703 |
Data Arrival Time | 3.114 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.882 | 0.280 | tNET | RR | 1 | R4C7[1][A] | \delay_1ms_cnt_lm_0[5] /I2 |
3.114 | 0.232 | tINS | RF | 1 | R4C7[1][A] | \delay_1ms_cnt_lm_0[5] /F |
3.114 | 0.000 | tNET | FF | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[5] | |||
2.411 | 0.011 | tHld | 1 | R4C7[1][A] | \delay_1ms_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 32.506%; route: 0.280, 39.192%; tC2Q: 0.202, 28.302% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path20
Path Summary:
Slack | 0.703 |
Data Arrival Time | 3.114 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.882 | 0.280 | tNET | RR | 1 | R4C7[1][B] | \delay_1ms_cnt_lm_0[7] /I2 |
3.114 | 0.232 | tINS | RF | 1 | R4C7[1][B] | \delay_1ms_cnt_lm_0[7] /F |
3.114 | 0.000 | tNET | FF | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[7] | |||
2.411 | 0.011 | tHld | 1 | R4C7[1][B] | \delay_1ms_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 32.506%; route: 0.280, 39.192%; tC2Q: 0.202, 28.302% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path21
Path Summary:
Slack | 0.703 |
Data Arrival Time | 3.114 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.882 | 0.280 | tNET | RR | 1 | R4C7[0][B] | \delay_1ms_cnt_lm_0[8] /I2 |
3.114 | 0.232 | tINS | RF | 1 | R4C7[0][B] | \delay_1ms_cnt_lm_0[8] /F |
3.114 | 0.000 | tNET | FF | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[8] | |||
2.411 | 0.011 | tHld | 1 | R4C7[0][B] | \delay_1ms_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 32.506%; route: 0.280, 39.192%; tC2Q: 0.202, 28.302% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path22
Path Summary:
Slack | 0.703 |
Data Arrival Time | 3.114 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.882 | 0.280 | tNET | RR | 1 | R4C7[0][A] | \delay_1ms_cnt_lm_0[6] /I2 |
3.114 | 0.232 | tINS | RF | 1 | R4C7[0][A] | \delay_1ms_cnt_lm_0[6] /F |
3.114 | 0.000 | tNET | FF | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[6] | |||
2.411 | 0.011 | tHld | 1 | R4C7[0][A] | \delay_1ms_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 32.506%; route: 0.280, 39.192%; tC2Q: 0.202, 28.302% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path23
Path Summary:
Slack | 0.703 |
Data Arrival Time | 3.114 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.882 | 0.280 | tNET | RR | 1 | R4C9[0][A] | \delay_1ms_cnt_lm_0[2] /I2 |
3.114 | 0.232 | tINS | RF | 1 | R4C9[0][A] | \delay_1ms_cnt_lm_0[2] /F |
3.114 | 0.000 | tNET | FF | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[2] | |||
2.411 | 0.011 | tHld | 1 | R4C9[0][A] | \delay_1ms_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.232, 32.502%; route: 0.280, 39.199%; tC2Q: 0.202, 28.299% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path24
Path Summary:
Slack | 0.749 |
Data Arrival Time | 3.160 |
Data Required Time | 2.411 |
From | \delay_1s_cnt[9] |
To | \delay_1s_cnt[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R4C13[0][A] | \delay_1s_cnt[9] /CLK |
2.602 | 0.202 | tC2Q | RR | 13 | R4C13[0][A] | \delay_1s_cnt[9] /Q |
2.870 | 0.268 | tNET | RR | 1 | R5C11[2][B] | \delay_1s_cnt_lm_0[7] /I3 |
3.160 | 0.290 | tINS | RF | 1 | R5C11[2][B] | \delay_1s_cnt_lm_0[7] /F |
3.160 | 0.000 | tNET | FF | 1 | R5C11[2][B] | \delay_1s_cnt[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C11[2][B] | \delay_1s_cnt[7] /CLK |
2.400 | 0.000 | tUnc | \delay_1s_cnt[7] | |||
2.411 | 0.011 | tHld | 1 | R5C11[2][B] | \delay_1s_cnt[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 38.177%; route: 0.268, 35.230%; tC2Q: 0.202, 26.593% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Path25
Path Summary:
Slack | 0.750 |
Data Arrival Time | 3.161 |
Data Required Time | 2.411 |
From | \delay_1ms_cnt_Z[4] |
To | \delay_1ms_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /CLK |
2.602 | 0.202 | tC2Q | RR | 14 | R3C5[0][A] | \delay_1ms_cnt_Z[4] /Q |
2.871 | 0.269 | tNET | RR | 1 | R5C4[2][A] | \delay_1ms_cnt_lm_0[3] /I2 |
3.161 | 0.290 | tINS | RF | 1 | R5C4[2][A] | \delay_1ms_cnt_lm_0[3] /F |
3.161 | 0.000 | tNET | FF | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 32 | IOL7[A] | clk_ibuf/O |
2.400 | 1.725 | tNET | RR | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] /CLK |
2.400 | 0.000 | tUnc | \delay_1ms_cnt_Z[3] | |||
2.411 | 0.011 | tHld | 1 | R5C4[2][A] | \delay_1ms_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Arrival Data Path Delay | cell: 0.290, 38.113%; route: 0.269, 35.339%; tC2Q: 0.202, 26.548% |
Required Clock Path Delay | cell: 0.675, 28.141%; route: 1.725, 71.859% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_fast_Z[6] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_fast_Z[6] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_fast_Z[6] /CLK |
MPW2
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_fast_Z[4] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_fast_Z[4] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_fast_Z[4] /CLK |
MPW3
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1s_cnt[6] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1s_cnt[6] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1s_cnt[6] /CLK |
MPW4
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1ms_cnt_Z[8] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1ms_cnt_Z[8] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1ms_cnt_Z[8] /CLK |
MPW5
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_Z[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_Z[2] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_Z[2] /CLK |
MPW6
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_Z[3] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_Z[3] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_Z[3] /CLK |
MPW7
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1ms_cnt_Z[9] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1ms_cnt_Z[9] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1ms_cnt_Z[9] /CLK |
MPW8
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_Z[4] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_Z[4] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_Z[4] /CLK |
MPW9
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1us_cnt_Z[5] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1us_cnt_Z[5] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1us_cnt_Z[5] /CLK |
MPW10
MPW Summary:
Slack: | 3.120 |
Actual Width: | 4.120 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \delay_1s_cnt[7] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
8.281 | 2.593 | tNET | FF | \delay_1s_cnt[7] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
12.400 | 1.725 | tNET | RR | \delay_1s_cnt[7] /CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
32 | clk_c | 6.215 | 2.593 |
14 | delay_1ms_cnt[4] | 6.482 | 0.708 |
13 | un2_pwm_on_9 | 6.552 | 0.862 |
11 | N_6_0 | 6.578 | 0.706 |
10 | N_33_mux | 6.760 | 0.707 |
10 | N_28 | 7.621 | 0.426 |
10 | delay_1ms | 6.215 | 0.839 |
10 | delay_1us_cnt9_i | 7.744 | 0.845 |
10 | m25_3 | 7.207 | 0.467 |
6 | delay_1us_cnt[5] | 7.456 | 0.501 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R4C11 | 0.431 |
R4C12 | 0.403 |
R4C4 | 0.347 |
R4C7 | 0.319 |
R4C10 | 0.264 |
R4C17 | 0.264 |
R4C6 | 0.194 |
R4C13 | 0.194 |
R4C5 | 0.167 |
R5C11 | 0.153 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|