#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-HW-017

# Tue Dec 10 11:00:11 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\src\LED_test.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module IO_test
@N:CG364 : LED_test.v(2) | Synthesizing module IO_test in library work.
@N:CG179 : LED_test.v(51) | Removing redundant assignment.
Running optimization stage 1 on IO_test .......
Running optimization stage 2 on IO_test .......
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[26] is always 0.
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[27] is always 0.
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[28] is always 0.
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[29] is always 0.
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[30] is always 0.
@N:CL189 : LED_test.v(21) | Register bit clk_cnt[31] is always 0.
@W:CL279 : LED_test.v(21) | Pruning register bits 31 to 26 of clk_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 10 11:00:15 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:NF107 : led_test.v(2) | Selected library: work cell: IO_test view verilog as top level
@N:NF107 : led_test.v(2) | Selected library: work cell: IO_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 86MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 10 11:00:17 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  LED_test_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 10 11:00:17 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
File E:\Gowin\Test_Project\DK-START-GW2A55-V1.1-V1.2\LED\LED_Blink\impl\synthesize\rev_1\synwork\LED_test_comp.srs changed - recompiling
@N:NF107 : led_test.v(2) | Selected library: work cell: IO_test view verilog as top level
@N:NF107 : led_test.v(2) | Selected library: work cell: IO_test view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 86MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 10 11:00:18 2019

###########################################################]


Premap Report



# Tue Dec 10 11:00:21 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  LED_test_scck.rpt
Printing clock  summary report in "E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\impl\synthesize\rev_1\LED_test_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 124MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 124MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 216MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)



Clock Summary
******************

          Start           Requested     Requested     Clock        Clock                     Clock
Level     Clock           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------
0 -       IO_test|clk     381.1 MHz     2.624         inferred     Autoconstr_clkgroup_0     31   
==================================================================================================



Clock Load Summary
***********************

                Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
Clock           Load      Pin           Seq Example     Seq Example       Comb Example 
---------------------------------------------------------------------------------------
IO_test|clk     31        clk(port)     T1S.C           -                 -            
=======================================================================================

@W:MT529 : led_test.v(44) | Found inferred clock IO_test|clk which controls 31 sequential elements including led_reg[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 31 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 port                   31         led_reg[3:0]   
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\impl\synthesize\rev_1\LED_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 218MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 218MB peak: 218MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 219MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Tue Dec 10 11:00:24 2019

###########################################################]


Map & Optimize Report



# Tue Dec 10 11:00:25 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-HW-017

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 214MB peak: 214MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 218MB peak: 218MB)

@N:MO231 : led_test.v(21) | Found counter in view:work.IO_test(verilog) instance clk_cnt[25:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 218MB peak: 218MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 219MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 221MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.07ns		  42 /        31

   2		0h:00m:01s		    -1.05ns		  69 /        31
   3		0h:00m:01s		    -1.18ns		  69 /        31
   4		0h:00m:01s		    -1.05ns		  70 /        31
   5		0h:00m:01s		    -1.32ns		  71 /        31
   6		0h:00m:01s		    -1.32ns		  72 /        31


   7		0h:00m:01s		    -1.05ns		  73 /        31

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 223MB)

Writing Analyst data base E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\impl\synthesize\rev_1\synwork\LED_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 223MB peak: 223MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 223MB peak: 223MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 222MB peak: 223MB)

@W:MT420 :  | Found inferred clock IO_test|clk with period 4.23ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Dec 10 11:00:29 2019
#


Top view:               IO_test
Requested Frequency:    236.6 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.746

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
IO_test|clk        236.6 MHz     201.1 MHz     4.226         4.972         -0.746     inferred     Autoconstr_clkgroup_0
System             150.0 MHz     329.3 MHz     6.667         3.036         3.630      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------
System       IO_test|clk  |  4.226       3.630   |  No paths    -      |  No paths    -      |  No paths    -    
IO_test|clk  IO_test|clk  |  4.226       -0.746  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found


##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 223MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 223MB)

---------------------------------------
Resource Usage Report for IO_test 

Mapping to part: gw2a_18pbga484-8
Cell usage:
ALU             26 uses
DFF             3 uses
DFFR            24 uses
DFFRE           1 use
DFFSE           3 uses
GSR             1 use
INV             1 use
MUX2_LUT5       2 uses
MUX2_LUT6       1 use
LUT2            2 uses
LUT3            6 uses
LUT4            20 uses

I/O ports: 6
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   31 of 15552 (0%)
Total load per clock:
   IO_test|clk: 31

@S |Mapping Summary:
Total  LUTs: 28 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 72MB peak: 223MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Dec 10 11:00:29 2019

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