Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\impl\synthesize\rev_1\LED_test.vm |
Physical Constraints File | E:\Gowin\Test_Project\DK-VIDEO-GW2A18-PG484-V1.1\LED_Blink\src\LED_test.cst |
Timing Constraint File | --- |
GOWIN version | V1.9.2.01Beta |
Part Number | GW2A-LV18PG484C8/I7 |
Created Time | Tue Dec 10 11:00:38 2019 |
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C |
Hold Delay Model | Fast 1.05V 0C |
Numbers of Paths Analyzed | 95 |
Numbers of Endpoints Analyzed | 67 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 214.993(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt[7] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
2 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[20] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
3 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[9] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
4 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[6] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
5 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[21] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
6 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt[16] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
7 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[8] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
8 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt[18] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
9 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt[17] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
10 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[5] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
11 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[19] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
12 | 5.349 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[4] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.416 |
13 | 5.352 | \clk_cnt_Z[9] /Q | \clk_cnt[25] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.413 |
14 | 5.352 | \clk_cnt_Z[9] /Q | \clk_cnt[24] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.413 |
15 | 5.352 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[23] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.413 |
16 | 5.352 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[22] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.413 |
17 | 5.356 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[3] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.409 |
18 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[15] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
19 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[14] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
20 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[11] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
21 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[10] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
22 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[13] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
23 | 5.376 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[12] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.389 |
24 | 5.703 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 4.062 |
25 | 5.980 | \clk_cnt[24] /Q | \clk_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 3.785 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.310 | \led_reg[3] /Q | \led_reg[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.321 |
2 | 0.557 | \clk_cnt[25] /Q | \clk_cnt[25] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
3 | 0.557 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[23] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
4 | 0.557 | \clk_cnt_Z[19] /Q | \clk_cnt_Z[19] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
5 | 0.557 | \clk_cnt[17] /Q | \clk_cnt[17] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
6 | 0.557 | \clk_cnt_Z[13] /Q | \clk_cnt_Z[13] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
7 | 0.557 | \clk_cnt_Z[11] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
8 | 0.557 | \clk_cnt[7] /Q | \clk_cnt[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
9 | 0.557 | \clk_cnt_Z[5] /Q | \clk_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.568 |
10 | 0.578 | T1S_Z/Q | \led_reg[3] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.589 |
11 | 0.578 | T1S_Z/Q | \led_reg[2] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.589 |
12 | 0.578 | T1S_Z/Q | \led_reg[1] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.589 |
13 | 0.578 | T1S_Z/Q | \led_reg[0] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.589 |
14 | 0.654 | \led_reg[2] /Q | \led_reg[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.665 |
15 | 0.659 | \led_reg[0] /Q | \led_reg[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.670 |
16 | 0.674 | \clk_cnt[18] /Q | \clk_cnt[18] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
17 | 0.674 | \clk_cnt[16] /Q | \clk_cnt[16] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
18 | 0.674 | \clk_cnt_Z[22] /Q | \clk_cnt_Z[22] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
19 | 0.674 | \clk_cnt_Z[10] /Q | \clk_cnt_Z[10] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
20 | 0.674 | \clk_cnt_Z[8] /Q | \clk_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
21 | 0.674 | \clk_cnt_Z[6] /Q | \clk_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
22 | 0.674 | \clk_cnt_Z[9] /Q | \clk_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
23 | 0.674 | \clk_cnt_Z[14] /Q | \clk_cnt_Z[14] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
24 | 0.674 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.685 |
25 | 0.678 | \clk_cnt_Z[21] /Q | \clk_cnt_Z[21] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.689 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \led_reg[0] |
2 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \led_reg[2] |
3 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[0] |
4 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[9] |
5 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt[25] |
6 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt[24] |
7 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[8] |
8 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[23] |
9 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[22] |
10 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[1] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[1][B] | \clk_cnt[7] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[1][B] | \clk_cnt[7] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[7] | |||
11.648 | -0.035 | tSu | 1 | R26C28[1][B] | \clk_cnt[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path2
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[2][A] | \clk_cnt_Z[20] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[2][A] | \clk_cnt_Z[20] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[20] | |||
11.648 | -0.035 | tSu | 1 | R26C30[2][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path3
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[9] | |||
11.648 | -0.035 | tSu | 1 | R26C28[2][B] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path4
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[1][A] | \clk_cnt_Z[6] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[1][A] | \clk_cnt_Z[6] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R26C28[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path5
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[2][B] | \clk_cnt_Z[21] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[2][B] | \clk_cnt_Z[21] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[21] | |||
11.648 | -0.035 | tSu | 1 | R26C30[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path6
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[0][A] | \clk_cnt[16] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[0][A] | \clk_cnt[16] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[16] | |||
11.648 | -0.035 | tSu | 1 | R26C30[0][A] | \clk_cnt[16] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path7
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[2][A] | \clk_cnt_Z[8] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[2][A] | \clk_cnt_Z[8] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[8] | |||
11.648 | -0.035 | tSu | 1 | R26C28[2][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path8
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[1][A] | \clk_cnt[18] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[1][A] | \clk_cnt[18] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[18] | |||
11.648 | -0.035 | tSu | 1 | R26C30[1][A] | \clk_cnt[18] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path9
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[0][B] | \clk_cnt[17] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[0][B] | \clk_cnt[17] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[17] | |||
11.648 | -0.035 | tSu | 1 | R26C30[0][B] | \clk_cnt[17] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path10
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[0][B] | \clk_cnt_Z[5] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[0][B] | \clk_cnt_Z[5] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[5] | |||
11.648 | -0.035 | tSu | 1 | R26C28[0][B] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path11
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C30[1][B] | \clk_cnt_Z[19] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C30[1][B] | \clk_cnt_Z[19] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[19] | |||
11.648 | -0.035 | tSu | 1 | R26C30[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path12
Path Summary:
Slack | 5.349 |
Data Arrival Time | 6.299 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.299 | 0.506 | tNET | RR | 1 | R26C28[0][A] | \clk_cnt_Z[4] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C28[0][A] | \clk_cnt_Z[4] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[4] | |||
11.648 | -0.035 | tSu | 1 | R26C28[0][A] | \clk_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.052%; route: 2.636, 59.695%; tC2Q: 0.232, 5.253% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path13
Path Summary:
Slack | 5.352 |
Data Arrival Time | 6.296 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.296 | 0.502 | tNET | RR | 1 | R26C31[1][B] | \clk_cnt[25] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C31[1][B] | \clk_cnt[25] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[25] | |||
11.648 | -0.035 | tSu | 1 | R26C31[1][B] | \clk_cnt[25] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.081%; route: 2.633, 59.661%; tC2Q: 0.232, 5.258% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path14
Path Summary:
Slack | 5.352 |
Data Arrival Time | 6.296 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.296 | 0.502 | tNET | RR | 1 | R26C31[1][A] | \clk_cnt[24] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C31[1][A] | \clk_cnt[24] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt[24] | |||
11.648 | -0.035 | tSu | 1 | R26C31[1][A] | \clk_cnt[24] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.081%; route: 2.633, 59.661%; tC2Q: 0.232, 5.258% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path15
Path Summary:
Slack | 5.352 |
Data Arrival Time | 6.296 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.296 | 0.502 | tNET | RR | 1 | R26C31[0][B] | \clk_cnt_Z[23] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C31[0][B] | \clk_cnt_Z[23] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[23] | |||
11.648 | -0.035 | tSu | 1 | R26C31[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.081%; route: 2.633, 59.661%; tC2Q: 0.232, 5.258% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path16
Path Summary:
Slack | 5.352 |
Data Arrival Time | 6.296 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.296 | 0.502 | tNET | RR | 1 | R26C31[0][A] | \clk_cnt_Z[22] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C31[0][A] | \clk_cnt_Z[22] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[22] | |||
11.648 | -0.035 | tSu | 1 | R26C31[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.081%; route: 2.633, 59.661%; tC2Q: 0.232, 5.258% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path17
Path Summary:
Slack | 5.356 |
Data Arrival Time | 6.292 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.292 | 0.499 | tNET | RR | 1 | R26C27[2][B] | \clk_cnt_Z[3] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C27[2][B] | \clk_cnt_Z[3] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R26C27[2][B] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.110%; route: 2.629, 59.628%; tC2Q: 0.232, 5.262% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path18
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[2][B] | \clk_cnt_Z[15] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[2][B] | \clk_cnt_Z[15] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[15] | |||
11.648 | -0.035 | tSu | 1 | R26C29[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path19
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[2][A] | \clk_cnt_Z[14] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[2][A] | \clk_cnt_Z[14] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[14] | |||
11.648 | -0.035 | tSu | 1 | R26C29[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path20
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[0][B] | \clk_cnt_Z[11] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[0][B] | \clk_cnt_Z[11] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[11] | |||
11.648 | -0.035 | tSu | 1 | R26C29[0][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path21
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[0][A] | \clk_cnt_Z[10] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[0][A] | \clk_cnt_Z[10] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[10] | |||
11.648 | -0.035 | tSu | 1 | R26C29[0][A] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path22
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[1][B] | \clk_cnt_Z[13] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[1][B] | \clk_cnt_Z[13] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[13] | |||
11.648 | -0.035 | tSu | 1 | R26C29[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path23
Path Summary:
Slack | 5.376 |
Data Arrival Time | 6.272 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.466 | 0.401 | tNET | FF | 1 | R27C29[1][B] | clk_cnt10_i_cZ/I2 |
5.793 | 0.327 | tINS | FR | 23 | R27C29[1][B] | clk_cnt10_i_cZ/F |
6.272 | 0.479 | tNET | RR | 1 | R26C29[1][A] | \clk_cnt_Z[12] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R26C29[1][A] | \clk_cnt_Z[12] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[12] | |||
11.648 | -0.035 | tSu | 1 | R26C29[1][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.548, 35.268%; route: 2.609, 59.447%; tC2Q: 0.232, 5.286% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path24
Path Summary:
Slack | 5.703 |
Data Arrival Time | 5.945 |
Data Required Time | 11.648 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
2.115 | 0.232 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
2.522 | 0.407 | tNET | FF | 1 | R27C28[2][A] | g0_6/I1 |
3.039 | 0.517 | tINS | FF | 2 | R27C28[2][A] | g0_6/F |
3.457 | 0.418 | tNET | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/S0 |
3.708 | 0.251 | tINS | FF | 1 | R29C29[2][B] | clk_cnt10_i_1_0_1_cZ/O |
4.612 | 0.904 | tNET | FF | 1 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/I1 |
5.065 | 0.453 | tINS | FF | 2 | R29C29[0][B] | clk_cnt10_i_1_0_cZ/F |
5.483 | 0.418 | tNET | FF | 1 | R27C28[1][A] | \clk_cntd[0] /I0 |
5.945 | 0.462 | tINS | FR | 1 | R27C28[1][A] | \clk_cntd[0] /F |
5.945 | 0.000 | tNET | RR | 1 | R27C28[1][A] | \clk_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R27C28[1][A] | \clk_cnt_Z[0] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R27C28[1][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.683, 41.438%; route: 2.147, 52.850%; tC2Q: 0.232, 5.712% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path25
Path Summary:
Slack | 5.980 |
Data Arrival Time | 5.668 |
Data Required Time | 11.648 |
From | \clk_cnt[24] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.883 | 1.201 | tNET | RR | 1 | R26C31[1][A] | \clk_cnt[24] /CLK |
2.115 | 0.232 | tC2Q | RF | 6 | R26C31[1][A] | \clk_cnt[24] /Q |
2.786 | 0.670 | tNET | FF | 1 | R27C28[3][A] | g0_0_0_a4_9_cZ/I3 |
3.157 | 0.371 | tINS | FF | 2 | R27C28[3][A] | g0_0_0_a4_9_cZ/F |
3.561 | 0.405 | tNET | FF | 1 | R29C28[0][B] | clk_cnt10_i_1_1_cZ/I3 |
3.932 | 0.371 | tINS | FF | 3 | R29C28[0][B] | clk_cnt10_i_1_1_cZ/F |
4.354 | 0.422 | tNET | FF | 1 | R27C29[2][A] | clk_cnt10_i_1_cZ/I0 |
4.924 | 0.570 | tINS | FR | 2 | R27C29[2][A] | clk_cnt10_i_1_cZ/F |
5.098 | 0.174 | tNET | RR | 1 | R27C28[0][A] | \clk_cntd[2] /I0 |
5.668 | 0.570 | tINS | RR | 1 | R27C28[0][A] | \clk_cntd[2] /F |
5.668 | 0.000 | tNET | RR | 1 | R27C28[0][A] | \clk_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R27C28[0][A] | \clk_cnt_Z[2] /CLK |
11.683 | -0.200 | tUnc | \clk_cnt_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R27C28[0][A] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Arrival Data Path Delay | cell: 1.882, 49.723%; route: 1.671, 44.147%; tC2Q: 0.232, 6.130% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.310 |
Data Arrival Time | 1.899 |
Data Required Time | 1.588 |
From | \led_reg[3] |
To | \led_reg[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][B] | \led_reg[3] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R27C30[0][B] | \led_reg[3] /Q |
1.899 | 0.120 | tNET | FF | 1 | R27C30[0][A] | \led_reg[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][A] | \led_reg[0] /CLK |
1.577 | 0.000 | tUnc | \led_reg[0] | |||
1.588 | 0.011 | tHld | 1 | R27C30[0][A] | \led_reg[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path2
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt[25] |
To | \clk_cnt[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[1][B] | \clk_cnt[25] /CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R26C31[1][B] | \clk_cnt[25] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C31[1][B] | \clk_cnt_s_0[25] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C31[1][B] | \clk_cnt_s_0[25] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C31[1][B] | \clk_cnt[25] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[1][B] | \clk_cnt[25] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt[25] | |||
1.588 | 0.011 | tHld | 1 | R26C31[1][B] | \clk_cnt[25] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path3
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[0][B] | \clk_cnt_Z[23] /CLK |
1.779 | 0.202 | tC2Q | RR | 2 | R26C31[0][B] | \clk_cnt_Z[23] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C31[0][B] | \clk_cnt_cry_0[23] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C31[0][B] | \clk_cnt_cry_0[23] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C31[0][B] | \clk_cnt_Z[23] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[0][B] | \clk_cnt_Z[23] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[23] | |||
1.588 | 0.011 | tHld | 1 | R26C31[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path4
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[19] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[1][B] | \clk_cnt_Z[19] /CLK |
1.779 | 0.202 | tC2Q | RR | 2 | R26C30[1][B] | \clk_cnt_Z[19] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C30[1][B] | \clk_cnt_cry_0[19] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C30[1][B] | \clk_cnt_cry_0[19] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C30[1][B] | \clk_cnt_Z[19] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[1][B] | \clk_cnt_Z[19] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[19] | |||
1.588 | 0.011 | tHld | 1 | R26C30[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path5
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt[17] |
To | \clk_cnt[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[0][B] | \clk_cnt[17] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R26C30[0][B] | \clk_cnt[17] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C30[0][B] | \clk_cnt_cry_0[17] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C30[0][B] | \clk_cnt_cry_0[17] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C30[0][B] | \clk_cnt[17] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[0][B] | \clk_cnt[17] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt[17] | |||
1.588 | 0.011 | tHld | 1 | R26C30[0][B] | \clk_cnt[17] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path6
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[13] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[1][B] | \clk_cnt_Z[13] /CLK |
1.779 | 0.202 | tC2Q | RR | 6 | R26C29[1][B] | \clk_cnt_Z[13] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C29[1][B] | \clk_cnt_cry_0[13] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C29[1][B] | \clk_cnt_cry_0[13] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C29[1][B] | \clk_cnt_Z[13] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[1][B] | \clk_cnt_Z[13] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[13] | |||
1.588 | 0.011 | tHld | 1 | R26C29[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path7
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[11] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[0][B] | \clk_cnt_Z[11] /CLK |
1.779 | 0.202 | tC2Q | RR | 3 | R26C29[0][B] | \clk_cnt_Z[11] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C29[0][B] | \clk_cnt_cry_0[11] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C29[0][B] | \clk_cnt_cry_0[11] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C29[0][B] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[0][B] | \clk_cnt_Z[11] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[11] | |||
1.588 | 0.011 | tHld | 1 | R26C29[0][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path8
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt[7] |
To | \clk_cnt[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[1][B] | \clk_cnt[7] /CLK |
1.779 | 0.202 | tC2Q | RR | 6 | R26C28[1][B] | \clk_cnt[7] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C28[1][B] | \clk_cnt_cry_0[7] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C28[1][B] | \clk_cnt_cry_0[7] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C28[1][B] | \clk_cnt[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[1][B] | \clk_cnt[7] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt[7] | |||
1.588 | 0.011 | tHld | 1 | R26C28[1][B] | \clk_cnt[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path9
Path Summary:
Slack | 0.557 |
Data Arrival Time | 2.146 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[5] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[0][B] | \clk_cnt_Z[5] /CLK |
1.779 | 0.202 | tC2Q | RR | 2 | R26C28[0][B] | \clk_cnt_Z[5] /Q |
1.782 | 0.002 | tNET | RR | 2 | R26C28[0][B] | \clk_cnt_cry_0[5] /I0 |
2.146 | 0.364 | tINS | RF | 1 | R26C28[0][B] | \clk_cnt_cry_0[5] /SUM |
2.146 | 0.000 | tNET | FF | 1 | R26C28[0][B] | \clk_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[0][B] | \clk_cnt_Z[5] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[5] | |||
1.588 | 0.011 | tHld | 1 | R26C28[0][B] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path10
Path Summary:
Slack | 0.578 |
Data Arrival Time | 2.166 |
Data Required Time | 1.588 |
From | T1S_Z |
To | \led_reg[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C29[1][A] | T1S_Z/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R27C29[1][A] | T1S_Z/Q |
2.166 | 0.387 | tNET | RR | 1 | R27C30[0][B] | \led_reg[3] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][B] | \led_reg[3] /CLK |
1.577 | 0.000 | tUnc | \led_reg[3] | |||
1.588 | 0.011 | tHld | 1 | R27C30[0][B] | \led_reg[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.695%; tC2Q: 0.202, 34.305% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path11
Path Summary:
Slack | 0.578 |
Data Arrival Time | 2.166 |
Data Required Time | 1.588 |
From | T1S_Z |
To | \led_reg[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C29[1][A] | T1S_Z/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R27C29[1][A] | T1S_Z/Q |
2.166 | 0.387 | tNET | RR | 1 | R27C30[1][A] | \led_reg[2] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[1][A] | \led_reg[2] /CLK |
1.577 | 0.000 | tUnc | \led_reg[2] | |||
1.588 | 0.011 | tHld | 1 | R27C30[1][A] | \led_reg[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.695%; tC2Q: 0.202, 34.305% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path12
Path Summary:
Slack | 0.578 |
Data Arrival Time | 2.166 |
Data Required Time | 1.588 |
From | T1S_Z |
To | \led_reg[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C29[1][A] | T1S_Z/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R27C29[1][A] | T1S_Z/Q |
2.166 | 0.387 | tNET | RR | 1 | R27C30[1][B] | \led_reg[1] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[1][B] | \led_reg[1] /CLK |
1.577 | 0.000 | tUnc | \led_reg[1] | |||
1.588 | 0.011 | tHld | 1 | R27C30[1][B] | \led_reg[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.695%; tC2Q: 0.202, 34.305% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path13
Path Summary:
Slack | 0.578 |
Data Arrival Time | 2.166 |
Data Required Time | 1.588 |
From | T1S_Z |
To | \led_reg[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C29[1][A] | T1S_Z/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R27C29[1][A] | T1S_Z/Q |
2.166 | 0.387 | tNET | RR | 1 | R27C30[0][A] | \led_reg[0] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][A] | \led_reg[0] /CLK |
1.577 | 0.000 | tUnc | \led_reg[0] | |||
1.588 | 0.011 | tHld | 1 | R27C30[0][A] | \led_reg[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.695%; tC2Q: 0.202, 34.305% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path14
Path Summary:
Slack | 0.654 |
Data Arrival Time | 2.243 |
Data Required Time | 1.588 |
From | \led_reg[2] |
To | \led_reg[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[1][A] | \led_reg[2] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R27C30[1][A] | \led_reg[2] /Q |
2.243 | 0.464 | tNET | FF | 1 | R27C30[0][B] | \led_reg[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][B] | \led_reg[3] /CLK |
1.577 | 0.000 | tUnc | \led_reg[3] | |||
1.588 | 0.011 | tHld | 1 | R27C30[0][B] | \led_reg[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.464, 69.786%; tC2Q: 0.201, 30.214% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path15
Path Summary:
Slack | 0.659 |
Data Arrival Time | 2.248 |
Data Required Time | 1.588 |
From | \led_reg[0] |
To | \led_reg[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[0][A] | \led_reg[0] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R27C30[0][A] | \led_reg[0] /Q |
2.248 | 0.469 | tNET | FF | 1 | R27C30[1][B] | \led_reg[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R27C30[1][B] | \led_reg[1] /CLK |
1.577 | 0.000 | tUnc | \led_reg[1] | |||
1.588 | 0.011 | tHld | 1 | R27C30[1][B] | \led_reg[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.469, 70.008%; tC2Q: 0.201, 29.992% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path16
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt[18] |
To | \clk_cnt[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[1][A] | \clk_cnt[18] /CLK |
1.778 | 0.201 | tC2Q | RF | 5 | R26C30[1][A] | \clk_cnt[18] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C30[1][A] | \clk_cnt_cry_0[18] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C30[1][A] | \clk_cnt_cry_0[18] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C30[1][A] | \clk_cnt[18] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[1][A] | \clk_cnt[18] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt[18] | |||
1.588 | 0.011 | tHld | 1 | R26C30[1][A] | \clk_cnt[18] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path17
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt[16] |
To | \clk_cnt[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[0][A] | \clk_cnt[16] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R26C30[0][A] | \clk_cnt[16] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C30[0][A] | \clk_cnt_cry_0[16] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C30[0][A] | \clk_cnt_cry_0[16] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C30[0][A] | \clk_cnt[16] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[0][A] | \clk_cnt[16] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt[16] | |||
1.588 | 0.011 | tHld | 1 | R26C30[0][A] | \clk_cnt[16] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path18
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[22] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[0][A] | \clk_cnt_Z[22] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R26C31[0][A] | \clk_cnt_Z[22] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C31[0][A] | \clk_cnt_cry_0[22] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C31[0][A] | \clk_cnt_cry_0[22] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C31[0][A] | \clk_cnt_Z[22] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C31[0][A] | \clk_cnt_Z[22] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[22] | |||
1.588 | 0.011 | tHld | 1 | R26C31[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path19
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[10] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[0][A] | \clk_cnt_Z[10] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R26C29[0][A] | \clk_cnt_Z[10] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C29[0][A] | \clk_cnt_cry_0[10] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C29[0][A] | \clk_cnt_cry_0[10] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C29[0][A] | \clk_cnt_Z[10] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[0][A] | \clk_cnt_Z[10] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[10] | |||
1.588 | 0.011 | tHld | 1 | R26C29[0][A] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path20
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[8] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[2][A] | \clk_cnt_Z[8] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R26C28[2][A] | \clk_cnt_Z[8] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C28[2][A] | \clk_cnt_cry_0[8] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C28[2][A] | \clk_cnt_cry_0[8] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C28[2][A] | \clk_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[2][A] | \clk_cnt_Z[8] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[8] | |||
1.588 | 0.011 | tHld | 1 | R26C28[2][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path21
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[6] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[1][A] | \clk_cnt_Z[6] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R26C28[1][A] | \clk_cnt_Z[6] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C28[1][A] | \clk_cnt_cry_0[6] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C28[1][A] | \clk_cnt_cry_0[6] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C28[1][A] | \clk_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[1][A] | \clk_cnt_Z[6] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[6] | |||
1.588 | 0.011 | tHld | 1 | R26C28[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path22
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[9] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
1.778 | 0.201 | tC2Q | RF | 3 | R26C28[2][B] | \clk_cnt_Z[9] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C28[2][B] | \clk_cnt_cry_0[9] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C28[2][B] | \clk_cnt_cry_0[9] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C28[2][B] | \clk_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C28[2][B] | \clk_cnt_Z[9] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[9] | |||
1.588 | 0.011 | tHld | 1 | R26C28[2][B] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path23
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[14] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[2][A] | \clk_cnt_Z[14] /CLK |
1.778 | 0.201 | tC2Q | RF | 6 | R26C29[2][A] | \clk_cnt_Z[14] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C29[2][A] | \clk_cnt_cry_0[14] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C29[2][A] | \clk_cnt_cry_0[14] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C29[2][A] | \clk_cnt_Z[14] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[2][A] | \clk_cnt_Z[14] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[14] | |||
1.588 | 0.011 | tHld | 1 | R26C29[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path24
Path Summary:
Slack | 0.674 |
Data Arrival Time | 2.263 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[1][A] | \clk_cnt_Z[12] /CLK |
1.778 | 0.201 | tC2Q | RF | 4 | R26C29[1][A] | \clk_cnt_Z[12] /Q |
1.899 | 0.120 | tNET | FF | 2 | R26C29[1][A] | \clk_cnt_cry_0[12] /I0 |
2.263 | 0.364 | tINS | FF | 1 | R26C29[1][A] | \clk_cnt_cry_0[12] /SUM |
2.263 | 0.000 | tNET | FF | 1 | R26C29[1][A] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C29[1][A] | \clk_cnt_Z[12] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[12] | |||
1.588 | 0.011 | tHld | 1 | R26C29[1][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path25
Path Summary:
Slack | 0.678 |
Data Arrival Time | 2.266 |
Data Required Time | 1.588 |
From | \clk_cnt_Z[21] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[2][B] | \clk_cnt_Z[21] /CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R26C30[2][B] | \clk_cnt_Z[21] /Q |
1.902 | 0.124 | tNET | FF | 2 | R26C30[2][B] | \clk_cnt_cry_0[21] /I0 |
2.266 | 0.364 | tINS | FF | 1 | R26C30[2][B] | \clk_cnt_cry_0[21] /SUM |
2.266 | 0.000 | tNET | FF | 1 | R26C30[2][B] | \clk_cnt_Z[21] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 31 | IOR27[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R26C30[2][B] | \clk_cnt_Z[21] /CLK |
1.577 | 0.000 | tUnc | \clk_cnt_Z[21] | |||
1.588 | 0.011 | tHld | 1 | R26C30[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.364, 52.855%; route: 0.124, 17.958%; tC2Q: 0.201, 29.187% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \led_reg[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \led_reg[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \led_reg[0] /CLK |
MPW2
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \led_reg[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \led_reg[2] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \led_reg[2] /CLK |
MPW3
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[0] /CLK |
MPW4
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[9] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[9] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[9] /CLK |
MPW5
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt[25] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt[25] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt[25] /CLK |
MPW6
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt[24] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt[24] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt[24] /CLK |
MPW7
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[8] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[8] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[8] /CLK |
MPW8
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[23] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[23] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[23] /CLK |
MPW9
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[22] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[22] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[22] /CLK |
MPW10
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[1] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | \clk_cnt_Z[1] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | \clk_cnt_Z[1] /CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
31 | clk_c | 5.349 | 1.228 |
23 | clk_cnt10_i | 5.349 | 0.580 |
6 | clk_cnt[13] | 5.780 | 0.438 |
6 | clk_cnt[14] | 5.665 | 0.515 |
6 | clk_cnt[15] | 5.844 | 0.588 |
6 | un3lto24 | 5.980 | 0.670 |
6 | un3lto7 | 5.680 | 0.684 |
5 | un3lto18 | 6.089 | 0.427 |
4 | T1S | 9.062 | 0.546 |
4 | clk_cnt10_i_1 | 6.711 | 0.571 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R26C28 | 0.278 |
R26C29 | 0.264 |
R27C29 | 0.194 |
R27C28 | 0.194 |
R26C30 | 0.181 |
R27C30 | 0.181 |
R29C29 | 0.153 |
R29C28 | 0.153 |
R26C31 | 0.125 |
R26C27 | 0.097 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|