Project Settings
Project Name LED_test Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 15 1 0 - 00m:06s - 2019/12/10
11:00:17
(premap)Complete 5 1 0 0m:01s 0m:02s 219MB 2019/12/10
11:00:24
(fpga_mapper)Complete 10 1 0 0m:04s 0m:04s 223MB 2019/12/10
11:00:29
Multi-srs Generator Complete2019/12/10
11:00:18

Area Summary
I/O ports (io_port) 6 Non I/O Register bits (non_io_reg) 31 (0%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 0 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 28 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
IO_test|clk236.6 MHz201.1 MHz-0.746
System150.0 MHz329.3 MHz3.630

Optimizations Summary
Combined Clock Conversion 1 / 0