Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPADDSUB\data\FP_Add_Sub.v
C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPADDSUB\data\FP_Add_Sub_wrap.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-1
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Tue May 16 17:42:57 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module FP_Add_Sub_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 29.859MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 29.859MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 29.859MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 29.859MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 29.859MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 29.859MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 29.859MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 29.859MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 29.859MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 29.859MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 29.859MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 29.859MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 46.625MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 46.625MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 46.625MB
Total Time and Memory Usage CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 46.625MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 103
I/O Buf 103
    IBUF 67
    OBUF 36
Register 182
    DFFCE 182
LUT 1168
    LUT2 86
    LUT3 443
    LUT4 639
ALU 95
    ALU 95
INV 1
    INV 1
DSP 1
    ALU54D 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1264(1169 LUTs, 95 ALUs) / 54720 3%
Register 182 / 41997 <1%
  --Register as Latch 0 / 41997 0%
  --Register as FF 182 / 41997 <1%
BSRAM 0 / 140 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 86.3(MHz) 17 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.585
Data Arrival Time 12.413
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_28_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.970 0.470 tINS FF 3 FP_Add_Sub_inst/n788_s/SUM
3.207 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s17/I1
3.762 0.555 tINS FF 4 FP_Add_Sub_inst/shift_num_4_s17/F
3.999 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s30/I0
4.516 0.517 tINS FF 1 FP_Add_Sub_inst/shift_num_2_s30/F
4.753 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s11/I3
5.124 0.371 tINS FF 2 FP_Add_Sub_inst/shift_num_2_s11/F
5.361 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s9/I1
5.916 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s9/F
6.153 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I1
6.708 0.555 tINS FF 9 FP_Add_Sub_inst/shift_num_0_s5/F
6.945 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s4/I1
7.500 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_1_s4/F
7.737 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s3/I1
8.292 0.555 tINS FF 2 FP_Add_Sub_inst/shift_num_1_s3/F
8.529 0.237 tNET FF 1 FP_Add_Sub_inst/n1218_s8/I1
9.084 0.555 tINS FF 7 FP_Add_Sub_inst/n1218_s8/F
9.321 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s8/I0
9.838 0.517 tINS FF 1 FP_Add_Sub_inst/n1210_s8/F
10.075 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s4/I0
10.592 0.517 tINS FF 2 FP_Add_Sub_inst/n1210_s4/F
10.829 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s2/I1
11.384 0.555 tINS FF 1 FP_Add_Sub_inst/n1210_s2/F
11.621 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s0/I1
12.176 0.555 tINS FF 1 FP_Add_Sub_inst/n1210_s0/F
12.413 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_28_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_28_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_28_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.000, 69.265%; route: 3.318, 28.726%; tC2Q: 0.232, 2.009%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -1.521
Data Arrival Time 12.349
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.970 0.470 tINS FF 3 FP_Add_Sub_inst/n788_s/SUM
3.207 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s17/I1
3.762 0.555 tINS FF 4 FP_Add_Sub_inst/shift_num_4_s17/F
3.999 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s30/I0
4.516 0.517 tINS FF 1 FP_Add_Sub_inst/shift_num_2_s30/F
4.753 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s11/I3
5.124 0.371 tINS FF 2 FP_Add_Sub_inst/shift_num_2_s11/F
5.361 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s9/I1
5.916 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s9/F
6.153 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I1
6.708 0.555 tINS FF 9 FP_Add_Sub_inst/shift_num_0_s5/F
6.945 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s4/I1
7.500 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_1_s4/F
7.737 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s3/I1
8.292 0.555 tINS FF 2 FP_Add_Sub_inst/shift_num_1_s3/F
8.529 0.237 tNET FF 1 FP_Add_Sub_inst/n1218_s8/I1
9.084 0.555 tINS FF 7 FP_Add_Sub_inst/n1218_s8/F
9.321 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s9/I0
9.838 0.517 tINS FF 1 FP_Add_Sub_inst/n1214_s9/F
10.075 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s4/I2
10.528 0.453 tINS FF 2 FP_Add_Sub_inst/n1214_s4/F
10.765 0.237 tNET FF 1 FP_Add_Sub_inst/n1230_s2/I1
11.320 0.555 tINS FF 1 FP_Add_Sub_inst/n1230_s2/F
11.557 0.237 tNET FF 1 FP_Add_Sub_inst/n1230_s0/I1
12.112 0.555 tINS FF 1 FP_Add_Sub_inst/n1230_s0/F
12.349 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_8_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.936, 69.094%; route: 3.318, 28.886%; tC2Q: 0.232, 2.020%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -1.521
Data Arrival Time 12.349
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.970 0.470 tINS FF 3 FP_Add_Sub_inst/n788_s/SUM
3.207 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s17/I1
3.762 0.555 tINS FF 4 FP_Add_Sub_inst/shift_num_4_s17/F
3.999 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s30/I0
4.516 0.517 tINS FF 1 FP_Add_Sub_inst/shift_num_2_s30/F
4.753 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s11/I3
5.124 0.371 tINS FF 2 FP_Add_Sub_inst/shift_num_2_s11/F
5.361 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s9/I1
5.916 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s9/F
6.153 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I1
6.708 0.555 tINS FF 9 FP_Add_Sub_inst/shift_num_0_s5/F
6.945 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s4/I1
7.500 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_1_s4/F
7.737 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s3/I1
8.292 0.555 tINS FF 2 FP_Add_Sub_inst/shift_num_1_s3/F
8.529 0.237 tNET FF 1 FP_Add_Sub_inst/n1218_s8/I1
9.084 0.555 tINS FF 7 FP_Add_Sub_inst/n1218_s8/F
9.321 0.237 tNET FF 1 FP_Add_Sub_inst/n1213_s6/I0
9.838 0.517 tINS FF 1 FP_Add_Sub_inst/n1213_s6/F
10.075 0.237 tNET FF 1 FP_Add_Sub_inst/n1213_s4/I2
10.528 0.453 tINS FF 2 FP_Add_Sub_inst/n1213_s4/F
10.765 0.237 tNET FF 1 FP_Add_Sub_inst/n1229_s2/I1
11.320 0.555 tINS FF 1 FP_Add_Sub_inst/n1229_s2/F
11.557 0.237 tNET FF 1 FP_Add_Sub_inst/n1229_s0/I1
12.112 0.555 tINS FF 1 FP_Add_Sub_inst/n1229_s0/F
12.349 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_9_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.936, 69.094%; route: 3.318, 28.886%; tC2Q: 0.232, 2.020%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -1.483
Data Arrival Time 12.311
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.970 0.470 tINS FF 3 FP_Add_Sub_inst/n788_s/SUM
3.207 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s17/I1
3.762 0.555 tINS FF 4 FP_Add_Sub_inst/shift_num_4_s17/F
3.999 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s30/I0
4.516 0.517 tINS FF 1 FP_Add_Sub_inst/shift_num_2_s30/F
4.753 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s11/I3
5.124 0.371 tINS FF 2 FP_Add_Sub_inst/shift_num_2_s11/F
5.361 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s9/I1
5.916 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s9/F
6.153 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I1
6.708 0.555 tINS FF 9 FP_Add_Sub_inst/shift_num_0_s5/F
6.945 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s4/I1
7.500 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_1_s4/F
7.737 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s3/I1
8.292 0.555 tINS FF 2 FP_Add_Sub_inst/shift_num_1_s3/F
8.529 0.237 tNET FF 1 FP_Add_Sub_inst/n1218_s8/I1
9.084 0.555 tINS FF 7 FP_Add_Sub_inst/n1218_s8/F
9.321 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s8/I0
9.838 0.517 tINS FF 1 FP_Add_Sub_inst/n1210_s8/F
10.075 0.237 tNET FF 1 FP_Add_Sub_inst/n1210_s4/I0
10.592 0.517 tINS FF 2 FP_Add_Sub_inst/n1210_s4/F
10.829 0.237 tNET FF 1 FP_Add_Sub_inst/n1226_s2/I2
11.282 0.453 tINS FF 1 FP_Add_Sub_inst/n1226_s2/F
11.519 0.237 tNET FF 1 FP_Add_Sub_inst/n1226_s0/I1
12.074 0.555 tINS FF 1 FP_Add_Sub_inst/n1226_s0/F
12.311 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_12_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.898, 68.992%; route: 3.318, 28.982%; tC2Q: 0.232, 2.026%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -1.483
Data Arrival Time 12.311
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_24_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.970 0.470 tINS FF 3 FP_Add_Sub_inst/n788_s/SUM
3.207 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s17/I1
3.762 0.555 tINS FF 4 FP_Add_Sub_inst/shift_num_4_s17/F
3.999 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s30/I0
4.516 0.517 tINS FF 1 FP_Add_Sub_inst/shift_num_2_s30/F
4.753 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_2_s11/I3
5.124 0.371 tINS FF 2 FP_Add_Sub_inst/shift_num_2_s11/F
5.361 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s9/I1
5.916 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s9/F
6.153 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I1
6.708 0.555 tINS FF 9 FP_Add_Sub_inst/shift_num_0_s5/F
6.945 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s4/I1
7.500 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_1_s4/F
7.737 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_1_s3/I1
8.292 0.555 tINS FF 2 FP_Add_Sub_inst/shift_num_1_s3/F
8.529 0.237 tNET FF 1 FP_Add_Sub_inst/n1218_s8/I1
9.084 0.555 tINS FF 7 FP_Add_Sub_inst/n1218_s8/F
9.321 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s9/I0
9.838 0.517 tINS FF 1 FP_Add_Sub_inst/n1214_s9/F
10.075 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s4/I2
10.528 0.453 tINS FF 2 FP_Add_Sub_inst/n1214_s4/F
10.765 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s2/I0
11.282 0.517 tINS FF 1 FP_Add_Sub_inst/n1214_s2/F
11.519 0.237 tNET FF 1 FP_Add_Sub_inst/n1214_s0/I1
12.074 0.555 tINS FF 1 FP_Add_Sub_inst/n1214_s0/F
12.311 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_24_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_24_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.898, 68.992%; route: 3.318, 28.982%; tC2Q: 0.232, 2.026%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%