Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPMULT\data\FP_Mult.v C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPMULT\data\FP_Mult_wrap.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-1 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Tue May 16 17:52:02 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | FP_Mult_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 29.625MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 29.625MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 29.625MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 29.625MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 29.625MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 29.625MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 29.625MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 29.625MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 29.625MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 29.625MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 29.625MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 29.625MB Tech-Mapping Phase 3: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 46.070MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 46.070MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 46.070MB |
Total Time and Memory Usage | CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 46.070MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 102 |
I/O Buf | 102 |
    IBUF | 66 |
    OBUF | 36 |
Register | 134 |
    DFFP | 4 |
    DFFC | 129 |
    DFFCE | 1 |
LUT | 1147 |
    LUT2 | 87 |
    LUT3 | 429 |
    LUT4 | 631 |
ALU | 28 |
    ALU | 28 |
INV | 3 |
    INV | 3 |
DSP | 1 |
    MULT36X36 | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1178(1150 LUTs, 28 ALUs) / 54720 | 3% |
Register | 134 / 41997 | <1% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 134 / 41997 | <1% |
BSRAM | 0 / 140 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 76.7(MHz) | 18 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -3.034 |
Data Arrival Time | 13.861 |
Data Required Time | 10.828 |
From | FP_Mult_inst/mant_prod_r_36_s0 |
To | FP_Mult_inst/round_mant_r_18_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/mant_prod_r_36_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | FP_Mult_inst/mant_prod_r_36_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s1/I1 |
1.887 | 0.555 | tINS | FF | 4 | FP_Mult_inst/P0/shift_num0_3_s1/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s/I1 |
2.679 | 0.555 | tINS | FF | 23 | FP_Mult_inst/P0/shift_num0_3_s/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s1/I1 |
3.471 | 0.555 | tINS | FF | 65 | FP_Mult_inst/P0/shift_num0_0_s1/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s10/I3 |
4.079 | 0.371 | tINS | FF | 13 | FP_Mult_inst/P0/shift_num0_0_s10/F |
4.316 | 0.237 | tNET | FF | 2 | FP_Mult_inst/n712_s/I1 |
4.886 | 0.570 | tINS | FR | 1 | FP_Mult_inst/n712_s/COUT |
4.886 | 0.000 | tNET | RR | 2 | FP_Mult_inst/n711_s/CIN |
4.921 | 0.035 | tINS | RF | 1 | FP_Mult_inst/n711_s/COUT |
4.921 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n710_s/CIN |
4.956 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n710_s/COUT |
4.956 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n709_s/CIN |
4.991 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n709_s/COUT |
4.991 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n708_s/CIN |
5.026 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n708_s/COUT |
5.026 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n707_s/CIN |
5.496 | 0.470 | tINS | FF | 4 | FP_Mult_inst/n707_s/SUM |
5.733 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1173_s13/I1 |
6.288 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1173_s13/F |
6.525 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s6/I3 |
6.896 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1179_s6/F |
7.133 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s3/I0 |
7.650 | 0.517 | tINS | FF | 51 | FP_Mult_inst/n1179_s3/F |
7.887 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1186_s22/I1 |
8.442 | 0.555 | tINS | FF | 3 | FP_Mult_inst/n1186_s22/F |
8.679 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s12/I3 |
9.050 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1191_s12/F |
9.287 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s5/I1 |
9.842 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1191_s5/F |
10.079 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s2/I2 |
10.532 | 0.453 | tINS | FF | 3 | FP_Mult_inst/n1191_s2/F |
10.769 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1190_s6/I0 |
11.286 | 0.517 | tINS | FF | 3 | FP_Mult_inst/n1190_s6/F |
11.523 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1175_s11/I0 |
12.040 | 0.517 | tINS | FF | 6 | FP_Mult_inst/n1175_s11/F |
12.277 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1188_s2/I1 |
12.832 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1188_s2/F |
13.069 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1188_s1/I1 |
13.624 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1188_s1/F |
13.861 | 0.237 | tNET | FF | 1 | FP_Mult_inst/round_mant_r_18_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/round_mant_r_18_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Mult_inst/round_mant_r_18_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.738, 67.220%; route: 4.029, 30.995%; tC2Q: 0.232, 1.785% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | -2.970 |
Data Arrival Time | 13.797 |
Data Required Time | 10.828 |
From | FP_Mult_inst/mant_prod_r_36_s0 |
To | FP_Mult_inst/round_mant_r_17_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/mant_prod_r_36_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | FP_Mult_inst/mant_prod_r_36_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s1/I1 |
1.887 | 0.555 | tINS | FF | 4 | FP_Mult_inst/P0/shift_num0_3_s1/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s/I1 |
2.679 | 0.555 | tINS | FF | 23 | FP_Mult_inst/P0/shift_num0_3_s/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s1/I1 |
3.471 | 0.555 | tINS | FF | 65 | FP_Mult_inst/P0/shift_num0_0_s1/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s10/I3 |
4.079 | 0.371 | tINS | FF | 13 | FP_Mult_inst/P0/shift_num0_0_s10/F |
4.316 | 0.237 | tNET | FF | 2 | FP_Mult_inst/n712_s/I1 |
4.886 | 0.570 | tINS | FR | 1 | FP_Mult_inst/n712_s/COUT |
4.886 | 0.000 | tNET | RR | 2 | FP_Mult_inst/n711_s/CIN |
4.921 | 0.035 | tINS | RF | 1 | FP_Mult_inst/n711_s/COUT |
4.921 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n710_s/CIN |
4.956 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n710_s/COUT |
4.956 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n709_s/CIN |
4.991 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n709_s/COUT |
4.991 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n708_s/CIN |
5.026 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n708_s/COUT |
5.026 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n707_s/CIN |
5.496 | 0.470 | tINS | FF | 4 | FP_Mult_inst/n707_s/SUM |
5.733 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1173_s13/I1 |
6.288 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1173_s13/F |
6.525 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s6/I3 |
6.896 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1179_s6/F |
7.133 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s3/I0 |
7.650 | 0.517 | tINS | FF | 51 | FP_Mult_inst/n1179_s3/F |
7.887 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1186_s22/I1 |
8.442 | 0.555 | tINS | FF | 3 | FP_Mult_inst/n1186_s22/F |
8.679 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s12/I3 |
9.050 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1191_s12/F |
9.287 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s5/I1 |
9.842 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1191_s5/F |
10.079 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s2/I2 |
10.532 | 0.453 | tINS | FF | 3 | FP_Mult_inst/n1191_s2/F |
10.769 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1190_s6/I0 |
11.286 | 0.517 | tINS | FF | 3 | FP_Mult_inst/n1190_s6/F |
11.523 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1189_s10/I1 |
12.078 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1189_s10/F |
12.315 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1189_s2/I2 |
12.768 | 0.453 | tINS | FF | 1 | FP_Mult_inst/n1189_s2/F |
13.005 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1189_s1/I1 |
13.560 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1189_s1/F |
13.797 | 0.237 | tNET | FF | 1 | FP_Mult_inst/round_mant_r_17_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/round_mant_r_17_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Mult_inst/round_mant_r_17_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.674, 67.057%; route: 4.029, 31.149%; tC2Q: 0.232, 1.794% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | -2.932 |
Data Arrival Time | 13.759 |
Data Required Time | 10.828 |
From | FP_Mult_inst/mant_prod_r_36_s0 |
To | FP_Mult_inst/round_exp_r_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/mant_prod_r_36_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | FP_Mult_inst/mant_prod_r_36_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s1/I1 |
1.887 | 0.555 | tINS | FF | 4 | FP_Mult_inst/P0/shift_num0_3_s1/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s/I1 |
2.679 | 0.555 | tINS | FF | 23 | FP_Mult_inst/P0/shift_num0_3_s/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s1/I1 |
3.471 | 0.555 | tINS | FF | 65 | FP_Mult_inst/P0/shift_num0_0_s1/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s10/I3 |
4.079 | 0.371 | tINS | FF | 13 | FP_Mult_inst/P0/shift_num0_0_s10/F |
4.316 | 0.237 | tNET | FF | 2 | FP_Mult_inst/n712_s/I1 |
4.886 | 0.570 | tINS | FR | 1 | FP_Mult_inst/n712_s/COUT |
4.886 | 0.000 | tNET | RR | 2 | FP_Mult_inst/n711_s/CIN |
4.921 | 0.035 | tINS | RF | 1 | FP_Mult_inst/n711_s/COUT |
4.921 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n710_s/CIN |
4.956 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n710_s/COUT |
4.956 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n709_s/CIN |
4.991 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n709_s/COUT |
4.991 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n708_s/CIN |
5.026 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n708_s/COUT |
5.026 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n707_s/CIN |
5.496 | 0.470 | tINS | FF | 4 | FP_Mult_inst/n707_s/SUM |
5.733 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1173_s13/I1 |
6.288 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1173_s13/F |
6.525 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s6/I3 |
6.896 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1179_s6/F |
7.133 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s3/I0 |
7.650 | 0.517 | tINS | FF | 51 | FP_Mult_inst/n1179_s3/F |
7.887 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1186_s22/I1 |
8.442 | 0.555 | tINS | FF | 3 | FP_Mult_inst/n1186_s22/F |
8.679 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s12/I3 |
9.050 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1191_s12/F |
9.287 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s5/I1 |
9.842 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1191_s5/F |
10.079 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1191_s2/I2 |
10.532 | 0.453 | tINS | FF | 3 | FP_Mult_inst/n1191_s2/F |
10.769 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1190_s6/I0 |
11.286 | 0.517 | tINS | FF | 3 | FP_Mult_inst/n1190_s6/F |
11.523 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1175_s11/I0 |
12.040 | 0.517 | tINS | FF | 6 | FP_Mult_inst/n1175_s11/F |
12.277 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1182_s2/I1 |
12.832 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1182_s2/F |
13.069 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1182_s1/I2 |
13.522 | 0.453 | tINS | FF | 1 | FP_Mult_inst/n1182_s1/F |
13.759 | 0.237 | tNET | FF | 1 | FP_Mult_inst/round_exp_r_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/round_exp_r_0_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Mult_inst/round_exp_r_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.636, 66.961%; route: 4.029, 31.240%; tC2Q: 0.232, 1.799% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | -2.850 |
Data Arrival Time | 13.677 |
Data Required Time | 10.828 |
From | FP_Mult_inst/mant_prod_r_36_s0 |
To | FP_Mult_inst/round_mant_r_5_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/mant_prod_r_36_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | FP_Mult_inst/mant_prod_r_36_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s1/I1 |
1.887 | 0.555 | tINS | FF | 4 | FP_Mult_inst/P0/shift_num0_3_s1/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s/I1 |
2.679 | 0.555 | tINS | FF | 23 | FP_Mult_inst/P0/shift_num0_3_s/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s1/I1 |
3.471 | 0.555 | tINS | FF | 65 | FP_Mult_inst/P0/shift_num0_0_s1/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s10/I3 |
4.079 | 0.371 | tINS | FF | 13 | FP_Mult_inst/P0/shift_num0_0_s10/F |
4.316 | 0.237 | tNET | FF | 2 | FP_Mult_inst/n712_s/I1 |
4.886 | 0.570 | tINS | FR | 1 | FP_Mult_inst/n712_s/COUT |
4.886 | 0.000 | tNET | RR | 2 | FP_Mult_inst/n711_s/CIN |
4.921 | 0.035 | tINS | RF | 1 | FP_Mult_inst/n711_s/COUT |
4.921 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n710_s/CIN |
4.956 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n710_s/COUT |
4.956 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n709_s/CIN |
4.991 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n709_s/COUT |
4.991 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n708_s/CIN |
5.026 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n708_s/COUT |
5.026 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n707_s/CIN |
5.496 | 0.470 | tINS | FF | 4 | FP_Mult_inst/n707_s/SUM |
5.733 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1173_s13/I1 |
6.288 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1173_s13/F |
6.525 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s6/I3 |
6.896 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1179_s6/F |
7.133 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s3/I0 |
7.650 | 0.517 | tINS | FF | 51 | FP_Mult_inst/n1179_s3/F |
7.887 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s53/I1 |
8.442 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1205_s53/F |
8.679 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s33/I3 |
9.050 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1205_s33/F |
9.287 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s20/I0 |
9.804 | 0.517 | tINS | FF | 1 | FP_Mult_inst/n1205_s20/F |
10.041 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s8/I2 |
10.494 | 0.453 | tINS | FF | 5 | FP_Mult_inst/n1205_s8/F |
10.731 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s3/I3 |
11.102 | 0.371 | tINS | FF | 5 | FP_Mult_inst/n1205_s3/F |
11.339 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1202_s3/I0 |
11.856 | 0.517 | tINS | FF | 14 | FP_Mult_inst/n1202_s3/F |
12.093 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1201_s2/I1 |
12.648 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1201_s2/F |
12.885 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1201_s1/I1 |
13.440 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1201_s1/F |
13.677 | 0.237 | tNET | FF | 1 | FP_Mult_inst/round_mant_r_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/round_mant_r_5_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Mult_inst/round_mant_r_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.554, 66.750%; route: 4.029, 31.440%; tC2Q: 0.232, 1.810% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | -2.850 |
Data Arrival Time | 13.677 |
Data Required Time | 10.828 |
From | FP_Mult_inst/mant_prod_r_36_s0 |
To | FP_Mult_inst/round_mant_r_6_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/mant_prod_r_36_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | FP_Mult_inst/mant_prod_r_36_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s1/I1 |
1.887 | 0.555 | tINS | FF | 4 | FP_Mult_inst/P0/shift_num0_3_s1/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_3_s/I1 |
2.679 | 0.555 | tINS | FF | 23 | FP_Mult_inst/P0/shift_num0_3_s/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s1/I1 |
3.471 | 0.555 | tINS | FF | 65 | FP_Mult_inst/P0/shift_num0_0_s1/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Mult_inst/P0/shift_num0_0_s10/I3 |
4.079 | 0.371 | tINS | FF | 13 | FP_Mult_inst/P0/shift_num0_0_s10/F |
4.316 | 0.237 | tNET | FF | 2 | FP_Mult_inst/n712_s/I1 |
4.886 | 0.570 | tINS | FR | 1 | FP_Mult_inst/n712_s/COUT |
4.886 | 0.000 | tNET | RR | 2 | FP_Mult_inst/n711_s/CIN |
4.921 | 0.035 | tINS | RF | 1 | FP_Mult_inst/n711_s/COUT |
4.921 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n710_s/CIN |
4.956 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n710_s/COUT |
4.956 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n709_s/CIN |
4.991 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n709_s/COUT |
4.991 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n708_s/CIN |
5.026 | 0.035 | tINS | FF | 1 | FP_Mult_inst/n708_s/COUT |
5.026 | 0.000 | tNET | FF | 2 | FP_Mult_inst/n707_s/CIN |
5.496 | 0.470 | tINS | FF | 4 | FP_Mult_inst/n707_s/SUM |
5.733 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1173_s13/I1 |
6.288 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1173_s13/F |
6.525 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s6/I3 |
6.896 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1179_s6/F |
7.133 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1179_s3/I0 |
7.650 | 0.517 | tINS | FF | 51 | FP_Mult_inst/n1179_s3/F |
7.887 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s53/I1 |
8.442 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1205_s53/F |
8.679 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s33/I3 |
9.050 | 0.371 | tINS | FF | 1 | FP_Mult_inst/n1205_s33/F |
9.287 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s20/I0 |
9.804 | 0.517 | tINS | FF | 1 | FP_Mult_inst/n1205_s20/F |
10.041 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s8/I2 |
10.494 | 0.453 | tINS | FF | 5 | FP_Mult_inst/n1205_s8/F |
10.731 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1205_s3/I3 |
11.102 | 0.371 | tINS | FF | 5 | FP_Mult_inst/n1205_s3/F |
11.339 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1202_s3/I0 |
11.856 | 0.517 | tINS | FF | 14 | FP_Mult_inst/n1202_s3/F |
12.093 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1200_s2/I1 |
12.648 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1200_s2/F |
12.885 | 0.237 | tNET | FF | 1 | FP_Mult_inst/n1200_s1/I1 |
13.440 | 0.555 | tINS | FF | 1 | FP_Mult_inst/n1200_s1/F |
13.677 | 0.237 | tNET | FF | 1 | FP_Mult_inst/round_mant_r_6_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 134 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Mult_inst/round_mant_r_6_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Mult_inst/round_mant_r_6_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.554, 66.750%; route: 4.029, 31.440%; tC2Q: 0.232, 1.810% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |