Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\SERDES_IP\IPlib\1GSERETH\data\ge_pcs.v D:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\SERDES_IP\IPlib\1GSERETH\data\ge_pcs_wrap.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-1 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Thu May 25 16:58:45 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Giga_Serial_Ethernet_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.635s, Peak memory usage = 49.629MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 49.629MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 49.629MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 49.629MB Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.2s, Peak memory usage = 49.629MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 49.629MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 49.629MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 49.629MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 49.629MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 49.629MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 49.629MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 49.629MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 63.840MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.273s, Peak memory usage = 63.840MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 63.840MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 63.840MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 418 |
| I/O Buf | 415 |
| IBUF | 173 |
| OBUF | 242 |
| Register | 1249 |
| DFFRE | 53 |
| DFFPE | 81 |
| DFFCE | 1115 |
| LUT | 1610 |
| LUT2 | 208 |
| LUT3 | 368 |
| LUT4 | 1034 |
| ALU | 43 |
| ALU | 43 |
| SSRAM | 27 |
| RAM16S4 | 27 |
| INV | 16 |
| INV | 16 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1831(1626 LUTs, 43 ALUs, 27 SSRAMs) / 138240 | 2% |
| Register | 1249 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1249 / 139140 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| serdes_pcs_tx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
| serdes_pcs_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
| clk_in_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_in_i_ibuf/I | ||
| miim_hs_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_i_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | serdes_pcs_tx_clk_i | 100.0(MHz) | 225.9(MHz) | 6 | TOP |
| 2 | serdes_pcs_rx_clk_i | 100.0(MHz) | 201.7(MHz) | 8 | TOP |
| 3 | clk_in_i | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 4 | miim_hs_clk_i | 100.0(MHz) | 244.1(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.043 |
| Data Arrival Time | 5.785 |
| Data Required Time | 10.828 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s0 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.315 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/I2 |
| 2.768 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/F |
| 3.005 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s3/I2 |
| 3.458 | 0.453 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n_state_0_s3/F |
| 3.695 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.066 | 0.371 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n276_s3/F |
| 4.303 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s2/I1 |
| 4.858 | 0.555 | tINS | FF | 21 | u_ge_pcs/u_ge_an/n276_s2/F |
| 5.095 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n318_s2/I2 |
| 5.548 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n318_s2/F |
| 5.785 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.031, 61.580%; route: 1.659, 33.706%; tC2Q: 0.232, 4.714% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 5.043 |
| Data Arrival Time | 5.785 |
| Data Required Time | 10.828 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s0 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.315 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/I2 |
| 2.768 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/F |
| 3.005 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s3/I2 |
| 3.458 | 0.453 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n_state_0_s3/F |
| 3.695 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.066 | 0.371 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n276_s3/F |
| 4.303 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s2/I1 |
| 4.858 | 0.555 | tINS | FF | 21 | u_ge_pcs/u_ge_an/n276_s2/F |
| 5.095 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n316_s2/I2 |
| 5.548 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n316_s2/F |
| 5.785 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.031, 61.580%; route: 1.659, 33.706%; tC2Q: 0.232, 4.714% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 5.043 |
| Data Arrival Time | 5.785 |
| Data Required Time | 10.828 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s0 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.315 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/I2 |
| 2.768 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/F |
| 3.005 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s3/I2 |
| 3.458 | 0.453 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n_state_0_s3/F |
| 3.695 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.066 | 0.371 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n276_s3/F |
| 4.303 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s2/I1 |
| 4.858 | 0.555 | tINS | FF | 21 | u_ge_pcs/u_ge_an/n276_s2/F |
| 5.095 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n315_s2/I2 |
| 5.548 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n315_s2/F |
| 5.785 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.031, 61.580%; route: 1.659, 33.706%; tC2Q: 0.232, 4.714% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 5.043 |
| Data Arrival Time | 5.785 |
| Data Required Time | 10.828 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s0 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_6_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.315 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/I2 |
| 2.768 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/F |
| 3.005 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s3/I2 |
| 3.458 | 0.453 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n_state_0_s3/F |
| 3.695 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.066 | 0.371 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n276_s3/F |
| 4.303 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s2/I1 |
| 4.858 | 0.555 | tINS | FF | 21 | u_ge_pcs/u_ge_an/n276_s2/F |
| 5.095 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n313_s2/I2 |
| 5.548 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n313_s2/F |
| 5.785 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_6_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_6_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_6_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.031, 61.580%; route: 1.659, 33.706%; tC2Q: 0.232, 4.714% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 5.043 |
| Data Arrival Time | 5.785 |
| Data Required Time | 10.828 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s0 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_7_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.315 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/I2 |
| 2.768 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s11/F |
| 3.005 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n_state_0_s3/I2 |
| 3.458 | 0.453 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n_state_0_s3/F |
| 3.695 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.066 | 0.371 | tINS | FF | 3 | u_ge_pcs/u_ge_an/n276_s3/F |
| 4.303 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n276_s2/I1 |
| 4.858 | 0.555 | tINS | FF | 21 | u_ge_pcs/u_ge_an/n276_s2/F |
| 5.095 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/n312_s2/I2 |
| 5.548 | 0.453 | tINS | FF | 1 | u_ge_pcs/u_ge_an/n312_s2/F |
| 5.785 | 0.237 | tNET | FF | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 695 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_7_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_7_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.031, 61.580%; route: 1.659, 33.706%; tC2Q: 0.232, 4.714% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |