Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v
D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v
D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\InputStage.v
D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v
D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v
D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.3Beta
Created Time Wed Dec 18 11:32:13 2019
Legal Announcement Copyright (C)2014-2019 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: Gowin_AHB_Arbiter_Top
Design Language: verilog
Part Number: GW2A-LV18PG256C8/I7

Resource

Resource Usage Summary

IOPORT Usage: 240
IOBUF Usage: 240
    IBUF 121
    OBUF 119
REG Usage: 63
    DFFPE 1
    DFFCE 62
LUT Usage: 149
    LUT2 41
    LUT3 25
    LUT4 83
INV Usage: 1
    INV 1

Resource Utilization Summary

Target Device: GW2A-18-PBGA256
CFU Logics 150(150 LUTs, 0 ALUs) / 20736 1%
Registers 63 / 16173 1%
BSRAMs 0 / 46 0%
DSP Macros 0 / (12*2) 0%


Timing

Clock Summary:

Clock Type Frequency Period Rise Fall Source Master Object
DEFAULT_CLK Base 100.0 MHz 10.000 0.000 5.000

Timing Report:

Top View: Gowin_AHB_Arbiter_Top
Requested Frequency: 100.0 MHz
Paths Requested: 5
Constraint File(ignored):
All time values displayed in nanoseconds(ns).

Performance Summary:

Worst Slack in Design: 5.416
Start Clock Slack Requested Frequency Estimated Frequency Requested Period Estimated Period Clock Type
DEFAULT_CLK 5.416 100.0 MHz 218.2 MHz 10.000 4.584 Base

Detail Timing Paths Information

Path information for path number 1 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(critical): 5.416
Data Arrival Time: 5.212
Data Required Time: 10.628
Number of Logic Level: 6
Starting Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
Ending Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
HCLK_ibuf5101 IBUF I In - 0.000 -
HCLK_ibuf5101 IBUF O Out 0.683 0.683 -
HCLK Net - - 0.180 - 63
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CLK In - 0.863 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE Q Out 0.232 1.095 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[3] Net - - 0.237 - 5
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 I1 In - 1.332 -
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 F Out 0.555 1.887 -
\u_busmatrix16_uOutputstage0_iHTRANSM[0] Net - - 0.237 - 5
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 I1 In - 2.124 -
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 F Out 0.555 2.679 -
u_busmatrix16_uInputStage0_n115 Net - - 0.237 - 50
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 I1 In - 2.916 -
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 F Out 0.555 3.471 -
SHSELM0 Net - - 0.237 - 6
\u_busmatrix16/uOutputstage0/uOutputArb/n28_ins8601 LUT4 I0 In - 3.708 -
\u_busmatrix16/uOutputstage0/uOutputArb/n28_ins8601 LUT4 F Out 0.517 4.225 -
u_busmatrix16_uOutputstage0_uOutputArb_n28 Net - - 0.237 - 2
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[0]_ins8562 LUT3 I1 In - 4.462 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[0]_ins8562 LUT3 F Out 0.570 5.032 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[0] Net - - 0.180 - 1
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CE In - 5.212 -

Total Path Delay: 5.211
Logic Delay: 3.667(70.4%)
Route Delay: 1.545(29.6%)


Path information for path number 2 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 5.558
Data Arrival Time: 5.070
Data Required Time: 10.628
Number of Logic Level: 6
Starting Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
Ending Point: u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[3]_ins7983
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
HCLK_ibuf5101 IBUF I In - 0.000 -
HCLK_ibuf5101 IBUF O Out 0.683 0.683 -
HCLK Net - - 0.180 - 63
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CLK In - 0.863 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE Q Out 0.232 1.095 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[3] Net - - 0.237 - 5
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 I1 In - 1.332 -
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 F Out 0.555 1.887 -
\u_busmatrix16_uOutputstage0_iHTRANSM[0] Net - - 0.237 - 5
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 I1 In - 2.124 -
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 F Out 0.555 2.679 -
u_busmatrix16_uInputStage0_n115 Net - - 0.237 - 50
\u_busmatrix16/uOutputstage0/iHBURSTM[2]_ins8714 LUT4 I3 In - 2.916 -
\u_busmatrix16/uOutputstage0/iHBURSTM[2]_ins8714 LUT4 F Out 0.371 3.287 -
SHBURSTM0[2] Net - - 0.237 - 3
\u_busmatrix16/uOutputstage0/uOutputArb/n19_ins8665 LUT4 I1 In - 3.524 -
\u_busmatrix16/uOutputstage0/uOutputArb/n19_ins8665 LUT4 F Out 0.555 4.079 -
u_busmatrix16_uOutputstage0_uOutputArb_n19 Net - - 0.237 - 1
\u_busmatrix16/uOutputstage0/uOutputArb/n19_ins8563 LUT2 I0 In - 4.316 -
\u_busmatrix16/uOutputstage0/uOutputArb/n19_ins8563 LUT2 F Out 0.517 4.833 -
u_busmatrix16_uOutputstage0_uOutputArb_n19_25 Net - - 0.237 - 1
\u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[3]_ins7983 DFFCE D In - 5.070 -

Total Path Delay: 5.070
Logic Delay: 3.468(68.4%)
Route Delay: 1.602(31.6%)


Path information for path number 3 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 5.806
Data Arrival Time: 4.822
Data Required Time: 10.628
Number of Logic Level: 6
Starting Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
Ending Point: u_busmatrix16/uOutputstage0/uOutputArb/iNoPort_ins7986
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
HCLK_ibuf5101 IBUF I In - 0.000 -
HCLK_ibuf5101 IBUF O Out 0.683 0.683 -
HCLK Net - - 0.180 - 63
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CLK In - 0.863 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE Q Out 0.232 1.095 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[3] Net - - 0.237 - 5
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 I1 In - 1.332 -
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 F Out 0.555 1.887 -
\u_busmatrix16_uOutputstage0_iHTRANSM[0] Net - - 0.237 - 5
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 I1 In - 2.124 -
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 F Out 0.555 2.679 -
u_busmatrix16_uInputStage0_n115 Net - - 0.237 - 50
\u_busmatrix16/uOutputstage0/iHMASTLOCKM_ins8711 LUT4 I3 In - 2.916 -
\u_busmatrix16/uOutputstage0/iHMASTLOCKM_ins8711 LUT4 F Out 0.371 3.287 -
SHMASTLOCKM0 Net - - 0.237 - 4
\u_busmatrix16/uOutputstage0/uOutputArb/NoPortNext_ins8671 LUT4 I3 In - 3.524 -
\u_busmatrix16/uOutputstage0/uOutputArb/NoPortNext_ins8671 LUT4 F Out 0.371 3.895 -
u_busmatrix16_uOutputstage0_uOutputArb_NoPortNext Net - - 0.237 - 1
\u_busmatrix16/uOutputstage0/uOutputArb/NoPortNext_ins8600 LUT3 I2 In - 4.132 -
\u_busmatrix16/uOutputstage0/uOutputArb/NoPortNext_ins8600 LUT3 F Out 0.453 4.585 -
u_busmatrix16_uOutputstage0_uOutputArb_NoPortNext_11 Net - - 0.237 - 1
\u_busmatrix16/uOutputstage0/uOutputArb/iNoPort_ins7986 DFFPE D In - 4.822 -

Total Path Delay: 4.822
Logic Delay: 3.220(66.8%)
Route Delay: 1.602(33.2%)


Path information for path number 4 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 6.166
Data Arrival Time: 4.462
Data Required Time: 10.628
Number of Logic Level: 5
Starting Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
Ending Point: u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_ins7972
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
HCLK_ibuf5101 IBUF I In - 0.000 -
HCLK_ibuf5101 IBUF O Out 0.683 0.683 -
HCLK Net - - 0.180 - 63
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CLK In - 0.863 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE Q Out 0.232 1.095 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[3] Net - - 0.237 - 5
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 I1 In - 1.332 -
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 F Out 0.555 1.887 -
\u_busmatrix16_uOutputstage0_iHTRANSM[0] Net - - 0.237 - 5
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 I1 In - 2.124 -
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 F Out 0.555 2.679 -
u_busmatrix16_uInputStage0_n115 Net - - 0.237 - 50
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 I1 In - 2.916 -
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 F Out 0.555 3.471 -
SHSELM0 Net - - 0.237 - 6
\u_busmatrix16/uOutputstage0/uOutputArb/n28_ins8601 LUT4 I0 In - 3.708 -
\u_busmatrix16/uOutputstage0/uOutputArb/n28_ins8601 LUT4 F Out 0.517 4.225 -
u_busmatrix16_uOutputstage0_uOutputArb_n28 Net - - 0.237 - 2
\u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_ins7972 DFFCE D In - 4.462 -

Total Path Delay: 4.462
Logic Delay: 3.097(69.4%)
Route Delay: 1.365(30.6%)


Path information for path number 5 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 6.170
Data Arrival Time: 4.457
Data Required Time: 10.628
Number of Logic Level: 5
Starting Point: u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975
Ending Point: u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[3]_ins7983
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
HCLK_ibuf5101 IBUF I In - 0.000 -
HCLK_ibuf5101 IBUF O Out 0.683 0.683 -
HCLK Net - - 0.180 - 63
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE CLK In - 0.863 -
\u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort[3]_ins7975 DFFCE Q Out 0.232 1.095 -
\u_busmatrix16_uOutputstage0_uOutputArb_iAddrInPort[3] Net - - 0.237 - 5
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 I1 In - 1.332 -
\u_busmatrix16/uOutputstage0/iHTRANSM[0]_ins8677 LUT4 F Out 0.555 1.887 -
\u_busmatrix16_uOutputstage0_iHTRANSM[0] Net - - 0.237 - 5
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 I1 In - 2.124 -
\u_busmatrix16/uInputStage0/n115_ins8657 LUT2 F Out 0.555 2.679 -
u_busmatrix16_uInputStage0_n115 Net - - 0.237 - 50
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 I1 In - 2.916 -
\u_busmatrix16/uOutputstage0/iHSELM_ins8652 LUT4 F Out 0.555 3.471 -
SHSELM0 Net - - 0.237 - 6
\u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[2]_ins8561 LUT4 I1 In - 3.708 -
\u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[2]_ins8561 LUT4 F Out 0.570 4.278 -
\u_busmatrix16_uOutputstage0_uOutputArb_BurstCount[2] Net - - 0.180 - 4
\u_busmatrix16/uOutputstage0/uOutputArb/BurstCount[3]_ins7983 DFFCE CE In - 4.457 -

Total Path Delay: 4.457
Logic Delay: 3.150(70.7%)
Route Delay: 1.308(29.3%)


Message

Info (EXT0100) : Run analyzation & elaboration
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\ahb_arb_defs.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v:22)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v:22)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\gowin_ahb_arbiter_name.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v:23)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v:23)
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\ahb_arb_defs.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v:1392)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v:1392)
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\InputStage.v'
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\ahb_arb_defs.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v:147)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v:147)
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v'
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\ahb_arb_defs.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v:836)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v:836)
Info (EXT1018) : Compiling module 'Gowin_AHB_Arbiter_Top'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v:25)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\InputStage.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.3.01Alpha\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v:0)
Info (EXT0101) : Current top module is "Gowin_AHB_Arbiter_Top"
Info (CVT0001) : Run conversion
Info (DIO0001) : Run device independent optimization
Info (DIO0006) : Register and gate optimizing before inferencing
Info (DSP0001) : DSP inferencing
Info (RAM0001) : RAM inferencing
Info (ATO0001) : Adder tree reduction
Info (ATO0002) : Rebuild ALU instances from adder tree nodes
Info (DIO0001) : Run device independent optimization
Info (DIO0007) : Register and gate optimizing before mapping
Info (MAP0001) : Run tech-mapping
Info (MAP0003) : Run logic optimization
Info (DIO0001) : Run device independent optimization
Info (SYN0009) : Write post-map netlist to file: D:\user-bak\Users\root\Desktop\ahb_arbiter\src\gowin_ahb_arbiter\temp\ahb_bus_arbiter\gowin_ahb_arbiter.vg

Summary

Total Warnings: 0
Total Informations: 37

Synthesis completed successfully!
Process took 0h:0m:3s realtime, 0h:0m:3s cputime
Memory peak: 53.7MB