Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v
D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v
D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\InputStage.v
D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v
D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v
D:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.05Beta
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18C
Created Time Thu Apr 29 09:27:56 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_AHB_Arbiter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.488MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 46.488MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 46.488MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 46.488MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 46.488MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.488MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 46.488MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 46.488MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 46.488MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 46.488MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.488MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 46.488MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.514s, Peak memory usage = 56.496MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.496MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 56.496MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 56.496MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 240
I/O Buf 240
    IBUF 121
    OBUF 119
Register 64
    DFFPE 1
    DFFCE 63
LUT 152
    LUT2 41
    LUT3 20
    LUT4 91
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 153(153 LUTs, 0 ALUs) / 20736 1%
Register 64 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 64 / 16173 1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.0(MHz) 275.2(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegTrans_1_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegTrans_1_s0/CLK
1.095 0.232 tC2Q RF 1 u_busmatrix16/uInputStage0/RegTrans_1_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHBURSTM0_d_0_s0/I1
1.887 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/SHBURSTM0_d_0_s0/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n20_s13/I1
2.679 0.555 tINS FF 7 u_busmatrix16/uOutputstage0/uOutputArb/n20_s13/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/I1
3.471 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n28_s2/I0
4.225 0.517 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n28_s2/F
4.462 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.370
Data Arrival Time 4.457
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_26_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_26_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_26_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/I1
2.679 0.555 tINS FF 5 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
3.471 0.555 tINS FF 7 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
4.278 0.570 tINS FR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
4.457 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.235, 62.170%; route: 1.128, 31.377%; tC2Q: 0.232, 6.453%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.370
Data Arrival Time 4.457
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_26_s0
To u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_26_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_26_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/I1
2.679 0.555 tINS FF 5 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s2/I1
3.471 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/n230_s2/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s3/I1
4.278 0.570 tINS FR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s3/F
4.457 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.235, 62.170%; route: 1.128, 31.377%; tC2Q: 0.232, 6.453%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.370
Data Arrival Time 4.457
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_26_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_26_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_26_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/I1
2.679 0.555 tINS FF 5 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
3.471 0.555 tINS FF 7 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
4.278 0.570 tINS FR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
4.457 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.235, 62.170%; route: 1.128, 31.377%; tC2Q: 0.232, 6.453%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.370
Data Arrival Time 4.457
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_26_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_26_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_26_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/I1
2.679 0.555 tINS FF 5 u_busmatrix16/uOutputstage0/uOutputArb/n230_s4/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
3.471 0.555 tINS FF 7 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
4.278 0.570 tINS FR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
4.457 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.235, 62.170%; route: 1.128, 31.377%; tC2Q: 0.232, 6.453%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%