Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_define.vh
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_static_macro_define.vh
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_define.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_name.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\triple_speed_mac_name.v
C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v
C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v
C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh
C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v
C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Sun Aug 20 16:24:30 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M1_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 8s, Elapsed time = 0h 0m 10s, Peak memory usage = 93.730MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 93.730MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.587s, Peak memory usage = 93.730MB
    Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 93.730MB
    Optimizing Phase 2: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.538s, Peak memory usage = 93.730MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.855s, Peak memory usage = 93.730MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 93.730MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 93.730MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 93.730MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.591s, Peak memory usage = 93.730MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 93.730MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 93.730MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 94.344MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.751s, Peak memory usage = 94.344MB
Generate output files:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.428s, Peak memory usage = 94.344MB
Total Time and Memory Usage CPU time = 0h 0m 38s, Elapsed time = 0h 0m 40s, Peak memory usage = 94.344MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 132
I/O Buf 131
    IBUF 37
    OBUF 88
    IOBUF 6
Register 1838
    DFF 13
    DFFSE 1
    DFFR 3
    DFFRE 1
    DFFP 29
    DFFPE 89
    DFFC 366
    DFFCE 1327
    DFFNPE 7
    DL 1
    DLN 1
LUT 4556
    LUT2 386
    LUT3 1364
    LUT4 2806
ALU 170
    ALU 170
SSRAM 32
    RAM16SDP4 32
INV 8
    INV 8
DSP
    MULT36X36 1
BSRAM 32
    SP 32

Resource Utilization Summary

Resource Usage Utilization
Logic 4926(4564 LUT, 170 ALU, 32 RAM16) / 20736 24%
Register 1838 / 16173 12%
  --Register as Latch 2 / 16173 <1%
  --Register as FF 1836 / 16173 12%
BSRAM 32 / 46 70%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I
u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_6 Base 10.000 100.0 0.000 5.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_s2/O
u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 Base 10.000 100.0 0.000 5.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.0(MHz) 79.4(MHz) 19 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -5.250
Data Arrival Time 10.417
Data Required Time 5.167
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1890 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/CLK
1.095 0.232 tC2Q RF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/Q
1.332 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.887 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.124 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/I1
2.679 0.555 tINS FF 8 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/F
2.916 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2
3.369 0.453 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
3.606 0.237 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.155 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.155 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
4.624 0.470 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM
4.861 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0
5.378 0.517 tINS FF 24 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F
5.615 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2
6.069 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F
6.306 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1
6.409 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O
6.646 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1
6.749 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O
6.986 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1
7.089 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O
7.326 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1
7.881 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F
8.118 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1
8.673 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F
8.910 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0
9.427 0.517 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F
9.664 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/I0
10.181 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/F
10.418 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.237 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/CLK
5.202 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
5.167 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
Path Statistics:
Clock Skew: -0.626
Setup Relationship: 5.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 6.005, 62.847%; route: 3.318, 34.725%; tC2Q: 0.232, 2.428%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -5.186
Data Arrival Time 10.354
Data Required Time 5.167
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1890 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/CLK
1.095 0.232 tC2Q RF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/Q
1.332 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.887 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.124 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/I1
2.679 0.555 tINS FF 8 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/F
2.916 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2
3.369 0.453 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
3.606 0.237 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.155 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.155 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
4.624 0.470 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM
4.861 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0
5.378 0.517 tINS FF 24 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F
5.615 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2
6.069 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F
6.306 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1
6.409 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O
6.646 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1
6.749 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O
6.986 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1
7.089 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O
7.326 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1
7.881 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F
8.118 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1
8.673 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F
8.910 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0
9.427 0.517 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F
9.664 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/I2
10.117 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/F
10.354 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.237 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/CLK
5.202 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
5.167 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
Path Statistics:
Clock Skew: -0.626
Setup Relationship: 5.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.941, 62.597%; route: 3.318, 34.959%; tC2Q: 0.232, 2.444%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -2.646
Data Arrival Time 7.813
Data Required Time 5.167
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_2_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1890 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/CLK
1.095 0.232 tC2Q RF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/Q
1.332 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.887 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.124 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/I1
2.679 0.555 tINS FF 8 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/F
2.916 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2
3.369 0.453 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
3.606 0.237 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.155 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.155 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
4.190 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/COUT
4.190 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1230_s/CIN
4.660 0.470 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1230_s/SUM
4.897 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_2_s0/I0
5.414 0.517 tINS FF 28 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_2_s0/F
5.651 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s16/I2
6.104 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s16/F
6.341 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s14/I0
6.444 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s14/O
6.681 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s13/I0
6.784 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1239_s13/O
7.021 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n361_s2/I1
7.576 0.555 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n361_s2/F
7.813 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_2_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.237 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_2_s2/CLK
5.202 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_2_s2
5.167 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_2_s2
Path Statistics:
Clock Skew: -0.626
Setup Relationship: 5.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.348, 62.562%; route: 2.370, 34.100%; tC2Q: 0.232, 3.338%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -2.646
Data Arrival Time 7.813
Data Required Time 5.167
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_3_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1890 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/CLK
1.095 0.232 tC2Q RF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/Q
1.332 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.887 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.124 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/I1
2.679 0.555 tINS FF 8 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s6/F
2.916 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2
3.369 0.453 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
3.606 0.237 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.155 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.155 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
4.190 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/COUT
4.190 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1230_s/CIN
4.660 0.470 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1230_s/SUM
4.897 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_2_s0/I0
5.414 0.517 tINS FF 28 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_2_s0/F
5.651 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s16/I2
6.104 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s16/F
6.341 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s14/I0
6.444 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s14/O
6.681 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s13/I0
6.784 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1238_s13/O
7.021 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n360_s2/I1
7.576 0.555 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n360_s2/F
7.813 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_3_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.237 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_3_s2/CLK
5.202 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_3_s2
5.167 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_3_s2
Path Statistics:
Clock Skew: -0.626
Setup Relationship: 5.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.348, 62.562%; route: 2.370, 34.100%; tC2Q: 0.232, 3.338%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -2.589
Data Arrival Time 13.416
Data Required Time 10.828
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1890 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/CLK
1.095 0.232 tC2Q RF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s3/Q
1.332 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1
1.887 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F
2.124 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0
2.641 0.517 tINS FF 14 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F
2.878 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2
3.331 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F
3.568 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1
4.138 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT
4.138 0.000 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN
4.173 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT
4.173 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN
4.208 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT
4.208 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN
4.243 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT
4.243 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN
4.278 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT
4.278 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN
4.314 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT
4.314 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN
4.349 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT
4.349 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN
4.384 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT
4.384 0.000 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN
4.419 0.035 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT
4.656 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s8/I0
5.173 0.517 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s8/F
5.410 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I0
5.927 0.517 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F
6.164 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s9/I2
6.617 0.453 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s9/F
6.854 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s5/I2
7.307 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s5/F
7.544 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s4/I3
7.915 0.371 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s4/F
8.152 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s7/I1
8.707 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s7/F
8.944 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s4/I1
9.499 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s4/F
9.736 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/I0
10.253 0.517 tINS FF 16 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/F
10.490 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/I1
11.045 0.555 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/F
11.282 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/I2
11.735 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/F
11.972 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/I0
12.489 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/COUT
12.726 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/I2
13.179 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/F
13.416 0.237 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1890 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/CLK
10.828 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 19
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.293, 66.058%; route: 4.029, 32.094%; tC2Q: 0.232, 1.848%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%