Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_define.vh D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_static_macro_define.vh D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_define.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_name.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M1\data\debug\triple_speed_mac_name.v C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v C:\Users\liukai\Desktop\ahb_arbiter\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Mon Aug 21 09:25:34 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 13s, Peak memory usage = 115.242MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 115.242MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.939s, Peak memory usage = 115.242MB Optimizing Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.329s, Peak memory usage = 115.242MB Optimizing Phase 2: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.984s, Peak memory usage = 115.242MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.63s, Peak memory usage = 115.242MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 115.242MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 115.242MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 115.242MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 115.242MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.252s, Peak memory usage = 115.242MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.452s, Peak memory usage = 115.242MB Tech-Mapping Phase 3: CPU time = 0h 0m 35s, Elapsed time = 0h 0m 35s, Peak memory usage = 115.242MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 115.242MB Generate output files: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.781s, Peak memory usage = 115.242MB |
Total Time and Memory Usage | CPU time = 0h 0m 52s, Elapsed time = 0h 0m 54s, Peak memory usage = 115.242MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 149 |
I/O Buf | 148 |
    IBUF | 40 |
    OBUF | 101 |
    IOBUF | 7 |
Register | 3101 |
    DFFSE | 1 |
    DFFRE | 40 |
    DFFPE | 151 |
    DFFCE | 2907 |
    DLCE | 2 |
LUT | 6882 |
    LUT2 | 518 |
    LUT3 | 2114 |
    LUT4 | 4250 |
ALU | 285 |
    ALU | 285 |
SSRAM | 32 |
    RAM16SDP4 | 32 |
INV | 13 |
    INV | 13 |
DSP | |
    MULT27X36 | 2 |
BSRAM | 32 |
    DPB | 32 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 7372(6895 LUT, 285 ALU, 32 RAM16) / 23040 | 32% |
Register | 3101 / 23685 | 14% |
  --Register as Latch | 2 / 23685 | <1% |
  --Register as FF | 3099 / 23685 | 14% |
BSRAM | 32 / 56 | 58% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I | ||
JTAG_9 | Base | 10.000 | 100.0 | 0.000 | 5.000 | JTAG_9_ibuf/I | ||
M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TCKn_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TCKn_s2/O | ||
u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_s2/O | ||
u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F | ||
u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_21 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s10/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 100.0(MHz) | 78.4(MHz) | 13 | TOP |
2 | JTAG_9 | 100.0(MHz) | 151.8(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -2.763 |
Data Arrival Time | 13.570 |
Data Required Time | 10.807 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
6.239 | 5.376 | tC2Q | RR | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
6.419 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
6.924 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
7.104 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
7.599 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.779 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.275 | 0.496 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
8.455 | 0.180 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
8.995 | 0.540 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
8.995 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
9.043 | 0.048 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
9.043 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
9.091 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
9.091 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
9.139 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
9.139 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
9.187 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
9.187 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
9.235 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
9.235 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
9.283 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
9.283 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
9.331 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
9.331 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
9.379 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
9.379 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
9.427 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
9.427 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
9.475 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
9.475 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
9.523 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
9.523 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
9.571 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
9.571 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
9.619 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
9.619 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
9.667 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
9.667 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
9.715 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
9.715 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
9.763 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
9.763 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
9.811 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
9.811 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
9.859 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
9.859 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
9.907 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
9.907 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
9.955 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
9.955 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
10.003 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
10.003 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
10.051 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
10.051 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
10.099 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
10.099 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
10.147 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
10.147 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
10.195 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
10.195 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
10.243 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
10.243 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
10.291 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
10.291 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
10.339 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
10.339 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
10.573 | 0.234 | tINS | RR | 6 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
10.753 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I0 |
11.258 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
11.438 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I0 |
11.943 | 0.505 | tINS | RR | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
12.123 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
12.375 | 0.252 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
12.555 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I3 |
12.781 | 0.226 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F |
12.949 | 0.168 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0 |
13.137 | 0.188 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
13.305 | 0.168 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
13.403 | 0.097 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
13.571 | 0.168 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
10.807 | -0.055 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.388, 42.399%; route: 1.944, 15.297%; tC2Q: 5.376, 42.304% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | -2.439 |
Data Arrival Time | 13.240 |
Data Required Time | 10.801 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
6.239 | 5.376 | tC2Q | RR | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
6.419 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
6.924 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
7.104 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
7.599 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.779 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.275 | 0.496 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
8.455 | 0.180 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
8.995 | 0.540 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
8.995 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
9.043 | 0.048 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
9.043 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
9.091 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
9.091 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
9.139 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
9.139 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
9.187 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
9.187 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
9.235 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
9.235 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
9.283 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
9.283 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
9.331 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
9.331 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
9.379 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
9.379 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
9.427 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
9.427 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
9.475 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
9.475 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
9.523 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
9.523 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
9.571 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
9.571 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
9.619 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
9.619 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
9.667 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
9.667 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
9.715 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
9.715 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
9.763 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
9.763 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
9.811 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
9.811 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
9.859 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
9.859 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
9.907 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
9.907 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
9.955 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
9.955 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
10.003 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
10.003 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
10.051 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
10.051 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
10.099 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
10.099 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
10.147 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
10.147 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
10.195 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
10.195 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
10.243 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
10.243 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
10.291 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
10.291 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
10.339 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
10.339 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
10.573 | 0.234 | tINS | RR | 6 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
10.753 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I0 |
11.258 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
11.438 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I0 |
11.943 | 0.505 | tINS | RR | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
12.123 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I0 |
12.629 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
12.809 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
13.061 | 0.252 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
13.241 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
10.801 | -0.061 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.382, 43.480%; route: 1.620, 13.088%; tC2Q: 5.376, 43.432% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | -2.430 |
Data Arrival Time | 13.231 |
Data Required Time | 10.801 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
6.239 | 5.376 | tC2Q | RR | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
6.419 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
6.924 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
7.104 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
7.599 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.779 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.275 | 0.496 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
8.455 | 0.180 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
8.995 | 0.540 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
8.995 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
9.043 | 0.048 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
9.043 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
9.091 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
9.091 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
9.139 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
9.139 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
9.187 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
9.187 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
9.235 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
9.235 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
9.283 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
9.283 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
9.331 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
9.331 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
9.379 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
9.379 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
9.427 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
9.427 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
9.475 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
9.475 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
9.523 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
9.523 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
9.571 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
9.571 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
9.619 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
9.619 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
9.667 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
9.667 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
9.715 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
9.715 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
9.763 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
9.763 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
9.811 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
9.811 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
9.859 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
9.859 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
9.907 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
9.907 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
9.955 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
9.955 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
10.003 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
10.003 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
10.051 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
10.051 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
10.099 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
10.099 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
10.147 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
10.147 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
10.195 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
10.195 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
10.243 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
10.243 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
10.291 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
10.291 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
10.339 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
10.339 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
10.573 | 0.234 | tINS | RR | 6 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
10.753 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I0 |
11.258 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
11.438 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I0 |
11.943 | 0.505 | tINS | RR | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
12.123 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
12.375 | 0.252 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
12.555 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I1 |
13.051 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F |
13.231 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
10.801 | -0.061 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.372, 43.437%; route: 1.620, 13.098%; tC2Q: 5.376, 43.465% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | -2.377 |
Data Arrival Time | 13.178 |
Data Required Time | 10.801 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
6.239 | 5.376 | tC2Q | RR | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
6.419 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
6.924 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
7.104 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
7.599 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.779 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.275 | 0.496 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
8.455 | 0.180 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
8.995 | 0.540 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
8.995 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
9.043 | 0.048 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
9.043 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
9.091 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
9.091 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
9.139 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
9.139 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
9.187 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
9.187 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
9.235 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
9.235 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
9.283 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
9.283 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
9.331 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
9.331 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
9.379 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
9.379 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
9.427 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
9.427 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
9.475 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
9.475 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
9.523 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
9.523 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
9.571 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
9.571 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
9.619 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
9.619 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
9.667 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
9.667 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
9.715 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
9.715 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
9.763 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
9.763 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
9.811 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
9.811 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
9.859 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
9.859 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
9.907 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
9.907 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
9.955 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
9.955 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
10.003 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
10.003 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
10.051 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
10.051 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
10.099 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
10.099 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
10.147 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
10.147 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
10.195 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
10.195 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
10.243 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
10.243 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
10.291 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
10.291 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
10.339 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
10.339 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
10.573 | 0.234 | tINS | RR | 6 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
10.753 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I0 |
11.258 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
11.438 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I0 |
11.943 | 0.505 | tINS | RR | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
12.123 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
12.375 | 0.252 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
12.555 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I2 |
12.998 | 0.443 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F |
13.178 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
10.801 | -0.061 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.320, 43.194%; route: 1.620, 13.154%; tC2Q: 5.376, 43.652% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | -2.179 |
Data Arrival Time | 12.980 |
Data Required Time | 10.801 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_15122_REDUCAREG_G_s |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
6.239 | 5.376 | tC2Q | RR | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
6.419 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
6.924 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
7.104 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
7.599 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.779 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.275 | 0.496 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
8.455 | 0.180 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
8.995 | 0.540 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
8.995 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
9.043 | 0.048 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
9.043 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
9.091 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
9.091 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
9.139 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
9.139 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
9.187 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
9.187 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
9.235 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
9.235 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
9.283 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
9.283 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
9.331 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
9.331 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
9.379 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
9.379 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
9.427 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
9.427 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
9.475 | 0.048 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
9.475 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
9.709 | 0.234 | tINS | RR | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/SUM |
9.889 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/DTCMADDR_Z_13_s7/I1 |
10.385 | 0.496 | tINS | RR | 42 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/DTCMADDR_Z_13_s7/F |
10.565 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s21/I1 |
11.060 | 0.496 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s21/F |
11.240 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s18/I0 |
11.745 | 0.505 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s18/F |
11.925 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s14/I3 |
12.177 | 0.252 | tINS | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s14/F |
12.357 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s23/I2 |
12.800 | 0.443 | tINS | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_ITCMRDATA[8]_DOAL_G_0_s23/F |
12.980 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_15122_REDUCAREG_G_s/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2861 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_15122_REDUCAREG_G_s/CLK |
10.801 | -0.061 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem1_15122_REDUCAREG_G_s |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.942, 40.780%; route: 1.800, 14.854%; tC2Q: 5.376, 44.366% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |