Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\InputStage.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Sun Aug 20 16:23:31 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_AHB_Arbiter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.496s, Peak memory usage = 46.531MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 46.531MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 46.531MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 46.531MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 46.531MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.531MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 46.531MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.531MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 46.531MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 46.531MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.531MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.531MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.58s, Peak memory usage = 57.391MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 57.391MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 57.391MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.391MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 240
I/O Buf 240
    IBUF 121
    OBUF 119
Register 64
    DFFPE 1
    DFFCE 63
LUT 154
    LUT2 44
    LUT3 18
    LUT4 92
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 155(155 LUT, 0 ALU) / 20736 <1%
Register 64 / 16173 <1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 64 / 16173 <1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.0(MHz) 275.2(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From u_busmatrix16/uInputStage0/PendTranReg_s1
To u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/PendTranReg_s1/CLK
1.095 0.232 tC2Q RF 67 u_busmatrix16/uInputStage0/PendTranReg_s1/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s3/I1
1.887 0.555 tINS FF 3 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s3/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s7/I1
2.679 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s7/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/I1
3.471 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n28_s1/I0
4.225 0.517 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n28_s1/F
4.462 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstHold_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.391
Data Arrival Time 4.437
Data Required Time 10.828
From u_busmatrix16/uInputStage0/PendTranReg_s1
To u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/PendTranReg_s1/CLK
1.095 0.232 tC2Q RF 67 u_busmatrix16/uInputStage0/PendTranReg_s1/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s3/I1
1.887 0.555 tINS FF 3 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s3/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s7/I1
2.679 0.555 tINS FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s7/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/I1
3.471 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/F
3.708 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/I0
4.257 0.549 tINS FR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/F
4.437 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.214, 61.948%; route: 1.128, 31.561%; tC2Q: 0.232, 6.491%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.408
Data Arrival Time 4.419
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_29_s0
To u_busmatrix16/uOutputstage0/HselLock_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_29_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_29_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1
2.679 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/n177_s1/I0
3.433 0.517 tINS FF 6 u_busmatrix16/uOutputstage0/n177_s1/F
3.670 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/HselLock_s3/I1
4.240 0.570 tINS FR 1 u_busmatrix16/uOutputstage0/HselLock_s3/F
4.419 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/HselLock_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/HselLock_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/HselLock_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.197, 61.766%; route: 1.128, 31.712%; tC2Q: 0.232, 6.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.429
Data Arrival Time 4.398
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_29_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_29_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_29_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1
2.679 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0
3.433 0.517 tINS FF 6 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.670 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0
4.219 0.549 tINS FR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
4.398 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.176, 61.539%; route: 1.128, 31.900%; tC2Q: 0.232, 6.561%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.429
Data Arrival Time 4.398
Data Required Time 10.828
From u_busmatrix16/uInputStage0/RegAddr_29_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 64 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_busmatrix16/uInputStage0/RegAddr_29_s0/CLK
1.095 0.232 tC2Q RF 2 u_busmatrix16/uInputStage0/RegAddr_29_s0/Q
1.332 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I1
1.887 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F
2.124 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1
2.679 0.555 tINS FF 2 u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F
2.916 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0
3.433 0.517 tINS FF 6 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.670 0.237 tNET FF 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0
4.219 0.549 tINS FR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
4.398 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 64 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CLK
10.828 -0.035 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.176, 61.539%; route: 1.128, 31.900%; tC2Q: 0.232, 6.561%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%