Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\InputStage.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Mon Aug 21 09:24:19 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_AHB_Arbiter_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.273MB Running netlist conversion: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 51.273MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 51.273MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 51.273MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 51.273MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 51.273MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 51.273MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 51.273MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 51.273MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 51.273MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 51.273MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 51.273MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.764s, Peak memory usage = 60.273MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 60.273MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 60.273MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 60.273MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 240 |
I/O Buf | 240 |
    IBUF | 121 |
    OBUF | 119 |
Register | 64 |
    DFFPE | 1 |
    DFFCE | 63 |
LUT | 154 |
    LUT2 | 44 |
    LUT3 | 18 |
    LUT4 | 92 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 155(155 LUT, 0 ALU) / 23040 | <1% |
Register | 64 / 23685 | <1% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 64 / 23685 | <1% |
BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 100.0(MHz) | 278.8(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 6.413 |
Data Arrival Time | 4.151 |
Data Required Time | 10.564 |
From | u_busmatrix16/uInputStage0/PendTranReg_s1 |
To | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uInputStage0/PendTranReg_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 67 | u_busmatrix16/uInputStage0/PendTranReg_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n22_s9/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n22_s9/F |
2.095 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n22_s8/I0 |
2.600 | 0.505 | tINS | RR | 3 | u_busmatrix16/uOutputstage0/uOutputArb/n22_s8/F |
2.780 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/I0 |
3.285 | 0.505 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s9/F |
3.465 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/I0 |
3.971 | 0.505 | tINS | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/F |
4.151 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK |
10.564 | -0.299 | tSu | 1 | u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.021, 61.460%; route: 0.900, 27.372%; tC2Q: 0.367, 11.168% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 6.423 |
Data Arrival Time | 4.141 |
Data Required Time | 10.564 |
From | u_busmatrix16/uInputStage0/RegAddr_30_s0 |
To | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uInputStage0/RegAddr_30_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 2 | u_busmatrix16/uInputStage0/RegAddr_30_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I0 |
1.915 | 0.505 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F |
2.095 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1 |
2.591 | 0.496 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F |
2.771 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0 |
3.276 | 0.505 | tINS | RR | 6 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/F |
3.456 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0 |
3.961 | 0.505 | tINS | RR | 4 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F |
4.141 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CLK |
10.564 | -0.299 | tSu | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.423 |
Data Arrival Time | 4.141 |
Data Required Time | 10.564 |
From | u_busmatrix16/uInputStage0/RegAddr_30_s0 |
To | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uInputStage0/RegAddr_30_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 2 | u_busmatrix16/uInputStage0/RegAddr_30_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I0 |
1.915 | 0.505 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F |
2.095 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1 |
2.591 | 0.496 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F |
2.771 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0 |
3.276 | 0.505 | tINS | RR | 6 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/F |
3.456 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0 |
3.961 | 0.505 | tINS | RR | 4 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F |
4.141 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CLK |
10.564 | -0.299 | tSu | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.423 |
Data Arrival Time | 4.141 |
Data Required Time | 10.564 |
From | u_busmatrix16/uInputStage0/RegAddr_30_s0 |
To | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uInputStage0/RegAddr_30_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 2 | u_busmatrix16/uInputStage0/RegAddr_30_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I0 |
1.915 | 0.505 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F |
2.095 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1 |
2.591 | 0.496 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F |
2.771 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0 |
3.276 | 0.505 | tINS | RR | 6 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/F |
3.456 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0 |
3.961 | 0.505 | tINS | RR | 4 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F |
4.141 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CLK |
10.564 | -0.299 | tSu | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.423 |
Data Arrival Time | 4.141 |
Data Required Time | 10.564 |
From | u_busmatrix16/uInputStage0/RegAddr_30_s0 |
To | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uInputStage0/RegAddr_30_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 2 | u_busmatrix16/uInputStage0/RegAddr_30_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/I0 |
1.915 | 0.505 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/uOutputArb/n230_s10/F |
2.095 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/I1 |
2.591 | 0.496 | tINS | RR | 2 | u_busmatrix16/uOutputstage0/SHSELM0_d_s0/F |
2.771 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/I0 |
3.276 | 0.505 | tINS | RR | 6 | u_busmatrix16/uOutputstage0/SHSELM0_d_s/F |
3.456 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I0 |
3.961 | 0.505 | tINS | RR | 4 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F |
4.141 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 64 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s0/CLK |
10.564 | -0.299 | tSu | 1 | u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |