Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\demo.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\fpga_project.sdc
Version V1.9.8.07
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jul 06 11:08:40 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 1186
Numbers of Endpoints Analyzed 1384
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
SYM_CLK Base 20.000 50.000 0.000 10.000 SYM_CLK
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYM_CLK 50.000(MHz) 226.814(MHz) 5 TOP
2 tck_pad_i 20.000(MHz) 177.981(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
SYM_CLK Setup 0.000 0
SYM_CLK Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.652 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 4.057
2 4.729 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.980
3 4.858 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.851
4 4.905 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.804
5 4.905 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.804
6 5.039 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.670
7 5.101 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.608
8 5.121 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.588
9 5.121 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.588
10 5.121 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.588
11 5.130 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.579
12 5.130 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.579
13 5.477 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.232
14 5.540 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.169
15 5.619 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.090
16 5.622 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.087
17 5.698 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 3.011
18 5.791 gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 2.918
19 5.796 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 2.914
20 6.060 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 2.649
21 6.170 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 2.539
22 6.179 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 2.530
23 7.139 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 1.570
24 7.309 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_7_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 1.400
25 7.409 gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 1.300

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
2 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
3 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
4 0.322 BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/Q BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_2_s0/CE SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.333
5 0.322 BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/Q BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_3_s0/CE SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.333
6 0.352 gw_gao_inst_0/u_la0_top/triger_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.601
7 0.353 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.602
8 0.353 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.602
9 0.353 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.602
10 0.425 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.436
11 0.425 cycle_cnt_1_s0/Q cycle_cnt_1_s0/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.436
12 0.425 gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q gw_gao_inst_0/u_la0_top/bit_count_4_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.436
13 0.425 gw_gao_inst_0/u_la0_top/word_count_11_s0/Q gw_gao_inst_0/u_la0_top/word_count_11_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.436
14 0.427 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.438
15 0.427 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.438
16 0.427 gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.438
17 0.427 gw_gao_inst_0/u_la0_top/word_count_5_s0/Q gw_gao_inst_0/u_la0_top/word_count_5_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.438
18 0.427 cycle_cnt_0_s0/Q cycle_cnt_0_s0/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.438
19 0.428 gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q gw_gao_inst_0/u_la0_top/bit_count_0_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.439
20 0.428 gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q gw_gao_inst_0/u_la0_top/bit_count_1_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.439
21 0.428 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.439
22 0.428 din_6_s1/Q din_6_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.439
23 0.429 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.440
24 0.429 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.440
25 0.429 din_4_s1/Q din_4_s1/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.440

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 8.260 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.682
2 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
3 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
4 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
5 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
6 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
7 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
8 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
9 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
10 8.465 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.477
11 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
12 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
13 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
14 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
15 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
16 8.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.469
17 8.481 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.461
18 8.481 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.461
19 8.481 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.461
20 8.481 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.461
21 8.481 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.461
22 8.736 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.206
23 8.736 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.206
24 8.736 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.206
25 8.736 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 0.023 1.206

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.825 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.824
2 10.825 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.824
3 10.825 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.824
4 10.825 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.824
5 10.825 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.824
6 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
7 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
8 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
9 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
10 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
11 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
12 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
13 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
14 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
15 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
16 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
17 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
18 10.830 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.829
19 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
20 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
21 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
22 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
23 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
24 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834
25 10.835 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 0.012 0.834

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 8.911 9.911 1.000 Low Pulse Width SYM_CLK cycle_cnt_2_s0
2 8.911 9.911 1.000 Low Pulse Width SYM_CLK cycle_cnt_0_s0
3 8.911 9.911 1.000 Low Pulse Width SYM_CLK din_6_s1
4 8.911 9.911 1.000 Low Pulse Width SYM_CLK gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
5 8.911 9.911 1.000 Low Pulse Width SYM_CLK gw_gao_inst_0/u_la0_top/rst_ao_syn_s1
6 8.911 9.911 1.000 Low Pulse Width SYM_CLK gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
7 8.911 9.911 1.000 Low Pulse Width SYM_CLK BCH_Encoder_Top/BCH_Encoder/eop_in_shift_6_s0
8 8.911 9.911 1.000 Low Pulse Width SYM_CLK BCH_Encoder_Top/BCH_Encoder/eop_in_shift_8_s0
9 8.911 9.911 1.000 Low Pulse Width SYM_CLK gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10 8.911 9.911 1.000 Low Pulse Width SYM_CLK BCH_Encoder_Top/BCH_Encoder/eop_in_shift_10_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.652
Data Arrival Time 56.204
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.598 0.440 tNET FF 1 R23C28[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
56.060 0.462 tINS FR 1 R23C28[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
56.204 0.144 tNET RR 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
60.856 -0.035 tSu 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.920, 47.326%; route: 1.905, 46.956%; tC2Q: 0.232, 5.719%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack 4.729
Data Arrival Time 56.127
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.578 0.420 tNET FF 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s1/I3
56.127 0.549 tINS FR 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s1/F
56.127 0.000 tNET RR 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
60.856 -0.035 tSu 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 2.007, 50.424%; route: 1.741, 43.747%; tC2Q: 0.232, 5.829%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack 4.858
Data Arrival Time 55.998
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.428 0.270 tNET FF 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s1/I3
55.998 0.570 tINS FR 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s1/F
55.998 0.000 tNET RR 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
60.856 -0.035 tSu 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 2.028, 52.656%; route: 1.591, 41.320%; tC2Q: 0.232, 6.024%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack 4.905
Data Arrival Time 55.951
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.580 0.422 tNET FF 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n273_s1/I2
55.951 0.371 tINS FF 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n273_s1/F
55.951 0.000 tNET FF 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
60.856 -0.035 tSu 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 48.076%; route: 1.743, 45.826%; tC2Q: 0.232, 6.098%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack 4.905
Data Arrival Time 55.951
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.580 0.422 tNET FF 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s1/I2
55.951 0.371 tINS FF 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s1/F
55.951 0.000 tNET FF 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
60.856 -0.035 tSu 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 48.076%; route: 1.743, 45.826%; tC2Q: 0.232, 6.098%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack 5.039
Data Arrival Time 55.817
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.355 0.197 tNET FF 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n268_s1/I3
55.817 0.462 tINS FR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n268_s1/F
55.817 0.000 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
60.856 -0.035 tSu 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.920, 52.315%; route: 1.518, 41.363%; tC2Q: 0.232, 6.321%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack 5.101
Data Arrival Time 55.755
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.598 1.145 tNET FF 1 R22C30[2][B] gw_gao_inst_0/u_la0_top/n1549_s1/I0
55.060 0.462 tINS FR 1 R22C30[2][B] gw_gao_inst_0/u_la0_top/n1549_s1/F
55.062 0.001 tNET RR 1 R22C30[1][B] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
55.611 0.549 tINS RR 1 R22C30[1][B] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
55.755 0.144 tNET RR 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
60.856 -0.035 tSu 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.687, 46.745%; route: 1.689, 46.825%; tC2Q: 0.232, 6.430%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack 5.121
Data Arrival Time 55.735
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.364 0.206 tNET FF 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n272_s3/I3
55.735 0.371 tINS FF 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n272_s3/F
55.735 0.000 tNET FF 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
60.856 -0.035 tSu 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 50.974%; route: 1.527, 42.560%; tC2Q: 0.232, 6.466%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack 5.121
Data Arrival Time 55.735
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.364 0.206 tNET FF 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n271_s1/I3
55.735 0.371 tINS FF 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n271_s1/F
55.735 0.000 tNET FF 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
60.856 -0.035 tSu 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 50.974%; route: 1.527, 42.560%; tC2Q: 0.232, 6.466%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack 5.121
Data Arrival Time 55.735
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.364 0.206 tNET FF 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n269_s1/I3
55.735 0.371 tINS FF 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n269_s1/F
55.735 0.000 tNET FF 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
60.856 -0.035 tSu 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 50.974%; route: 1.527, 42.560%; tC2Q: 0.232, 6.466%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack 5.130
Data Arrival Time 55.726
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.355 0.197 tNET FF 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s1/I2
55.726 0.371 tINS FF 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s1/F
55.726 0.000 tNET FF 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
60.856 -0.035 tSu 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 51.103%; route: 1.518, 42.415%; tC2Q: 0.232, 6.482%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack 5.130
Data Arrival Time 55.726
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
55.158 0.371 tINS FF 11 R22C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
55.355 0.197 tNET FF 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s1/I2
55.726 0.371 tINS FF 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s1/F
55.726 0.000 tNET FF 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
60.856 -0.035 tSu 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.829, 51.103%; route: 1.518, 42.415%; tC2Q: 0.232, 6.482%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack 5.477
Data Arrival Time 55.378
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/CLK
52.379 0.232 tC2Q RF 3 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q
53.175 0.796 tNET FF 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
53.745 0.570 tINS FR 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
53.917 0.172 tNET RR 1 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.487 0.570 tINS RR 3 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.664 0.177 tNET RR 1 R20C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
55.234 0.570 tINS RR 1 R20C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
55.378 0.144 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
60.856 -0.035 tSu 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.710, 52.914%; route: 1.290, 39.907%; tC2Q: 0.232, 7.179%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack 5.540
Data Arrival Time 55.316
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/CLK
52.379 0.232 tC2Q RF 3 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q
53.175 0.796 tNET FF 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
53.745 0.570 tINS FR 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
53.917 0.172 tNET RR 1 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.487 0.570 tINS RR 3 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.661 0.174 tNET RR 1 R20C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
54.988 0.327 tINS RR 1 R20C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
55.316 0.328 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
60.856 -0.035 tSu 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.467, 46.290%; route: 1.470, 46.390%; tC2Q: 0.232, 7.321%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack 5.619
Data Arrival Time 55.236
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.116 0.663 tNET FF 1 R21C25[3][B] gw_gao_inst_0/u_la0_top/n1529_s2/I1
54.686 0.570 tINS FR 1 R21C25[3][B] gw_gao_inst_0/u_la0_top/n1529_s2/F
54.687 0.001 tNET RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/n1528_s1/I3
55.236 0.549 tINS RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/n1528_s1/F
55.236 0.000 tNET RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
60.856 -0.035 tSu 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.795, 58.083%; route: 1.063, 34.408%; tC2Q: 0.232, 7.509%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack 5.622
Data Arrival Time 55.234
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/CLK
52.379 0.232 tC2Q RF 3 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q
53.175 0.796 tNET FF 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
53.745 0.570 tINS FR 1 R20C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
53.917 0.172 tNET RR 1 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.487 0.570 tINS RR 3 R20C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.664 0.177 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n155_s3/I1
55.234 0.570 tINS RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n155_s3/F
55.234 0.000 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
60.856 -0.035 tSu 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.710, 55.385%; route: 1.145, 37.100%; tC2Q: 0.232, 7.514%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack 5.698
Data Arrival Time 55.158
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
52.379 0.232 tC2Q RF 2 R21C21[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
53.037 0.658 tNET FF 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/I1
53.607 0.570 tINS FR 1 R22C24[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s13/F
53.608 0.001 tNET RR 1 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I2
54.125 0.517 tINS RF 2 R22C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
54.787 0.662 tNET FF 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n274_s2/I2
55.158 0.371 tINS FF 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n274_s2/F
55.158 0.000 tNET FF 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
60.856 -0.035 tSu 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.458, 48.422%; route: 1.321, 43.873%; tC2Q: 0.232, 7.705%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack 5.791
Data Arrival Time 55.065
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R21C24[0][B] gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
52.379 0.232 tC2Q RF 5 R21C24[0][B] gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q
52.784 0.406 tNET FF 2 R21C25[0][B] gw_gao_inst_0/u_la0_top/n1479_s9/I0
53.333 0.549 tINS FR 1 R21C25[0][B] gw_gao_inst_0/u_la0_top/n1479_s9/COUT
53.333 0.000 tNET RR 2 R21C25[1][A] gw_gao_inst_0/u_la0_top/n1479_s10/CIN
53.369 0.035 tINS RF 1 R21C25[1][A] gw_gao_inst_0/u_la0_top/n1479_s10/COUT
54.495 1.126 tNET FF 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg1_s0/I3
55.065 0.570 tINS FR 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg1_s0/F
55.065 0.000 tNET RR 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/start_reg_s0
60.856 -0.035 tSu 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.154, 39.557%; route: 1.532, 52.491%; tC2Q: 0.232, 7.951%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack 5.796
Data Arrival Time 55.060
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.598 1.145 tNET FF 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/n1549_s2/I1
55.060 0.462 tINS FR 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/n1549_s2/F
55.060 0.000 tNET RR 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/triger_s0
60.856 -0.035 tSu 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.138, 39.046%; route: 1.544, 52.992%; tC2Q: 0.232, 7.963%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack 6.060
Data Arrival Time 54.796
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.334 0.880 tNET FF 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/n1530_s3/I2
54.796 0.462 tINS FR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/n1530_s3/F
54.796 0.000 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
60.856 -0.035 tSu 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.138, 42.947%; route: 1.279, 48.295%; tC2Q: 0.232, 8.758%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack 6.170
Data Arrival Time 54.686
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.116 0.663 tNET FF 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/n1529_s3/I3
54.686 0.570 tINS FR 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/n1529_s3/F
54.686 0.000 tNET RR 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
60.856 -0.035 tSu 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.246, 49.051%; route: 1.062, 41.812%; tC2Q: 0.232, 9.136%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack 6.179
Data Arrival Time 54.677
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379 0.232 tC2Q RF 2 R22C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
52.778 0.399 tNET FF 2 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/I1
53.348 0.570 tINS FR 1 R22C25[0][B] gw_gao_inst_0/u_la0_top/n1505_s0/COUT
53.348 0.000 tNET RR 2 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/CIN
53.383 0.035 tINS RF 1 R22C25[1][A] gw_gao_inst_0/u_la0_top/n1506_s0/COUT
53.383 0.000 tNET FF 2 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/CIN
53.418 0.035 tINS FF 1 R22C25[1][B] gw_gao_inst_0/u_la0_top/n1507_s0/COUT
53.418 0.000 tNET FF 2 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/CIN
53.453 0.035 tINS FF 6 R22C25[2][A] gw_gao_inst_0/u_la0_top/n1508_s0/COUT
54.107 0.654 tNET FF 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/n1527_s3/I2
54.677 0.570 tINS FR 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/n1527_s3/F
54.677 0.000 tNET RR 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
60.856 -0.035 tSu 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 1.246, 49.227%; route: 1.053, 41.604%; tC2Q: 0.232, 9.169%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack 7.139
Data Arrival Time 53.717
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/CLK
52.379 0.232 tC2Q RF 3 R25C22[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q
53.147 0.768 tNET FF 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n173_s2/I1
53.717 0.570 tINS FR 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n173_s2/F
53.717 0.000 tNET RR 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
60.856 -0.035 tSu 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 0.570, 36.311%; route: 0.768, 48.910%; tC2Q: 0.232, 14.779%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack 7.309
Data Arrival Time 53.546
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_7_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R20C21[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_7_s0/CLK
52.379 0.232 tC2Q RF 3 R20C21[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_7_s0/Q
52.997 0.619 tNET FF 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n175_s0/I0
53.546 0.549 tINS FR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n175_s0/F
53.546 0.000 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
60.856 -0.035 tSu 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 0.549, 39.226%; route: 0.619, 44.198%; tC2Q: 0.232, 16.576%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack 7.409
Data Arrival Time 53.446
Data Required Time 60.856
From gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
52.147 0.782 tNET RR 1 R20C23[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/CLK
52.379 0.232 tC2Q RF 3 R20C23[1][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q
52.876 0.498 tNET FF 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n176_s2/I1
53.446 0.570 tINS FR 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n176_s2/F
53.446 0.000 tNET RR 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
60.000 60.000 active clock edge time
60.000 0.000 SYM_CLK
60.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
60.682 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
60.926 0.243 tNET RR 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
60.891 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
60.856 -0.035 tSu 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay cell: 0.570, 43.855%; route: 0.498, 38.295%; tC2Q: 0.232, 17.850%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 10 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 10 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 10 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack 0.322
Data Arrival Time 1.193
Data Required Time 0.871
From BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0
To BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_2_s0
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C21[2][A] BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/CLK
1.062 0.202 tC2Q RR 8 R35C21[2][A] BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/Q
1.193 0.131 tNET RR 1 R35C21[0][B] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C21[0][B] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_2_s0/CLK
0.871 0.011 tHld 1 R35C21[0][B] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack 0.322
Data Arrival Time 1.193
Data Required Time 0.871
From BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0
To BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_3_s0
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C21[2][A] BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/CLK
1.062 0.202 tC2Q RR 8 R35C21[2][A] BCH_Encoder_Top/BCH_Encoder/sop_in_shift_3_s0/Q
1.193 0.131 tNET RR 1 R35C21[0][A] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C21[0][A] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_3_s0/CLK
0.871 0.011 tHld 1 R35C21[0][A] BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/dividend_tmp_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 0.352
Data Arrival Time 1.461
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/triger_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.062 0.202 tC2Q RR 13 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/Q
1.461 0.399 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.399, 66.410%; tC2Q: 0.202, 33.590%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 0.353
Data Arrival Time 1.462
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.062 0.202 tC2Q RR 3 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.462 0.400 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 66.472%; tC2Q: 0.202, 33.528%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack 0.353
Data Arrival Time 1.462
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.062 0.202 tC2Q RR 3 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.462 0.400 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 66.472%; tC2Q: 0.202, 33.528%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack 0.353
Data Arrival Time 1.462
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.062 0.202 tC2Q RR 3 R24C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.462 0.400 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 66.472%; tC2Q: 0.202, 33.528%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack 0.425
Data Arrival Time 1.296
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.062 0.202 tC2Q RR 4 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q
1.064 0.002 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n175_s0/I1
1.296 0.232 tINS RF 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n175_s0/F
1.296 0.000 tNET FF 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871 0.011 tHld 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 0.425
Data Arrival Time 1.296
Data Required Time 0.871
From cycle_cnt_1_s0
To cycle_cnt_1_s0
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R34C29[1][A] cycle_cnt_1_s0/CLK
1.062 0.202 tC2Q RR 4 R34C29[1][A] cycle_cnt_1_s0/Q
1.064 0.002 tNET RR 1 R34C29[1][A] n12_s0/I1
1.296 0.232 tINS RF 1 R34C29[1][A] n12_s0/F
1.296 0.000 tNET FF 1 R34C29[1][A] cycle_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R34C29[1][A] cycle_cnt_1_s0/CLK
0.871 0.011 tHld 1 R34C29[1][A] cycle_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 0.425
Data Arrival Time 2.353
Data Required Time 1.927
From gw_gao_inst_0/u_la0_top/bit_count_4_s1
To gw_gao_inst_0/u_la0_top/bit_count_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.118 0.202 tC2Q RR 3 R26C30[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q
2.121 0.002 tNET RR 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/n496_s1/I0
2.353 0.232 tINS RF 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/n496_s1/F
2.353 0.000 tNET FF 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
1.927 0.011 tHld 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%

Path13

Path Summary:

Slack 0.425
Data Arrival Time 2.353
Data Required Time 1.927
From gw_gao_inst_0/u_la0_top/word_count_11_s0
To gw_gao_inst_0/u_la0_top/word_count_11_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.118 0.202 tC2Q RR 2 R30C22[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/Q
2.121 0.002 tNET RR 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/I1
2.353 0.232 tINS RF 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/F
2.353 0.000 tNET FF 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
1.927 0.011 tHld 1 R30C22[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%

Path14

Path Summary:

Slack 0.427
Data Arrival Time 1.297
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.062 0.202 tC2Q RR 6 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
1.065 0.004 tNET RR 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n182_s1/I1
1.297 0.232 tINS RF 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n182_s1/F
1.297 0.000 tNET FF 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871 0.011 tHld 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 0.427
Data Arrival Time 1.297
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.062 0.202 tC2Q RR 4 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.065 0.004 tNET RR 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n180_s0/I1
1.297 0.232 tINS RF 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n180_s0/F
1.297 0.000 tNET FF 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871 0.011 tHld 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 0.427
Data Arrival Time 1.297
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.062 0.202 tC2Q RR 6 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/Q
1.065 0.004 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/n1530_s3/I0
1.297 0.232 tINS RF 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/n1530_s3/F
1.297 0.000 tNET FF 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871 0.011 tHld 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 0.427
Data Arrival Time 2.354
Data Required Time 1.927
From gw_gao_inst_0/u_la0_top/word_count_5_s0
To gw_gao_inst_0/u_la0_top/word_count_5_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
2.118 0.202 tC2Q RR 4 R30C21[1][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/Q
2.122 0.004 tNET RR 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/I1
2.354 0.232 tINS RF 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/F
2.354 0.000 tNET FF 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
1.927 0.011 tHld 1 R30C21[1][A] gw_gao_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%

Path18

Path Summary:

Slack 0.427
Data Arrival Time 1.297
Data Required Time 0.871
From cycle_cnt_0_s0
To cycle_cnt_0_s0
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R34C29[0][A] cycle_cnt_0_s0/CLK
1.062 0.202 tC2Q RR 5 R34C29[0][A] cycle_cnt_0_s0/Q
1.065 0.004 tNET RR 1 R34C29[0][A] n13_s2/I0
1.297 0.232 tINS RF 1 R34C29[0][A] n13_s2/F
1.297 0.000 tNET FF 1 R34C29[0][A] cycle_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R34C29[0][A] cycle_cnt_0_s0/CLK
0.871 0.011 tHld 1 R34C29[0][A] cycle_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 0.428
Data Arrival Time 2.355
Data Required Time 1.927
From gw_gao_inst_0/u_la0_top/bit_count_0_s1
To gw_gao_inst_0/u_la0_top/bit_count_0_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
2.118 0.202 tC2Q RR 7 R26C30[1][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q
2.123 0.005 tNET RR 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/n500_s1/I0
2.355 0.232 tINS RF 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/n500_s1/F
2.355 0.000 tNET FF 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
1.927 0.011 tHld 1 R26C30[1][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%

Path20

Path Summary:

Slack 0.428
Data Arrival Time 2.355
Data Required Time 1.927
From gw_gao_inst_0/u_la0_top/bit_count_1_s1
To gw_gao_inst_0/u_la0_top/bit_count_1_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
2.118 0.202 tC2Q RR 7 R26C29[1][A] gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q
2.123 0.005 tNET RR 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/n499_s1/I1
2.355 0.232 tINS RF 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/n499_s1/F
2.355 0.000 tNET FF 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/bit_count_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 249 - gw_gao_inst_0/u_gw_jtag/tck_o
1.916 0.565 tNET RR 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
1.927 0.011 tHld 1 R26C29[1][A] gw_gao_inst_0/u_la0_top/bit_count_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay cell: 1.351, 70.497%; route: 0.565, 29.503%

Path21

Path Summary:

Slack 0.428
Data Arrival Time 1.299
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.062 0.202 tC2Q RR 6 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.067 0.005 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n268_s1/I2
1.299 0.232 tINS RF 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n268_s1/F
1.299 0.000 tNET FF 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871 0.011 tHld 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 0.428
Data Arrival Time 1.299
Data Required Time 0.871
From din_6_s1
To din_6_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C30[0][A] din_6_s1/CLK
1.062 0.202 tC2Q RR 5 R35C30[0][A] din_6_s1/Q
1.067 0.005 tNET RR 1 R35C30[0][A] n35_s1/I3
1.299 0.232 tINS RF 1 R35C30[0][A] n35_s1/F
1.299 0.000 tNET FF 1 R35C30[0][A] din_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C30[0][A] din_6_s1/CLK
0.871 0.011 tHld 1 R35C30[0][A] din_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 0.429
Data Arrival Time 1.300
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.062 0.202 tC2Q RR 9 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q
1.068 0.006 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/n1565_s3/I0
1.300 0.232 tINS RF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/n1565_s3/F
1.300 0.000 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871 0.011 tHld 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 0.429
Data Arrival Time 1.300
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.062 0.202 tC2Q RR 7 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
1.068 0.006 tNET RR 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/n1564_s1/I0
1.300 0.232 tINS RF 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/n1564_s1/F
1.300 0.000 tNET FF 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871 0.011 tHld 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 0.429
Data Arrival Time 1.300
Data Required Time 0.871
From din_4_s1
To din_4_s1
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C30[1][A] din_4_s1/CLK
1.062 0.202 tC2Q RR 7 R35C30[1][A] din_4_s1/Q
1.068 0.006 tNET RR 1 R35C30[1][A] n37_s1/I0
1.300 0.232 tINS RF 1 R35C30[1][A] n37_s1/F
1.300 0.000 tNET FF 1 R35C30[1][A] din_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R35C30[1][A] din_4_s1/CLK
0.871 0.011 tHld 1 R35C30[1][A] din_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 8.260
Data Arrival Time 12.630
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.630 1.450 tNET FF 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
20.891 -0.035 tSu 1 R22C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.450, 86.203%; tC2Q: 0.232, 13.797%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
20.891 -0.035 tSu 1 R22C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
20.891 -0.035 tSu 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
20.891 -0.035 tSu 1 R21C30[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R21C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
20.891 -0.035 tSu 1 R21C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R21C30[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C30[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
20.891 -0.035 tSu 1 R21C30[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
20.891 -0.035 tSu 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
20.891 -0.035 tSu 1 R22C30[2][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
20.891 -0.035 tSu 1 R21C30[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack 8.465
Data Arrival Time 12.426
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.426 1.245 tNET FF 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
20.891 -0.035 tSu 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.245, 84.292%; tC2Q: 0.232, 15.708%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
20.891 -0.035 tSu 1 R21C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
20.891 -0.035 tSu 1 R21C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
20.891 -0.035 tSu 1 R21C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
20.891 -0.035 tSu 1 R21C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
20.891 -0.035 tSu 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack 8.473
Data Arrival Time 12.418
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.418 1.237 tNET FF 1 R20C29[2][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R20C29[2][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
20.891 -0.035 tSu 1 R20C29[2][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.237, 84.208%; tC2Q: 0.232, 15.792%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack 8.481
Data Arrival Time 12.410
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.410 1.229 tNET FF 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.891 -0.035 tSu 1 R23C29[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.229, 84.123%; tC2Q: 0.232, 15.877%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack 8.481
Data Arrival Time 12.410
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.410 1.229 tNET FF 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
20.891 -0.035 tSu 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.229, 84.123%; tC2Q: 0.232, 15.877%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack 8.481
Data Arrival Time 12.410
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.410 1.229 tNET FF 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
20.891 -0.035 tSu 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.229, 84.123%; tC2Q: 0.232, 15.877%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack 8.481
Data Arrival Time 12.410
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.410 1.229 tNET FF 1 R24C30[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R24C30[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
20.891 -0.035 tSu 1 R24C30[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.229, 84.123%; tC2Q: 0.232, 15.877%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack 8.481
Data Arrival Time 12.410
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.410 1.229 tNET FF 1 R24C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R24C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
20.891 -0.035 tSu 1 R24C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.229, 84.123%; tC2Q: 0.232, 15.877%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack 8.736
Data Arrival Time 12.155
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.155 0.974 tNET FF 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
20.891 -0.035 tSu 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.974, 80.764%; tC2Q: 0.232, 19.236%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack 8.736
Data Arrival Time 12.155
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.155 0.974 tNET FF 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
20.891 -0.035 tSu 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.974, 80.764%; tC2Q: 0.232, 19.236%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack 8.736
Data Arrival Time 12.155
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.155 0.974 tNET FF 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
20.891 -0.035 tSu 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.974, 80.764%; tC2Q: 0.232, 19.236%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack 8.736
Data Arrival Time 12.155
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.688 0.688 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.949 0.261 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.155 0.974 tNET FF 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
20.683 0.683 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
20.926 0.243 tNET RR 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
20.891 -0.035 tSu 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.974, 80.764%; tC2Q: 0.232, 19.236%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.825
Data Arrival Time 11.696
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.696 0.622 tNET RR 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871 0.011 tHld 1 R23C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.622, 75.481%; tC2Q: 0.202, 24.519%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack 10.825
Data Arrival Time 11.696
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.696 0.622 tNET RR 1 R21C27[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C27[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
0.871 0.011 tHld 1 R21C27[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.622, 75.481%; tC2Q: 0.202, 24.519%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack 10.825
Data Arrival Time 11.696
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.696 0.622 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871 0.011 tHld 1 R22C27[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.622, 75.481%; tC2Q: 0.202, 24.519%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack 10.825
Data Arrival Time 11.696
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.696 0.622 tNET RR 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871 0.011 tHld 1 R21C25[2][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.622, 75.481%; tC2Q: 0.202, 24.519%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack 10.825
Data Arrival Time 11.696
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.696 0.622 tNET RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871 0.011 tHld 1 R21C25[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.622, 75.481%; tC2Q: 0.202, 24.519%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.871 0.011 tHld 1 R21C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871 0.011 tHld 1 R21C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871 0.011 tHld 1 R21C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871 0.011 tHld 1 R21C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C27[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.871 0.011 tHld 1 R20C27[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.871 0.011 tHld 1 R20C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.871 0.011 tHld 1 R20C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871 0.011 tHld 1 R20C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871 0.011 tHld 1 R21C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871 0.011 tHld 1 R21C26[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R21C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R21C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
0.871 0.011 tHld 1 R21C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
0.871 0.011 tHld 1 R20C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack 10.830
Data Arrival Time 11.701
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.701 0.627 tNET RR 1 R20C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R20C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
0.871 0.011 tHld 1 R20C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.627, 75.628%; tC2Q: 0.202, 24.372%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.871 0.011 tHld 1 R25C26[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.871 0.011 tHld 1 R25C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871 0.011 tHld 1 R25C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.871 0.011 tHld 1 R22C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871 0.011 tHld 1 R22C28[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.871 0.011 tHld 1 R22C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 10.835
Data Arrival Time 11.706
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
10.677 0.678 tINS FF 220 IOT27[A] SYM_CLK_ibuf/O
10.872 0.195 tNET FF 1 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 51 R26C26[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.706 0.632 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
0.675 0.675 tINS RR 220 IOT27[A] SYM_CLK_ibuf/O
0.860 0.184 tNET RR 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871 0.011 tHld 1 R22C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.632, 75.774%; tC2Q: 0.202, 24.226%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: cycle_cnt_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF cycle_cnt_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR cycle_cnt_2_s0/CLK

MPW2

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: cycle_cnt_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF cycle_cnt_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR cycle_cnt_0_s0/CLK

MPW3

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: din_6_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF din_6_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR din_6_s1/CLK

MPW4

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK

MPW5

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: gw_gao_inst_0/u_la0_top/rst_ao_syn_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/rst_ao_syn_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/rst_ao_syn_s1/CLK

MPW6

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK

MPW7

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: BCH_Encoder_Top/BCH_Encoder/eop_in_shift_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF BCH_Encoder_Top/BCH_Encoder/eop_in_shift_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR BCH_Encoder_Top/BCH_Encoder/eop_in_shift_6_s0/CLK

MPW8

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: BCH_Encoder_Top/BCH_Encoder/eop_in_shift_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF BCH_Encoder_Top/BCH_Encoder/eop_in_shift_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR BCH_Encoder_Top/BCH_Encoder/eop_in_shift_8_s0/CLK

MPW9

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK

MPW10

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: SYM_CLK
Objects: BCH_Encoder_Top/BCH_Encoder/eop_in_shift_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF SYM_CLK_ibuf/I
10.688 0.688 tINS FF SYM_CLK_ibuf/O
10.949 0.261 tNET FF BCH_Encoder_Top/BCH_Encoder/eop_in_shift_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR SYM_CLK_ibuf/I
20.676 0.675 tINS RR SYM_CLK_ibuf/O
20.860 0.184 tNET RR BCH_Encoder_Top/BCH_Encoder/eop_in_shift_10_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
249 control0[0] 4.652 0.912
220 SYM_CLK_d 8.260 0.261
51 rst_ao 8.260 1.450
44 n20_3 46.873 1.361
38 op_reg_en 45.089 0.954
36 jtag_strobe_i 45.096 0.866
32 crc_28_9 46.209 0.939
26 n610_5 45.210 1.104
25 module_state[1] 44.485 0.720
24 data_out_shift_reg_21_7 45.490 1.247

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R22C26 83.33%
R27C21 83.33%
R29C21 83.33%
R29C23 81.94%
R27C22 81.94%
R35C30 81.94%
R29C32 80.56%
R29C20 80.56%
R25C23 79.17%
R34C23 79.17%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name SYM_CLK -period 20 -waveform {0 10} [get_ports {SYM_CLK}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {SYM_CLK}] -to [get_clocks {tck_pad_i}]