Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\BCH_exp.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\bch_encoder\bch_encoder.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jul 06 09:00:45 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module BCH_exp
Synthesis Process Running parser:
    CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 367.973MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 367.973MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 367.973MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 367.973MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 367.973MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 367.973MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 367.973MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 367.973MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 367.973MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 367.973MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 367.973MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 367.973MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 367.973MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 367.973MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 367.973MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 17
I/O Buf 17
    IBUF 5
    OBUF 12
Register 426
    DFF 9
    DFFP 1
    DFFPE 33
    DFFC 105
    DFFCE 272
    DFFNP 2
    DFFNC 4
LUT 410
    LUT2 92
    LUT3 93
    LUT4 225
MUX 1
    MUX16 1
ALU 10
    ALU 10
SSRAM 4
    RAM16S4 4
INV 5
    INV 5
BSRAM 3
    SDPX9B 3
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 457(423 LUTs, 10 ALUs, 4 SSRAMs) / 20736 2%
Register 426 / 16173 3%
  --Register as Latch 0 / 16173 0%
  --Register as FF 426 / 16173 3%
BSRAM 3 / 46 7%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
SYM_CLK Base 10.000 100.0 0.000 5.000 SYM_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYM_CLK 100.0(MHz) 280.0(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.429
Data Arrival Time 4.398
Data Required Time 10.828
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.683 0.683 tINS RR 220 SYM_CLK_ibuf/O
0.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 8 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/I0
1.849 0.517 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/F
2.086 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I1
2.641 0.555 tINS FF 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
2.878 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
3.433 0.555 tINS FF 11 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
3.670 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.219 0.549 tINS FR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.398 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.682 0.683 tINS RR 220 SYM_CLK_ibuf/O
10.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.828 -0.035 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.176, 61.539%; route: 1.128, 31.900%; tC2Q: 0.232, 6.561%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.430
Data Arrival Time 4.398
Data Required Time 10.828
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.683 0.683 tINS RR 220 SYM_CLK_ibuf/O
0.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.095 0.232 tC2Q RF 6 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.332 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s3/I1
1.887 0.555 tINS FF 4 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s3/F
2.124 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s3/I1
2.679 0.555 tINS FF 4 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s3/F
2.916 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s2/I1
3.471 0.555 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s2/F
3.708 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s1/I2
4.161 0.453 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n266_s1/F
4.398 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.682 0.683 tINS RR 220 SYM_CLK_ibuf/O
10.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.828 -0.035 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.118, 59.915%; route: 1.185, 33.522%; tC2Q: 0.232, 6.563%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.430
Data Arrival Time 4.398
Data Required Time 10.828
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.683 0.683 tINS RR 220 SYM_CLK_ibuf/O
0.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.095 0.232 tC2Q RF 6 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.332 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s3/I1
1.887 0.555 tINS FF 4 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s3/F
2.124 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s3/I1
2.679 0.555 tINS FF 4 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n267_s3/F
2.916 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s3/I2
3.369 0.453 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s3/F
3.606 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s1/I1
4.161 0.555 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n265_s1/F
4.398 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.682 0.683 tINS RR 220 SYM_CLK_ibuf/O
10.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.828 -0.035 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.118, 59.915%; route: 1.185, 33.522%; tC2Q: 0.232, 6.563%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.683 0.683 tINS RR 220 SYM_CLK_ibuf/O
0.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 8 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/I0
1.849 0.517 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/F
2.086 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I1
2.641 0.555 tINS FF 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
2.878 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
3.433 0.555 tINS FF 11 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
3.670 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n273_s1/I2
4.122 0.453 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n273_s1/F
4.359 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.682 0.683 tINS RR 220 SYM_CLK_ibuf/O
10.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.828 -0.035 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.683 0.683 tINS RR 220 SYM_CLK_ibuf/O
0.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 8 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/I0
1.849 0.517 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s12/F
2.086 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/I1
2.641 0.555 tINS FF 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s7/F
2.878 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/I1
3.433 0.555 tINS FF 11 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n264_s4/F
3.670 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s1/I2
4.122 0.453 tINS FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n270_s1/F
4.359 0.237 tNET FF 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.682 0.683 tINS RR 220 SYM_CLK_ibuf/O
10.863 0.180 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.828 -0.035 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%