Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\BCH_Encoder\data\BCH_Encoder_top.v
C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\BCH_Encoder\data\BCH_Encoder_top_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jul 06 08:44:18 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module BCH_Encoder_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 44.480MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 44.480MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.480MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 44.480MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.480MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.480MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.480MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.480MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.480MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.480MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.480MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.480MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 53.027MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 53.027MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 53.027MB
Total Time and Memory Usage CPU time = 0h 0m 0.372s, Elapsed time = 0h 0m 0.386s, Peak memory usage = 53.027MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 25
I/O Buf 24
    IBUF 12
    OBUF 12
Register 151
    DFFC 86
    DFFCE 65
LUT 45
    LUT2 38
    LUT3 7
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 47(47 LUTs, 0 ALUs) / 20736 1%
Register 151 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 151 / 16173 1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 771.6(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.704
Data Arrival Time 2.123
Data Required Time 10.828
From BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0
To BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 151 clk_ibuf/O
0.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0/CLK
1.095 0.232 tC2Q RF 4 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0/Q
1.332 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_7_s0/I1
1.887 0.555 tINS FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_7_s0/F
2.124 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 151 clk_ibuf/O
10.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_8_s0/CLK
10.828 -0.035 tSu 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 8.704
Data Arrival Time 2.123
Data Required Time 10.828
From BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_4_s0
To BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 151 clk_ibuf/O
0.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_4_s0/CLK
1.095 0.232 tC2Q RF 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_4_s0/Q
1.332 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_4_s0/I1
1.887 0.555 tINS FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_4_s0/F
2.124 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 151 clk_ibuf/O
10.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_5_s0/CLK
10.828 -0.035 tSu 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 8.704
Data Arrival Time 2.123
Data Required Time 10.828
From BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_2_s0
To BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 151 clk_ibuf/O
0.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_2_s0/CLK
1.095 0.232 tC2Q RF 2 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_2_s0/Q
1.332 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_6_s0/I1
1.887 0.555 tINS FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/r_6_s0/F
2.124 0.237 tNET FF 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 151 clk_ibuf/O
10.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_7_s0/CLK
10.828 -0.035 tSu 1 BCH_Encoder/deconv_shift[5].deconv_shift/dividend_tmp_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 8.704
Data Arrival Time 2.123
Data Required Time 10.828
From BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_8_s0
To BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 151 clk_ibuf/O
0.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_8_s0/CLK
1.095 0.232 tC2Q RF 4 BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_8_s0/Q
1.332 0.237 tNET FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/r_7_s0/I1
1.887 0.555 tINS FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/r_7_s0/F
2.124 0.237 tNET FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 151 clk_ibuf/O
10.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0/CLK
10.828 -0.035 tSu 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 8.704
Data Arrival Time 2.123
Data Required Time 10.828
From BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_4_s0
To BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 151 clk_ibuf/O
0.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_4_s0/CLK
1.095 0.232 tC2Q RF 1 BCH_Encoder/deconv_shift[3].deconv_shift/dividend_tmp_4_s0/Q
1.332 0.237 tNET FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/r_4_s0/I1
1.887 0.555 tINS FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/r_4_s0/F
2.124 0.237 tNET FF 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 151 clk_ibuf/O
10.863 0.180 tNET RR 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_5_s0/CLK
10.828 -0.035 tSu 1 BCH_Encoder/deconv_shift[4].deconv_shift/dividend_tmp_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%