Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7Beta\IDE\ipcore\CORDIC\data\cordic.v
C:\Gowin\Gowin_V1.9.7Beta\IDE\ipcore\CORDIC\data\cordic_wrap.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Sun Sep 27 16:47:30 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: CORDIC_Top
Part Number: GW2A-LV55PG484C8/I7
Device: GW2A-55

Resource

Resource Usage Summary

I/O Port 104
I/O Buf 104
    IBUF 53
    OBUF 51
Register 816
    DFFR 816
ALU 758
    ALU 758
INV 16
    INV 16

Resource Utilization Summary

Logic 774(16 LUTs, 758 ALUs) / 54720 1%
Register 816 / 42000 2%
BSRAM 0 / 140 0%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0 MHz 426.6 MHz 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8
Data Arrival Time 3
Data Required Time 11
From u_cordic/[14].U/y_1_15_s0
To u_cordic/[15].U/x_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[14].U/y_1_15_s0/CLK
1.094 0.232 tC2Q RF 2 u_cordic/[14].U/y_1_15_s0/Q
1.331 0.237 tNET FF 2 u_cordic/[15].U/n198_1_s/I1
1.901 0.57 tINS FR 1 u_cordic/[15].U/n198_1_s/COUT
1.901 0 tNET RR 2 u_cordic/[15].U/n197_1_s/CIN
1.936 0.035 tINS RF 1 u_cordic/[15].U/n197_1_s/COUT
1.936 0 tNET FF 2 u_cordic/[15].U/n196_1_s/CIN
1.971 0.035 tINS FF 1 u_cordic/[15].U/n196_1_s/COUT
1.971 0 tNET FF 2 u_cordic/[15].U/n195_1_s/CIN
2.007 0.035 tINS FF 1 u_cordic/[15].U/n195_1_s/COUT
2.007 0 tNET FF 2 u_cordic/[15].U/n194_1_s/CIN
2.042 0.035 tINS FF 1 u_cordic/[15].U/n194_1_s/COUT
2.042 0 tNET FF 2 u_cordic/[15].U/n193_1_s/CIN
2.077 0.035 tINS FF 1 u_cordic/[15].U/n193_1_s/COUT
2.077 0 tNET FF 2 u_cordic/[15].U/n192_1_s/CIN
2.112 0.035 tINS FF 1 u_cordic/[15].U/n192_1_s/COUT
2.112 0 tNET FF 2 u_cordic/[15].U/n191_1_s/CIN
2.147 0.035 tINS FF 1 u_cordic/[15].U/n191_1_s/COUT
2.147 0 tNET FF 2 u_cordic/[15].U/n190_1_s/CIN
2.183 0.035 tINS FF 1 u_cordic/[15].U/n190_1_s/COUT
2.183 0 tNET FF 2 u_cordic/[15].U/n189_1_s/CIN
2.218 0.035 tINS FF 1 u_cordic/[15].U/n189_1_s/COUT
2.218 0 tNET FF 2 u_cordic/[15].U/n188_1_s/CIN
2.253 0.035 tINS FF 1 u_cordic/[15].U/n188_1_s/COUT
2.253 0 tNET FF 2 u_cordic/[15].U/n187_1_s/CIN
2.288 0.035 tINS FF 1 u_cordic/[15].U/n187_1_s/COUT
2.288 0 tNET FF 2 u_cordic/[15].U/n186_1_s/CIN
2.323 0.035 tINS FF 1 u_cordic/[15].U/n186_1_s/COUT
2.323 0 tNET FF 2 u_cordic/[15].U/n185_1_s/CIN
2.359 0.035 tINS FF 1 u_cordic/[15].U/n185_1_s/COUT
2.359 0 tNET FF 2 u_cordic/[15].U/n184_1_s/CIN
2.394 0.035 tINS FF 1 u_cordic/[15].U/n184_1_s/COUT
2.394 0 tNET FF 2 u_cordic/[15].U/n183_1_s/CIN
2.429 0.035 tINS FF 1 u_cordic/[15].U/n183_1_s/COUT
2.429 0 tNET FF 2 u_cordic/[15].U/n182_1_s/CIN
2.899 0.47 tINS FF 1 u_cordic/[15].U/n182_1_s/SUM
3.136 0.237 tNET FF 1 u_cordic/[15].U/x_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[15].U/x_1_16_s0/CLK

Path Statistic:
Clock Skew: 0
Hold Relationship: 10
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.568, 68.953%; route: 0.474, 20.844%; tC2Q: 0.232, 10.202%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 7.656
Data Arrival Time 3.137
Data Required Time 10.793
From u_cordic/[14].U/x_1_15_s0
To u_cordic/[15].U/y_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[14].U/x_1_15_s0/CLK
1.094 0.232 tC2Q RF 2 u_cordic/[14].U/x_1_15_s0/Q
1.331 0.237 tNET FF 2 u_cordic/[15].U/n215_1_s/I1
1.901 0.57 tINS FR 1 u_cordic/[15].U/n215_1_s/COUT
1.901 0 tNET RR 2 u_cordic/[15].U/n214_1_s/CIN
1.936 0.035 tINS RF 1 u_cordic/[15].U/n214_1_s/COUT
1.936 0 tNET FF 2 u_cordic/[15].U/n213_1_s/CIN
1.971 0.035 tINS FF 1 u_cordic/[15].U/n213_1_s/COUT
1.971 0 tNET FF 2 u_cordic/[15].U/n212_1_s/CIN
2.007 0.035 tINS FF 1 u_cordic/[15].U/n212_1_s/COUT
2.007 0 tNET FF 2 u_cordic/[15].U/n211_1_s/CIN
2.042 0.035 tINS FF 1 u_cordic/[15].U/n211_1_s/COUT
2.042 0 tNET FF 2 u_cordic/[15].U/n210_1_s/CIN
2.077 0.035 tINS FF 1 u_cordic/[15].U/n210_1_s/COUT
2.077 0 tNET FF 2 u_cordic/[15].U/n209_1_s/CIN
2.112 0.035 tINS FF 1 u_cordic/[15].U/n209_1_s/COUT
2.112 0 tNET FF 2 u_cordic/[15].U/n208_1_s/CIN
2.147 0.035 tINS FF 1 u_cordic/[15].U/n208_1_s/COUT
2.147 0 tNET FF 2 u_cordic/[15].U/n207_1_s/CIN
2.183 0.035 tINS FF 1 u_cordic/[15].U/n207_1_s/COUT
2.183 0 tNET FF 2 u_cordic/[15].U/n206_1_s/CIN
2.218 0.035 tINS FF 1 u_cordic/[15].U/n206_1_s/COUT
2.218 0 tNET FF 2 u_cordic/[15].U/n205_1_s/CIN
2.253 0.035 tINS FF 1 u_cordic/[15].U/n205_1_s/COUT
2.253 0 tNET FF 2 u_cordic/[15].U/n204_1_s/CIN
2.288 0.035 tINS FF 1 u_cordic/[15].U/n204_1_s/COUT
2.288 0 tNET FF 2 u_cordic/[15].U/n203_1_s/CIN
2.323 0.035 tINS FF 1 u_cordic/[15].U/n203_1_s/COUT
2.323 0 tNET FF 2 u_cordic/[15].U/n202_1_s/CIN
2.359 0.035 tINS FF 1 u_cordic/[15].U/n202_1_s/COUT
2.359 0 tNET FF 2 u_cordic/[15].U/n201_1_s/CIN
2.394 0.035 tINS FF 1 u_cordic/[15].U/n201_1_s/COUT
2.394 0 tNET FF 2 u_cordic/[15].U/n200_1_s/CIN
2.429 0.035 tINS FF 1 u_cordic/[15].U/n200_1_s/COUT
2.429 0 tNET FF 2 u_cordic/[15].U/n199_1_s/CIN
2.899 0.47 tINS FF 1 u_cordic/[15].U/n199_1_s/SUM
3.136 0.237 tNET FF 1 u_cordic/[15].U/y_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[15].U/y_1_16_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 3.136, 72.660%; route: 0.948, 21.965%; tC2Q: 0.232, 5.375%
Required Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%

Path 3

Path Summary:
Slack 7.656
Data Arrival Time 3.137
Data Required Time 10.793
From u_cordic/[13].U/y_1_14_s0
To u_cordic/[14].U/x_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[13].U/y_1_14_s0/CLK
1.094 0.232 tC2Q RF 2 u_cordic/[13].U/y_1_14_s0/Q
1.331 0.237 tNET FF 2 u_cordic/[14].U/n196_1_s/I1
1.901 0.57 tINS FR 1 u_cordic/[14].U/n196_1_s/COUT
1.901 0 tNET RR 2 u_cordic/[14].U/n195_1_s/CIN
1.936 0.035 tINS RF 1 u_cordic/[14].U/n195_1_s/COUT
1.936 0 tNET FF 2 u_cordic/[14].U/n194_1_s/CIN
1.971 0.035 tINS FF 1 u_cordic/[14].U/n194_1_s/COUT
1.971 0 tNET FF 2 u_cordic/[14].U/n193_1_s/CIN
2.007 0.035 tINS FF 1 u_cordic/[14].U/n193_1_s/COUT
2.007 0 tNET FF 2 u_cordic/[14].U/n192_1_s/CIN
2.042 0.035 tINS FF 1 u_cordic/[14].U/n192_1_s/COUT
2.042 0 tNET FF 2 u_cordic/[14].U/n191_1_s/CIN
2.077 0.035 tINS FF 1 u_cordic/[14].U/n191_1_s/COUT
2.077 0 tNET FF 2 u_cordic/[14].U/n190_1_s/CIN
2.112 0.035 tINS FF 1 u_cordic/[14].U/n190_1_s/COUT
2.112 0 tNET FF 2 u_cordic/[14].U/n189_1_s/CIN
2.147 0.035 tINS FF 1 u_cordic/[14].U/n189_1_s/COUT
2.147 0 tNET FF 2 u_cordic/[14].U/n188_1_s/CIN
2.183 0.035 tINS FF 1 u_cordic/[14].U/n188_1_s/COUT
2.183 0 tNET FF 2 u_cordic/[14].U/n187_1_s/CIN
2.218 0.035 tINS FF 1 u_cordic/[14].U/n187_1_s/COUT
2.218 0 tNET FF 2 u_cordic/[14].U/n186_1_s/CIN
2.253 0.035 tINS FF 1 u_cordic/[14].U/n186_1_s/COUT
2.253 0 tNET FF 2 u_cordic/[14].U/n185_1_s/CIN
2.288 0.035 tINS FF 1 u_cordic/[14].U/n185_1_s/COUT
2.288 0 tNET FF 2 u_cordic/[14].U/n184_1_s/CIN
2.323 0.035 tINS FF 1 u_cordic/[14].U/n184_1_s/COUT
2.323 0 tNET FF 2 u_cordic/[14].U/n183_1_s/CIN
2.359 0.035 tINS FF 1 u_cordic/[14].U/n183_1_s/COUT
2.359 0 tNET FF 2 u_cordic/[14].U/n182_1_s/CIN
2.394 0.035 tINS FF 1 u_cordic/[14].U/n182_1_s/COUT
2.394 0 tNET FF 2 u_cordic/[14].U/n181_1_s/CIN
2.429 0.035 tINS FF 1 u_cordic/[14].U/n181_1_s/COUT
2.429 0 tNET FF 2 u_cordic/[14].U/n180_1_s/CIN
2.899 0.47 tINS FF 1 u_cordic/[14].U/n180_1_s/SUM
3.136 0.237 tNET FF 1 u_cordic/[14].U/x_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[14].U/x_1_16_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 4.704, 73.986%; route: 1.422, 22.366%; tC2Q: 0.232, 3.649%
Required Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%

Path 4

Path Summary:
Slack 7.656
Data Arrival Time 3.137
Data Required Time 10.793
From u_cordic/[13].U/x_1_14_s0
To u_cordic/[14].U/y_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[13].U/x_1_14_s0/CLK
1.094 0.232 tC2Q RF 2 u_cordic/[13].U/x_1_14_s0/Q
1.331 0.237 tNET FF 2 u_cordic/[14].U/n213_1_s/I1
1.901 0.57 tINS FR 1 u_cordic/[14].U/n213_1_s/COUT
1.901 0 tNET RR 2 u_cordic/[14].U/n212_1_s/CIN
1.936 0.035 tINS RF 1 u_cordic/[14].U/n212_1_s/COUT
1.936 0 tNET FF 2 u_cordic/[14].U/n211_1_s/CIN
1.971 0.035 tINS FF 1 u_cordic/[14].U/n211_1_s/COUT
1.971 0 tNET FF 2 u_cordic/[14].U/n210_1_s/CIN
2.007 0.035 tINS FF 1 u_cordic/[14].U/n210_1_s/COUT
2.007 0 tNET FF 2 u_cordic/[14].U/n209_1_s/CIN
2.042 0.035 tINS FF 1 u_cordic/[14].U/n209_1_s/COUT
2.042 0 tNET FF 2 u_cordic/[14].U/n208_1_s/CIN
2.077 0.035 tINS FF 1 u_cordic/[14].U/n208_1_s/COUT
2.077 0 tNET FF 2 u_cordic/[14].U/n207_1_s/CIN
2.112 0.035 tINS FF 1 u_cordic/[14].U/n207_1_s/COUT
2.112 0 tNET FF 2 u_cordic/[14].U/n206_1_s/CIN
2.147 0.035 tINS FF 1 u_cordic/[14].U/n206_1_s/COUT
2.147 0 tNET FF 2 u_cordic/[14].U/n205_1_s/CIN
2.183 0.035 tINS FF 1 u_cordic/[14].U/n205_1_s/COUT
2.183 0 tNET FF 2 u_cordic/[14].U/n204_1_s/CIN
2.218 0.035 tINS FF 1 u_cordic/[14].U/n204_1_s/COUT
2.218 0 tNET FF 2 u_cordic/[14].U/n203_1_s/CIN
2.253 0.035 tINS FF 1 u_cordic/[14].U/n203_1_s/COUT
2.253 0 tNET FF 2 u_cordic/[14].U/n202_1_s/CIN
2.288 0.035 tINS FF 1 u_cordic/[14].U/n202_1_s/COUT
2.288 0 tNET FF 2 u_cordic/[14].U/n201_1_s/CIN
2.323 0.035 tINS FF 1 u_cordic/[14].U/n201_1_s/COUT
2.323 0 tNET FF 2 u_cordic/[14].U/n200_1_s/CIN
2.359 0.035 tINS FF 1 u_cordic/[14].U/n200_1_s/COUT
2.359 0 tNET FF 2 u_cordic/[14].U/n199_1_s/CIN
2.394 0.035 tINS FF 1 u_cordic/[14].U/n199_1_s/COUT
2.394 0 tNET FF 2 u_cordic/[14].U/n198_1_s/CIN
2.429 0.035 tINS FF 1 u_cordic/[14].U/n198_1_s/COUT
2.429 0 tNET FF 2 u_cordic/[14].U/n197_1_s/CIN
2.899 0.47 tINS FF 1 u_cordic/[14].U/n197_1_s/SUM
3.136 0.237 tNET FF 1 u_cordic/[14].U/y_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[14].U/y_1_16_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 6.272, 74.667%; route: 1.896, 22.571%; tC2Q: 0.232, 2.762%
Required Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%

Path 5

Path Summary:
Slack 7.656
Data Arrival Time 3.137
Data Required Time 10.793
From u_cordic/[12].U/y_1_13_s0
To u_cordic/[13].U/x_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[12].U/y_1_13_s0/CLK
1.094 0.232 tC2Q RF 2 u_cordic/[12].U/y_1_13_s0/Q
1.331 0.237 tNET FF 2 u_cordic/[13].U/n194_1_s/I1
1.901 0.57 tINS FR 1 u_cordic/[13].U/n194_1_s/COUT
1.901 0 tNET RR 2 u_cordic/[13].U/n193_1_s/CIN
1.936 0.035 tINS RF 1 u_cordic/[13].U/n193_1_s/COUT
1.936 0 tNET FF 2 u_cordic/[13].U/n192_1_s/CIN
1.971 0.035 tINS FF 1 u_cordic/[13].U/n192_1_s/COUT
1.971 0 tNET FF 2 u_cordic/[13].U/n191_1_s/CIN
2.007 0.035 tINS FF 1 u_cordic/[13].U/n191_1_s/COUT
2.007 0 tNET FF 2 u_cordic/[13].U/n190_1_s/CIN
2.042 0.035 tINS FF 1 u_cordic/[13].U/n190_1_s/COUT
2.042 0 tNET FF 2 u_cordic/[13].U/n189_1_s/CIN
2.077 0.035 tINS FF 1 u_cordic/[13].U/n189_1_s/COUT
2.077 0 tNET FF 2 u_cordic/[13].U/n188_1_s/CIN
2.112 0.035 tINS FF 1 u_cordic/[13].U/n188_1_s/COUT
2.112 0 tNET FF 2 u_cordic/[13].U/n187_1_s/CIN
2.147 0.035 tINS FF 1 u_cordic/[13].U/n187_1_s/COUT
2.147 0 tNET FF 2 u_cordic/[13].U/n186_1_s/CIN
2.183 0.035 tINS FF 1 u_cordic/[13].U/n186_1_s/COUT
2.183 0 tNET FF 2 u_cordic/[13].U/n185_1_s/CIN
2.218 0.035 tINS FF 1 u_cordic/[13].U/n185_1_s/COUT
2.218 0 tNET FF 2 u_cordic/[13].U/n184_1_s/CIN
2.253 0.035 tINS FF 1 u_cordic/[13].U/n184_1_s/COUT
2.253 0 tNET FF 2 u_cordic/[13].U/n183_1_s/CIN
2.288 0.035 tINS FF 1 u_cordic/[13].U/n183_1_s/COUT
2.288 0 tNET FF 2 u_cordic/[13].U/n182_1_s/CIN
2.323 0.035 tINS FF 1 u_cordic/[13].U/n182_1_s/COUT
2.323 0 tNET FF 2 u_cordic/[13].U/n181_1_s/CIN
2.359 0.035 tINS FF 1 u_cordic/[13].U/n181_1_s/COUT
2.359 0 tNET FF 2 u_cordic/[13].U/n180_1_s/CIN
2.394 0.035 tINS FF 1 u_cordic/[13].U/n180_1_s/COUT
2.394 0 tNET FF 2 u_cordic/[13].U/n179_1_s/CIN
2.429 0.035 tINS FF 1 u_cordic/[13].U/n179_1_s/COUT
2.429 0 tNET FF 2 u_cordic/[13].U/n178_1_s/CIN
2.899 0.47 tINS FF 1 u_cordic/[13].U/n178_1_s/SUM
3.136 0.237 tNET FF 1 u_cordic/[13].U/x_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 816 clk_ibuf/O
0.862 0.18 tNET RR 1 u_cordic/[13].U/x_1_16_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 7.840, 75.081%; route: 2.370, 22.697%; tC2Q: 0.232, 2.222%
Required Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%

Synthesis completed successfully!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
Memory peak: 50.2MB