Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\release_verify\Release\cordic\ref_design\vector_iterate_degree\project\src\cordic\cordic.v
E:\myWork\IP\release_verify\Release\cordic\ref_design\vector_iterate_degree\project\src\top.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Sun Sep 27 16:55:03 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: top
Part Number: GW2A-LV55PG484C8/I7
Device: GW2A-55

Resource

Resource Usage Summary

I/O Port 37
I/O Buf 37
    IBUF 2
    OBUF 35
Register 91
    DFF 1
    DFFE 6
    DFFR 72
    DFFRE 8
    DFFC 4
LUT 352
    LUT2 9
    LUT3 165
    LUT4 178
ALU 79
    ALU 79
INV 4
    INV 4
BSRAM 3
    pROM 3

Resource Utilization Summary

Logic 435(356 LUTs, 79 ALUs) / 54720 1%
Register 91 / 42000 1%
BSRAM 3 / 140 2%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0 MHz 142.5 MHz 11 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3
Data Arrival Time 8
Data Required Time 11
From uut/u_cordic/U/y_1_5_s0
To uut/u_cordic/U/x_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/y_1_5_s0/CLK
1.094 0.232 tC2Q RF 1 uut/u_cordic/U/y_1_5_s0/Q
1.331 0.237 tNET FF 1 uut/u_cordic/y_i_5_s/I0
1.848 0.517 tINS FF 4 uut/u_cordic/y_i_5_s/F
2.085 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/I1
2.640 0.555 tINS FF 3 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/F
2.877 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/I1
3.432 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/F
3.669 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/I1
4.224 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/F
4.461 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/I1
5.016 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/F
5.253 0.237 tNET FF 2 uut/u_cordic/U/n215_1_s/I1
5.823 0.57 tINS FR 1 uut/u_cordic/U/n215_1_s/COUT
5.823 0 tNET RR 2 uut/u_cordic/U/n214_1_s/CIN
5.858 0.035 tINS RF 1 uut/u_cordic/U/n214_1_s/COUT
5.858 0 tNET FF 2 uut/u_cordic/U/n213_1_s/CIN
5.893 0.035 tINS FF 1 uut/u_cordic/U/n213_1_s/COUT
5.893 0 tNET FF 2 uut/u_cordic/U/n212_1_s/CIN
5.929 0.035 tINS FF 1 uut/u_cordic/U/n212_1_s/COUT
5.929 0 tNET FF 2 uut/u_cordic/U/n211_1_s/CIN
5.964 0.035 tINS FF 1 uut/u_cordic/U/n211_1_s/COUT
5.964 0 tNET FF 2 uut/u_cordic/U/n210_1_s/CIN
5.999 0.035 tINS FF 1 uut/u_cordic/U/n210_1_s/COUT
5.999 0 tNET FF 2 uut/u_cordic/U/n209_1_s/CIN
6.034 0.035 tINS FF 1 uut/u_cordic/U/n209_1_s/COUT
6.034 0 tNET FF 2 uut/u_cordic/U/n208_1_s/CIN
6.069 0.035 tINS FF 1 uut/u_cordic/U/n208_1_s/COUT
6.069 0 tNET FF 2 uut/u_cordic/U/n207_1_s/CIN
6.105 0.035 tINS FF 1 uut/u_cordic/U/n207_1_s/COUT
6.105 0 tNET FF 2 uut/u_cordic/U/n206_1_s/CIN
6.140 0.035 tINS FF 1 uut/u_cordic/U/n206_1_s/COUT
6.140 0 tNET FF 2 uut/u_cordic/U/n205_1_s/CIN
6.175 0.035 tINS FF 1 uut/u_cordic/U/n205_1_s/COUT
6.175 0 tNET FF 2 uut/u_cordic/U/n204_1_s/CIN
6.210 0.035 tINS FF 1 uut/u_cordic/U/n204_1_s/COUT
6.210 0 tNET FF 2 uut/u_cordic/U/n203_1_s/CIN
6.245 0.035 tINS FF 1 uut/u_cordic/U/n203_1_s/COUT
6.245 0 tNET FF 2 uut/u_cordic/U/n202_1_s/CIN
6.281 0.035 tINS FF 1 uut/u_cordic/U/n202_1_s/COUT
6.281 0 tNET FF 2 uut/u_cordic/U/n201_1_s/CIN
6.316 0.035 tINS FF 1 uut/u_cordic/U/n201_1_s/COUT
6.316 0 tNET FF 2 uut/u_cordic/U/n200_1_s/CIN
6.351 0.035 tINS FF 1 uut/u_cordic/U/n200_1_s/COUT
6.351 0 tNET FF 2 uut/u_cordic/U/n199_1_s/CIN
6.821 0.47 tINS FF 1 uut/u_cordic/U/n199_1_s/SUM
7.058 0.237 tNET FF 1 uut/u_cordic/U/n250_s0/I0
7.575 0.517 tINS FF 1 uut/u_cordic/U/n250_s0/F
7.812 0.237 tNET FF 1 uut/u_cordic/U/x_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/x_1_16_s0/CLK

Path Statistic:
Clock Skew: 0
Hold Relationship: 10
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.822, 69.381%; route: 1.896, 27.281%; tC2Q: 0.232, 3.338%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.015
Data Arrival Time 7.777
Data Required Time 10.793
From uut/u_cordic/U/x_1_4_s0
To uut/u_cordic/U/y_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/x_1_4_s0/CLK
1.094 0.232 tC2Q RF 1 uut/u_cordic/U/x_1_4_s0/Q
1.331 0.237 tNET FF 1 uut/u_cordic/x_i_4_s/I0
1.848 0.517 tINS FF 5 uut/u_cordic/x_i_4_s/F
2.085 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s6/I1
2.640 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s6/F
2.877 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s3/I1
3.432 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s3/F
3.669 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s1/I1
4.224 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s1/F
4.461 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s/I1
5.016 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s/F
5.253 0.237 tNET FF 2 uut/u_cordic/U/n231_1_s/I1
5.823 0.57 tINS FR 1 uut/u_cordic/U/n231_1_s/COUT
5.823 0 tNET RR 2 uut/u_cordic/U/n230_1_s/CIN
5.858 0.035 tINS RF 1 uut/u_cordic/U/n230_1_s/COUT
5.858 0 tNET FF 2 uut/u_cordic/U/n229_1_s/CIN
5.893 0.035 tINS FF 1 uut/u_cordic/U/n229_1_s/COUT
5.893 0 tNET FF 2 uut/u_cordic/U/n228_1_s/CIN
5.929 0.035 tINS FF 1 uut/u_cordic/U/n228_1_s/COUT
5.929 0 tNET FF 2 uut/u_cordic/U/n227_1_s/CIN
5.964 0.035 tINS FF 1 uut/u_cordic/U/n227_1_s/COUT
5.964 0 tNET FF 2 uut/u_cordic/U/n226_1_s/CIN
5.999 0.035 tINS FF 1 uut/u_cordic/U/n226_1_s/COUT
5.999 0 tNET FF 2 uut/u_cordic/U/n225_1_s/CIN
6.034 0.035 tINS FF 1 uut/u_cordic/U/n225_1_s/COUT
6.034 0 tNET FF 2 uut/u_cordic/U/n224_1_s/CIN
6.069 0.035 tINS FF 1 uut/u_cordic/U/n224_1_s/COUT
6.069 0 tNET FF 2 uut/u_cordic/U/n223_1_s/CIN
6.105 0.035 tINS FF 1 uut/u_cordic/U/n223_1_s/COUT
6.105 0 tNET FF 2 uut/u_cordic/U/n222_1_s/CIN
6.140 0.035 tINS FF 1 uut/u_cordic/U/n222_1_s/COUT
6.140 0 tNET FF 2 uut/u_cordic/U/n221_1_s/CIN
6.175 0.035 tINS FF 1 uut/u_cordic/U/n221_1_s/COUT
6.175 0 tNET FF 2 uut/u_cordic/U/n220_1_s/CIN
6.210 0.035 tINS FF 1 uut/u_cordic/U/n220_1_s/COUT
6.210 0 tNET FF 2 uut/u_cordic/U/n219_1_s/CIN
6.245 0.035 tINS FF 1 uut/u_cordic/U/n219_1_s/COUT
6.245 0 tNET FF 2 uut/u_cordic/U/n218_1_s/CIN
6.281 0.035 tINS FF 1 uut/u_cordic/U/n218_1_s/COUT
6.281 0 tNET FF 2 uut/u_cordic/U/n217_1_s/CIN
6.316 0.035 tINS FF 1 uut/u_cordic/U/n217_1_s/COUT
6.316 0 tNET FF 2 uut/u_cordic/U/n216_1_s/CIN
6.786 0.47 tINS FF 1 uut/u_cordic/U/n216_1_s/SUM
7.023 0.237 tNET FF 1 uut/u_cordic/U/n267_s0/I0
7.540 0.517 tINS FF 1 uut/u_cordic/U/n267_s0/F
7.777 0.237 tNET FF 1 uut/u_cordic/U/y_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/y_1_16_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 9.609, 70.483%; route: 3.792, 27.815%; tC2Q: 0.232, 1.702%
Required Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%

Path 3

Path Summary:
Slack 3.015
Data Arrival Time 7.777
Data Required Time 10.793
From uut/u_cordic/U/y_1_5_s0
To uut/u_cordic/U/x_1_15_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/y_1_5_s0/CLK
1.094 0.232 tC2Q RF 1 uut/u_cordic/U/y_1_5_s0/Q
1.331 0.237 tNET FF 1 uut/u_cordic/y_i_5_s/I0
1.848 0.517 tINS FF 4 uut/u_cordic/y_i_5_s/F
2.085 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/I1
2.640 0.555 tINS FF 3 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/F
2.877 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/I1
3.432 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/F
3.669 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/I1
4.224 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/F
4.461 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/I1
5.016 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/F
5.253 0.237 tNET FF 2 uut/u_cordic/U/n215_1_s/I1
5.823 0.57 tINS FR 1 uut/u_cordic/U/n215_1_s/COUT
5.823 0 tNET RR 2 uut/u_cordic/U/n214_1_s/CIN
5.858 0.035 tINS RF 1 uut/u_cordic/U/n214_1_s/COUT
5.858 0 tNET FF 2 uut/u_cordic/U/n213_1_s/CIN
5.893 0.035 tINS FF 1 uut/u_cordic/U/n213_1_s/COUT
5.893 0 tNET FF 2 uut/u_cordic/U/n212_1_s/CIN
5.929 0.035 tINS FF 1 uut/u_cordic/U/n212_1_s/COUT
5.929 0 tNET FF 2 uut/u_cordic/U/n211_1_s/CIN
5.964 0.035 tINS FF 1 uut/u_cordic/U/n211_1_s/COUT
5.964 0 tNET FF 2 uut/u_cordic/U/n210_1_s/CIN
5.999 0.035 tINS FF 1 uut/u_cordic/U/n210_1_s/COUT
5.999 0 tNET FF 2 uut/u_cordic/U/n209_1_s/CIN
6.034 0.035 tINS FF 1 uut/u_cordic/U/n209_1_s/COUT
6.034 0 tNET FF 2 uut/u_cordic/U/n208_1_s/CIN
6.069 0.035 tINS FF 1 uut/u_cordic/U/n208_1_s/COUT
6.069 0 tNET FF 2 uut/u_cordic/U/n207_1_s/CIN
6.105 0.035 tINS FF 1 uut/u_cordic/U/n207_1_s/COUT
6.105 0 tNET FF 2 uut/u_cordic/U/n206_1_s/CIN
6.140 0.035 tINS FF 1 uut/u_cordic/U/n206_1_s/COUT
6.140 0 tNET FF 2 uut/u_cordic/U/n205_1_s/CIN
6.175 0.035 tINS FF 1 uut/u_cordic/U/n205_1_s/COUT
6.175 0 tNET FF 2 uut/u_cordic/U/n204_1_s/CIN
6.210 0.035 tINS FF 1 uut/u_cordic/U/n204_1_s/COUT
6.210 0 tNET FF 2 uut/u_cordic/U/n203_1_s/CIN
6.245 0.035 tINS FF 1 uut/u_cordic/U/n203_1_s/COUT
6.245 0 tNET FF 2 uut/u_cordic/U/n202_1_s/CIN
6.281 0.035 tINS FF 1 uut/u_cordic/U/n202_1_s/COUT
6.281 0 tNET FF 2 uut/u_cordic/U/n201_1_s/CIN
6.316 0.035 tINS FF 1 uut/u_cordic/U/n201_1_s/COUT
6.316 0 tNET FF 2 uut/u_cordic/U/n200_1_s/CIN
6.786 0.47 tINS FF 1 uut/u_cordic/U/n200_1_s/SUM
7.023 0.237 tNET FF 1 uut/u_cordic/U/n251_s0/I0
7.540 0.517 tINS FF 1 uut/u_cordic/U/n251_s0/F
7.777 0.237 tNET FF 1 uut/u_cordic/U/x_1_15_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/x_1_15_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 14.396, 70.860%; route: 5.688, 27.998%; tC2Q: 0.232, 1.142%
Required Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%

Path 4

Path Summary:
Slack 3.050
Data Arrival Time 7.742
Data Required Time 10.793
From uut/u_cordic/U/x_1_4_s0
To uut/u_cordic/U/y_1_15_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/x_1_4_s0/CLK
1.094 0.232 tC2Q RF 1 uut/u_cordic/U/x_1_4_s0/Q
1.331 0.237 tNET FF 1 uut/u_cordic/x_i_4_s/I0
1.848 0.517 tINS FF 5 uut/u_cordic/x_i_4_s/F
2.085 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s6/I1
2.640 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s6/F
2.877 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s3/I1
3.432 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s3/F
3.669 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s1/I1
4.224 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s1/F
4.461 0.237 tNET FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s/I1
5.016 0.555 tINS FF 1 uut/u_cordic/U/x_shifter/x_i_shifted_1_s/F
5.253 0.237 tNET FF 2 uut/u_cordic/U/n231_1_s/I1
5.823 0.57 tINS FR 1 uut/u_cordic/U/n231_1_s/COUT
5.823 0 tNET RR 2 uut/u_cordic/U/n230_1_s/CIN
5.858 0.035 tINS RF 1 uut/u_cordic/U/n230_1_s/COUT
5.858 0 tNET FF 2 uut/u_cordic/U/n229_1_s/CIN
5.893 0.035 tINS FF 1 uut/u_cordic/U/n229_1_s/COUT
5.893 0 tNET FF 2 uut/u_cordic/U/n228_1_s/CIN
5.929 0.035 tINS FF 1 uut/u_cordic/U/n228_1_s/COUT
5.929 0 tNET FF 2 uut/u_cordic/U/n227_1_s/CIN
5.964 0.035 tINS FF 1 uut/u_cordic/U/n227_1_s/COUT
5.964 0 tNET FF 2 uut/u_cordic/U/n226_1_s/CIN
5.999 0.035 tINS FF 1 uut/u_cordic/U/n226_1_s/COUT
5.999 0 tNET FF 2 uut/u_cordic/U/n225_1_s/CIN
6.034 0.035 tINS FF 1 uut/u_cordic/U/n225_1_s/COUT
6.034 0 tNET FF 2 uut/u_cordic/U/n224_1_s/CIN
6.069 0.035 tINS FF 1 uut/u_cordic/U/n224_1_s/COUT
6.069 0 tNET FF 2 uut/u_cordic/U/n223_1_s/CIN
6.105 0.035 tINS FF 1 uut/u_cordic/U/n223_1_s/COUT
6.105 0 tNET FF 2 uut/u_cordic/U/n222_1_s/CIN
6.140 0.035 tINS FF 1 uut/u_cordic/U/n222_1_s/COUT
6.140 0 tNET FF 2 uut/u_cordic/U/n221_1_s/CIN
6.175 0.035 tINS FF 1 uut/u_cordic/U/n221_1_s/COUT
6.175 0 tNET FF 2 uut/u_cordic/U/n220_1_s/CIN
6.210 0.035 tINS FF 1 uut/u_cordic/U/n220_1_s/COUT
6.210 0 tNET FF 2 uut/u_cordic/U/n219_1_s/CIN
6.245 0.035 tINS FF 1 uut/u_cordic/U/n219_1_s/COUT
6.245 0 tNET FF 2 uut/u_cordic/U/n218_1_s/CIN
6.281 0.035 tINS FF 1 uut/u_cordic/U/n218_1_s/COUT
6.281 0 tNET FF 2 uut/u_cordic/U/n217_1_s/CIN
6.751 0.47 tINS FF 1 uut/u_cordic/U/n217_1_s/SUM
6.988 0.237 tNET FF 1 uut/u_cordic/U/n268_s0/I0
7.505 0.517 tINS FF 1 uut/u_cordic/U/n268_s0/F
7.742 0.237 tNET FF 1 uut/u_cordic/U/y_1_15_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/y_1_15_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 19.147, 71.012%; route: 7.584, 28.127%; tC2Q: 0.232, 0.860%
Required Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%

Path 5

Path Summary:
Slack 3.050
Data Arrival Time 7.742
Data Required Time 10.793
From uut/u_cordic/U/y_1_5_s0
To uut/u_cordic/U/x_1_14_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/y_1_5_s0/CLK
1.094 0.232 tC2Q RF 1 uut/u_cordic/U/y_1_5_s0/Q
1.331 0.237 tNET FF 1 uut/u_cordic/y_i_5_s/I0
1.848 0.517 tINS FF 4 uut/u_cordic/y_i_5_s/F
2.085 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/I1
2.640 0.555 tINS FF 3 uut/u_cordic/U/y_shifter/y_i_shifted_2_s6/F
2.877 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/I1
3.432 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s4/F
3.669 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/I1
4.224 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s1/F
4.461 0.237 tNET FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/I1
5.016 0.555 tINS FF 1 uut/u_cordic/U/y_shifter/y_i_shifted_0_s/F
5.253 0.237 tNET FF 2 uut/u_cordic/U/n215_1_s/I1
5.823 0.57 tINS FR 1 uut/u_cordic/U/n215_1_s/COUT
5.823 0 tNET RR 2 uut/u_cordic/U/n214_1_s/CIN
5.858 0.035 tINS RF 1 uut/u_cordic/U/n214_1_s/COUT
5.858 0 tNET FF 2 uut/u_cordic/U/n213_1_s/CIN
5.893 0.035 tINS FF 1 uut/u_cordic/U/n213_1_s/COUT
5.893 0 tNET FF 2 uut/u_cordic/U/n212_1_s/CIN
5.929 0.035 tINS FF 1 uut/u_cordic/U/n212_1_s/COUT
5.929 0 tNET FF 2 uut/u_cordic/U/n211_1_s/CIN
5.964 0.035 tINS FF 1 uut/u_cordic/U/n211_1_s/COUT
5.964 0 tNET FF 2 uut/u_cordic/U/n210_1_s/CIN
5.999 0.035 tINS FF 1 uut/u_cordic/U/n210_1_s/COUT
5.999 0 tNET FF 2 uut/u_cordic/U/n209_1_s/CIN
6.034 0.035 tINS FF 1 uut/u_cordic/U/n209_1_s/COUT
6.034 0 tNET FF 2 uut/u_cordic/U/n208_1_s/CIN
6.069 0.035 tINS FF 1 uut/u_cordic/U/n208_1_s/COUT
6.069 0 tNET FF 2 uut/u_cordic/U/n207_1_s/CIN
6.105 0.035 tINS FF 1 uut/u_cordic/U/n207_1_s/COUT
6.105 0 tNET FF 2 uut/u_cordic/U/n206_1_s/CIN
6.140 0.035 tINS FF 1 uut/u_cordic/U/n206_1_s/COUT
6.140 0 tNET FF 2 uut/u_cordic/U/n205_1_s/CIN
6.175 0.035 tINS FF 1 uut/u_cordic/U/n205_1_s/COUT
6.175 0 tNET FF 2 uut/u_cordic/U/n204_1_s/CIN
6.210 0.035 tINS FF 1 uut/u_cordic/U/n204_1_s/COUT
6.210 0 tNET FF 2 uut/u_cordic/U/n203_1_s/CIN
6.245 0.035 tINS FF 1 uut/u_cordic/U/n203_1_s/COUT
6.245 0 tNET FF 2 uut/u_cordic/U/n202_1_s/CIN
6.281 0.035 tINS FF 1 uut/u_cordic/U/n202_1_s/COUT
6.281 0 tNET FF 2 uut/u_cordic/U/n201_1_s/CIN
6.751 0.47 tINS FF 1 uut/u_cordic/U/n201_1_s/SUM
6.988 0.237 tNET FF 1 uut/u_cordic/U/n252_s0/I0
7.505 0.517 tINS FF 1 uut/u_cordic/U/n252_s0/F
7.742 0.237 tNET FF 1 uut/u_cordic/U/x_1_14_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 94 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/U/x_1_14_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 23.899, 71.105%; route: 9.480, 28.205%; tC2Q: 0.232, 0.690%
Required Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%

Synthesis completed successfully!
Process took 0h:0m:1s realtime, 0h:0m:0s cputime
Memory peak: 644.6MB