Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\release_verify\Release\cordic\ref_design\rotate_pipeline_radian\project\src\cordic\cordic.v
E:\myWork\IP\release_verify\Release\cordic\ref_design\rotate_pipeline_radian\project\src\top.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Sun Sep 27 16:49:18 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: top
Part Number: GW2A-LV55PG484C8/I7
Device: GW2A-55

Resource

Resource Usage Summary

I/O Port 73
I/O Buf 73
    IBUF 2
    OBUF 71
Register 816
    DFF 3
    DFFE 6
    DFFR 803
    DFFRE 4
LUT 60
    LUT2 23
    LUT3 9
    LUT4 28
ALU 778
    ALU 778
INV 21
    INV 21
BSRAM 3
    pROM 2
    pROMX9 1

Resource Utilization Summary

Logic 859(81 LUTs, 778 ALUs) / 54720 2%
Register 816 / 42000 2%
BSRAM 3 / 140 2%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0 MHz 336.5 MHz 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7
Data Arrival Time 4
Data Required Time 11
From theta_i_0_s51
To uut/u_cordic/[0].U/z_1_16_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 theta_i_0_s51/CLK
1.094 0.232 tC2Q RF 16 theta_i_0_s51/Q
1.331 0.237 tNET FF 1 theta_i_3_s8/I0
1.848 0.517 tINS FF 1 theta_i_3_s8/F
2.085 0.237 tNET FF 2 uut/u_cordic/[0].U/n223_1_s/I0
2.634 0.549 tINS FR 1 uut/u_cordic/[0].U/n223_1_s/COUT
2.634 0 tNET RR 2 uut/u_cordic/[0].U/n222_1_s/CIN
2.669 0.035 tINS RF 1 uut/u_cordic/[0].U/n222_1_s/COUT
2.669 0 tNET FF 2 uut/u_cordic/[0].U/n221_1_s/CIN
2.704 0.035 tINS FF 1 uut/u_cordic/[0].U/n221_1_s/COUT
2.704 0 tNET FF 2 uut/u_cordic/[0].U/n220_1_s/CIN
2.740 0.035 tINS FF 1 uut/u_cordic/[0].U/n220_1_s/COUT
2.740 0 tNET FF 2 uut/u_cordic/[0].U/n219_1_s/CIN
2.775 0.035 tINS FF 1 uut/u_cordic/[0].U/n219_1_s/COUT
2.775 0 tNET FF 2 uut/u_cordic/[0].U/n218_1_s/CIN
2.810 0.035 tINS FF 1 uut/u_cordic/[0].U/n218_1_s/COUT
2.810 0 tNET FF 2 uut/u_cordic/[0].U/n217_1_s/CIN
2.845 0.035 tINS FF 1 uut/u_cordic/[0].U/n217_1_s/COUT
2.845 0 tNET FF 2 uut/u_cordic/[0].U/n216_1_s/CIN
2.880 0.035 tINS FF 1 uut/u_cordic/[0].U/n216_1_s/COUT
2.880 0 tNET FF 2 uut/u_cordic/[0].U/n215_1_s/CIN
2.916 0.035 tINS FF 1 uut/u_cordic/[0].U/n215_1_s/COUT
2.916 0 tNET FF 2 uut/u_cordic/[0].U/n214_1_s/CIN
2.951 0.035 tINS FF 1 uut/u_cordic/[0].U/n214_1_s/COUT
2.951 0 tNET FF 2 uut/u_cordic/[0].U/n213_1_s/CIN
2.986 0.035 tINS FF 1 uut/u_cordic/[0].U/n213_1_s/COUT
2.986 0 tNET FF 2 uut/u_cordic/[0].U/n212_1_s/CIN
3.021 0.035 tINS FF 1 uut/u_cordic/[0].U/n212_1_s/COUT
3.021 0 tNET FF 2 uut/u_cordic/[0].U/n211_1_s/CIN
3.056 0.035 tINS FF 1 uut/u_cordic/[0].U/n211_1_s/COUT
3.056 0 tNET FF 2 uut/u_cordic/[0].U/n210_1_s/CIN
3.526 0.47 tINS FF 1 uut/u_cordic/[0].U/n210_1_s/SUM
3.763 0.237 tNET FF 1 uut/u_cordic/[0].U/z_1_16_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/[0].U/z_1_16_s0/CLK

Path Statistic:
Clock Skew: 0
Hold Relationship: 10
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.958, 67.498%; route: 0.711, 24.505%; tC2Q: 0.232, 7.996%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 7.064
Data Arrival Time 3.729
Data Required Time 10.793
From theta_i_0_s51
To uut/u_cordic/[0].U/z_1_15_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 theta_i_0_s51/CLK
1.094 0.232 tC2Q RF 16 theta_i_0_s51/Q
1.331 0.237 tNET FF 1 theta_i_3_s8/I0
1.848 0.517 tINS FF 1 theta_i_3_s8/F
2.085 0.237 tNET FF 2 uut/u_cordic/[0].U/n223_1_s/I0
2.634 0.549 tINS FR 1 uut/u_cordic/[0].U/n223_1_s/COUT
2.634 0 tNET RR 2 uut/u_cordic/[0].U/n222_1_s/CIN
2.669 0.035 tINS RF 1 uut/u_cordic/[0].U/n222_1_s/COUT
2.669 0 tNET FF 2 uut/u_cordic/[0].U/n221_1_s/CIN
2.704 0.035 tINS FF 1 uut/u_cordic/[0].U/n221_1_s/COUT
2.704 0 tNET FF 2 uut/u_cordic/[0].U/n220_1_s/CIN
2.740 0.035 tINS FF 1 uut/u_cordic/[0].U/n220_1_s/COUT
2.740 0 tNET FF 2 uut/u_cordic/[0].U/n219_1_s/CIN
2.775 0.035 tINS FF 1 uut/u_cordic/[0].U/n219_1_s/COUT
2.775 0 tNET FF 2 uut/u_cordic/[0].U/n218_1_s/CIN
2.810 0.035 tINS FF 1 uut/u_cordic/[0].U/n218_1_s/COUT
2.810 0 tNET FF 2 uut/u_cordic/[0].U/n217_1_s/CIN
2.845 0.035 tINS FF 1 uut/u_cordic/[0].U/n217_1_s/COUT
2.845 0 tNET FF 2 uut/u_cordic/[0].U/n216_1_s/CIN
2.880 0.035 tINS FF 1 uut/u_cordic/[0].U/n216_1_s/COUT
2.880 0 tNET FF 2 uut/u_cordic/[0].U/n215_1_s/CIN
2.916 0.035 tINS FF 1 uut/u_cordic/[0].U/n215_1_s/COUT
2.916 0 tNET FF 2 uut/u_cordic/[0].U/n214_1_s/CIN
2.951 0.035 tINS FF 1 uut/u_cordic/[0].U/n214_1_s/COUT
2.951 0 tNET FF 2 uut/u_cordic/[0].U/n213_1_s/CIN
2.986 0.035 tINS FF 1 uut/u_cordic/[0].U/n213_1_s/COUT
2.986 0 tNET FF 2 uut/u_cordic/[0].U/n212_1_s/CIN
3.021 0.035 tINS FF 1 uut/u_cordic/[0].U/n212_1_s/COUT
3.021 0 tNET FF 2 uut/u_cordic/[0].U/n211_1_s/CIN
3.491 0.47 tINS FF 1 uut/u_cordic/[0].U/n211_1_s/SUM
3.728 0.237 tNET FF 1 uut/u_cordic/[0].U/z_1_15_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/[0].U/z_1_15_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 3.882, 70.121%; route: 1.422, 25.688%; tC2Q: 0.232, 4.191%
Required Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%

Path 3

Path Summary:
Slack 7.099
Data Arrival Time 3.694
Data Required Time 10.793
From theta_i_0_s51
To uut/u_cordic/[0].U/z_1_14_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 theta_i_0_s51/CLK
1.094 0.232 tC2Q RF 16 theta_i_0_s51/Q
1.331 0.237 tNET FF 1 theta_i_3_s8/I0
1.848 0.517 tINS FF 1 theta_i_3_s8/F
2.085 0.237 tNET FF 2 uut/u_cordic/[0].U/n223_1_s/I0
2.634 0.549 tINS FR 1 uut/u_cordic/[0].U/n223_1_s/COUT
2.634 0 tNET RR 2 uut/u_cordic/[0].U/n222_1_s/CIN
2.669 0.035 tINS RF 1 uut/u_cordic/[0].U/n222_1_s/COUT
2.669 0 tNET FF 2 uut/u_cordic/[0].U/n221_1_s/CIN
2.704 0.035 tINS FF 1 uut/u_cordic/[0].U/n221_1_s/COUT
2.704 0 tNET FF 2 uut/u_cordic/[0].U/n220_1_s/CIN
2.740 0.035 tINS FF 1 uut/u_cordic/[0].U/n220_1_s/COUT
2.740 0 tNET FF 2 uut/u_cordic/[0].U/n219_1_s/CIN
2.775 0.035 tINS FF 1 uut/u_cordic/[0].U/n219_1_s/COUT
2.775 0 tNET FF 2 uut/u_cordic/[0].U/n218_1_s/CIN
2.810 0.035 tINS FF 1 uut/u_cordic/[0].U/n218_1_s/COUT
2.810 0 tNET FF 2 uut/u_cordic/[0].U/n217_1_s/CIN
2.845 0.035 tINS FF 1 uut/u_cordic/[0].U/n217_1_s/COUT
2.845 0 tNET FF 2 uut/u_cordic/[0].U/n216_1_s/CIN
2.880 0.035 tINS FF 1 uut/u_cordic/[0].U/n216_1_s/COUT
2.880 0 tNET FF 2 uut/u_cordic/[0].U/n215_1_s/CIN
2.916 0.035 tINS FF 1 uut/u_cordic/[0].U/n215_1_s/COUT
2.916 0 tNET FF 2 uut/u_cordic/[0].U/n214_1_s/CIN
2.951 0.035 tINS FF 1 uut/u_cordic/[0].U/n214_1_s/COUT
2.951 0 tNET FF 2 uut/u_cordic/[0].U/n213_1_s/CIN
2.986 0.035 tINS FF 1 uut/u_cordic/[0].U/n213_1_s/COUT
2.986 0 tNET FF 2 uut/u_cordic/[0].U/n212_1_s/CIN
3.456 0.47 tINS FF 1 uut/u_cordic/[0].U/n212_1_s/SUM
3.693 0.237 tNET FF 1 uut/u_cordic/[0].U/z_1_14_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/[0].U/z_1_14_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 5.770, 70.927%; route: 2.133, 26.221%; tC2Q: 0.232, 2.852%
Required Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%

Path 4

Path Summary:
Slack 7.134
Data Arrival Time 3.658
Data Required Time 10.793
From theta_i_0_s51
To uut/u_cordic/[0].U/z_1_13_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 theta_i_0_s51/CLK
1.094 0.232 tC2Q RF 16 theta_i_0_s51/Q
1.331 0.237 tNET FF 1 theta_i_3_s8/I0
1.848 0.517 tINS FF 1 theta_i_3_s8/F
2.085 0.237 tNET FF 2 uut/u_cordic/[0].U/n223_1_s/I0
2.634 0.549 tINS FR 1 uut/u_cordic/[0].U/n223_1_s/COUT
2.634 0 tNET RR 2 uut/u_cordic/[0].U/n222_1_s/CIN
2.669 0.035 tINS RF 1 uut/u_cordic/[0].U/n222_1_s/COUT
2.669 0 tNET FF 2 uut/u_cordic/[0].U/n221_1_s/CIN
2.704 0.035 tINS FF 1 uut/u_cordic/[0].U/n221_1_s/COUT
2.704 0 tNET FF 2 uut/u_cordic/[0].U/n220_1_s/CIN
2.740 0.035 tINS FF 1 uut/u_cordic/[0].U/n220_1_s/COUT
2.740 0 tNET FF 2 uut/u_cordic/[0].U/n219_1_s/CIN
2.775 0.035 tINS FF 1 uut/u_cordic/[0].U/n219_1_s/COUT
2.775 0 tNET FF 2 uut/u_cordic/[0].U/n218_1_s/CIN
2.810 0.035 tINS FF 1 uut/u_cordic/[0].U/n218_1_s/COUT
2.810 0 tNET FF 2 uut/u_cordic/[0].U/n217_1_s/CIN
2.845 0.035 tINS FF 1 uut/u_cordic/[0].U/n217_1_s/COUT
2.845 0 tNET FF 2 uut/u_cordic/[0].U/n216_1_s/CIN
2.880 0.035 tINS FF 1 uut/u_cordic/[0].U/n216_1_s/COUT
2.880 0 tNET FF 2 uut/u_cordic/[0].U/n215_1_s/CIN
2.916 0.035 tINS FF 1 uut/u_cordic/[0].U/n215_1_s/COUT
2.916 0 tNET FF 2 uut/u_cordic/[0].U/n214_1_s/CIN
2.951 0.035 tINS FF 1 uut/u_cordic/[0].U/n214_1_s/COUT
2.951 0 tNET FF 2 uut/u_cordic/[0].U/n213_1_s/CIN
3.421 0.47 tINS FF 1 uut/u_cordic/[0].U/n213_1_s/SUM
3.658 0.237 tNET FF 1 uut/u_cordic/[0].U/z_1_13_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/[0].U/z_1_13_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 7.622, 71.248%; route: 2.844, 26.583%; tC2Q: 0.232, 2.169%
Required Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%

Path 5

Path Summary:
Slack 7.169
Data Arrival Time 3.623
Data Required Time 10.793
From theta_i_0_s51
To uut/u_cordic/[0].U/z_1_12_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 theta_i_0_s51/CLK
1.094 0.232 tC2Q RF 16 theta_i_0_s51/Q
1.331 0.237 tNET FF 1 theta_i_3_s8/I0
1.848 0.517 tINS FF 1 theta_i_3_s8/F
2.085 0.237 tNET FF 2 uut/u_cordic/[0].U/n223_1_s/I0
2.634 0.549 tINS FR 1 uut/u_cordic/[0].U/n223_1_s/COUT
2.634 0 tNET RR 2 uut/u_cordic/[0].U/n222_1_s/CIN
2.669 0.035 tINS RF 1 uut/u_cordic/[0].U/n222_1_s/COUT
2.669 0 tNET FF 2 uut/u_cordic/[0].U/n221_1_s/CIN
2.704 0.035 tINS FF 1 uut/u_cordic/[0].U/n221_1_s/COUT
2.704 0 tNET FF 2 uut/u_cordic/[0].U/n220_1_s/CIN
2.740 0.035 tINS FF 1 uut/u_cordic/[0].U/n220_1_s/COUT
2.740 0 tNET FF 2 uut/u_cordic/[0].U/n219_1_s/CIN
2.775 0.035 tINS FF 1 uut/u_cordic/[0].U/n219_1_s/COUT
2.775 0 tNET FF 2 uut/u_cordic/[0].U/n218_1_s/CIN
2.810 0.035 tINS FF 1 uut/u_cordic/[0].U/n218_1_s/COUT
2.810 0 tNET FF 2 uut/u_cordic/[0].U/n217_1_s/CIN
2.845 0.035 tINS FF 1 uut/u_cordic/[0].U/n217_1_s/COUT
2.845 0 tNET FF 2 uut/u_cordic/[0].U/n216_1_s/CIN
2.880 0.035 tINS FF 1 uut/u_cordic/[0].U/n216_1_s/COUT
2.880 0 tNET FF 2 uut/u_cordic/[0].U/n215_1_s/CIN
2.916 0.035 tINS FF 1 uut/u_cordic/[0].U/n215_1_s/COUT
2.916 0 tNET FF 2 uut/u_cordic/[0].U/n214_1_s/CIN
3.386 0.47 tINS FF 1 uut/u_cordic/[0].U/n214_1_s/SUM
3.623 0.237 tNET FF 1 uut/u_cordic/[0].U/z_1_12_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 819 clk_ibuf/O
0.862 0.18 tNET RR 1 uut/u_cordic/[0].U/z_1_12_s0/CLK

Path Statistic:
Clock Skew: 0.000
Hold Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 9.440, 71.369%; route: 3.555, 26.877%; tC2Q: 0.232, 1.754%
Required Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%

Synthesis completed successfully!
Process took 0h:0m:5s realtime, 0h:0m:5s cputime
Memory peak: 105.0MB