Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.8.02\IDE\ipcore\CFA\data\CFA_top.v C:\Gowin\Gowin_V1.9.8.02\IDE\ipcore\CFA\data\CFA_top_wrap.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.02 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Wed Dec 29 14:06:42 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Color_Filter_Array_Interpolation_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.272s, Peak memory usage = 45.730MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.730MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 45.730MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 45.730MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 45.730MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 45.730MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.730MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 45.730MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 45.730MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 45.730MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 45.730MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 45.730MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 59.309MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 59.309MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 59.309MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 59.309MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 40 |
I/O Buf | 40 |
    IBUF | 13 |
    OBUF | 27 |
Register | 553 |
    DFF | 1 |
    DFFR | 24 |
    DFFP | 12 |
    DFFPE | 10 |
    DFFC | 421 |
    DFFCE | 85 |
LUT | 684 |
    LUT2 | 99 |
    LUT3 | 224 |
    LUT4 | 361 |
ALU | 524 |
    ALU | 524 |
SSRAM | 2 |
    RAM16S4 | 2 |
INV | 6 |
    INV | 6 |
BSRAM | 6 |
    SDPB | 6 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1226(690 LUTs, 524 ALUs, 2 SSRAMs) / 20736 | 6% |
Register | 553 / 16173 | 3% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 553 / 16173 | 3% |
BSRAM | 6 / 46 | 13% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 152.5(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.445 |
Data Arrival Time | 7.383 |
Data Required Time | 10.828 |
From | cfa_top/interpolation/data_layer_1[4]_3_s0 |
To | cfa_top/interpolation/layer_3_3_12_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/data_layer_1[4]_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | cfa_top/interpolation/data_layer_1[4]_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_4_s6/I1 |
1.887 | 0.555 | tINS | FF | 4 | cfa_top/interpolation/layer_1_1_3_4_s6/F |
2.124 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s7/I3 |
2.495 | 0.371 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s7/F |
2.732 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s5/I1 |
3.287 | 0.555 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s5/F |
3.524 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2850_s/I1 |
4.094 | 0.570 | tINS | FR | 1 | cfa_top/interpolation/n2850_s/COUT |
4.094 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2849_s4/CIN |
4.129 | 0.035 | tINS | RF | 1 | cfa_top/interpolation/n2849_s4/COUT |
4.129 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2848_s4/CIN |
4.164 | 0.035 | tINS | FF | 1 | cfa_top/interpolation/n2848_s4/COUT |
4.164 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2847_s4/CIN |
4.634 | 0.470 | tINS | FF | 1 | cfa_top/interpolation/n2847_s4/SUM |
4.871 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2847_s2/I0 |
5.420 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2847_s2/COUT |
5.420 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2846_s2/CIN |
5.890 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2846_s2/SUM |
6.127 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2846_s3/I0 |
6.676 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2846_s3/COUT |
6.676 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2845_s3/CIN |
7.146 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2845_s3/SUM |
7.383 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_3_3_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/layer_3_3_12_s0/CLK |
10.828 | -0.035 | tSu | 1 | cfa_top/interpolation/layer_3_3_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.629, 70.999%; route: 1.659, 25.443%; tC2Q: 0.232, 3.558% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 3.445 |
Data Arrival Time | 7.383 |
Data Required Time | 10.828 |
From | cfa_top/interpolation/data_layer_1[4]_3_s0 |
To | cfa_top/interpolation/layer_1_3_12_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/data_layer_1[4]_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | cfa_top/interpolation/data_layer_1[4]_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_4_s6/I1 |
1.887 | 0.555 | tINS | FF | 4 | cfa_top/interpolation/layer_1_1_3_4_s6/F |
2.124 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s7/I3 |
2.495 | 0.371 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s7/F |
2.732 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s5/I1 |
3.287 | 0.555 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s5/F |
3.524 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2448_s/I1 |
4.094 | 0.570 | tINS | FR | 1 | cfa_top/interpolation/n2448_s/COUT |
4.094 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2447_s4/CIN |
4.129 | 0.035 | tINS | RF | 1 | cfa_top/interpolation/n2447_s4/COUT |
4.129 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2446_s4/CIN |
4.164 | 0.035 | tINS | FF | 1 | cfa_top/interpolation/n2446_s4/COUT |
4.164 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2445_s4/CIN |
4.634 | 0.470 | tINS | FF | 1 | cfa_top/interpolation/n2445_s4/SUM |
4.871 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2445_s2/I0 |
5.420 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2445_s2/COUT |
5.420 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2444_s2/CIN |
5.890 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2444_s2/SUM |
6.127 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2444_s3/I0 |
6.676 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2444_s3/COUT |
6.676 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2443_s3/CIN |
7.146 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2443_s3/SUM |
7.383 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_3_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/layer_1_3_12_s0/CLK |
10.828 | -0.035 | tSu | 1 | cfa_top/interpolation/layer_1_3_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.629, 70.999%; route: 1.659, 25.443%; tC2Q: 0.232, 3.558% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 3.480 |
Data Arrival Time | 7.348 |
Data Required Time | 10.828 |
From | cfa_top/interpolation/data_layer_1[4]_3_s0 |
To | cfa_top/interpolation/layer_3_3_11_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/data_layer_1[4]_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | cfa_top/interpolation/data_layer_1[4]_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_4_s6/I1 |
1.887 | 0.555 | tINS | FF | 4 | cfa_top/interpolation/layer_1_1_3_4_s6/F |
2.124 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s7/I3 |
2.495 | 0.371 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s7/F |
2.732 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s5/I1 |
3.287 | 0.555 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s5/F |
3.524 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2850_s/I1 |
4.094 | 0.570 | tINS | FR | 1 | cfa_top/interpolation/n2850_s/COUT |
4.094 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2849_s4/CIN |
4.129 | 0.035 | tINS | RF | 1 | cfa_top/interpolation/n2849_s4/COUT |
4.129 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2848_s4/CIN |
4.599 | 0.470 | tINS | FF | 1 | cfa_top/interpolation/n2848_s4/SUM |
4.836 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2848_s2/I0 |
5.385 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2848_s2/COUT |
5.385 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2847_s2/CIN |
5.855 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2847_s2/SUM |
6.092 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2847_s3/I0 |
6.641 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2847_s3/COUT |
6.641 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2846_s3/CIN |
7.111 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2846_s3/SUM |
7.348 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_3_3_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/layer_3_3_11_s0/CLK |
10.828 | -0.035 | tSu | 1 | cfa_top/interpolation/layer_3_3_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.594, 70.842%; route: 1.659, 25.581%; tC2Q: 0.232, 3.577% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 3.480 |
Data Arrival Time | 7.348 |
Data Required Time | 10.828 |
From | cfa_top/interpolation/data_layer_1[4]_3_s0 |
To | cfa_top/interpolation/layer_1_3_11_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/data_layer_1[4]_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | cfa_top/interpolation/data_layer_1[4]_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_4_s6/I1 |
1.887 | 0.555 | tINS | FF | 4 | cfa_top/interpolation/layer_1_1_3_4_s6/F |
2.124 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s7/I3 |
2.495 | 0.371 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s7/F |
2.732 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s5/I1 |
3.287 | 0.555 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s5/F |
3.524 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2448_s/I1 |
4.094 | 0.570 | tINS | FR | 1 | cfa_top/interpolation/n2448_s/COUT |
4.094 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2447_s4/CIN |
4.129 | 0.035 | tINS | RF | 1 | cfa_top/interpolation/n2447_s4/COUT |
4.129 | 0.000 | tNET | FF | 2 | cfa_top/interpolation/n2446_s4/CIN |
4.599 | 0.470 | tINS | FF | 1 | cfa_top/interpolation/n2446_s4/SUM |
4.836 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2446_s2/I0 |
5.385 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2446_s2/COUT |
5.385 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2445_s2/CIN |
5.855 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2445_s2/SUM |
6.092 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2445_s3/I0 |
6.641 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2445_s3/COUT |
6.641 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2444_s3/CIN |
7.111 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2444_s3/SUM |
7.348 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_3_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/layer_1_3_11_s0/CLK |
10.828 | -0.035 | tSu | 1 | cfa_top/interpolation/layer_1_3_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.594, 70.842%; route: 1.659, 25.581%; tC2Q: 0.232, 3.577% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 3.515 |
Data Arrival Time | 7.312 |
Data Required Time | 10.828 |
From | cfa_top/interpolation/data_layer_1[4]_3_s0 |
To | cfa_top/interpolation/layer_3_3_10_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/data_layer_1[4]_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | cfa_top/interpolation/data_layer_1[4]_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_4_s6/I1 |
1.887 | 0.555 | tINS | FF | 4 | cfa_top/interpolation/layer_1_1_3_4_s6/F |
2.124 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s7/I3 |
2.495 | 0.371 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s7/F |
2.732 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_1_1_3_7_s5/I1 |
3.287 | 0.555 | tINS | FF | 2 | cfa_top/interpolation/layer_1_1_3_7_s5/F |
3.524 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2850_s/I1 |
4.094 | 0.570 | tINS | FR | 1 | cfa_top/interpolation/n2850_s/COUT |
4.094 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2849_s4/CIN |
4.563 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2849_s4/SUM |
4.800 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2849_s2/I0 |
5.349 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2849_s2/COUT |
5.349 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2848_s2/CIN |
5.819 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2848_s2/SUM |
6.056 | 0.237 | tNET | FF | 2 | cfa_top/interpolation/n2848_s3/I0 |
6.605 | 0.549 | tINS | FR | 1 | cfa_top/interpolation/n2848_s3/COUT |
6.605 | 0.000 | tNET | RR | 2 | cfa_top/interpolation/n2847_s3/CIN |
7.075 | 0.470 | tINS | RF | 1 | cfa_top/interpolation/n2847_s3/SUM |
7.312 | 0.237 | tNET | FF | 1 | cfa_top/interpolation/layer_3_3_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 567 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | cfa_top/interpolation/layer_3_3_10_s0/CLK |
10.828 | -0.035 | tSu | 1 | cfa_top/interpolation/layer_3_3_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.559, 70.682%; route: 1.659, 25.721%; tC2Q: 0.232, 3.597% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |