//
// Written by Synplify Pro 
// Product Version "O-2018.09G-SP1-1-Beta1"
// Program "Synplify Pro", Mapper "mapgw2018q4p1, Build 001R"
// Mon May  6 08:20:46 2019
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\c:\gowin\1.9.02\synplifypro\lib\generic\gw2a.v "
// file 1 "\c:\gowin\1.9.02\synplifypro\lib\vlog\hypermods.v "
// file 2 "\c:\gowin\1.9.02\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\c:\gowin\1.9.02\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\c:\gowin\1.9.02\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\c:\gowin\1.9.02\ide\ipcore\ddr3_phy\data\ddr3_1_2code.v "
// file 6 "\f:\gwip_test\refdesign_sdc\gowin_ddr3_memory_interface_refdesign\ddr3_phy_1vs2_2a55k\project\src\ddr3_phy_interface\temp\ddr3_phy\ddr3_name.v "
// file 7 "\f:\gwip_test\refdesign_sdc\gowin_ddr3_memory_interface_refdesign\ddr3_phy_1vs2_2a55k\project\src\ddr3_phy_interface\temp\ddr3_phy\gwmc_param.v "
// file 8 "\c:\gowin\1.9.02\ide\ipcore\ddr3_phy\data\gwmc_local_param.v "
// file 9 "\f:\gwip_test\refdesign_sdc\gowin_ddr3_memory_interface_refdesign\ddr3_phy_1vs2_2a55k\project\src\ddr3_phy_interface\temp\ddr3_phy\ddr3_define.v "
// file 10 "\f:\gwip_test\refdesign_sdc\gowin_ddr3_memory_interface_refdesign\ddr3_phy_1vs2_2a55k\project\src\ddr3_phy_interface\temp\ddr3_phy\ddr3_pll_config.v "
// file 11 "\c:\gowin\1.9.02\ide\ipcore\ddr3_phy\data\ddr3_phy_top.v "
// file 12 "\c:\gowin\1.9.02\synplifypro\lib\nlconst.dat "

`timescale 100 ps/100 ps
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
`pragma protect key_block
EO5mMEWvR2OuAuWBTXF/kIL7eOHVrJnfHBcnvAorhaE5KfBdlfQQ3qt5aawaqO2Gv719FuhV0lFE
hiZe3ORb5CmiSzrd3nMPth9Pm6ojZwRim9kKrrZmILBRtPpLcnfgYLXFmGjLVyRd+ocz/APqWHkA
da+Ls6Gl2mgEo1mDTRpI3FjEFsiQD+tmPWzFkIIBezrUr0yTybCGMiLpiEOfiEeT8wsH21bKfqw2
VaD61JN8LziROFdJ10E/h6jZuDrfN2KM4oxVahhnfDn0/u0CldcqOJTgAovzmBIxhfw1WkM9cHwb
fv0wXUbLxQKxyQc2V6mwcOUTC5pw5GJYdGcqDQ==

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GoWin"
`pragma protect key_keyname="GoWin2016"
`pragma protect key_method="rsa"
`pragma protect key_block
vB+PAYeOwbWXWEISuIS+1IsQmZTcQc8Fh432LB6qAM5OElfpZmWbVTyr8gF+4BNXUprGH5A8mBHa
YoZlVoi+spWQrlipL2AqYbyL7ZC90AsX2tQC7qaJVmNVXCK/V99dpJaZG/tbSG9bqdIaQs2YJzhD
jcuhrRlkQzS2eD+7OCuL4U5mbvgLrYUPvwhe9Y1baSGw/dLVezuCIKuZl5AaPdrZg1Z2GlA/rJFC
wrWg4IyWo0V/x6D7JuFloUGUdWZfgZWXku/vpcto5+9/FLjXYfzVTIf6BvZ5EWBbzVYCf5SOl0g4
Ktoo3vMpIDibZ4a1XSbcK8C8qgjZ2Lu9X4gHvQ==

`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=297424)
`pragma protect data_block
[encoded data, 396568 characters]
`pragma protect end_protected
module DDR3_PHY_Interface_Top (
  clk,
  rst_n,
  mc_cs_n,
  mc_ras_n,
  mc_cas_n,
  mc_we_n,
  mc_address,
  mc_bank,
  mc_odt,
  mc_reset_n,
  mc_cke,
  mc_cmd_wren,
  mc_wrdata_en,
  mc_wrdata,
  mc_wrdata_mask,
  phy_rd_data_valid,
  phy_rd_data,
  ddr_init_complete,
  O_ddr_addr,
  O_ddr_ba,
  O_ddr_cs_n,
  O_ddr_ras_n,
  O_ddr_cas_n,
  O_ddr_we_n,
  O_ddr_clk,
  O_ddr_clk_n,
  O_ddr_cke,
  O_ddr_odt,
  O_ddr_reset_n,
  O_ddr_dqm,
  IO_ddr_dq,
  IO_ddr_dqs,
  IO_ddr_dqs_n,
  clk_x1,
  ddr_rst
)
;

/*  Synopsys
.origName=DDR3_PHY_Interface_Top
.langParams="DRAM_TYPE nCK_PER_CLK tCK REG_CTRL DQ_WIDTH DRAM_WIDTH ECC RANK_WIDTH BANK_WIDTH ROW_WIDTH COL_WIDTH tRP tRRD tRTP tRCD tRC tRAS tFAW tWTR tCKE tREFI tRFC tDLLK BURST_MODE BURST_TYPE CL CWL AL WR_CYC SLOT_0_CONFIG SLOT_1_CONFIG RTT_NOM RTT_WR USER_REFRESH ADDR_CMD_MODE OUTPUT_DRV"
DRAM_TYPE="DDR3"
nCK_PER_CLK=2
tCK=5000
REG_CTRL="OFF"
DQ_WIDTH=16
DRAM_WIDTH=8
ECC="OFF"
RANK_WIDTH=1
BANK_WIDTH=3
ROW_WIDTH=15
COL_WIDTH=10
tRP=12500
tRRD=7500
tRTP=7500
tRCD=12500
tRC=5500
tRAS=37500
tFAW=40000
tWTR=7500
tCKE=75000
tREFI=7800000
tRFC=160000
tDLLK=512
BURST_MODE="4"
BURST_TYPE="SEQ"
CL=11
CWL=5
AL="0"
WR_CYC=6
SLOT_0_CONFIG=8'b00000001
SLOT_1_CONFIG=8'b00000000
RTT_NOM="40"
RTT_WR="OFF"
USER_REFRESH="OFF"
ADDR_CMD_MODE="1T"
OUTPUT_DRV="LOW"
 */
input clk ;
input rst_n ;
input [1:0] mc_cs_n ;
input [1:0] mc_ras_n ;
input [1:0] mc_cas_n ;
input [1:0] mc_we_n ;
input [29:0] mc_address ;
input [5:0] mc_bank ;
input [1:0] mc_odt ;
input mc_reset_n ;
input [1:0] mc_cke ;
input mc_cmd_wren ;
input mc_wrdata_en ;
input [63:0] mc_wrdata ;
input [7:0] mc_wrdata_mask ;
output phy_rd_data_valid ;
output [63:0] phy_rd_data ;
output ddr_init_complete ;
output [14:0] O_ddr_addr ;
output [2:0] O_ddr_ba ;
output O_ddr_cs_n ;
output O_ddr_ras_n ;
output O_ddr_cas_n ;
output O_ddr_we_n ;
output O_ddr_clk ;
output O_ddr_clk_n ;
output O_ddr_cke ;
output O_ddr_odt ;
output O_ddr_reset_n ;
output [1:0] O_ddr_dqm ;
inout [15:0] IO_ddr_dq /* synthesis syn_tristate = 1 */ ;
inout [1:0] IO_ddr_dqs /* synthesis syn_tristate = 1 */ ;
inout [1:0] IO_ddr_dqs_n /* synthesis syn_tristate = 1 */ ;
output clk_x1 /* synthesis syn_tristate = 1 */ ;
output ddr_rst ;
wire clk ;
wire rst_n ;
wire mc_reset_n ;
wire mc_cmd_wren ;
wire mc_wrdata_en ;
wire phy_rd_data_valid ;
wire ddr_init_complete ;
wire O_ddr_cs_n ;
wire O_ddr_ras_n ;
wire O_ddr_cas_n ;
wire O_ddr_we_n ;
wire O_ddr_clk ;
wire O_ddr_clk_n ;
wire O_ddr_cke ;
wire O_ddr_odt ;
wire O_ddr_reset_n ;
wire clk_x1 ;
wire ddr_rst ;
wire GND ;
wire VCC ;
  GSR GSR_INST (
	.GSRI(VCC)
);
// @11:90
  \~gw3_phy.DDR3_PHY_Interface_Top_  u_gw3_phy_top (
	.clk(clk),
	.rst_n(rst_n),
	.mc_cs_n(mc_cs_n[1:0]),
	.mc_ras_n(mc_ras_n[1:0]),
	.mc_cas_n(mc_cas_n[1:0]),
	.mc_we_n(mc_we_n[1:0]),
	.mc_address(mc_address[29:0]),
	.mc_bank(mc_bank[5:0]),
	.mc_odt({GND, mc_odt[0]}),
	.mc_reset_n(mc_reset_n),
	.mc_cke(mc_cke[1:0]),
	.mc_cmd_wren(mc_cmd_wren),
	.mc_wrdata_en(mc_wrdata_en),
	.mc_wrdata(mc_wrdata[63:0]),
	.mc_wrdata_mask(mc_wrdata_mask[7:0]),
	.phy_rd_data_valid(phy_rd_data_valid),
	.phy_rd_data(phy_rd_data[63:0]),
	.ddr_init_complete(ddr_init_complete),
	.O_ddr_addr(O_ddr_addr[14:0]),
	.O_ddr_ba(O_ddr_ba[2:0]),
	.O_ddr_cs_n(O_ddr_cs_n),
	.O_ddr_ras_n(O_ddr_ras_n),
	.O_ddr_cas_n(O_ddr_cas_n),
	.O_ddr_we_n(O_ddr_we_n),
	.O_ddr_clk(O_ddr_clk),
	.O_ddr_clk_n(O_ddr_clk_n),
	.O_ddr_cke(O_ddr_cke),
	.O_ddr_odt(O_ddr_odt),
	.O_ddr_reset_n(O_ddr_reset_n),
	.O_ddr_dqm(O_ddr_dqm[1:0]),
	.IO_ddr_dq(IO_ddr_dq[15:0]),
	.IO_ddr_dqs(IO_ddr_dqs[1:0]),
	.IO_ddr_dqs_n(IO_ddr_dqs_n[1:0]),
	.clk_x1(clk_x1),
	.ddr_rst(ddr_rst)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* DDR3_PHY_Interface_Top */

