# project files
add_file -verilog "D:/gowin_ip/IP_Test/DDR/DDR3_1_8/Gowin_DDR3_RefDesign/src/DDR3_Memory_Interface/DDR3_Memory_Interface.v"
add_file -verilog "D:/gowin_ip/IP_Test/DDR/DDR3_1_8/Gowin_DDR3_RefDesign/src/DDR3_test_rst.v"
add_file -verilog "D:/gowin_ip/IP_Test/DDR/DDR3_1_8/Gowin_DDR3_RefDesign/src/ddr3_syn_top.v"
add_file -verilog "D:/gowin_ip/IP_Test/DDR/DDR3_1_8/Gowin_DDR3_RefDesign/src/key_debounce.v"

# implementation: "rev_1"
impl -add rev_1 -type fpga

# device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_18
set_option -package PBGA256
set_option -speed_grade -8

set_option -top_module ddr3_syn_top
set_option -include_path {..\..\..\src\DDR3_Memory_Interface\temp\DDR3}
set_option -frequency auto
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -update_models_cp 0
set_option -rw_check_on_ram 1
set_option -run_prop_extract 1
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -pipe 1
set_option -retiming 0
set_option -write_apr_constraint 1
set_option -vlog_std sysv
set_option -compiler_compatible 0
set_option -multi_file_compilation_unit 1
set_option -looplimit 2000
set_option -fix_gated_and_generated_clocks 1

# set result format/file
project -result_file "Gowin_DDR3_RefDesign.vm"
impl -active "rev_1"


