# project files
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/DDR3_test_rst.v"
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v"
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/key_debounce.v"
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/DDR3_TOP.v"
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/GWMC.v"
add_file "F:/gwip_test/refDesign_sdc/Gowin_DDR3_Memory_Interface_RefDesign/DDR3_PHY_1vs2_2A55K/project/src/ddr3_phy_interface/ddr3_phy_interface.v"

# implementation: "rev_1"
impl -add rev_1 -type fpga

# device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_55
set_option -package PBGA484
set_option -speed_grade -8

set_option -frequency auto
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -update_models_cp 0
set_option -rw_check_on_ram 1
set_option -run_prop_extract 1
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -pipe 1
set_option -retiming 0
set_option -write_apr_constraint 1
set_option -vlog_std sysv
set_option -compiler_compatible 0
set_option -multi_file_compilation_unit 1
set_option -looplimit 2000
set_option -fix_gated_and_generated_clocks 0
set_option -top_module ddr3_syn_top
set_option -include_path {..\..\..\src\DDR3_PHY_Interface\temp\DDR3_PHY}
set_option -top_module ddr3_syn_top
set_option -include_path {..\..\..\src\ddr3_phy_interface\temp\DDR3_PHY}

# set result format/file
project -result_file "ddr3_ref_design.vm"
impl -active "rev_1"

