//Copyright (C)2014-2019 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.0.02 Beta
//Created Time: 2019-04-30 08:54:07
create_clock -name clk_x1 -period 6.667 -waveform {0 3.33} [get_nets {clk_x1}]
create_clock -name clk_x4 -period 1.667 -waveform {0 0.83} [get_nets {u_ddr3/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4}]
create_clock -name clk_x4i -period 1.667 -waveform {0 0.83} [get_nets {u_ddr3/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i}]
