//Copyright (C)2014-2020 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.5.02 Beta
//Created Time: 2020-05-21 14:13:03
create_clock -name clk_x1 -period 10 -waveform {0 5} [get_nets {clk_x1}]
create_clock -name clk_x4 -period 2.5 -waveform {0 1.25} [get_nets {u_ddr3/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4}]
create_clock -name clk_x4i -period 2.5 -waveform {0 1.25} [get_nets {u_ddr3/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i}]
