Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2AR : GW2AR_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:03s - 2020/5/21
13:36:02
(premap)Complete 6 0 0 0m:02s 0m:03s 228MB 2020/5/21
13:36:07
(fpga_mapper)Complete 9 2 0 0m:09s 0m:10s 256MB 2020/5/21
13:36:18
Multi-srs Generator Complete00m:01s2020/5/21
13:36:04

Area Summary
I/O ports (io_port) 77 Non I/O Register bits (non_io_reg) 444 (2%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 4 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 441 (2%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i228.9 MHz194.6 MHz-0.771
ao_top_0|control[0]175.0 MHz148.7 MHz-1.008

Optimizations Summary
Combined Clock Conversion 2 / 0