Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR1\data\ddr_code.v D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR1\data\DDR1_TOP.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.07 |
Part Number | GW2AR-LV18LQ176C8/I7 |
Device | GW2AR-18 |
Created Time | Mon Jul 25 17:07:02 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.936s, Elapsed time = 0h 0m 0.941s, Peak memory usage = 65.652MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 65.652MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 65.652MB Optimizing Phase 1: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 65.652MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.314s, Peak memory usage = 65.652MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 65.652MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 65.652MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 65.652MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 65.652MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.191s, Peak memory usage = 65.652MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.302s, Peak memory usage = 65.652MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 65.652MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 80.164MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 80.164MB Generate output files: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 80.164MB |
Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 80.164MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 114 |
Embedded Port | 41 |
I/O Buf | 149 |
    IBUF | 67 |
    OBUF | 64 |
    IOBUF | 18 |
Register | 912 |
    DFF | 83 |
    DFFE | 83 |
    DFFS | 21 |
    DFFSE | 8 |
    DFFR | 5 |
    DFFRE | 14 |
    DFFP | 29 |
    DFFPE | 4 |
    DFFC | 434 |
    DFFCE | 231 |
LUT | 1022 |
    LUT2 | 220 |
    LUT3 | 264 |
    LUT4 | 538 |
ALU | 82 |
    ALU | 82 |
SSRAM | 40 |
    RAM16S4 | 3 |
    RAM16SDP4 | 37 |
INV | 15 |
    INV | 15 |
IOLOGIC | 73 |
    IDDR_MEM | 16 |
    ODDR | 2 |
    ODDR_MEM | 18 |
    IODELAY | 37 |
CLOCK | 3 |
    DQS | 2 |
    DQCE | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1359(1037 LUTs, 82 ALUs, 40 SSRAMs) / 20736 | 7% |
Register | 912 / 16095 | 6% |
  --Register as Latch | 0 / 16095 | 0% |
  --Register as FF | 912 / 16095 | 6% |
BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
clk_out_d | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 255.6(MHz) | 6 | TOP |
2 | clk_out_d | 100.0(MHz) | 92.4(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -0.409 |
Data Arrival Time | 5.159 |
Data Required Time | 4.750 |
From | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0 |
To | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | clk_out_d[F] |
Latch Clk | clk_out_d[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_out_d | |||
0.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
0.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0/CLK |
0.412 | 0.232 | tC2Q | RF | 7 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0/Q |
0.649 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n2007_s2/I1 |
1.204 | 0.555 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n2007_s2/F |
1.441 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I1 |
1.996 | 0.555 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F |
2.233 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/I0 |
2.750 | 0.517 | tINS | FF | 5 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/F |
2.987 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/I2 |
3.440 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/F |
3.677 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1549_s0/I2 |
4.130 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1549_s0/F |
4.367 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/I1 |
4.922 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
5.159 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_out_d | |||
5.000 | 0.000 | tCL | FF | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
5.237 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
4.750 | -0.487 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.057 |
Setup Relationship: | 5.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:Slack | -0.409 |
Data Arrival Time | 5.159 |
Data Required Time | 4.750 |
From | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0 |
To | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | clk_out_d[F] |
Latch Clk | clk_out_d[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_out_d | |||
0.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
0.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0/CLK |
0.412 | 0.232 | tC2Q | RF | 7 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_8_s0/Q |
0.649 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n2007_s2/I1 |
1.204 | 0.555 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n2007_s2/F |
1.441 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I1 |
1.996 | 0.555 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F |
2.233 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/I0 |
2.750 | 0.517 | tINS | FF | 5 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/F |
2.987 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/I2 |
3.440 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/F |
3.677 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1549_s0/I2 |
4.130 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1549_s0/F |
4.367 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/I1 |
4.922 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
5.159 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_out_d | |||
5.000 | 0.000 | tCL | FF | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
5.237 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
4.750 | -0.487 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.057 |
Setup Relationship: | 5.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:Slack | 4.073 |
Data Arrival Time | 6.072 |
Data Required Time | 10.145 |
From | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_1_s0 |
To | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
Launch Clk | clk_out_d[R] |
Latch Clk | clk_out_d[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_out_d | |||
0.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
0.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_1_s0/CLK |
0.412 | 0.232 | tC2Q | RF | 5 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_1_s0/Q |
0.649 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/n1401_s5/I1 |
1.204 | 0.555 | tINS | FF | 8 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/n1401_s5/F |
1.441 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/I2 |
1.894 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/F |
2.131 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I1 |
2.686 | 0.555 | tINS | FF | 43 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
2.923 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_0_s3/I1 |
3.478 | 0.555 | tINS | FF | 3 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_0_s3/F |
3.715 | 0.237 | tNET | FF | 2 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_0_s/I1 |
4.285 | 0.570 | tINS | FR | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_0_s/COUT |
4.285 | 0.000 | tNET | RR | 2 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_1_s/CIN |
4.320 | 0.035 | tINS | RF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_1_s/COUT |
4.320 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_2_s/CIN |
4.355 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_2_s/COUT |
4.355 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/CIN |
4.391 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/COUT |
4.628 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/I2 |
5.081 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/F |
5.318 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/I0 |
5.835 | 0.517 | tINS | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/F |
6.072 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_out_d | |||
10.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
10.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/CLK |
10.145 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.764, 63.881%; route: 1.896, 32.181%; tC2Q: 0.232, 3.938% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:Slack | 4.427 |
Data Arrival Time | 5.718 |
Data Required Time | 10.145 |
From | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0 |
To | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_1_s0 |
Launch Clk | clk_out_d[R] |
Latch Clk | clk_out_d[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_out_d | |||
0.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
0.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0/CLK |
0.412 | 0.232 | tC2Q | RF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0/Q |
0.649 | 0.237 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n389_s/I1 |
1.219 | 0.570 | tINS | FR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n389_s/COUT |
1.219 | 0.000 | tNET | RR | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n388_s/CIN |
1.254 | 0.035 | tINS | RF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n388_s/COUT |
1.254 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n387_s/CIN |
1.289 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n387_s/COUT |
1.289 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n386_s/CIN |
1.325 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n386_s/COUT |
1.325 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n385_s/CIN |
1.360 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n385_s/COUT |
1.360 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n384_s/CIN |
1.395 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n384_s/COUT |
1.395 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n383_s/CIN |
1.865 | 0.470 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n383_s/SUM |
2.102 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s8/I1 |
2.657 | 0.555 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s8/F |
2.894 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s6/I0 |
3.411 | 0.517 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s6/F |
3.648 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s3/I2 |
4.101 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s3/F |
4.338 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s2/I2 |
4.791 | 0.453 | tINS | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s2/F |
5.028 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n414_s1/I2 |
5.481 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n414_s1/F |
5.718 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_out_d | |||
10.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
10.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_1_s0/CLK |
10.145 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.647, 65.854%; route: 1.659, 29.957%; tC2Q: 0.232, 4.189% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:Slack | 4.509 |
Data Arrival Time | 5.636 |
Data Required Time | 10.145 |
From | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0 |
To | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_2_s0 |
Launch Clk | clk_out_d[R] |
Latch Clk | clk_out_d[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_out_d | |||
0.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
0.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0/CLK |
0.412 | 0.232 | tC2Q | RF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/dll_step_d_0_s0/Q |
0.649 | 0.237 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n389_s/I1 |
1.219 | 0.570 | tINS | FR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n389_s/COUT |
1.219 | 0.000 | tNET | RR | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n388_s/CIN |
1.254 | 0.035 | tINS | RF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n388_s/COUT |
1.254 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n387_s/CIN |
1.289 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n387_s/COUT |
1.289 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n386_s/CIN |
1.325 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n386_s/COUT |
1.325 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n385_s/CIN |
1.360 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n385_s/COUT |
1.360 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n384_s/CIN |
1.395 | 0.035 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n384_s/COUT |
1.395 | 0.000 | tNET | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n383_s/CIN |
1.865 | 0.470 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n383_s/SUM |
2.102 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s8/I1 |
2.657 | 0.555 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s8/F |
2.894 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s6/I0 |
3.411 | 0.517 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s6/F |
3.648 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s3/I2 |
4.101 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s3/F |
4.338 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s2/I2 |
4.791 | 0.453 | tINS | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/n415_s2/F |
5.028 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n413_s3/I3 |
5.399 | 0.371 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/n413_s3/F |
5.636 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_out_d | |||
10.000 | 0.000 | tCL | RR | 956 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
10.180 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_2_s0/CLK |
10.145 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/updata_cnt_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.565, 65.341%; route: 1.659, 30.407%; tC2Q: 0.232, 4.252% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |