`

    #Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
    #install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-003

    # Thu May 21 10:09:20 2020

    #Implementation: rev_1

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_expression.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
    @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
    @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
    @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
    @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
    @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
    @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
    @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
    @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
    @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
    @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
    @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
    @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
    @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
    @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
    @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
    @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
    @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
    @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
    @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
    @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
    @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top_0
    Running optimization stage 1 on ao_mem_ctrl_0_1024s_34s_10s .......
    Running optimization stage 1 on ao_crc32_0 .......
    Running optimization stage 1 on ao_match_0_0s_1s_34s_1_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_top_0 .......
    Running optimization stage 2 on ao_match_0_0s_1s_34s_1_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_top_0 .......
    Extracted state machine for register module_state
    State machine has 11 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1001
       1010
       1011
    Running optimization stage 2 on ao_crc32_0 .......
    Running optimization stage 2 on ao_mem_ctrl_0_1024s_34s_10s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 110MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 10:09:22 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 10:09:22 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  ao_0_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 22MB peak: 22MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 10:09:22 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 10:09:24 2020

    ###########################################################]

`
`

    Premap Report

`
`

    # Thu May 21 10:09:24 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  ao_0_scck.rpt
    See clock summary report "F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1\ao_0_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

    Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
    original code -> new code
       0000 -> 00000000001
       0001 -> 00000000010
       0010 -> 00000000100
       0011 -> 00000001000
       0100 -> 00000010000
       0101 -> 00000100000
       0110 -> 00001000000
       0111 -> 00010000000
       1001 -> 00100000000
       1010 -> 01000000000
       1011 -> 10000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Clock Summary
    ******************

              Start                   Requested     Requested     Clock        Clock                     Clock
    Level     Clock                   Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------------------
    0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     305

    0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     110
    ==========================================================================================================

    Clock Load Summary
    ***********************

                            Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|control[0]     305       control[0](port)     data_register[54:0].C                    -                 -

    ao_top_0|clk_i          110       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    ======================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 382 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           port                   77         ENCRYPTED
    ClockId_0_1       ENCRYPTED           IO_port                305        ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 228MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Thu May 21 10:09:27 2020

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Thu May 21 10:09:28 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 129MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)

    Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

    Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 233MB peak: 233MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 234MB peak: 234MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 234MB peak: 234MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 234MB peak: 234MB)

    Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 234MB peak: 234MB)

    Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 250MB peak: 250MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:03s		    -2.87ns		 427 /       341
       2		0h:00m:03s		    -2.87ns		 422 /       341
       3		0h:00m:03s		    -2.60ns		 422 /       341
       4		0h:00m:03s		    -2.73ns		 422 /       341
       5		0h:00m:03s		    -2.46ns		 422 /       341
       6		0h:00m:03s		    -2.60ns		 422 /       341

       7		0h:00m:04s		    -2.59ns		 435 /       341
       8		0h:00m:04s		    -2.59ns		 435 /       341
       9		0h:00m:04s		    -2.46ns		 436 /       341
      10		0h:00m:04s		    -2.59ns		 437 /       341
      11		0h:00m:04s		    -2.59ns		 436 /       341
      12		0h:00m:04s		    -2.59ns		 438 /       341

      13		0h:00m:04s		    -2.46ns		 434 /       341
      14		0h:00m:04s		    -2.59ns		 435 /       341
      15		0h:00m:04s		    -2.59ns		 434 /       341
      16		0h:00m:04s		    -2.59ns		 435 /       341
      17		0h:00m:04s		    -2.59ns		 434 /       341

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 253MB peak: 253MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 254MB peak: 254MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 181MB peak: 254MB)

    Writing Analyst data base F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 255MB peak: 255MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 255MB peak: 255MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 255MB peak: 255MB)

    Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 252MB peak: 256MB)

    @W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.64ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 6.49ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu May 21 10:09:37 2020
    #

    Top view:               ao_top_0
    Requested Frequency:    154.1 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.145

                            Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i          215.5 MHz     183.2 MHz     4.639         5.458         -0.819     inferred     Autoconstr_clkgroup_0
    ao_top_0|control[0]     154.1 MHz     131.0 MHz     6.490         7.636         -1.145     inferred     Autoconstr_clkgroup_1
    =============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------
    Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i       ao_top_0|clk_i       |  4.639       -0.819  |  4.639       3.800  |  No paths    -      |  2.320       1.481
    ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|control[0]  |  6.490       -1.145  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top_0|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                                                 Arrival
    Instance                             Reference          Type     Pin     Net                                  Time        Slack
                                         Clock
    --------------------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[0]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[0]                  0.243       -0.819
    genblk1\.u_ao_match_0.match_sep      ao_top_0|clk_i     DFFC     Q       match                                0.243       -0.798
    triger_level_cnt[1]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[1]                  0.243       -0.711
    capture_window_sel[2]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[2]                0.243       -0.507
    capture_window_sel[0]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[0]                0.243       -0.486
    capture_window_sel[1]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[1]                0.243       -0.395
    u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC     Q       capture_length[0]                    0.243       -0.201
    u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC     Q       capture_length[1]                    0.243       -0.093
    internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.243       0.132
    triger_level_cnt[2]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[2]                  0.243       0.239
    ================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                        Required
    Instance                              Reference          Type      Pin     Net                        Time         Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]      4.579        -0.819
    triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]      4.579        -0.711
    triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]      4.579        -0.620
    u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      un1_start_reg              4.579        -0.507
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      g0                         4.579        -0.365
    triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]      4.579        0.199
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7           4.579        0.208
    u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6       4.579        0.288
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]     4.579        0.288
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]     4.579        0.288
    =========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.639
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.579

        - Propagation time:                      5.397
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.819

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[0] / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK

    Instance / Net                      Pin      Pin               Arrival     No. of
    Name                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------
    triger_level_cnt[0]        DFFC     Q        Out     0.243     0.243 r     -
    triger_level_cnt[0]        Net      -        -       0.535     -           5
    g0_1_1_0                   LUT3     I1       In      -         0.778 r     -
    g0_1_1_0                   LUT3     F        Out     0.570     1.348 r     -
    g0_1_1_0                   Net      -        -       0.401     -           1
    g0_1                       LUT4     I0       In      -         1.749 r     -
    g0_1                       LUT4     F        Out     0.549     2.298 r     -
    un1_match_final            Net      -        -       0.535     -           3
    g0_0                       LUT3     I2       In      -         2.833 r     -
    g0_0                       LUT3     F        Out     0.462     3.295 r     -
    triger_level_cnt13         Net      -        -       0.535     -           4
    un1_triger_level_cnt12     LUT4     I2       In      -         3.830 r     -
    un1_triger_level_cnt12     LUT4     F        Out     0.462     4.292 r     -
    un1_triger_level_cnt12     Net      -        -       0.535     -           3
    triger_level_cnt_4[2]      LUT3     I1       In      -         4.827 r     -
    triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.397 r     -
    triger_level_cnt_4[2]      Net      -        -       0.000     -           1
    triger_level_cnt[2]        DFFC     D        In      -         5.397 r     -
    =====================================================================================
    Total path delay (propagation time + setup) of 5.458 is 2.917(53.4%) logic and 2.541(46.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.639
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.579

        - Propagation time:                      5.376
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.798

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243 r     -
    match                               Net      -        -       0.535     -           1
    g0_1_1_0                            LUT3     I0       In      -         0.778 r     -
    g0_1_1_0                            LUT3     F        Out     0.549     1.327 r     -
    g0_1_1_0                            Net      -        -       0.401     -           1
    g0_1                                LUT4     I0       In      -         1.728 r     -
    g0_1                                LUT4     F        Out     0.549     2.277 r     -
    un1_match_final                     Net      -        -       0.535     -           3
    g0_0                                LUT3     I2       In      -         2.812 r     -
    g0_0                                LUT3     F        Out     0.462     3.274 r     -
    triger_level_cnt13                  Net      -        -       0.535     -           4
    un1_triger_level_cnt12              LUT4     I2       In      -         3.809 r     -
    un1_triger_level_cnt12              LUT4     F        Out     0.462     4.271 r     -
    un1_triger_level_cnt12              Net      -        -       0.535     -           3
    triger_level_cnt_4[2]               LUT3     I1       In      -         4.806 r     -
    triger_level_cnt_4[2]               LUT3     F        Out     0.570     5.376 r     -
    triger_level_cnt_4[2]               Net      -        -       0.000     -           1
    triger_level_cnt[2]                 DFFC     D        In      -         5.376 r     -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.437 is 2.896(53.3%) logic and 2.541(46.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.639
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.579

        - Propagation time:                      5.376
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.798

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[0] / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    triger_level_cnt[0]            DFFC     Q        Out     0.243     0.243 r     -
    triger_level_cnt[0]            Net      -        -       0.535     -           5
    g0_1_1_0                       LUT3     I1       In      -         0.778 r     -
    g0_1_1_0                       LUT3     F        Out     0.570     1.348 r     -
    g0_1_1_0                       Net      -        -       0.401     -           1
    g0_1                           LUT4     I0       In      -         1.749 r     -
    g0_1                           LUT4     F        Out     0.549     2.298 r     -
    un1_match_final                Net      -        -       0.535     -           3
    g0_0                           LUT3     I2       In      -         2.833 r     -
    g0_0                           LUT3     F        Out     0.462     3.295 r     -
    triger_level_cnt13             Net      -        -       0.535     -           4
    un1_triger_level_cnt_ac0_1     LUT3     I0       In      -         3.830 r     -
    un1_triger_level_cnt_ac0_1     LUT3     F        Out     0.549     4.379 r     -
    un1_triger_level_cnt_c2        Net      -        -       0.535     -           2
    triger_level_cnt_4[2]          LUT3     I2       In      -         4.914 r     -
    triger_level_cnt_4[2]          LUT3     F        Out     0.462     5.376 r     -
    triger_level_cnt_4[2]          Net      -        -       0.000     -           1
    triger_level_cnt[2]            DFFC     D        In      -         5.376 r     -
    =========================================================================================
    Total path delay (propagation time + setup) of 5.437 is 2.896(53.3%) logic and 2.541(46.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.639
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.579

        - Propagation time:                      5.355
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.777

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243 r     -
    match                               Net      -        -       0.535     -           1
    g0_1_1_0                            LUT3     I0       In      -         0.778 r     -
    g0_1_1_0                            LUT3     F        Out     0.549     1.327 r     -
    g0_1_1_0                            Net      -        -       0.401     -           1
    g0_1                                LUT4     I0       In      -         1.728 r     -
    g0_1                                LUT4     F        Out     0.549     2.277 r     -
    un1_match_final                     Net      -        -       0.535     -           3
    g0_0                                LUT3     I2       In      -         2.812 r     -
    g0_0                                LUT3     F        Out     0.462     3.274 r     -
    triger_level_cnt13                  Net      -        -       0.535     -           4
    un1_triger_level_cnt_ac0_1          LUT3     I0       In      -         3.809 r     -
    un1_triger_level_cnt_ac0_1          LUT3     F        Out     0.549     4.358 r     -
    un1_triger_level_cnt_c2             Net      -        -       0.535     -           2
    triger_level_cnt_4[2]               LUT3     I2       In      -         4.893 r     -
    triger_level_cnt_4[2]               LUT3     F        Out     0.462     5.355 r     -
    triger_level_cnt_4[2]               Net      -        -       0.000     -           1
    triger_level_cnt[2]                 DFFC     D        In      -         5.355 r     -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.416 is 2.875(53.1%) logic and 2.541(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.639
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.579

        - Propagation time:                      5.289
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.711

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[1] / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.320 period=4.639) on pin CLK

    Instance / Net                      Pin      Pin               Arrival     No. of
    Name                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------
    triger_level_cnt[1]        DFFC     Q        Out     0.243     0.243 r     -
    triger_level_cnt[1]        Net      -        -       0.535     -           4
    g0_1_1_0                   LUT3     I2       In      -         0.778 r     -
    g0_1_1_0                   LUT3     F        Out     0.462     1.240 r     -
    g0_1_1_0                   Net      -        -       0.401     -           1
    g0_1                       LUT4     I0       In      -         1.641 r     -
    g0_1                       LUT4     F        Out     0.549     2.190 r     -
    un1_match_final            Net      -        -       0.535     -           3
    g0_0                       LUT3     I2       In      -         2.725 r     -
    g0_0                       LUT3     F        Out     0.462     3.187 r     -
    triger_level_cnt13         Net      -        -       0.535     -           4
    un1_triger_level_cnt12     LUT4     I2       In      -         3.722 r     -
    un1_triger_level_cnt12     LUT4     F        Out     0.462     4.184 r     -
    un1_triger_level_cnt12     Net      -        -       0.535     -           3
    triger_level_cnt_4[2]      LUT3     I1       In      -         4.719 r     -
    triger_level_cnt_4[2]      LUT3     F        Out     0.570     5.289 r     -
    triger_level_cnt_4[2]      Net      -        -       0.000     -           1
    triger_level_cnt[2]        DFFC     D        In      -         5.289 r     -
    =====================================================================================
    Total path delay (propagation time + setup) of 5.350 is 2.809(52.5%) logic and 2.541(47.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top_0|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                   Arrival
    Instance                         Reference               Type      Pin     Net                              Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -1.145
    internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -1.124
    internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -1.124
    internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -1.103
    internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -1.037
    internal_register_select[11]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[11]     0.243       -0.946
    data_register[51]                ao_top_0|control[0]     DFFCE     Q       data_register[51]                0.243       -0.319
    data_register[50]                ao_top_0|control[0]     DFFCE     Q       data_register[50]                0.243       -0.298
    word_count[0]                    ao_top_0|control[0]     DFFCE     Q       word_count[0]                    0.243       -0.293
    word_count[1]                    ao_top_0|control[0]     DFFCE     Q       word_count[1]                    0.243       -0.258
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                               Starting                                                               Required
    Instance                   Reference               Type      Pin     Net                          Time         Slack
                               Clock
    ---------------------------------------------------------------------------------------------------------------------
    data_out_shift_reg[1]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]      6.429        -1.145
    data_out_shift_reg[2]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]      6.429        -1.145
    data_out_shift_reg[0]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]      6.429        -1.058
    data_out_shift_reg[5]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[5]      6.429        -0.950
    data_out_shift_reg[6]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[6]      6.429        -0.950
    data_out_shift_reg[7]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[7]      6.429        -0.950
    data_out_shift_reg[8]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[8]      6.429        -0.950
    data_out_shift_reg[9]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[9]      6.429        -0.950
    data_out_shift_reg[10]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[10]     6.429        -0.950
    data_out_shift_reg[11]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[11]     6.429        -0.950
    =====================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.490
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.429

        - Propagation time:                      7.575
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.145

        Number of logic level(s):                7
        Starting point:                          internal_register_select[9] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_register_select[9]             DFFCE     Q        Out     0.243     0.243 r     -
    internal_register_select[9]             Net       -        -       0.535     -           1
    data_from_internal_reg100_14_i_o2_4     LUT4      I1       In      -         0.778 r     -
    data_from_internal_reg100_14_i_o2_4     LUT4      F        Out     0.570     1.348 r     -
    data_from_internal_reg100_14_i_o2_4     Net       -        -       0.401     -           1
    data_from_internal_reg100_14_i_o2       LUT4      I1       In      -         1.749 r     -
    data_from_internal_reg100_14_i_o2       LUT4      F        Out     0.570     2.319 r     -
    data_from_internal_reg100_14_i_o2       Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2_0         LUT3      I0       In      -         2.854 r     -
    data_from_internal_reg81_0_a2_0         LUT3      F        Out     0.549     3.403 r     -
    N_77                                    Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2           LUT4      I0       In      -         3.938 r     -
    data_from_internal_reg81_0_a2           LUT4      F        Out     0.549     4.487 r     -
    data_from_internal_reg81                Net       -        -       0.596     -           13
    data_from_internal_reg_0_iv_1[1]        LUT3      I0       In      -         5.083 r     -
    data_from_internal_reg_0_iv_1[1]        LUT3      F        Out     0.549     5.632 r     -
    data_from_internal_reg_0_iv_1[1]        Net       -        -       0.401     -           1
    data_from_internal_reg_0_iv_3[1]        LUT4      I1       In      -         6.033 r     -
    data_from_internal_reg_0_iv_3[1]        LUT4      F        Out     0.570     6.603 r     -
    data_from_internal_reg_0_iv_3[1]        Net       -        -       0.401     -           1
    data_out_shift_reg_4[1]                 LUT4      I1       In      -         7.005 r     -
    data_out_shift_reg_4[1]                 LUT4      F        Out     0.570     7.575 r     -
    data_out_shift_reg_4[1]                 Net       -        -       0.000     -           1
    data_out_shift_reg[1]                   DFFCE     D        In      -         7.575 r     -
    ===================================================================================================
    Total path delay (propagation time + setup) of 7.636 is 4.231(55.4%) logic and 3.405(44.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.490
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.429

        - Propagation time:                      7.575
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.145

        Number of logic level(s):                7
        Starting point:                          internal_register_select[9] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_register_select[9]             DFFCE     Q        Out     0.243     0.243 r     -
    internal_register_select[9]             Net       -        -       0.535     -           1
    data_from_internal_reg100_14_i_o2_4     LUT4      I1       In      -         0.778 r     -
    data_from_internal_reg100_14_i_o2_4     LUT4      F        Out     0.570     1.348 r     -
    data_from_internal_reg100_14_i_o2_4     Net       -        -       0.401     -           1
    data_from_internal_reg100_14_i_o2       LUT4      I1       In      -         1.749 r     -
    data_from_internal_reg100_14_i_o2       LUT4      F        Out     0.570     2.319 r     -
    data_from_internal_reg100_14_i_o2       Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2_0         LUT3      I0       In      -         2.854 r     -
    data_from_internal_reg81_0_a2_0         LUT3      F        Out     0.549     3.403 r     -
    N_77                                    Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2           LUT4      I0       In      -         3.938 r     -
    data_from_internal_reg81_0_a2           LUT4      F        Out     0.549     4.487 r     -
    data_from_internal_reg81                Net       -        -       0.596     -           13
    data_from_internal_reg_0_iv_1[2]        LUT3      I0       In      -         5.083 r     -
    data_from_internal_reg_0_iv_1[2]        LUT3      F        Out     0.549     5.632 r     -
    data_from_internal_reg_0_iv_1[2]        Net       -        -       0.401     -           1
    data_from_internal_reg_0_iv_3[2]        LUT4      I1       In      -         6.033 r     -
    data_from_internal_reg_0_iv_3[2]        LUT4      F        Out     0.570     6.603 r     -
    data_from_internal_reg_0_iv_3[2]        Net       -        -       0.401     -           1
    data_out_shift_reg_4[2]                 LUT4      I1       In      -         7.005 r     -
    data_out_shift_reg_4[2]                 LUT4      F        Out     0.570     7.575 r     -
    data_out_shift_reg_4[2]                 Net       -        -       0.000     -           1
    data_out_shift_reg[2]                   DFFCE     D        In      -         7.575 r     -
    ===================================================================================================
    Total path delay (propagation time + setup) of 7.636 is 4.231(55.4%) logic and 3.405(44.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.490
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.429

        - Propagation time:                      7.554
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.124

        Number of logic level(s):                7
        Starting point:                          internal_register_select[7] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_register_select[7]             DFFCE     Q        Out     0.243     0.243 r     -
    internal_register_select[7]             Net       -        -       0.535     -           1
    data_from_internal_reg100_14_i_o2_4     LUT4      I0       In      -         0.778 r     -
    data_from_internal_reg100_14_i_o2_4     LUT4      F        Out     0.549     1.327 r     -
    data_from_internal_reg100_14_i_o2_4     Net       -        -       0.401     -           1
    data_from_internal_reg100_14_i_o2       LUT4      I1       In      -         1.728 r     -
    data_from_internal_reg100_14_i_o2       LUT4      F        Out     0.570     2.298 r     -
    data_from_internal_reg100_14_i_o2       Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2_0         LUT3      I0       In      -         2.833 r     -
    data_from_internal_reg81_0_a2_0         LUT3      F        Out     0.549     3.382 r     -
    N_77                                    Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2           LUT4      I0       In      -         3.917 r     -
    data_from_internal_reg81_0_a2           LUT4      F        Out     0.549     4.466 r     -
    data_from_internal_reg81                Net       -        -       0.596     -           13
    data_from_internal_reg_0_iv_1[1]        LUT3      I0       In      -         5.062 r     -
    data_from_internal_reg_0_iv_1[1]        LUT3      F        Out     0.549     5.611 r     -
    data_from_internal_reg_0_iv_1[1]        Net       -        -       0.401     -           1
    data_from_internal_reg_0_iv_3[1]        LUT4      I1       In      -         6.012 r     -
    data_from_internal_reg_0_iv_3[1]        LUT4      F        Out     0.570     6.582 r     -
    data_from_internal_reg_0_iv_3[1]        Net       -        -       0.401     -           1
    data_out_shift_reg_4[1]                 LUT4      I1       In      -         6.984 r     -
    data_out_shift_reg_4[1]                 LUT4      F        Out     0.570     7.554 r     -
    data_out_shift_reg_4[1]                 Net       -        -       0.000     -           1
    data_out_shift_reg[1]                   DFFCE     D        In      -         7.554 r     -
    ===================================================================================================
    Total path delay (propagation time + setup) of 7.615 is 4.210(55.3%) logic and 3.405(44.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.490
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.429

        - Propagation time:                      7.554
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.124

        Number of logic level(s):                7
        Starting point:                          internal_register_select[13] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_register_select[13]            DFFCE     Q        Out     0.243     0.243 r     -
    internal_register_select[13]            Net       -        -       0.535     -           1
    data_from_internal_reg100_14_i_o2_3     LUT2      I1       In      -         0.778 r     -
    data_from_internal_reg100_14_i_o2_3     LUT2      F        Out     0.570     1.348 r     -
    data_from_internal_reg100_14_i_o2_3     Net       -        -       0.401     -           1
    data_from_internal_reg100_14_i_o2       LUT4      I0       In      -         1.749 r     -
    data_from_internal_reg100_14_i_o2       LUT4      F        Out     0.549     2.298 r     -
    data_from_internal_reg100_14_i_o2       Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2_0         LUT3      I0       In      -         2.833 r     -
    data_from_internal_reg81_0_a2_0         LUT3      F        Out     0.549     3.382 r     -
    N_77                                    Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2           LUT4      I0       In      -         3.917 r     -
    data_from_internal_reg81_0_a2           LUT4      F        Out     0.549     4.466 r     -
    data_from_internal_reg81                Net       -        -       0.596     -           13
    data_from_internal_reg_0_iv_1[1]        LUT3      I0       In      -         5.062 r     -
    data_from_internal_reg_0_iv_1[1]        LUT3      F        Out     0.549     5.611 r     -
    data_from_internal_reg_0_iv_1[1]        Net       -        -       0.401     -           1
    data_from_internal_reg_0_iv_3[1]        LUT4      I1       In      -         6.012 r     -
    data_from_internal_reg_0_iv_3[1]        LUT4      F        Out     0.570     6.582 r     -
    data_from_internal_reg_0_iv_3[1]        Net       -        -       0.401     -           1
    data_out_shift_reg_4[1]                 LUT4      I1       In      -         6.984 r     -
    data_out_shift_reg_4[1]                 LUT4      F        Out     0.570     7.554 r     -
    data_out_shift_reg_4[1]                 Net       -        -       0.000     -           1
    data_out_shift_reg[1]                   DFFCE     D        In      -         7.554 r     -
    ===================================================================================================
    Total path delay (propagation time + setup) of 7.615 is 4.210(55.3%) logic and 3.405(44.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.490
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.429

        - Propagation time:                      7.554
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.124

        Number of logic level(s):                7
        Starting point:                          internal_register_select[7] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=3.245 period=6.490) on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_register_select[7]             DFFCE     Q        Out     0.243     0.243 r     -
    internal_register_select[7]             Net       -        -       0.535     -           1
    data_from_internal_reg100_14_i_o2_4     LUT4      I0       In      -         0.778 r     -
    data_from_internal_reg100_14_i_o2_4     LUT4      F        Out     0.549     1.327 r     -
    data_from_internal_reg100_14_i_o2_4     Net       -        -       0.401     -           1
    data_from_internal_reg100_14_i_o2       LUT4      I1       In      -         1.728 r     -
    data_from_internal_reg100_14_i_o2       LUT4      F        Out     0.570     2.298 r     -
    data_from_internal_reg100_14_i_o2       Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2_0         LUT3      I0       In      -         2.833 r     -
    data_from_internal_reg81_0_a2_0         LUT3      F        Out     0.549     3.382 r     -
    N_77                                    Net       -        -       0.535     -           6
    data_from_internal_reg81_0_a2           LUT4      I0       In      -         3.917 r     -
    data_from_internal_reg81_0_a2           LUT4      F        Out     0.549     4.466 r     -
    data_from_internal_reg81                Net       -        -       0.596     -           13
    data_from_internal_reg_0_iv_1[2]        LUT3      I0       In      -         5.062 r     -
    data_from_internal_reg_0_iv_1[2]        LUT3      F        Out     0.549     5.611 r     -
    data_from_internal_reg_0_iv_1[2]        Net       -        -       0.401     -           1
    data_from_internal_reg_0_iv_3[2]        LUT4      I1       In      -         6.012 r     -
    data_from_internal_reg_0_iv_3[2]        LUT4      F        Out     0.570     6.582 r     -
    data_from_internal_reg_0_iv_3[2]        Net       -        -       0.401     -           1
    data_out_shift_reg_4[2]                 LUT4      I1       In      -         6.984 r     -
    data_out_shift_reg_4[2]                 LUT4      F        Out     0.570     7.554 r     -
    data_out_shift_reg_4[2]                 Net       -        -       0.000     -           1
    data_out_shift_reg[2]                   DFFCE     D        In      -         7.554 r     -
    ===================================================================================================
    Total path delay (propagation time + setup) of 7.615 is 4.210(55.3%) logic and 3.405(44.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 253MB peak: 256MB)

    Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 253MB peak: 256MB)

    ---------------------------------------
    Resource Usage Report for ao_top_0

    Mapping to part: gw2ar_18lqfp176-8
    Cell usage:
    ALU             70 uses
    DFF             33 uses
    DFFC            38 uses
    DFFCE           233 uses
    DFFNP           2 uses
    DFFP            3 uses
    DFFPE           32 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       6 uses
    MUX2_LUT6       2 uses
    SDPX9           2 uses
    LUT2            47 uses
    LUT3            93 uses
    LUT4            246 uses

    I/O ports: 45
    I/O primitives: 45
    IBUF           43 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   341 of 15552 (2%)

    RAM/ROM usage summary
    Block Rams : 2 of 46 (4%)

    Total load per clock:
       ao_top_0|clk_i: 1
       ao_top_0|control[0]: 267

    @S |Mapping Summary:
    Total Luts in terms of LUT4: LUT4 + LUT5 * 2 + LUT6 * 4 + LUT7 * 8 + LUT8 * 16 + MUX2 * 1 + MUX4 * 2 + MUX8 * 3 + MUX16 * 4 + MUX32 * 5
    Total  LUTs: 386 (1%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 79MB peak: 256MB)

    Process took 0h:00m:09s realtime, 0h:00m:08s cputime
    # Thu May 21 10:09:37 2020

    ###########################################################]

`