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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-003

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

Modified Files: 13
FID:  path (prevtimestamp, timestamp)
0        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v (N/A, 2020-05-18 14:21:44)
1        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v (N/A, 2020-05-18 14:21:44)
2        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v (N/A, 2020-05-18 14:21:44)
3        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v (N/A, 2020-05-18 14:21:44)
4        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v (N/A, 2020-05-18 14:21:44)
5        E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v (N/A, 2020-05-12 03:01:26)
6        E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v (N/A, 2020-05-12 03:02:52)
7        E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v (N/A, 2020-05-12 03:02:52)
8        E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh (N/A, 2020-05-12 03:02:52)
9        E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v (N/A, 2020-05-12 03:02:52)
10       F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_expression.v (N/A, 2020-05-21 10:08:50)
11       F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_parameter.v (N/A, 2020-05-21 10:08:50)
12       F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\gw_ao_top_define.v (N/A, 2020-05-21 10:08:50)

*******************************************************************
Modules that may have changed as a result of file changes: 4
MID:  lib.cell.view
0        work.ao_crc32_0.verilog may have changed because the following files changed:
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v (N/A, 2020-05-18 14:21:44) <-- (module definition)
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v (N/A, 2020-05-18 14:21:44) <-- (may instantiate this module)
1        work.ao_match_0.verilog may have changed because the following files changed:
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v (N/A, 2020-05-18 14:21:44) <-- (module definition)
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v (N/A, 2020-05-18 14:21:44) <-- (may instantiate this module)
2        work.ao_mem_ctrl_0.verilog may have changed because the following files changed:
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v (N/A, 2020-05-18 14:21:44) <-- (module definition)
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v (N/A, 2020-05-18 14:21:44) <-- (may instantiate this module)
3        work.ao_top_0.verilog may have changed because the following files changed:
                        E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v (N/A, 2020-05-18 14:21:44) <-- (module definition)

*******************************************************************
Unmodified files: 0
FID:  path (timestamp)

*******************************************************************
Unchanged modules: 0
MID:  lib.cell.view
