// ===========Oooo==========================================Oooo========
// =  Copyright (C) 2014-2017 Jinan Gowin Semiconductor Technology Co.,Ltd.
// =                     All rights reserved.
// =====================================================================
//
//  __      __      __
//  \ \    /  \    / /   [File name   ] DDR_TOP.v
//   \ \  / /\ \  / /    [Description ] TOP Verilog file for the DDR TOP design
//    \ \/ /  \ \/ /     [Timestamp   ] Tue Aug 17 15:30:00 2017
//     \  /    \  /      [version     ] 1.0
//      \/      \/
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author |Mod. Date |Changes Made:
// V1.0 | Horace |17/08/17  |Initial version
// ===========Oooo==========================================Oooo========

  `timescale 1ps/1ps
  `include "ddr_name.v"
  module DDR_TOP (
    // user interface
    clk,
    rst_n,
    cmd_ready,
    cmd,
    cmd_en,
    addr,
    wr_data_rdy,
    wr_data,
    wr_data_en,
    wr_data_end,
    wr_data_mask,
    rd_data,
    rd_data_valid,
    rd_data_end,
    sr_req,
    ref_req,
    sr_act,
    ref_ack,
    init_calib_complete,
    clk_out,
    ddr_rst,
    ecc_err,
    burst,
    // mem interface
    O_ddr_addr,
    O_ddr_ba,
    O_ddr_cs_n,
    O_ddr_ras_n,
    O_ddr_cas_n,
    O_ddr_we_n,
    O_ddr_clk,
    O_ddr_clk_n,
    O_ddr_cke,
    O_ddr_dqm,
    O_ddr_odt,
    IO_ddr_dq,
    IO_ddr_dqs,
    IO_ddr_dqs_n
    );

  `include "gwmc_param.v"
  `include "gwmc_local_param.v"

    // user interface
    input                          wr_data_en;
    input [APP_MASK_WIDTH-1:0]     wr_data_mask;
    input                          wr_data_end;
    input [APP_DATA_WIDTH-1:0]     wr_data;
    input                          cmd_en;
    input [2:0]                    cmd;
    input [ADDR_WIDTH-1:0]         addr;
    output                         sr_act;
    output                         ref_ack;
    output                         wr_data_rdy;
    output                         init_calib_complete;
    
    output                         cmd_ready;
    output                         rd_data_valid; 
    output                         rd_data_end;
    output [APP_DATA_WIDTH-1:0]    rd_data;
    output [APP_DATA_WIDTH/32-1:0] ecc_err;
    input                          sr_req;
    input                          ref_req;
    input                          burst;

    input                          clk;
    output                         clk_out;
    output                         ddr_rst;
    input                          rst_n;
    output [ROW_WIDTH-1:0]         O_ddr_addr;
    output [BANK_WIDTH-1:0]        O_ddr_ba;
    output                         O_ddr_cs_n;
    output                         O_ddr_ras_n;
    output                         O_ddr_cas_n;
    output                         O_ddr_we_n;
    output                         O_ddr_clk;
    output                         O_ddr_clk_n;
    output                         O_ddr_cke;
    output [DM_WIDTH-1:0]          O_ddr_dqm;
    output                         O_ddr_odt;
    inout  [DQ_WIDTH-1:0]          IO_ddr_dq;
    inout  [DQS_WIDTH-1:0]         IO_ddr_dqs;
    inout  [DQS_WIDTH-1:0]         IO_ddr_dqs_n;


    wire                           wr_data_en;
    wire  [APP_MASK_WIDTH-1:0]     wr_data_mask;
    wire                           wr_data_end; 
    wire [APP_DATA_WIDTH-1:0]      wr_data;
    wire                           cmd_en;
    wire [2:0]                     cmd;
    wire [ADDR_WIDTH-1:0]          addr;
    wire                           sr_req;
    wire                           ref_req;
    wire                           burst;
    wire                           clk;
    wire                           rst;
    wire                           rst_n;
    wire                           clk_out;
    wire                           ddr_rst;
    wire                           sr_act;
    wire                           ref_ack;
    wire                           wr_data_rdy;
    wire                           init_calib_complete;
    wire                           cmd_ready;
    wire                           rd_data_valid; 
    wire                           rd_data_end;
    wire [APP_DATA_WIDTH-1:0]      rd_data;
    wire [APP_DATA_WIDTH/32-1:0]   ecc_err;

    wire [nCK_PER_CLK-1:0]               mc_ras_n;
    wire [nCK_PER_CLK-1:0]               mc_cas_n;
    wire [nCK_PER_CLK-1:0]               mc_we_n;
    wire [nCK_PER_CLK*ROW_WIDTH-1:0]     mc_address;
    wire [nCK_PER_CLK*BANK_WIDTH-1:0]    mc_bank;
    wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n;
    wire [1:0]                           mc_odt;
    wire [nCK_PER_CLK-1:0]               mc_cke;
    wire                                 mc_reset_n;
    wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]    mc_wrdata;
    wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]  mc_wrdata_mask;
    wire                                 mc_wrdata_en;
    
    wire                                 mc_cmd_wren;
    // From PHY to MC
    wire                                 phy_mc_ctl_full;
    wire                                 phy_mc_cmd_full;
    wire                                 phy_mc_data_full;
    wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]    phy_rd_data;
    wire                                 phy_rddata_valid;

  
//////////////////////////////////////////////////////////////////
`ifdef SIM
\~gwmc_top.gwmc_top_ u_gwmc_top (
`else
`getname(gwmc_top,`module_name_ddr) u_gwmc_top(
`endif
    .app_wdf_wren            (wr_data_en),
    .app_wdf_mask            (wr_data_mask),
    .app_wdf_end             (wr_data_end),
    .app_wdf_data            (wr_data),
    //.app_raw_not_ecc         (2'b0),
    .app_en                  (cmd_en),
    .app_cmd                 (cmd),
    .app_addr                (addr),
    //.app_correct_en          (1'b0),
    .app_sre_act             (sr_act),
    .app_ref_ack             (ref_ack),
    .app_wdf_rdy             (wr_data_rdy),
    .init_complete           (init_calib_complete),
    .app_rdy                 (cmd_ready),
    .app_rd_data_valid       (rd_data_valid),
    .app_rd_data_end         (rd_data_end),
    .app_rd_data             (rd_data),
    .app_ecc_multiple_err    (ecc_err),
    .app_sre_req             (sr_req),
    .app_ref_req             (ref_req),
    .clk                     (clk_out),
    .rst                     (ddr_rst),
    .mc_cas_n                (mc_cas_n),
    .mc_ras_n                (mc_ras_n),
    .mc_we_n                 (mc_we_n),
    .mc_address              (mc_address),
    .mc_bank                 (mc_bank),
    .mc_cs_n                 (mc_cs_n),
    .mc_odt                  (mc_odt),
    .mc_cke                  (mc_cke),
    .mc_reset_n              (mc_reset_n),
    .mc_wrdata               (mc_wrdata),
    .mc_wrdata_mask          (mc_wrdata_mask),
    .mc_wrdata_en            (mc_wrdata_en),
    .mc_cmd_wren             (mc_cmd_wren),
    .phy_rd_data             (phy_rd_data),
    .phy_rddata_valid        (phy_rddata_valid),
    .init_done               (complete_done ),
    .app_burst               (burst)
    );


`module_name_ddr   u_ddr_phy_top
(
  .clk            (clk),                   
  .rst_n          (rst_n),                 
  .mc_cs_n           (mc_cs_n),               
  .mc_ras_n          (mc_ras_n),              
  .mc_cas_n          (mc_cas_n),              
  .mc_we_n           (mc_we_n),               
  .mc_address        (mc_address),            
  .mc_bank           (mc_bank),               
  .mc_reset_n        (mc_reset_n),            
  .mc_cke            (mc_cke),                
  .mc_cmd_wren       (mc_cmd_wren),           
  .mc_wrdata_en      (mc_wrdata_en),          
  .mc_wrdata         (mc_wrdata),             
  .mc_wrdata_mask    (mc_wrdata_mask),        
  .ddr_init_complete (complete_done),  
  .phy_rd_data_valid (phy_rddata_valid),     
  .phy_rd_data       (phy_rd_data),           
  .O_ddr_addr          (O_ddr_addr),         
  .O_ddr_ba          (O_ddr_ba),         
  .O_ddr_cs_n            (O_ddr_cs_n),           
  .O_ddr_ras_n           (O_ddr_ras_n),          
  .O_ddr_cas_n           (O_ddr_cas_n),          
  .O_ddr_we_n            (O_ddr_we_n),           
  .O_ddr_clk            (O_ddr_clk),           
  .O_ddr_clk_n          (O_ddr_clk_n),         
  .O_ddr_cke           (O_ddr_cke),          
  .O_ddr_dqm            (O_ddr_dqm),
  .IO_ddr_dq            (IO_ddr_dq),           
  .IO_ddr_dqs           (IO_ddr_dqs),          
  .clk_x1            (clk_out),
  .ddr_rst          (ddr_rst)
);

endmodule

