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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-003

Implementation : rev_1

# Written on Thu May 21 13:35:41 2020

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                Requested     Requested     Clock        Clock                     Clock
Level     Clock                Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------
0 -       gw_con_top|tck_i     297.4 MHz     3.362         inferred     Autoconstr_clkgroup_0     14   
=======================================================================================================


Clock Load Summary
******************

                     Clock     Source          Clock Pin                        Non-clock Pin     Non-clock Pin      
Clock                Load      Pin             Seq Example                      Seq Example       Comb Example       
---------------------------------------------------------------------------------------------------------------------
gw_con_top|tck_i     14        tck_i(port)     shift_dr_capture_dr_dly[0].C     -                 un1_tck_i.I[0](inv)
=====================================================================================================================
