`

    #Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
    #install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-003

    # Thu May 21 13:35:59 2020

    #Implementation: rev_1

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_expression.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
    @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
    @I::"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
    @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
    @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
    @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
    @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
    @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
    @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
    @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
    @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
    @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
    @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
    @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
    @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
    @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
    @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
    @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
    @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
    @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
    @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
    @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
    @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top_0
    Running optimization stage 1 on ao_mem_ctrl_0_1024s_66s_10s .......
    Running optimization stage 1 on ao_crc32_0 .......
    Running optimization stage 1 on ao_match_0_0s_1s_66s_1_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_top_0 .......
    Running optimization stage 2 on ao_match_0_0s_1s_66s_1_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_top_0 .......
    Extracted state machine for register module_state
    State machine has 11 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1001
       1010
       1011
    Running optimization stage 2 on ao_crc32_0 .......
    Running optimization stage 2 on ao_mem_ctrl_0_1024s_66s_10s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 112MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 13:36:01 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 13:36:02 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  ao_0_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 22MB peak: 22MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 13:36:02 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu May 21 13:36:04 2020

    ###########################################################]

`
`

    Premap Report

`
`

    # Thu May 21 13:36:04 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  ao_0_scck.rpt
    See clock summary report "F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\rev_1\ao_0_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)

    Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
    original code -> new code
       0000 -> 00000000001
       0001 -> 00000000010
       0010 -> 00000000100
       0011 -> 00000001000
       0100 -> 00000010000
       0101 -> 00000100000
       0110 -> 00001000000
       0111 -> 00010000000
       1001 -> 00100000000
       1010 -> 01000000000
       1011 -> 10000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Clock Summary
    ******************

              Start                   Requested     Requested     Clock        Clock                     Clock
    Level     Clock                   Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------------------
    0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     402

    0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     174
    ==========================================================================================================

    Clock Load Summary
    ***********************

                            Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|control[0]     402       control[0](port)     data_register[86:0].C                    -                 -

    ao_top_0|clk_i          174       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    ======================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 511 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           port                   109        ENCRYPTED
    ClockId_0_1       ENCRYPTED           IO_port                402        ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 227MB)

    Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 228MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Thu May 21 13:36:07 2020

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Thu May 21 13:36:08 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-003

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 129MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)

    Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB)

    Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 234MB peak: 234MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 235MB peak: 235MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 235MB peak: 235MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 235MB peak: 235MB)

    Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 235MB peak: 235MB)

    Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 251MB peak: 251MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:04s		    -2.49ns		 464 /       438
       2		0h:00m:04s		    -2.49ns		 468 /       438
       3		0h:00m:04s		    -2.36ns		 467 /       438
    Timing driven replication report
    Added 6 Registers via timing driven replication
    Added 3 LUTs via timing driven replication

       4		0h:00m:04s		    -2.15ns		 487 /       444
       5		0h:00m:05s		    -2.36ns		 489 /       444
       6		0h:00m:05s		    -2.36ns		 488 /       444

       7		0h:00m:05s		    -2.15ns		 494 /       444
       8		0h:00m:05s		    -2.36ns		 494 /       444
       9		0h:00m:05s		    -2.36ns		 494 /       444
      10		0h:00m:05s		    -2.23ns		 494 /       444
      11		0h:00m:05s		    -2.20ns		 495 /       444

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 253MB peak: 253MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 253MB peak: 253MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:05s; Memory used current: 181MB peak: 254MB)

    Writing Analyst data base F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 255MB peak: 255MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 255MB peak: 255MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 255MB peak: 256MB)

    Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 252MB peak: 256MB)

    @W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.37ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 5.71ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu May 21 13:36:18 2020
    #

    Top view:               ao_top_0
    Requested Frequency:    175.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.008

                            Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i          228.9 MHz     194.6 MHz     4.369         5.140         -0.771     inferred     Autoconstr_clkgroup_0
    ao_top_0|control[0]     175.0 MHz     148.7 MHz     5.715         6.723         -1.008     inferred     Autoconstr_clkgroup_1
    =============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------
    Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i       ao_top_0|clk_i       |  4.369       -0.771  |  4.369       3.530  |  No paths    -      |  2.184       1.345
    ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|control[0]  |  5.715       -1.008  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top_0|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                                  Arrival
    Instance                              Reference          Type      Pin     Net                                  Time        Slack
                                          Clock
    ----------------------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[0]                  0.243       -0.771
    capture_window_sel[1]                 ao_top_0|clk_i     DFFC      Q       capture_window_sel[1]                0.243       -0.757
    internal_reg_force_triger_syn[1]      ao_top_0|clk_i     DFFC      Q       internal_reg_force_triger_syn[1]     0.243       -0.750
    capture_window_sel[0]                 ao_top_0|clk_i     DFFC      Q       capture_window_sel[0]                0.243       -0.736
    triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[3]                  0.243       -0.727
    triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]                  0.243       -0.706
    triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[1]                  0.243       -0.663
    genblk1\.u_ao_match_0.match_sep       ao_top_0|clk_i     DFFC      Q       match                                0.243       -0.205
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     Q       capture_mem_addr[1]                  0.243       0.018
    capture_window_sel[2]                 ao_top_0|clk_i     DFFC      Q       capture_window_sel[2]                0.243       0.036
    ==================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                        Required
    Instance                              Reference          Type      Pin     Net                        Time         Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      g0_3                       4.308        -0.771
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      g0_0_0                     4.308        -0.771
    triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]      4.308        -0.334
    triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]      4.308        -0.226
    triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]      4.308        -0.135
    trigger_seq_start                     ao_top_0|clk_i     DFFCE     CE      un2_start_reg              4.308        -0.093
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7           4.308        -0.020
    u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6       4.308        0.018
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]     4.308        0.018
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]     4.308        0.018
    =========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.369
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.079
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.771

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[0] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    triger_level_cnt[0]              DFFC      Q        Out     0.243     0.243 r     -
    triger_level_cnt[0]              Net       -        -       0.535     -           6
    un1_match_final_3_x              LUT3      I1       In      -         0.778 r     -
    un1_match_final_3_x              LUT3      F        Out     0.570     1.348 r     -
    un1_match_final_3_x              Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa_1      LUT4      I0       In      -         1.749 r     -
    triger_level_cnt_0_sqmuxa_1      LUT4      F        Out     0.549     2.298 r     -
    triger_level_cnt_0_sqmuxa_1      Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa        LUT4      I2       In      -         2.699 r     -
    triger_level_cnt_0_sqmuxa        LUT4      F        Out     0.462     3.161 r     -
    triger_level_cnt_0_sqmuxa        Net       -        -       0.596     -           15
    u_ao_mem_ctrl.g0_0_1             LUT4      I3       In      -         3.757 r     -
    u_ao_mem_ctrl.g0_0_1             LUT4      F        Out     0.371     4.128 f     -
    g0_0_1                           Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0_3               LUT4      I0       In      -         4.530 f     -
    u_ao_mem_ctrl.g0_3               LUT4      F        Out     0.549     5.079 r     -
    g0_3                             Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.079 r     -
    ============================================================================================
    Total path delay (propagation time + setup) of 5.140 is 2.805(54.6%) logic and 2.335(45.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.369
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.079
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.771

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[0] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK

    Instance / Net                              Pin      Pin               Arrival     No. of
    Name                              Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------
    triger_level_cnt[0]               DFFC      Q        Out     0.243     0.243 r     -
    triger_level_cnt[0]               Net       -        -       0.535     -           6
    un1_match_final_3_x               LUT3      I1       In      -         0.778 r     -
    un1_match_final_3_x               LUT3      F        Out     0.570     1.348 r     -
    un1_match_final_3_x               Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa_1       LUT4      I0       In      -         1.749 r     -
    triger_level_cnt_0_sqmuxa_1       LUT4      F        Out     0.549     2.298 r     -
    triger_level_cnt_0_sqmuxa_1       Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa         LUT4      I2       In      -         2.699 r     -
    triger_level_cnt_0_sqmuxa         LUT4      F        Out     0.462     3.161 r     -
    triger_level_cnt_0_sqmuxa         Net       -        -       0.596     -           15
    u_ao_mem_ctrl.g0_2                LUT4      I3       In      -         3.757 r     -
    u_ao_mem_ctrl.g0_2                LUT4      F        Out     0.371     4.128 f     -
    g0_0                              Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0_0                LUT4      I0       In      -         4.530 f     -
    u_ao_mem_ctrl.g0_0                LUT4      F        Out     0.549     5.079 r     -
    g0_0_0                            Net       -        -       0.000     -           1
    u_ao_mem_ctrl.mem_addr_inc_en     DFFCE     CE       In      -         5.079 r     -
    =============================================================================================
    Total path delay (propagation time + setup) of 5.140 is 2.805(54.6%) logic and 2.335(45.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.369
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.064
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.757

        Number of logic level(s):                5
        Starting point:                          capture_window_sel[1] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    capture_window_sel[1]            DFFC      Q        Out     0.243     0.243 r     -
    capture_window_sel[1]            Net       -        -       0.535     -           5
    un6_start_reg_c2                 LUT4      I1       In      -         0.778 r     -
    un6_start_reg_c2                 LUT4      F        Out     0.570     1.348 r     -
    un6_start_reg_c2                 Net       -        -       0.401     -           1
    un6_start_reg_ac0_5_0            LUT4      I3       In      -         1.749 r     -
    un6_start_reg_ac0_5_0            LUT4      F        Out     0.371     2.120 f     -
    un6_start_reg_ac0_5_0            Net       -        -       0.535     -           3
    start_reg                        LUT3      I2       In      -         2.655 f     -
    start_reg                        LUT3      F        Out     0.462     3.117 r     -
    start_reg                        Net       -        -       0.535     -           3
    u_ao_mem_ctrl.g0_0_1             LUT4      I2       In      -         3.652 r     -
    u_ao_mem_ctrl.g0_0_1             LUT4      F        Out     0.462     4.114 r     -
    g0_0_1                           Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0_3               LUT4      I0       In      -         4.515 r     -
    u_ao_mem_ctrl.g0_3               LUT4      F        Out     0.549     5.064 r     -
    g0_3                             Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.064 r     -
    ============================================================================================
    Total path delay (propagation time + setup) of 5.125 is 2.718(53.0%) logic and 2.407(47.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.369
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.058
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.750

        Number of logic level(s):                5
        Starting point:                          internal_reg_force_triger_syn[1] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    internal_reg_force_triger_syn[1]     DFFC      Q        Out     0.243     0.243 r     -
    internal_reg_force_triger_syn[1]     Net       -        -       0.535     -           2
    un1_match_final_3_x                  LUT3      I0       In      -         0.778 r     -
    un1_match_final_3_x                  LUT3      F        Out     0.549     1.327 r     -
    un1_match_final_3_x                  Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa_1          LUT4      I0       In      -         1.728 r     -
    triger_level_cnt_0_sqmuxa_1          LUT4      F        Out     0.549     2.277 r     -
    triger_level_cnt_0_sqmuxa_1          Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa            LUT4      I2       In      -         2.678 r     -
    triger_level_cnt_0_sqmuxa            LUT4      F        Out     0.462     3.140 r     -
    triger_level_cnt_0_sqmuxa            Net       -        -       0.596     -           15
    u_ao_mem_ctrl.g0_0_1                 LUT4      I3       In      -         3.736 r     -
    u_ao_mem_ctrl.g0_0_1                 LUT4      F        Out     0.371     4.107 f     -
    g0_0_1                               Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0_3                   LUT4      I0       In      -         4.509 f     -
    u_ao_mem_ctrl.g0_3                   LUT4      F        Out     0.549     5.058 r     -
    g0_3                                 Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr         DFFCE     CE       In      -         5.058 r     -
    ================================================================================================
    Total path delay (propagation time + setup) of 5.119 is 2.784(54.4%) logic and 2.335(45.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.369
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.058
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.750

        Number of logic level(s):                5
        Starting point:                          internal_reg_force_triger_syn[1] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] (rise=0.000 fall=2.184 period=4.369) on pin CLK

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    internal_reg_force_triger_syn[1]     DFFC      Q        Out     0.243     0.243 r     -
    internal_reg_force_triger_syn[1]     Net       -        -       0.535     -           2
    un1_match_final_3_x                  LUT3      I0       In      -         0.778 r     -
    un1_match_final_3_x                  LUT3      F        Out     0.549     1.327 r     -
    un1_match_final_3_x                  Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa_1          LUT4      I0       In      -         1.728 r     -
    triger_level_cnt_0_sqmuxa_1          LUT4      F        Out     0.549     2.277 r     -
    triger_level_cnt_0_sqmuxa_1          Net       -        -       0.401     -           1
    triger_level_cnt_0_sqmuxa            LUT4      I2       In      -         2.678 r     -
    triger_level_cnt_0_sqmuxa            LUT4      F        Out     0.462     3.140 r     -
    triger_level_cnt_0_sqmuxa            Net       -        -       0.596     -           15
    u_ao_mem_ctrl.g0_2                   LUT4      I3       In      -         3.736 r     -
    u_ao_mem_ctrl.g0_2                   LUT4      F        Out     0.371     4.107 f     -
    g0_0                                 Net       -        -       0.401     -           1
    u_ao_mem_ctrl.g0_0                   LUT4      I0       In      -         4.509 f     -
    u_ao_mem_ctrl.g0_0                   LUT4      F        Out     0.549     5.058 r     -
    g0_0_0                               Net       -        -       0.000     -           1
    u_ao_mem_ctrl.mem_addr_inc_en        DFFCE     CE       In      -         5.058 r     -
    ================================================================================================
    Total path delay (propagation time + setup) of 5.119 is 2.784(54.4%) logic and 2.335(45.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top_0|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                   Arrival
    Instance                         Reference               Type      Pin     Net                              Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    bit_count[2]                     ao_top_0|control[0]     DFFCE     Q       bit_count[2]                     0.243       -1.008
    bit_count[1]                     ao_top_0|control[0]     DFFCE     Q       bit_count[1]                     0.243       -0.988
    bit_count[5]                     ao_top_0|control[0]     DFFCE     Q       bit_count[5]                     0.243       -0.900
    bit_count[6]                     ao_top_0|control[0]     DFFCE     Q       bit_count[6]                     0.243       -0.809
    internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -0.624
    internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -0.603
    internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.515
    internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -0.515
    internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -0.494
    module_state[7]                  ao_top_0|control[0]     DFFC      Q       module_state[7]                  0.243       -0.473
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                              Starting                                                              Required
    Instance                  Reference               Type      Pin     Net                         Time         Slack
                              Clock
    -------------------------------------------------------------------------------------------------------------------
    data_out_shift_reg[0]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]     5.654        -1.008
    data_out_shift_reg[1]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]     5.654        -1.008
    data_out_shift_reg[2]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]     5.654        -1.008
    data_out_shift_reg[3]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[3]     5.654        -1.008
    data_out_shift_reg[4]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[4]     5.654        -1.008
    data_out_shift_reg[5]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[5]     5.654        -1.008
    data_out_shift_reg[6]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[6]     5.654        -1.008
    data_out_shift_reg[7]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[7]     5.654        -1.008
    data_out_shift_reg[8]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[8]     5.654        -1.008
    data_out_shift_reg[9]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[9]     5.654        -1.008
    ===================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.715
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.654

        - Propagation time:                      6.662
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.008

        Number of logic level(s):                6
        Starting point:                          bit_count[2] / Q
        Ending point:                            data_out_shift_reg[0] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    bit_count[2]                  DFFCE     Q        Out     0.243     0.243 r     -
    bit_count[2]                  Net       -        -       0.535     -           4
    G_17_sx                       LUT4      I1       In      -         0.778 r     -
    G_17_sx                       LUT4      F        Out     0.570     1.348 r     -
    G_17_sx                       Net       -        -       0.401     -           1
    G_17                          LUT4      I0       In      -         1.749 r     -
    G_17                          LUT4      F        Out     0.549     2.298 r     -
    addr_ct_en_0_1_1_1_0          Net       -        -       0.596     -           12
    g0_0                          LUT4      I0       In      -         2.894 r     -
    g0_0                          LUT4      F        Out     0.549     3.443 r     -
    out_reg_ld_en_1_0_0           Net       -        -       0.535     -           2
    g0                            LUT4      I3       In      -         3.978 r     -
    g0                            LUT4      F        Out     0.371     4.349 f     -
    out_reg_ld_en                 Net       -        -       0.901     -           65
    data_out_shift_reg_4_0[0]     LUT3      I2       In      -         5.250 f     -
    data_out_shift_reg_4_0[0]     LUT3      F        Out     0.462     5.712 r     -
    N_453                         Net       -        -       0.401     -           1
    data_out_shift_reg_4[0]       LUT4      I0       In      -         6.113 r     -
    data_out_shift_reg_4[0]       LUT4      F        Out     0.549     6.662 r     -
    data_out_shift_reg_4[0]       Net       -        -       0.000     -           1
    data_out_shift_reg[0]         DFFCE     D        In      -         6.662 r     -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.723 is 3.354(49.9%) logic and 3.369(50.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.715
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.654

        - Propagation time:                      6.662
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.008

        Number of logic level(s):                6
        Starting point:                          bit_count[2] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    bit_count[2]                  DFFCE     Q        Out     0.243     0.243 r     -
    bit_count[2]                  Net       -        -       0.535     -           4
    G_17_sx                       LUT4      I1       In      -         0.778 r     -
    G_17_sx                       LUT4      F        Out     0.570     1.348 r     -
    G_17_sx                       Net       -        -       0.401     -           1
    G_17                          LUT4      I0       In      -         1.749 r     -
    G_17                          LUT4      F        Out     0.549     2.298 r     -
    addr_ct_en_0_1_1_1_0          Net       -        -       0.596     -           12
    g0_0                          LUT4      I0       In      -         2.894 r     -
    g0_0                          LUT4      F        Out     0.549     3.443 r     -
    out_reg_ld_en_1_0_0           Net       -        -       0.535     -           2
    g0                            LUT4      I3       In      -         3.978 r     -
    g0                            LUT4      F        Out     0.371     4.349 f     -
    out_reg_ld_en                 Net       -        -       0.901     -           65
    data_out_shift_reg_4_0[2]     LUT3      I2       In      -         5.250 f     -
    data_out_shift_reg_4_0[2]     LUT3      F        Out     0.462     5.712 r     -
    N_455                         Net       -        -       0.401     -           1
    data_out_shift_reg_4[2]       LUT4      I0       In      -         6.113 r     -
    data_out_shift_reg_4[2]       LUT4      F        Out     0.549     6.662 r     -
    data_out_shift_reg_4[2]       Net       -        -       0.000     -           1
    data_out_shift_reg[2]         DFFCE     D        In      -         6.662 r     -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.723 is 3.354(49.9%) logic and 3.369(50.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.715
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.654

        - Propagation time:                      6.662
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.008

        Number of logic level(s):                6
        Starting point:                          bit_count[2] / Q
        Ending point:                            data_out_shift_reg[14] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK

    Instance / Net                           Pin      Pin               Arrival     No. of
    Name                           Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    bit_count[2]                   DFFCE     Q        Out     0.243     0.243 r     -
    bit_count[2]                   Net       -        -       0.535     -           4
    G_17_sx                        LUT4      I1       In      -         0.778 r     -
    G_17_sx                        LUT4      F        Out     0.570     1.348 r     -
    G_17_sx                        Net       -        -       0.401     -           1
    G_17                           LUT4      I0       In      -         1.749 r     -
    G_17                           LUT4      F        Out     0.549     2.298 r     -
    addr_ct_en_0_1_1_1_0           Net       -        -       0.596     -           12
    g0_0                           LUT4      I0       In      -         2.894 r     -
    g0_0                           LUT4      F        Out     0.549     3.443 r     -
    out_reg_ld_en_1_0_0            Net       -        -       0.535     -           2
    g0                             LUT4      I3       In      -         3.978 r     -
    g0                             LUT4      F        Out     0.371     4.349 f     -
    out_reg_ld_en                  Net       -        -       0.901     -           65
    data_out_shift_reg_4_0[14]     LUT3      I2       In      -         5.250 f     -
    data_out_shift_reg_4_0[14]     LUT3      F        Out     0.462     5.712 r     -
    N_467                          Net       -        -       0.401     -           1
    data_out_shift_reg_4[14]       LUT4      I0       In      -         6.113 r     -
    data_out_shift_reg_4[14]       LUT4      F        Out     0.549     6.662 r     -
    data_out_shift_reg_4[14]       Net       -        -       0.000     -           1
    data_out_shift_reg[14]         DFFCE     D        In      -         6.662 r     -
    ==========================================================================================
    Total path delay (propagation time + setup) of 6.723 is 3.354(49.9%) logic and 3.369(50.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.715
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.654

        - Propagation time:                      6.662
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.008

        Number of logic level(s):                6
        Starting point:                          bit_count[2] / Q
        Ending point:                            data_out_shift_reg[11] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK

    Instance / Net                           Pin      Pin               Arrival     No. of
    Name                           Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    bit_count[2]                   DFFCE     Q        Out     0.243     0.243 r     -
    bit_count[2]                   Net       -        -       0.535     -           4
    G_17_sx                        LUT4      I1       In      -         0.778 r     -
    G_17_sx                        LUT4      F        Out     0.570     1.348 r     -
    G_17_sx                        Net       -        -       0.401     -           1
    G_17                           LUT4      I0       In      -         1.749 r     -
    G_17                           LUT4      F        Out     0.549     2.298 r     -
    addr_ct_en_0_1_1_1_0           Net       -        -       0.596     -           12
    g0_0                           LUT4      I0       In      -         2.894 r     -
    g0_0                           LUT4      F        Out     0.549     3.443 r     -
    out_reg_ld_en_1_0_0            Net       -        -       0.535     -           2
    g0                             LUT4      I3       In      -         3.978 r     -
    g0                             LUT4      F        Out     0.371     4.349 f     -
    out_reg_ld_en                  Net       -        -       0.901     -           65
    data_out_shift_reg_4_0[11]     LUT3      I2       In      -         5.250 f     -
    data_out_shift_reg_4_0[11]     LUT3      F        Out     0.462     5.712 r     -
    N_464                          Net       -        -       0.401     -           1
    data_out_shift_reg_4[11]       LUT4      I0       In      -         6.113 r     -
    data_out_shift_reg_4[11]       LUT4      F        Out     0.549     6.662 r     -
    data_out_shift_reg_4[11]       Net       -        -       0.000     -           1
    data_out_shift_reg[11]         DFFCE     D        In      -         6.662 r     -
    ==========================================================================================
    Total path delay (propagation time + setup) of 6.723 is 3.354(49.9%) logic and 3.369(50.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.715
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.654

        - Propagation time:                      6.662
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.008

        Number of logic level(s):                6
        Starting point:                          bit_count[2] / Q
        Ending point:                            data_out_shift_reg[9] / D
        The start point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] (rise=0.000 fall=2.857 period=5.715) on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    bit_count[2]                  DFFCE     Q        Out     0.243     0.243 r     -
    bit_count[2]                  Net       -        -       0.535     -           4
    G_17_sx                       LUT4      I1       In      -         0.778 r     -
    G_17_sx                       LUT4      F        Out     0.570     1.348 r     -
    G_17_sx                       Net       -        -       0.401     -           1
    G_17                          LUT4      I0       In      -         1.749 r     -
    G_17                          LUT4      F        Out     0.549     2.298 r     -
    addr_ct_en_0_1_1_1_0          Net       -        -       0.596     -           12
    g0_0                          LUT4      I0       In      -         2.894 r     -
    g0_0                          LUT4      F        Out     0.549     3.443 r     -
    out_reg_ld_en_1_0_0           Net       -        -       0.535     -           2
    g0                            LUT4      I3       In      -         3.978 r     -
    g0                            LUT4      F        Out     0.371     4.349 f     -
    out_reg_ld_en                 Net       -        -       0.901     -           65
    data_out_shift_reg_4_0[9]     LUT3      I2       In      -         5.250 f     -
    data_out_shift_reg_4_0[9]     LUT3      F        Out     0.462     5.712 r     -
    N_462                         Net       -        -       0.401     -           1
    data_out_shift_reg_4[9]       LUT4      I0       In      -         6.113 r     -
    data_out_shift_reg_4[9]       LUT4      F        Out     0.549     6.662 r     -
    data_out_shift_reg_4[9]       Net       -        -       0.000     -           1
    data_out_shift_reg[9]         DFFCE     D        In      -         6.662 r     -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.723 is 3.354(49.9%) logic and 3.369(50.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 252MB peak: 256MB)

    Finished timing report (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 252MB peak: 256MB)

    ---------------------------------------
    Resource Usage Report for ao_top_0

    Mapping to part: gw2ar_18lqfp176-8
    Cell usage:
    ALU             71 uses
    DFF             65 uses
    DFFC            46 uses
    DFFCE           293 uses
    DFFNP           2 uses
    DFFP            6 uses
    DFFPE           32 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       2 uses
    SDPX9           4 uses
    LUT2            65 uses
    LUT3            87 uses
    LUT4            289 uses

    I/O ports: 77
    I/O primitives: 77
    IBUF           75 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   444 of 15552 (2%)

    RAM/ROM usage summary
    Block Rams : 4 of 46 (8%)

    Total load per clock:
       ao_top_0|clk_i: 1
       ao_top_0|control[0]: 340

    @S |Mapping Summary:
    Total Luts in terms of LUT4: LUT4 + LUT5 * 2 + LUT6 * 4 + LUT7 * 8 + LUT8 * 16 + MUX2 * 1 + MUX4 * 2 + MUX8 * 3 + MUX16 * 4 + MUX32 * 5
    Total  LUTs: 441 (2%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 79MB peak: 256MB)

    Process took 0h:00m:10s realtime, 0h:00m:09s cputime
    # Thu May 21 13:36:18 2020

    ###########################################################]

`