`timescale 1ps/1ps
module ddr1_syn_top
(
     clk,
     rst_n,
     display,
     start,
     O_ddr_addr,
     O_ddr_ba,
     O_ddr_cs_n,
     O_ddr_ras_n,
     O_ddr_cas_n,
     O_ddr_we_n,
     O_ddr_clk,
     O_ddr_clk_n,
     O_ddr_cke,
     O_ddr_dqm,
     O_ddr_odt,
     IO_ddr_dq,
     IO_ddr_dqs,
     IO_ddr_dqs_n,
     init_calib_complete,
     seg_en,
     show_data,
     sw,
     sr_in,
     pll_out,
     test_out,
     read_in 
);

  //`include "gwmc_param.v"
  //`include "gwmc_local_param.v"

    input									clk;
    input									rst_n;
    input									display;
    input									start;
    output	[12-1:0]	                    O_ddr_addr;     //ROW_WIDTH=12
    output	[2-1:0]	                        O_ddr_ba;   //BANK_WIDTH=2
    output									O_ddr_cs_n;
    output									O_ddr_ras_n;
    output									O_ddr_cas_n;
    output									O_ddr_we_n;
    output									O_ddr_clk;
    output									O_ddr_clk_n;
    output									O_ddr_cke;
    output	[2-1:0]		                    O_ddr_dqm;      //DM_WIDTH=2
    output									O_ddr_odt;
    inout	[16-1:0]		                IO_ddr_dq;  //DQ_WIDTH=16
    inout	[2-1:0]		                    IO_ddr_dqs;     //DQS_WIDTH=2
    inout	[2-1:0]		                    IO_ddr_dqs_n;   //DQS_WIDTH=2
    output									init_calib_complete;
    output	[3:0]							seg_en;
    output	[3:0]							show_data;

    input									sw;
    input									sr_in;
    input									read_in;
    output									pll_out;
    output	[5:0]							test_out;


    wire									clk_x1;
    wire									app_sre_act;
    wire									app_wdf_wren;
    wire									app_wdf_end; 
    wire	[8-1:0]	                        app_wdf_mask;                           //APP_MASK_WIDTH=8
    wire	[64-1:0]	                    app_wdf_data;                           //APP_DATA_WIDTH=64
    reg	    [2*2-1:0]		                app_raw_not_ecc;                        //nCK_PER_CLK=2
    wire	[24-1:0]			            app_addr;                               //ADDR_WIDTH=24
    wire	[2:0]							app_cmd;
    wire									app_en;
    reg										pp_correct_en;
    wire									app_sre_req;
    wire									app_ref_req;
    wire									app_burst;
    wire									app_ref_ack;
    wire									app_wdf_rdy;
    wire									complete_done;
    wire									app_rdy;
    wire									app_rd_data_valid; 
    wire									app_rd_data_end;
    wire	[64-1:0]	                    app_rd_data;                            //APP_DATA_WIDTH=64
    wire	[2*2-1:0]		                app_ecc_multiple_err;                   //nCK_PER_CLK=2

    wire	[2-1:0]				            mc_ras_n/* synthesis syn_keep=1 */;     //nCK_PER_CLK=2
    wire	[2-1:0]				            mc_cas_n/* synthesis syn_keep=1 */;     //nCK_PER_CLK=2
    wire	[2-1:0]				            mc_we_n/* synthesis syn_keep=1 */;      //nCK_PER_CLK=2
    wire	[2*12-1:0]		                mc_address;                             //nCK_PER_CLK=2, ROW_WIDTH=12
    wire	[2*2-1:0]	                    mc_bank;                                //nCK_PER_CLK=2, BANK_WIDTH=2
    wire	[1*1*2-1:0] 	                mc_cs_n;                                //CS_WIDTH=1, nCS_PER_RANK=1, nCK_PER_CLK=2
    wire	[1:0]							mc_odt;
    wire	[2-1:0]				            mc_cke;                                 //nCK_PER_CLK=2
    wire									mc_reset_n;
    wire	[2*2*16-1:0]	                mc_wrdata;                              //nCK_PER_CLK=2, DQ_WIDTH=16
    wire	[2*2*16/8-1:0]                  mc_wrdata_mask;                         //nCK_PER_CLK=2,DQ_WIDTH=16,nDq_pre_Dqs=8
    wire									mc_wrdata_en;
    wire									mc_cmd_wren;
    wire	[1:0]							mc_cas_slot;
    // From PHY to MC
    wire									phy_mc_ctl_full;
    wire									phy_mc_cmd_full;
    wire									phy_mc_data_full;
    wire	[2*2*16-1:0]	                phy_rd_data;                            //nCK_PER_CLK=2, DQ_WIDTH=16
    wire									phy_rd_data_valid;

    wire [7:0]                               seg;

    assign test_out[0] = app_sre_act;  //white
    assign test_out[1] = app_ref_ack; //purple
//    assign test_out[2] = u_DDR_TOP.u_ddr_phy_top.u_ddr_init.phy_cas_n[0:0]; //red
//    assign test_out[3] = u_DDR_TOP.u_ddr_phy_top.u_ddr_init.phy_we_n[0:0];  //blue

`define SIM     //used for simulation

`ifdef SIM
    assign display_1        =   display;
    assign start_1          =   start;
    assign sw_1             =   sw;
    assign rst_n_1          =   rst_n;
    assign sr_in_1          =   sr_in;
`else
    key_debounce u2(
        .clk(clk),
        .rst_n(rst_n_1),
        .key_1(display_1),
        .key1_n(display)
        );   

    key_debounce u3(
        .clk(clk),
        .rst_n(rst_n),
        .key_1(start_1),
        .key1_n(start)
        );   

    key_debounce u4(
        .clk(clk),
        .rst_n(rst_n_1),
        .key_1(sw_1),
        .key1_n(sw)
        );  

    key_debounce u5(
        .clk(clk),
        .rst_n(1'b1),
        .key_1(rst_n_1),
        .key1_n(rst_n)
        ); 


    key_debounce u6(
        .clk(clk),
        .rst_n(rst_n),
        .key_1(sr_in_1),
        .key1_n(sr_in)
        ); 

    key_debounce u7(
        .clk(clk),
        .rst_n(rst_n),
        .key_1(read_in_1),
        .key1_n(read_in)
        ); 
`endif


GSR GSR(.GSRI(1'b1));


DDR1_test  #(
     .ADDR_WIDTH				(24	),  //ADDR_WIDTH=24
     .APP_DATA_WIDTH			(64),   //APP_DATA_WIDTH=64
     .APP_MASK_WIDTH			(8),   //APP_MASK_WIDTH=8
     .USER_REFRESH				("OFF")
    )u_rd(
    .clk						(clk_x1			),
    .rst						(ddr_rst		),
    .app_rdy					(app_rdy		),
    .app_en						(app_en			),
    .app_cmd					(app_cmd		),
    .app_addr					(app_addr		),
    .app_wdf_data				(app_wdf_data	),
    .app_wdf_wren				(app_wdf_wren	),
    .app_wdf_end				(app_wdf_end	),
    .app_wdf_mask				(app_wdf_mask	),
    .app_burst					(app_burst		),
    .app_rd_data_valid			(app_rd_data_valid),
    .app_rd_data				(app_rd_data	),
    .sr_req						(app_sre_req	),
    .ref_req					(app_ref_req	),
    .sr_in						(1'b0			),
    .read_in					(read_in_1		),
    .start						(start_1		),
    .display					(~display_1		),
    .seg						(seg			),
    .seg_en						(seg_en			),
    .show_data					(show_data		),
    .wr_data_rdy				(wr_data_rdy	),
    .init_calib_complete		(init_calib_complete),
    .sw							(~sw_1			)
    );


DDR_Memory_Interface_Top	u_DDR_TOP(
    .wr_data_en					(app_wdf_wren	),
    .wr_data_mask				(app_wdf_mask	),
    .wr_data_end				(app_wdf_end	),
    .wr_data					(app_wdf_data	),
    .cmd_en						(app_en			),
    .cmd						(app_cmd		),
    .addr						(app_addr		),
    .sr_ack						(app_sre_act	),
    .ref_ack					(app_ref_ack	),
    .wr_data_rdy				(wr_data_rdy	),
    .init_calib_complete		(init_calib_complete),
    .rd_data_valid				(app_rd_data_valid),
    .rd_data_end				(app_rd_data_end),
    .rd_data					(app_rd_data	),
  //  .ecc_err					(),
    .cmd_ready					(app_rdy		),
    .sr_req						(app_sre_req	),
    .ref_req					(app_ref_req	),
    .burst						(app_burst		),
    .clk						(clk			),
    .clk_out					(clk_x1			),
    .ddr_rst					(ddr_rst		),
    .rst_n						(rst_n_1		),
    .O_ddr_addr					(O_ddr_addr		),			//output
    .O_ddr_ba					(O_ddr_ba		),			//output
    .O_ddr_cs_n					(O_ddr_cs_n		),			//output
    .O_ddr_ras_n				(O_ddr_ras_n	),			//output
    .O_ddr_cas_n				(O_ddr_cas_n	),			//output
    .O_ddr_we_n					(O_ddr_we_n		),			//output
    .O_ddr_clk					(O_ddr_clk		),			//output
    .O_ddr_clk_n				(O_ddr_clk_n	),			//output
    .O_ddr_cke					(O_ddr_cke		),			//output
    .O_ddr_dqm					(O_ddr_dqm		),			//output
    .IO_ddr_dq					(IO_ddr_dq		),			//inout
    .IO_ddr_dqs					({IO_ddr_dqs[1],IO_ddr_dqs[0]})					//inout
    );

endmodule

