
`timescale 1ps /1ps
`define SIM
module tb();

  //`include "ddr1_parameters.vh"
  `include "gwmc_param.v"
  `include "gwmc_local_param.v"


   reg clk,rst,rst_n,display,start,sr_in,read_in;
   wire                  ddr_cs;
   wire                  ddr_ras;
   wire                  ddr_cas;
   wire                  ddr_we;
   wire                  ddr_ck;
   wire                  ddr_ck_n;
   wire                  ddr_cke;
   wire                  ddr_reset_n;
   wire [DM_WIDTH-1:0]   ddr_dm;
   wire [DQ_WIDTH-1:0]   ddr_dq;
   wire [DQS_WIDTH-1:0]  ddr_dqs;
   wire [DQS_WIDTH-1:0]  ddr_dqs_n;
   wire [ROW_WIDTH-1:0]  ddr_addr;
   wire [BANK_WIDTH-1:0] ddr_bank;

   wire [3:0]           seg_en;
   wire [3:0]           show_data;
   wire                 pll_out;
   wire [5:0]           test_out;

GSR GSR(.GSRI(1'b1));

ddr1_syn_top u_top(
  .clk(clk),
  .rst_n(rst_n),
  .start(start),
  .display(display),
  .sr_in(sr_in),
  .sw(1'b0),
  .read_in(read_in),
  .init_calib_complete(init_calib_complete),
  .O_ddr_addr(ddr_addr),
  .O_ddr_ba(ddr_bank),
  .O_ddr_cs_n(ddr_cs),
  .O_ddr_ras_n(ddr_ras),
  .O_ddr_cas_n(ddr_cas),
  .O_ddr_we_n(ddr_we),
  .O_ddr_clk(ddr_ck),
  .O_ddr_clk_n(ddr_ck_n),
  .O_ddr_cke(ddr_cke),
  .O_ddr_dqm(ddr_dm),
  .O_ddr_odt(ddr_odt),
  .IO_ddr_dq(ddr_dq),
  .IO_ddr_dqs(ddr_dqs),
  .IO_ddr_dqs_n(ddr_dqs_n),
  .seg_en(seg_en),
  .show_data(show_data),
  .pll_out(pll_out),
  .test_out(test_out)
);
 
localparam DQ_BITS = 8;   //4;//8;
localparam DQS_BITS = 1;     //2;//1;

localparam nDRAM = DQ_WIDTH / DQ_BITS; 
generate 
  genvar o;
    if(DRAM_TYPE == "DDR2")
      for(o = 0; o < nDRAM; o = o + 1'b1)
      begin:ddr2_model
        ddr2_model ddr_model(
          .ck               (ddr_ck),
          .ck_n             (ddr_ck_n),
          .cke              (ddr_cke),
          .cs_n             (ddr_cs),
          .ras_n            (ddr_ras),
          .cas_n            (ddr_cas),
          .we_n             (ddr_we),
          .dm_rdqs          (ddr_dm[((o+1)*DQS_BITS-1)-:DQS_BITS]),
          .ba               (ddr_bank),
          .addr             (ddr_addr),
          .dq               (ddr_dq[((o+1)*DQ_BITS-1)-:DQ_BITS]),
          .dqs              (ddr_dqs[((o+1)*DQS_BITS-1)-:DQS_BITS]),
          .dqs_n            (ddr_dqs_n[((o+1)*DQS_BITS-1)-:DQS_BITS]),
          .odt              (ddr_odt)
        );
      end
    else if(DRAM_TYPE == "DDR1")
      for(o = 0; o < nDRAM; o = o + 1'b1)
      begin:ddr1_model
        ddr1 ddr_model(
          .Clk              (ddr_ck),
          .Clk_n            (ddr_ck_n),
          .Cke              (ddr_cke),
          .Cs_n             (ddr_cs),
          .Ras_n            (ddr_ras),
          .Cas_n            (ddr_cas),
          .We_n             (ddr_we),
          .Dm               (ddr_dm[((o+1)*DQS_BITS-1)-:DQS_BITS]),
          .Ba               (ddr_bank),
          .Addr             (ddr_addr),
          .Dq               (ddr_dq[((o+1)*DQ_BITS-1)-:DQ_BITS]),
          .Dqs              (ddr_dqs[((o+1)*DQS_BITS-1)-:DQS_BITS])
        );
      end
endgenerate

always #10000 clk = ~clk;

initial begin
  $fsdbDumpfile("ddr.fsdb");
  $fsdbDumpvars;
end

initial
begin
    clk = 0;
    rst = 0;
    rst_n = 1;
    start = 0;
    display = 0;
    sr_in = 1'b0;
    read_in = 1'b0;
    
    #2400000
    rst_n = 0;
    #480000 
    rst_n = 1;
    #560000000  //560000000 

    start = 1'b1;
    #4800000
    start = 1'b0;
    #4800000;
    #136000000  
    start = 1'b1;
    #4800000
    start = 1'b0;

   
     #500000000;
    $finish;
end


endmodule


