# Written by Synplify Pro version mapgw, Build 1618R. Synopsys Run ID: sid1590039368 
# Top Level Design Parameters 

# Clocks 
create_clock -period 4.369 -waveform {0.000 2.184} -name {ao_top_0|clk_i} [get_ports {clk_i}] 
create_clock -period 5.715 -waveform {0.000 2.857} -name {ao_top_0|control[0]} [get_ports {control[0]}] 

# Virtual Clocks 

# Generated Clocks 

# Paths Between Clocks 

# Multicycle Constraints 

# Point-to-point Delay Constraints 

# False Path Constraints 

# Output Load Constraints 

# Driving Cell Constraints 

# Input Delay Constraints 

# Output Delay Constraints 

# Wire Loads 

# Other Constraints 

# syn_hier Attributes 

# set_case Attributes 

# Clock Delay Constraints 
set Autoconstr_clkgroup_0 [list ao_top_0|clk_i]
set Autoconstr_clkgroup_1 [list ao_top_0|control[0]]
set_clock_groups -asynchronous -group $Autoconstr_clkgroup_0 -group $Autoconstr_clkgroup_1

# syn_mode Attributes 

# Cells 

# Port DRC Rules 

# Input Transition Constraints 

# Unused constraints (intentionally commented out) 


# Non-forward-annotatable constraints (intentionally commented out) 

# Block Path constraints 

