# Thu May 21 10:09:02 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-003

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_control\rev_1\ao_control_scck.rpt 
See clock summary report "F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_control\rev_1\ao_control_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)

@N: BN133 |Ignoring syn_hier=hard property on top-level design.

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)



Clock Summary
******************

          Start                Requested     Requested     Clock        Clock                     Clock
Level     Clock                Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------
0 -       gw_con_top|tck_i     297.4 MHz     3.362         inferred     Autoconstr_clkgroup_0     14   
=======================================================================================================



Clock Load Summary
***********************

                     Clock     Source          Clock Pin                        Non-clock Pin     Non-clock Pin      
Clock                Load      Pin             Seq Example                      Seq Example       Comb Example       
---------------------------------------------------------------------------------------------------------------------
gw_con_top|tck_i     14        tck_i(port)     shift_dr_capture_dr_dly[0].C     -                 un1_tck_i.I[0](inv)
=====================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 14 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       ENCRYPTED           port                   14         ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_control\rev_1\ao_control.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 225MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu May 21 10:09:05 2020

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