./prim_sim.v
../../tb/tb.v
../../tb/GWMC.vo
../../project/src/ddr1_syn_top.v
../../project/src/DDR_TOP.v
../../project/src/DDR1_test_rst.v
../../project/src/key_debounce.v
../../project/src/ddr_phy_interface/ddr_phy_interface.vo
../../tb/sim_model/ddr1.v
+incdir+../../project/src/
+incdir+../../project/src/ddr_phy_interface/
+incdir+../../project/src/ddr_phy_interface/temp/DDR1_PHY/
+incdir+../../tb/sim_model/
+incdir+../../tb/
