NOTE:  This version of the software is not a production release. No warranty is made as to the general availability of features and functionality included in this version or described in the accompanying documentation. The final contents of a production release and its timing remain at the sole discretion of Synopsys.

Starting:    E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\bin64\mbin\synbatch.exe
Install:     E:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro
Hostname:    GW-SW-003
Date:        Thu May 21 13:35:36 2020
Version:     Q-2020.03G-Beta1

Arguments:   -product synplify_pro -batch -licensetype synplifypro_gowin F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs2/project/temp/gao/ao_control/ao_control.prj
ProductType: synplify_pro

License checkout: synplifypro_gowin
License: synplifypro_gowin from server 192.168.31.246 
Licensed Vendor: gowin

Running in Vendor Mode

log file: "F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\ao_control.srr"
Running: rev_1 in foreground

Running ao_control|rev_1

Running Flow: compile (Compile) on ao_control|rev_1
# Thu May 21 13:35:36 2020

Running Flow: compile_flow (Compile Process) on ao_control|rev_1
# Thu May 21 13:35:36 2020

Running: compiler (Compile Input) on ao_control|rev_1
# Thu May 21 13:35:36 2020
Copied F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\synwork\ao_control_comp.srs to F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\ao_control.srs

compiler completed
# Thu May 21 13:35:39 2020

Return Code: 0
Run Time:00h:00m:03s

Running: multi_srs_gen (Multi-srs Generator) on ao_control|rev_1
# Thu May 21 13:35:39 2020

multi_srs_gen completed
# Thu May 21 13:35:40 2020

Return Code: 0
Run Time:00h:00m:01s
Copied F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\synwork\ao_control_mult.srs to F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\ao_control.srs
Complete: Compile Process on ao_control|rev_1

Running: premap (Premap) on ao_control|rev_1
# Thu May 21 13:35:40 2020

premap completed
# Thu May 21 13:35:44 2020

Return Code: 0
Run Time:00h:00m:04s
Complete: Compile on ao_control|rev_1

Running Flow: map (Map) on ao_control|rev_1
# Thu May 21 13:35:44 2020

Running: fpga_mapper (Map & Optimize) on ao_control|rev_1
# Thu May 21 13:35:44 2020
Copied F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\synwork\ao_control_m.srm to F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_control\rev_1\ao_control.srm

fpga_mapper completed with warnings
# Thu May 21 13:35:49 2020

Return Code: 1
Run Time:00h:00m:05s
Complete: Map on ao_control|rev_1
Complete: Logic Synthesis on ao_control|rev_1
exit status=0
exit status=0
License checkin: synplifypro_gowin
