#--  Synopsys, Inc.
#--  Version Q-2020.03G-Beta1
#--  Project file F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1\scratchproject.prs

#project files
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_MC_PHY_1vs1/project/temp/gao/ao_0/gw_ao_parameter.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_MC_PHY_1vs1/project/temp/gao/ao_0/gw_ao_top_define.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_MC_PHY_1vs1/project/temp/gao/ao_0/gw_ao_expression.v"
add_file -verilog "E:/Gowin/Gowin_V1.9.5.02Beta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_crc32.v"
add_file -verilog "E:/Gowin/Gowin_V1.9.5.02Beta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_define.v"
add_file -verilog "E:/Gowin/Gowin_V1.9.5.02Beta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_match.v"
add_file -verilog "E:/Gowin/Gowin_V1.9.5.02Beta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_mem_ctrl.v"
add_file -verilog "E:/Gowin/Gowin_V1.9.5.02Beta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_top.v"


#implementation: "rev_1"
impl -add F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1 -type fpga

#device options
set_option -technology GOWIN-GW2AR
set_option -part GW2AR_18
set_option -package LQFP176
set_option -speed_grade -8
set_option -part_companion ""

#compilation/mapping options

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW2AR
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_MC_PHY_1vs1/project/temp/gao/ao_0/rev_1/ao_0.vm"
impl -active "rev_1"
