@N: CD630 :"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_MC_PHY_1vs1\project\temp\gao\ao_0\rev_1\syntmp\gentmp4998a12552":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a12552":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a12552":92:11:92:18|Bit 8 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 9 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 10 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 11 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 12 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 13 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 14 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a12552":92:11:92:18|Bit 15 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@N: CD630 :"syng0a12552":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a12552":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a12552":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Running optimization stage 1 on MUXCY_L .......
Post processing for work.eq_element.eqn
Running optimization stage 1 on eq_element .......
Post processing for work.cmp_eq.cell_level
Running optimization stage 1 on CMP_EQ .......
Post processing for work.top.gen
Running optimization stage 1 on top .......
Running optimization stage 2 on MUXCY_L .......
Running optimization stage 2 on eq_element .......
Running optimization stage 2 on CMP_EQ .......
Running optimization stage 2 on top .......
