//Copyright (C)2014-2020 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.5.02 Beta
//Created Time: 2020-05-21 09:27:40
create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
create_clock -name clk_x1 -period 10 -waveform {0 5} [get_nets {clk_x1}]
create_clock -name clk_x2 -period 5 -waveform {0 2.5} [get_nets {u_DDR_TOP/u_gw_phy_mc_top/u_ddr_phy_top/clk_x2}]
