# project files
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/GWMC.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/DDR_TOP.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/ddr1_syn_top.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/DDR1_test_rst.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/key_debounce.v"
add_file -verilog "F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/ddr_phy_interface/ddr_phy_interface.v"

# implementation: "rev_1"
impl -add rev_1 -type fpga

# device options
set_option -technology GOWIN-GW2AR
set_option -part GW2AR_18
set_option -package LQFP176
set_option -speed_grade -8

set_option -frequency 180
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -update_models_cp 0
set_option -rw_check_on_ram 1
set_option -run_prop_extract 1
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -pipe 1
set_option -retiming 0
set_option -write_apr_constraint 1
set_option -num_critical_paths 0
set_option -num_startend_points 0
set_option -vlog_std sysv
set_option -compiler_compatible 0
set_option -multi_file_compilation_unit 1
set_option -looplimit 2000
set_option -fix_gated_and_generated_clocks 1
set_option -top_module ddr1_syn_top
set_option -include_path {F:/gwip_test/refDesign_sdc/DDR_PSRAM_RefDesign/new_ref_design_v1_9_5_02/Gowin_DDR_Memory_Interface_RefDesign/DDR_PHY_1vs1/project/src/ddr_phy_interface/temp/DDR1_PHY}

# set result format/file
project -result_file "DDR_PHY_1vs1_Basic_Option.vm"
impl -active "rev_1"
project -run -clean

