//
// Written by Synplify Pro 
// Product Version "Q-2020.03G-Beta1"
// Program "Synplify Pro", Mapper "mapgw, Build 1618R"
// Thu May 21 11:07:33 2020
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\generic\gw2a.v "
// file 1 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\hypermods.v "
// file 2 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1_phy\data\ddr_code.v "
// file 6 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_phy_1vs1\project\src\ddr_phy_interface\temp\ddr1_phy\ddr_name.v "
// file 7 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_phy_1vs1\project\src\ddr_phy_interface\temp\ddr1_phy\gwmc_param.v "
// file 8 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1_phy\data\gwmc_local_param.v "
// file 9 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_phy_1vs1\project\src\ddr_phy_interface\temp\ddr1_phy\ddr_define.v "
// file 10 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_phy_1vs1\project\src\ddr_phy_interface\temp\ddr1_phy\ddr_pll_config.v "
// file 11 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1_phy\data\ddr1_phy_top.v "
// file 12 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\nlconst.dat "

`timescale 100 ps/100 ps
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
`pragma protect key_block
sXFjqum47GjBZjBjwQ7TzN2FYYS3zt1804fI2dW6rvk64vW+8qMssxdXDyWEoVkxIbWYianbXt+i
E9B3ddqSfYEQY1FD2ogQcMvqYwvwD0f/6ORE71RuQW3Zr2dFpkrhuSwkb+bFjMOekBSYwy6t3vxf
Ol/NCfJpyG3FY8An18E481Ray8ZJWVLY9yrYdvym4gNJdbuVzAcRqziWrHQybFfxY2lOJsyooKin
XKuLsUSi4JuvI+d7qO1i5T+3Am5LZIWrHrwdT2BFzo7ikEL5BFgUZPOiYPAxnLwRXpNEFAfqDxPN
BLj1Xf+pVoiJJCze9C1rA/wE4hBm7z1DbNQcIw==

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GoWin"
`pragma protect key_keyname="GoWin2016"
`pragma protect key_method="rsa"
`pragma protect key_block
XreXRoBn9YlPVcJaRPdeXYPvNM+eJp43wvj8jKiYyfHNn1O5b/SlGCSq7ciBHqSUFZaY1VSkK+pW
0FX4ipKksAtzbcIDBtVRYAYmJq965ntfS0TbbBYt4d7bw0wyKxCWfvJfkhxamlwc6z5uaHaBqp4Q
/Fq6U/NCGMTyD9qSHk71Nz/XZAiHKFizLfe7SDOK0HMDvW+xqpAHYqihd4LHvExSnPs0ClZOssFT
mohUIDthI0hRchN7RpOg8d5uISv/gLTQmkMeo5L7LI9BpvxcPu41oQ3uAM5szKTv48xob5DiY1Tx
8+pCUek1wCTcyQ3OQ1zx/rTTMJRoxe3CUC4gMQ==

`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=245424)
`pragma protect data_block
[encoded data, 327180 characters]
DXHNuGvYLDCCH/qam/VAx6ZNWkqA6kcgDFW77lixWFNCcko1Vqp0
`pragma protect end_protected
module DDR_PHY_Interface_Top (
  clk,
  rst_n,
  mc_cs_n,
  mc_ras_n,
  mc_cas_n,
  mc_we_n,
  mc_address,
  mc_bank,
  mc_reset_n,
  mc_cke,
  mc_cmd_wren,
  mc_wrdata_en,
  mc_wrdata,
  mc_wrdata_mask,
  phy_rd_data_valid,
  phy_rd_data,
  ddr_init_complete,
  O_ddr_addr,
  O_ddr_ba,
  O_ddr_cs_n,
  O_ddr_ras_n,
  O_ddr_cas_n,
  O_ddr_we_n,
  O_ddr_clk,
  O_ddr_clk_n,
  O_ddr_cke,
  O_ddr_dqm,
  IO_ddr_dq,
  IO_ddr_dqs,
  clk_x1,
  ddr_rst
)
;
input clk ;
input rst_n ;
input [0:0] mc_cs_n ;
input [0:0] mc_ras_n ;
input [0:0] mc_cas_n ;
input [0:0] mc_we_n ;
input [11:0] mc_address ;
input [1:0] mc_bank ;
input mc_reset_n ;
input [0:0] mc_cke ;
input mc_cmd_wren ;
input mc_wrdata_en ;
input [31:0] mc_wrdata ;
input [3:0] mc_wrdata_mask ;
output phy_rd_data_valid ;
output [31:0] phy_rd_data ;
output ddr_init_complete ;
output [11:0] O_ddr_addr ;
output [1:0] O_ddr_ba ;
output O_ddr_cs_n ;
output O_ddr_ras_n ;
output O_ddr_cas_n ;
output O_ddr_we_n ;
output O_ddr_clk ;
output O_ddr_clk_n ;
output O_ddr_cke ;
output [1:0] O_ddr_dqm ;
inout [15:0] IO_ddr_dq /* synthesis syn_tristate = 1 */ ;
inout [1:0] IO_ddr_dqs /* synthesis syn_tristate = 1 */ ;
output clk_x1 /* synthesis syn_tristate = 1 */ ;
output ddr_rst ;
wire clk ;
wire rst_n ;
wire mc_reset_n ;
wire mc_cmd_wren ;
wire mc_wrdata_en ;
wire phy_rd_data_valid ;
wire ddr_init_complete ;
wire O_ddr_cs_n ;
wire O_ddr_ras_n ;
wire O_ddr_cas_n ;
wire O_ddr_we_n ;
wire O_ddr_clk ;
wire O_ddr_clk_n ;
wire O_ddr_cke ;
wire clk_x1 ;
wire ddr_rst ;
wire GND ;
wire VCC ;
  GSR GSR (
	.GSRI(VCC)
);
// @11:47
  \~gw_phy.DDR_PHY_Interface_Top_  u_gw_phy_top (
	.clk(clk),
	.rst_n(rst_n),
	.mc_cs_n(mc_cs_n[0]),
	.mc_ras_n(mc_ras_n[0]),
	.mc_cas_n(mc_cas_n[0]),
	.mc_we_n(mc_we_n[0]),
	.mc_address(mc_address[11:0]),
	.mc_bank(mc_bank[1:0]),
	.mc_reset_n(GND),
	.mc_cke(mc_cke[0]),
	.mc_cmd_wren(mc_cmd_wren),
	.mc_wrdata_en(mc_wrdata_en),
	.mc_wrdata(mc_wrdata[31:0]),
	.mc_wrdata_mask({GND, GND, GND, GND}),
	.phy_rd_data_valid(phy_rd_data_valid),
	.phy_rd_data(phy_rd_data[31:0]),
	.ddr_init_complete(ddr_init_complete),
	.O_ddr_addr(O_ddr_addr[11:0]),
	.O_ddr_ba(O_ddr_ba[1:0]),
	.O_ddr_cs_n(O_ddr_cs_n),
	.O_ddr_ras_n(O_ddr_ras_n),
	.O_ddr_cas_n(O_ddr_cas_n),
	.O_ddr_we_n(O_ddr_we_n),
	.O_ddr_clk(O_ddr_clk),
	.O_ddr_clk_n(O_ddr_clk_n),
	.O_ddr_cke(O_ddr_cke),
	.O_ddr_dqm(O_ddr_dqm[1:0]),
	.IO_ddr_dq(IO_ddr_dq[15:0]),
	.IO_ddr_dqs(IO_ddr_dqs[1:0]),
	.clk_x1(clk_x1),
	.ddr_rst(ddr_rst)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* DDR_PHY_Interface_Top */

