//
// Written by Synplify Pro 
// Product Version "Q-2020.03G-Beta1"
// Program "Synplify Pro", Mapper "mapgw, Build 1618R"
// Thu May 21 10:03:53 2020
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\generic\gw2a.v "
// file 1 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\hypermods.v "
// file 2 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1\data\ddr_code.v "
// file 6 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_mc_phy_1vs1\project\src\ddr_memory_interface\temp\ddr1\ddr_name.v "
// file 7 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_mc_phy_1vs1\project\src\ddr_memory_interface\temp\ddr1\gwmc_param.v "
// file 8 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1\data\gwmc_local_param.v "
// file 9 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_mc_phy_1vs1\project\src\ddr_memory_interface\temp\ddr1\ddr_define.v "
// file 10 "\f:\gwip_test\refdesign_sdc\ddr_psram_refdesign\new_ref_design_v1_9_5_02\gowin_ddr_memory_interface_refdesign\ddr_mc_phy_1vs1\project\src\ddr_memory_interface\temp\ddr1\ddr_pll_config.v "
// file 11 "\e:\gowin\gowin_v1.9.5.02beta\ide\ipcore\ddr1\data\ddr1_top.v "
// file 12 "\e:\gowin\gowin_v1.9.5.02beta\synplifypro\lib\nlconst.dat "

`timescale 100 ps/100 ps
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
`pragma protect key_block
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`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GoWin"
`pragma protect key_keyname="GoWin2016"
`pragma protect key_method="rsa"
`pragma protect key_block
XreXRoBn9YlPVcJaRPdeXYPvNM+eJp43wvj8jKiYyfHNn1O5b/SlGCSq7ciBHqSUFZaY1VSkK+pW
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`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=420528)
`pragma protect data_block
[encoded data, 560652 characters]
+6ZMygHOSUGHjipnYvORv3JafdSHIHbvu3NGBFT2U/GyZ8/WJm0J
`pragma protect end_protected
module DDR_Memory_Interface_Top (
  clk,
  rst_n,
  cmd_ready,
  cmd,
  cmd_en,
  addr,
  wr_data_rdy,
  wr_data,
  wr_data_en,
  wr_data_end,
  wr_data_mask,
  rd_data,
  rd_data_valid,
  rd_data_end,
  sr_req,
  ref_req,
  sr_ack,
  ref_ack,
  init_calib_complete,
  clk_out,
  burst,
  ddr_rst,
  O_ddr_addr,
  O_ddr_ba,
  O_ddr_cs_n,
  O_ddr_ras_n,
  O_ddr_cas_n,
  O_ddr_we_n,
  O_ddr_clk,
  O_ddr_clk_n,
  O_ddr_cke,
  O_ddr_dqm,
  IO_ddr_dq,
  IO_ddr_dqs
)
;

/*  Synopsys
.origName=DDR_Memory_Interface_Top
.langParams="DRAM_TYPE nCK_PER_CLK tCK REG_CTRL DQ_WIDTH DRAM_WIDTH RANK_WIDTH BANK_WIDTH ROW_WIDTH COL_WIDTH tRP tRRD tRTP tRCD tRC tRAS tFAW tWTR tCKE tREFI tRFC tDLLK tWR tMRD tRAP BURST_MODE BURST_TYPE CL AL WR_CYC RTT_NOM USER_REFRESH ADDR_CMD_MODE OUTPUT_DRV CLKBUF_TYPE ECC HARD_DQS"
DRAM_TYPE="DDR1"
nCK_PER_CLK=1
tCK=6250
REG_CTRL="OFF"
DQ_WIDTH=16
DRAM_WIDTH=16
RANK_WIDTH=1
BANK_WIDTH=2
ROW_WIDTH=12
COL_WIDTH=9
tRP=15000
tRRD=10000
tRTP=7500
tRCD=15000
tRC=55000
tRAS=40000
tFAW=40000
tWTR=5000
tCKE=75000
tREFI=7800000
tRFC=70000
tDLLK=512
tWR=15000
tMRD=12000
tRAP=15000
BURST_MODE="4"
BURST_TYPE="SEQ"
CL=3
AL="0"
WR_CYC=6
RTT_NOM="OFF"
USER_REFRESH="OFF"
ADDR_CMD_MODE="1T"
OUTPUT_DRV="Reduced_strength"
CLKBUF_TYPE="SINGLE"
ECC="OFF"
HARD_DQS="ON"
 */
input clk ;
input rst_n ;
output cmd_ready ;
input [2:0] cmd ;
input cmd_en ;
input [23:0] addr ;
output wr_data_rdy ;
input [31:0] wr_data ;
input wr_data_en ;
input wr_data_end ;
input [3:0] wr_data_mask ;
output [31:0] rd_data ;
output rd_data_valid ;
output rd_data_end ;
input sr_req ;
input ref_req ;
output sr_ack /* synthesis syn_tristate = 1 */ ;
output ref_ack ;
output init_calib_complete ;
output clk_out ;
input burst ;
output ddr_rst ;
output [11:0] O_ddr_addr ;
output [1:0] O_ddr_ba ;
output O_ddr_cs_n ;
output O_ddr_ras_n ;
output O_ddr_cas_n ;
output O_ddr_we_n ;
output O_ddr_clk ;
output O_ddr_clk_n ;
output O_ddr_cke ;
output [1:0] O_ddr_dqm ;
inout [15:0] IO_ddr_dq /* synthesis syn_tristate = 1 */ ;
inout [1:0] IO_ddr_dqs /* synthesis syn_tristate = 1 */ ;
wire clk ;
wire rst_n ;
wire cmd_ready ;
wire cmd_en ;
wire wr_data_rdy ;
wire wr_data_en ;
wire wr_data_end ;
wire rd_data_valid ;
wire rd_data_end ;
wire sr_req ;
wire ref_req ;
wire sr_ack ;
wire ref_ack ;
wire init_calib_complete ;
wire clk_out ;
wire burst ;
wire ddr_rst ;
wire O_ddr_cs_n ;
wire O_ddr_ras_n ;
wire O_ddr_cas_n ;
wire O_ddr_we_n ;
wire O_ddr_clk ;
wire O_ddr_clk_n ;
wire O_ddr_cke ;
wire [0:0] ecc_err;
wire GND ;
wire sr_ack_0 ;
wire VCC ;
  GSR GSR (
	.GSRI(VCC)
);
// @11:110
  \~gw_phy_mc.DDR_Memory_Interface_Top_  u_gw_phy_mc_top (
	.clk(clk),
	.rst_n(rst_n),
	.cmd_ready(cmd_ready),
	.cmd(cmd[2:0]),
	.cmd_en(cmd_en),
	.addr({addr[23:22], GND, addr[20:0]}),
	.wr_data_rdy(wr_data_rdy),
	.wr_data(wr_data[31:0]),
	.wr_data_en(wr_data_en),
	.wr_data_end(wr_data_end),
	.wr_data_mask({GND, GND, GND, GND}),
	.rd_data(rd_data[31:0]),
	.rd_data_valid(rd_data_valid),
	.rd_data_end(rd_data_end),
	.sr_req(sr_req),
	.ref_req(GND),
	.sr_ack(sr_ack_0),
	.ref_ack(ref_ack),
	.init_calib_complete(init_calib_complete),
	.clk_out(clk_out),
	.ecc_err(ecc_err[0]),
	.burst(burst),
	.ddr_rst(ddr_rst),
	.O_ddr_addr(O_ddr_addr[11:0]),
	.O_ddr_ba(O_ddr_ba[1:0]),
	.O_ddr_cs_n(O_ddr_cs_n),
	.O_ddr_ras_n(O_ddr_ras_n),
	.O_ddr_cas_n(O_ddr_cas_n),
	.O_ddr_we_n(O_ddr_we_n),
	.O_ddr_clk(O_ddr_clk),
	.O_ddr_clk_n(O_ddr_clk_n),
	.O_ddr_cke(O_ddr_cke),
	.O_ddr_dqm(O_ddr_dqm[1:0]),
	.IO_ddr_dq(IO_ddr_dq[15:0]),
	.IO_ddr_dqs(IO_ddr_dqs[1:0])
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* DDR_Memory_Interface_Top */

