#OPTIONS:"|-layerid|0|-orig_srs|F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\rev_1\\synwork\\ao_0_comp.srs|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-I|F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\|-I|E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib|-sysv|-devicelib|E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\generic\\gw2a.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\bin64\\c_ver.exe":1589223566
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\generic\\gw2a.v":1589223686
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\vlog\\hypermods.v":1589223772
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\vlog\\umr_capim.v":1589223772
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1589223772
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1589223772
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_parameter.v":1590039327
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_top_define.v":1590039327
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_expression.v":1590039327
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_crc32.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_define.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_match.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_define.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_mem_ctrl.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_top.v":1589782904
#CUR:"E:\\Gowin\\Gowin_V1.9.5.02Beta\\IDE\\data\\ipcores\\GAO\\GW_AO_0\\gw_ao_define.v":1589782904
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_top_define.v":1590039327
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_expression.v":1590039327
#CUR:"F:\\gwip_test\\refDesign_sdc\\DDR_PSRAM_RefDesign\\new_ref_design_v1_9_5_02\\Gowin_DDR_Memory_Interface_RefDesign\\DDR_PHY_1vs2\\project\\temp\\gao\\ao_0\\gw_ao_parameter.v":1590039327
#numinternalfiles:5
#defaultlanguage:verilog
0			"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_parameter.v" verilog
1			"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_top_define.v" verilog
2			"F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_expression.v" verilog
3			"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" verilog
4			"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" verilog
5			"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" verilog
6			"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" verilog
7			"E:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" verilog
#Dependency Lists(Uses List)
0 4 1 2 0
1 4 2 0
2 4 1 0
3 0
4 1 2 0
5 4 0
6 0
7 4 1 2 0 6 3 5
#Dependency Lists(Users Of)
0 1 2 4 7 3 5 6
1 0 2 4 7
2 0 1 4 7
3 7
4 0 1 2 5 7
5 7
6 7
7 -1
#Design Unit to File Association
package work work_F:\gwip_test\refDesign_sdc\DDR_PSRAM_RefDesign\new_ref_design_v1_9_5_02\Gowin_DDR_Memory_Interface_RefDesign\DDR_PHY_1vs2\project\temp\gao\ao_0\gw_ao_parameter.v_unit 0
module work ao_crc32_0 3
module work ao_match_0 5
module work ao_mem_ctrl_0 6
module work ao_top_0 7
