Project Settings |
---|
Project Name | DIVIDER_WIDTH_16 | Device Name | rev_1: GOWIN-GW2A : GW2A_55 |
Implementation Name | rev_1 | Top Module | [auto] |
Pipelining | 1 | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
Clock Conversion | 1 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
10 |
1 |
0 |
- |
00m:01s |
- |
2018/9/28 15:24:28 |
(premap) | Complete |
13 |
0 |
0 |
0m:01s |
0m:02s |
192MB |
2018/9/28 15:24:33 |
(fpga_mapper) | Complete |
11 |
1 |
0 |
0m:04s |
0m:04s |
192MB |
2018/9/28 15:24:38 |
Multi-srs Generator |
Complete | | | | | | | 2018/9/28 15:24:30 |
Area Summary |
|
I/O ports
(io_port) | 52 |
Non I/O Register bits
(non_io_reg) | 68 (0%) |
I/O Register bits
(total_io_reg) | 0 |
Block Rams
(v_ram) | 0 (140) |
Block Multipliers
(dsp_used) | 0 (20) |
LUTs
(total_luts) | 92 (0%) |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
top|clk | 246.4 MHz | 209.4 MHz | -0.716 |
System | 150.0 MHz | 312.1 MHz | 3.463 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
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