Timing Messages

Report Title Gowin Timing Analysis Report
Tool Version v1.8.1.01Beta
Series, Device, Package, Speed, Operating Conditions GW2A, GW2A-55, PBGA484, 8, COMMERCIAL
Design Name top
Design File E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\impl\synthesize\rev_1\DIVIDER_WIDTH_16.vm
Timing Constraint File ---
Timing Report File E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\impl\pnr\DIVIDER_WIDTH_16.tr.html
Created Time Fri Sep 28 15:25:56 2018
Command Line D:\Gowin\1.8\Pnr\bin\gowin.exe -do E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\impl\pnr\cmd.do
Legal Announcement Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C
Hold Delay Model Fast 1.05V 0C
Numbers of Paths Analyzed 462
Numbers of Endpoints Analyzed 1501
Numbers of Falling Endpoints 1
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
DEFAULT_CLK Base 10.000 100.000 0.000 5.000

Max Frequency Summary:

NO. Clock Name Fmax Entity
1 DEFAULT_CLK 143.248(MHz) TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
DEFAULT_CLK Setup 0.000 0
DEFAULT_CLK Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
2 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[3]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
3 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_dly_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
4 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
5 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
6 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/capture_end_dly_Z/PRESET DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
7 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
8 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_syn_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
9 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
10 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
11 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel[3]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
12 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_dly_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
13 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
14 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
15 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
16 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
17 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
18 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
19 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
20 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
21 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
22 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
23 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
24 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
25 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.436 uut/u_fra_div/done_1/Q uut/u_fra_div/done_1/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.447
2 0.485 uut/u_fra_div/quotient[15]/Q uut/u_fra_div/quotient[15]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.496
3 0.547 uut/u_fra_div/divider_copy_Z[20]/Q uut/u_fra_div/divider_copy_Z[19]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.558
4 0.547 uut/u_fra_div/divider_copy_Z[16]/Q uut/u_fra_div/divider_copy_Z[15]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.558
5 0.547 uut/u_fra_div/divider_copy_Z[22]/Q uut/u_fra_div/divider_copy_Z[21]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.558
6 0.550 uut/u_fra_div/divider_copy_Z[10]/Q uut/u_fra_div/divider_copy_Z[9]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.561
7 0.553 uut/u_fra_div/divider_copy_Z[6]/Q uut/u_fra_div/divider_copy_Z[5]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.564
8 0.605 uut/u_fra_div/divider_copy_Z[28]/Q uut/u_fra_div/divider_copy_Z[27]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.616
9 0.654 uut/u_fra_div/divider_copy_Z[19]/Q uut/u_fra_div/divider_copy_Z[18]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
10 0.654 uut/u_fra_div/bi_Z[1]/Q uut/u_fra_div/bi_Z[1]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
11 0.654 uut/u_fra_div/divider_copy_Z[23]/Q uut/u_fra_div/divider_copy_Z[22]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
12 0.654 uut/u_fra_div/divider_copy_Z[21]/Q uut/u_fra_div/divider_copy_Z[20]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
13 0.654 uut/u_fra_div/divider_copy_Z[27]/Q uut/u_fra_div/divider_copy_Z[26]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
14 0.654 uut/u_fra_div/bi_Z[3]/Q uut/u_fra_div/bi_Z[3]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
15 0.654 uut/u_fra_div/divider_copy_Z[25]/Q uut/u_fra_div/divider_copy_Z[24]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.665
16 0.658 uut/u_fra_div/divider_copy_Z[5]/Q uut/u_fra_div/divider_copy_Z[4]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.669
17 0.658 uut/u_fra_div/bi_Z[5]/Q uut/u_fra_div/bi_Z[5]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.669
18 0.659 uut/u_fra_div/divider_copy_Z[15]/Q uut/u_fra_div/divider_copy_Z[14]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.670
19 0.661 uut/u_fra_div/bi_Z[2]/Q uut/u_fra_div/bi_Z[2]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.672
20 0.665 uut/u_fra_div/divider_copy_Z[14]/Q uut/u_fra_div/divider_copy_Z[13]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.676
21 0.674 uut/u_fra_div/divider_copy_Z[17]/Q uut/u_fra_div/divider_copy_Z[16]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.685
22 0.674 uut/u_fra_div/divider_copy_Z[11]/Q uut/u_fra_div/divider_copy_Z[10]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.685
23 0.674 uut/u_fra_div/divider_copy_Z[1]/Q uut/u_fra_div/divider_copy_Z[0]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.685
24 0.678 uut/u_fra_div/divider_copy_Z[13]/Q uut/u_fra_div/divider_copy_Z[12]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.689
25 0.678 uut/u_fra_div/divider_copy_Z[9]/Q uut/u_fra_div/divider_copy_Z[8]/D DEFAULT_CLK:[R] DEFAULT_CLK:[R] 0.000 0.000 0.689

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
2 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/trigger_seq_start_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
3 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
4 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
5 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
6 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
7 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
8 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
9 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
10 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
11 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
12 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
13 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
14 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
15 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
16 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
17 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
18 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
19 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
20 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
21 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
22 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
23 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
24 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714
25 2.019 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] 5.000 0.033 2.714

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
2 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
3 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
4 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
5 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
6 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
7 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
8 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
9 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
10 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
11 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
12 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
13 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
14 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
15 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
16 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
17 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
18 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
19 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
20 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
21 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
22 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
23 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
24 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809
25 6.611 u_la0_top/rst_ao_Z/Q u_la0_top/trigger_seq_start_Z/CLEAR DEFAULT_CLK:[F] DEFAULT_CLK:[R] -5.000 0.013 1.809

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/quotient[0]
2 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/quotient[13]
3 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/quotient[9]
4 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/quotient[1]
5 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/divider_copy_Z[9]
6 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/dividend_copy_Z[14]
7 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK u_la0_top/u_ao_mem_ctrl/data_reg_Z[5]
8 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK u_la0_top/u_ao_mem_ctrl/data_reg_Z[6]
9 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK uut/u_fra_div/dividend_copy_Z[13]
10 3.662 4.662 1.000 Low Pulse Width DEFAULT_CLK u_la0_top/u_ao_mem_ctrl/data_reg_Z[7]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C2[0][A] u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C2[0][A] u_la0_top/triger_level_cnt_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/triger_level_cnt_Z[2]
11.648 -0.035 tSu 1 R3C2[0][A] u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C2[0][B] u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C2[0][B] u_la0_top/triger_level_cnt_Z[3]/CLK
11.683 -0.200 tUnc u_la0_top/triger_level_cnt_Z[3]
11.648 -0.035 tSu 1 R3C2[0][B] u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C11[0][B] u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C11[0][B] u_la0_top/internal_reg_start_dly_Z[1]/CLK
11.683 -0.200 tUnc u_la0_top/internal_reg_start_dly_Z[1]
11.648 -0.035 tSu 1 R3C11[0][B] u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648 -0.035 tSu 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648 -0.035 tSu 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/capture_end_dly_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[1][A] u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[1][A] u_la0_top/capture_end_dly_Z/CLK
11.683 -0.200 tUnc u_la0_top/capture_end_dly_Z
11.648 -0.035 tSu 1 R7C11[1][A] u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 -0.035 tSu 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C12[0][A] u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C12[0][A] u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/internal_reg_start_syn_Z[0]
11.648 -0.035 tSu 1 R3C12[0][A] u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[1][B] u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[1][B] u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
11.683 -0.200 tUnc u_la0_top/internal_reg_force_triger_syn_Z[1]
11.648 -0.035 tSu 1 R7C11[1][B] u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[2][A] u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[2][A] u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648 -0.035 tSu 1 R7C11[2][A] u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C4[1][A] u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C4[1][A] u_la0_top/capture_window_sel[3]/CLK
11.683 -0.200 tUnc u_la0_top/capture_window_sel[3]
11.648 -0.035 tSu 1 R2C4[1][A] u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C6[1][A] u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C6[1][A] u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/internal_reg_start_dly_Z[0]
11.648 -0.035 tSu 1 R2C6[1][A] u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648 -0.035 tSu 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683 -0.200 tUnc u_la0_top/genblk1.u_ao_match_0/match_sep
11.648 -0.035 tSu 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648 -0.035 tSu 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C6[2][A] u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C6[2][A] u_la0_top/capture_window_sel_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/capture_window_sel_Z[2]
11.648 -0.035 tSu 1 R2C6[2][A] u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648 -0.035 tSu 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C6[1][B] u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C6[1][B] u_la0_top/capture_window_sel_Z[1]/CLK
11.683 -0.200 tUnc u_la0_top/capture_window_sel_Z[1]
11.648 -0.035 tSu 1 R2C6[1][B] u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648 -0.035 tSu 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648 -0.035 tSu 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648 -0.035 tSu 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648 -0.035 tSu 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648 -0.035 tSu 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 -0.035 tSu 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648 -0.035 tSu 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.436
Data Arrival Time 2.025
Data Required Time 1.588
From uut/u_fra_div/done_1
To uut/u_fra_div/done_1
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C53[0][A] uut/u_fra_div/done_1/CLK
1.779 0.202 tC2Q RR 74 R9C53[0][A] uut/u_fra_div/done_1/Q
1.793 0.013 tNET RR 1 R9C53[0][A] uut/u_fra_div/done_1_1_cZ/I1
2.025 0.232 tINS RF 1 R9C53[0][A] uut/u_fra_div/done_1_1_cZ/F
2.025 0.000 tNET FF 1 R9C53[0][A] uut/u_fra_div/done_1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C53[0][A] uut/u_fra_div/done_1/CLK
1.577 0.000 tUnc uut/u_fra_div/done_1
1.588 0.011 tHld 1 R9C53[0][A] uut/u_fra_div/done_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 51.850%; route: 0.013, 3.005%; tC2Q: 0.202, 45.145%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack 0.485
Data Arrival Time 2.073
Data Required Time 1.588
From uut/u_fra_div/quotient[15]
To uut/u_fra_div/quotient[15]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C53[2][A] uut/u_fra_div/quotient[15]/CLK
1.779 0.202 tC2Q RR 5 R23C53[2][A] uut/u_fra_div/quotient[15]/Q
1.783 0.004 tNET RR 1 R23C53[2][A] uut/u_fra_div/quotient_1_cZ[15]/I2
2.073 0.290 tINS RF 1 R23C53[2][A] uut/u_fra_div/quotient_1_cZ[15]/F
2.073 0.000 tNET FF 1 R23C53[2][A] uut/u_fra_div/quotient[15]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C53[2][A] uut/u_fra_div/quotient[15]/CLK
1.577 0.000 tUnc uut/u_fra_div/quotient[15]
1.588 0.011 tHld 1 R23C53[2][A] uut/u_fra_div/quotient[15]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack 0.547
Data Arrival Time 2.136
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[20]
To uut/u_fra_div/divider_copy_Z[19]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C38[2][B] uut/u_fra_div/divider_copy_Z[20]/CLK
1.778 0.201 tC2Q RF 2 R24C38[2][B] uut/u_fra_div/divider_copy_Z[20]/Q
1.904 0.125 tNET FF 1 R24C39[2][A] uut/u_fra_div/divider_copy_6_cZ[19]/I1
2.136 0.232 tINS FF 1 R24C39[2][A] uut/u_fra_div/divider_copy_6_cZ[19]/F
2.136 0.000 tNET FF 1 R24C39[2][A] uut/u_fra_div/divider_copy_Z[19]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C39[2][A] uut/u_fra_div/divider_copy_Z[19]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[19]
1.588 0.011 tHld 1 R24C39[2][A] uut/u_fra_div/divider_copy_Z[19]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack 0.547
Data Arrival Time 2.136
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[16]
To uut/u_fra_div/divider_copy_Z[15]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C40[2][B] uut/u_fra_div/divider_copy_Z[16]/CLK
1.778 0.201 tC2Q RF 2 R24C40[2][B] uut/u_fra_div/divider_copy_Z[16]/Q
1.904 0.125 tNET FF 1 R24C41[2][A] uut/u_fra_div/divider_copy_6_cZ[15]/I1
2.136 0.232 tINS FF 1 R24C41[2][A] uut/u_fra_div/divider_copy_6_cZ[15]/F
2.136 0.000 tNET FF 1 R24C41[2][A] uut/u_fra_div/divider_copy_Z[15]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C41[2][A] uut/u_fra_div/divider_copy_Z[15]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[15]
1.588 0.011 tHld 1 R24C41[2][A] uut/u_fra_div/divider_copy_Z[15]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack 0.547
Data Arrival Time 2.136
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[22]
To uut/u_fra_div/divider_copy_Z[21]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C37[2][B] uut/u_fra_div/divider_copy_Z[22]/CLK
1.778 0.201 tC2Q RF 2 R24C37[2][B] uut/u_fra_div/divider_copy_Z[22]/Q
1.904 0.125 tNET FF 1 R24C38[2][A] uut/u_fra_div/divider_copy_6_cZ[21]/I1
2.136 0.232 tINS FF 1 R24C38[2][A] uut/u_fra_div/divider_copy_6_cZ[21]/F
2.136 0.000 tNET FF 1 R24C38[2][A] uut/u_fra_div/divider_copy_Z[21]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C38[2][A] uut/u_fra_div/divider_copy_Z[21]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[21]
1.588 0.011 tHld 1 R24C38[2][A] uut/u_fra_div/divider_copy_Z[21]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack 0.550
Data Arrival Time 2.139
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[10]
To uut/u_fra_div/divider_copy_Z[9]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C31[2][B] uut/u_fra_div/divider_copy_Z[10]/CLK
1.778 0.201 tC2Q RF 3 R24C31[2][B] uut/u_fra_div/divider_copy_Z[10]/Q
1.907 0.128 tNET FF 1 R24C32[2][A] uut/u_fra_div/divider_copy_6_cZ[9]/I1
2.139 0.232 tINS FF 1 R24C32[2][A] uut/u_fra_div/divider_copy_6_cZ[9]/F
2.139 0.000 tNET FF 1 R24C32[2][A] uut/u_fra_div/divider_copy_Z[9]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C32[2][A] uut/u_fra_div/divider_copy_Z[9]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[9]
1.588 0.011 tHld 1 R24C32[2][A] uut/u_fra_div/divider_copy_Z[9]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 41.321%; route: 0.128, 22.879%; tC2Q: 0.201, 35.800%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack 0.553
Data Arrival Time 2.141
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[6]
To uut/u_fra_div/divider_copy_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C33[2][B] uut/u_fra_div/divider_copy_Z[6]/CLK
1.778 0.201 tC2Q RF 3 R24C33[2][B] uut/u_fra_div/divider_copy_Z[6]/Q
1.909 0.131 tNET FF 1 R24C34[2][A] uut/u_fra_div/divider_copy_6_cZ[5]/I1
2.141 0.232 tINS FF 1 R24C34[2][A] uut/u_fra_div/divider_copy_6_cZ[5]/F
2.141 0.000 tNET FF 1 R24C34[2][A] uut/u_fra_div/divider_copy_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C34[2][A] uut/u_fra_div/divider_copy_Z[5]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[5]
1.588 0.011 tHld 1 R24C34[2][A] uut/u_fra_div/divider_copy_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.232, 41.150%; route: 0.131, 23.199%; tC2Q: 0.201, 35.651%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack 0.605
Data Arrival Time 2.194
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[28]
To uut/u_fra_div/divider_copy_Z[27]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C37[2][A] uut/u_fra_div/divider_copy_Z[28]/CLK
1.778 0.201 tC2Q RF 2 R23C37[2][A] uut/u_fra_div/divider_copy_Z[28]/Q
1.904 0.125 tNET FF 1 R23C36[2][A] uut/u_fra_div/divider_copy_6_cZ[27]/I1
2.194 0.290 tINS FF 1 R23C36[2][A] uut/u_fra_div/divider_copy_6_cZ[27]/F
2.194 0.000 tNET FF 1 R23C36[2][A] uut/u_fra_div/divider_copy_Z[27]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C36[2][A] uut/u_fra_div/divider_copy_Z[27]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[27]
1.588 0.011 tHld 1 R23C36[2][A] uut/u_fra_div/divider_copy_Z[27]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.290, 47.065%; route: 0.125, 20.315%; tC2Q: 0.201, 32.621%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[19]
To uut/u_fra_div/divider_copy_Z[18]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C39[2][A] uut/u_fra_div/divider_copy_Z[19]/CLK
1.778 0.201 tC2Q RF 2 R24C39[2][A] uut/u_fra_div/divider_copy_Z[19]/Q
1.899 0.120 tNET FF 1 R24C39[2][B] uut/u_fra_div/divider_copy_6_cZ[18]/I1
2.243 0.344 tINS FF 1 R24C39[2][B] uut/u_fra_div/divider_copy_6_cZ[18]/F
2.243 0.000 tNET FF 1 R24C39[2][B] uut/u_fra_div/divider_copy_Z[18]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C39[2][B] uut/u_fra_div/divider_copy_Z[18]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[18]
1.588 0.011 tHld 1 R24C39[2][B] uut/u_fra_div/divider_copy_Z[18]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/bi_Z[1]
To uut/u_fra_div/bi_Z[1]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[1][A] uut/u_fra_div/bi_Z[1]/CLK
1.778 0.201 tC2Q RF 6 R2C49[1][A] uut/u_fra_div/bi_Z[1]/Q
1.899 0.120 tNET FF 2 R2C49[1][A] uut/u_fra_div/un1_bi_cry_1_0/I0
2.243 0.344 tINS FF 1 R2C49[1][A] uut/u_fra_div/un1_bi_cry_1_0/SUM
2.243 0.000 tNET FF 1 R2C49[1][A] uut/u_fra_div/bi_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[1][A] uut/u_fra_div/bi_Z[1]/CLK
1.577 0.000 tUnc uut/u_fra_div/bi_Z[1]
1.588 0.011 tHld 1 R2C49[1][A] uut/u_fra_div/bi_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[23]
To uut/u_fra_div/divider_copy_Z[22]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C37[2][A] uut/u_fra_div/divider_copy_Z[23]/CLK
1.778 0.201 tC2Q RF 2 R24C37[2][A] uut/u_fra_div/divider_copy_Z[23]/Q
1.899 0.120 tNET FF 1 R24C37[2][B] uut/u_fra_div/divider_copy_6_cZ[22]/I1
2.243 0.344 tINS FF 1 R24C37[2][B] uut/u_fra_div/divider_copy_6_cZ[22]/F
2.243 0.000 tNET FF 1 R24C37[2][B] uut/u_fra_div/divider_copy_Z[22]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C37[2][B] uut/u_fra_div/divider_copy_Z[22]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[22]
1.588 0.011 tHld 1 R24C37[2][B] uut/u_fra_div/divider_copy_Z[22]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[21]
To uut/u_fra_div/divider_copy_Z[20]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C38[2][A] uut/u_fra_div/divider_copy_Z[21]/CLK
1.778 0.201 tC2Q RF 2 R24C38[2][A] uut/u_fra_div/divider_copy_Z[21]/Q
1.899 0.120 tNET FF 1 R24C38[2][B] uut/u_fra_div/divider_copy_6_cZ[20]/I1
2.243 0.344 tINS FF 1 R24C38[2][B] uut/u_fra_div/divider_copy_6_cZ[20]/F
2.243 0.000 tNET FF 1 R24C38[2][B] uut/u_fra_div/divider_copy_Z[20]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C38[2][B] uut/u_fra_div/divider_copy_Z[20]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[20]
1.588 0.011 tHld 1 R24C38[2][B] uut/u_fra_div/divider_copy_Z[20]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[27]
To uut/u_fra_div/divider_copy_Z[26]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C36[2][A] uut/u_fra_div/divider_copy_Z[27]/CLK
1.778 0.201 tC2Q RF 2 R23C36[2][A] uut/u_fra_div/divider_copy_Z[27]/Q
1.899 0.120 tNET FF 1 R23C36[2][B] uut/u_fra_div/divider_copy_6_cZ[26]/I1
2.243 0.344 tINS FF 1 R23C36[2][B] uut/u_fra_div/divider_copy_6_cZ[26]/F
2.243 0.000 tNET FF 1 R23C36[2][B] uut/u_fra_div/divider_copy_Z[26]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R23C36[2][B] uut/u_fra_div/divider_copy_Z[26]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[26]
1.588 0.011 tHld 1 R23C36[2][B] uut/u_fra_div/divider_copy_Z[26]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/bi_Z[3]
To uut/u_fra_div/bi_Z[3]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[2][A] uut/u_fra_div/bi_Z[3]/CLK
1.778 0.201 tC2Q RF 3 R2C49[2][A] uut/u_fra_div/bi_Z[3]/Q
1.899 0.120 tNET FF 2 R2C49[2][A] uut/u_fra_div/un1_bi_cry_3_0/I0
2.243 0.344 tINS FF 1 R2C49[2][A] uut/u_fra_div/un1_bi_cry_3_0/SUM
2.243 0.000 tNET FF 1 R2C49[2][A] uut/u_fra_div/bi_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[2][A] uut/u_fra_div/bi_Z[3]/CLK
1.577 0.000 tUnc uut/u_fra_div/bi_Z[3]
1.588 0.011 tHld 1 R2C49[2][A] uut/u_fra_div/bi_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack 0.654
Data Arrival Time 2.243
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[25]
To uut/u_fra_div/divider_copy_Z[24]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C30[2][A] uut/u_fra_div/divider_copy_Z[25]/CLK
1.778 0.201 tC2Q RF 2 R24C30[2][A] uut/u_fra_div/divider_copy_Z[25]/Q
1.899 0.120 tNET FF 1 R24C30[2][B] uut/u_fra_div/divider_copy_6_cZ[24]/I1
2.243 0.344 tINS FF 1 R24C30[2][B] uut/u_fra_div/divider_copy_6_cZ[24]/F
2.243 0.000 tNET FF 1 R24C30[2][B] uut/u_fra_div/divider_copy_Z[24]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C30[2][B] uut/u_fra_div/divider_copy_Z[24]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[24]
1.588 0.011 tHld 1 R24C30[2][B] uut/u_fra_div/divider_copy_Z[24]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.710%; route: 0.120, 18.076%; tC2Q: 0.201, 30.214%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack 0.658
Data Arrival Time 2.246
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[5]
To uut/u_fra_div/divider_copy_Z[4]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C34[2][A] uut/u_fra_div/divider_copy_Z[5]/CLK
1.778 0.201 tC2Q RF 3 R24C34[2][A] uut/u_fra_div/divider_copy_Z[5]/Q
1.902 0.124 tNET FF 1 R24C34[2][B] uut/u_fra_div/divider_copy_6_cZ[4]/I1
2.246 0.344 tINS FF 1 R24C34[2][B] uut/u_fra_div/divider_copy_6_cZ[4]/F
2.246 0.000 tNET FF 1 R24C34[2][B] uut/u_fra_div/divider_copy_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C34[2][B] uut/u_fra_div/divider_copy_Z[4]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[4]
1.588 0.011 tHld 1 R24C34[2][B] uut/u_fra_div/divider_copy_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.456%; route: 0.124, 18.478%; tC2Q: 0.201, 30.066%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack 0.658
Data Arrival Time 2.246
Data Required Time 1.588
From uut/u_fra_div/bi_Z[5]
To uut/u_fra_div/bi_Z[5]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C50[0][A] uut/u_fra_div/bi_Z[5]/CLK
1.778 0.201 tC2Q RF 3 R2C50[0][A] uut/u_fra_div/bi_Z[5]/Q
1.902 0.124 tNET FF 2 R2C50[0][A] uut/u_fra_div/un1_bi_s_5_0/I0
2.246 0.344 tINS FF 1 R2C50[0][A] uut/u_fra_div/un1_bi_s_5_0/SUM
2.246 0.000 tNET FF 1 R2C50[0][A] uut/u_fra_div/bi_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C50[0][A] uut/u_fra_div/bi_Z[5]/CLK
1.577 0.000 tUnc uut/u_fra_div/bi_Z[5]
1.588 0.011 tHld 1 R2C50[0][A] uut/u_fra_div/bi_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.456%; route: 0.124, 18.478%; tC2Q: 0.201, 30.066%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack 0.659
Data Arrival Time 2.248
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[15]
To uut/u_fra_div/divider_copy_Z[14]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C41[2][A] uut/u_fra_div/divider_copy_Z[15]/CLK
1.778 0.201 tC2Q RF 3 R24C41[2][A] uut/u_fra_div/divider_copy_Z[15]/Q
1.904 0.125 tNET FF 1 R24C41[2][B] uut/u_fra_div/divider_copy_6_cZ[14]/I1
2.248 0.344 tINS FF 1 R24C41[2][B] uut/u_fra_div/divider_copy_6_cZ[14]/F
2.248 0.000 tNET FF 1 R24C41[2][B] uut/u_fra_div/divider_copy_Z[14]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C41[2][B] uut/u_fra_div/divider_copy_Z[14]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[14]
1.588 0.011 tHld 1 R24C41[2][B] uut/u_fra_div/divider_copy_Z[14]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.330%; route: 0.125, 18.678%; tC2Q: 0.201, 29.992%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack 0.661
Data Arrival Time 2.249
Data Required Time 1.588
From uut/u_fra_div/bi_Z[2]
To uut/u_fra_div/bi_Z[2]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[1][B] uut/u_fra_div/bi_Z[2]/CLK
1.778 0.201 tC2Q RF 17 R2C49[1][B] uut/u_fra_div/bi_Z[2]/Q
1.905 0.127 tNET FF 2 R2C49[1][B] uut/u_fra_div/un1_bi_cry_2_0/I0
2.249 0.344 tINS FF 1 R2C49[1][B] uut/u_fra_div/un1_bi_cry_2_0/SUM
2.249 0.000 tNET FF 1 R2C49[1][B] uut/u_fra_div/bi_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C49[1][B] uut/u_fra_div/bi_Z[2]/CLK
1.577 0.000 tUnc uut/u_fra_div/bi_Z[2]
1.588 0.011 tHld 1 R2C49[1][B] uut/u_fra_div/bi_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 51.205%; route: 0.127, 18.876%; tC2Q: 0.201, 29.919%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack 0.665
Data Arrival Time 2.253
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[14]
To uut/u_fra_div/divider_copy_Z[13]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C41[2][B] uut/u_fra_div/divider_copy_Z[14]/CLK
1.778 0.201 tC2Q RF 3 R24C41[2][B] uut/u_fra_div/divider_copy_Z[14]/Q
1.909 0.131 tNET FF 1 R24C42[2][A] uut/u_fra_div/divider_copy_6_cZ[13]/I1
2.253 0.344 tINS FF 1 R24C42[2][A] uut/u_fra_div/divider_copy_6_cZ[13]/F
2.253 0.000 tNET FF 1 R24C42[2][A] uut/u_fra_div/divider_copy_Z[13]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C42[2][A] uut/u_fra_div/divider_copy_Z[13]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[13]
1.588 0.011 tHld 1 R24C42[2][A] uut/u_fra_div/divider_copy_Z[13]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.344, 50.903%; route: 0.131, 19.354%; tC2Q: 0.201, 29.743%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack 0.674
Data Arrival Time 2.263
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[17]
To uut/u_fra_div/divider_copy_Z[16]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C40[2][A] uut/u_fra_div/divider_copy_Z[17]/CLK
1.778 0.201 tC2Q RF 2 R24C40[2][A] uut/u_fra_div/divider_copy_Z[17]/Q
1.899 0.120 tNET FF 1 R24C40[2][B] uut/u_fra_div/divider_copy_6_cZ[16]/I1
2.263 0.364 tINS FF 1 R24C40[2][B] uut/u_fra_div/divider_copy_6_cZ[16]/F
2.263 0.000 tNET FF 1 R24C40[2][B] uut/u_fra_div/divider_copy_Z[16]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C40[2][B] uut/u_fra_div/divider_copy_Z[16]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[16]
1.588 0.011 tHld 1 R24C40[2][B] uut/u_fra_div/divider_copy_Z[16]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack 0.674
Data Arrival Time 2.263
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[11]
To uut/u_fra_div/divider_copy_Z[10]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C31[2][A] uut/u_fra_div/divider_copy_Z[11]/CLK
1.778 0.201 tC2Q RF 3 R24C31[2][A] uut/u_fra_div/divider_copy_Z[11]/Q
1.899 0.120 tNET FF 1 R24C31[2][B] uut/u_fra_div/divider_copy_6_cZ[10]/I1
2.263 0.364 tINS FF 1 R24C31[2][B] uut/u_fra_div/divider_copy_6_cZ[10]/F
2.263 0.000 tNET FF 1 R24C31[2][B] uut/u_fra_div/divider_copy_Z[10]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C31[2][B] uut/u_fra_div/divider_copy_Z[10]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[10]
1.588 0.011 tHld 1 R24C31[2][B] uut/u_fra_div/divider_copy_Z[10]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack 0.674
Data Arrival Time 2.263
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[1]
To uut/u_fra_div/divider_copy_Z[0]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C36[2][A] uut/u_fra_div/divider_copy_Z[1]/CLK
1.778 0.201 tC2Q RF 3 R24C36[2][A] uut/u_fra_div/divider_copy_Z[1]/Q
1.899 0.120 tNET FF 1 R24C36[2][B] uut/u_fra_div/divider_copy_6_cZ[0]/I1
2.263 0.364 tINS FF 1 R24C36[2][B] uut/u_fra_div/divider_copy_6_cZ[0]/F
2.263 0.000 tNET FF 1 R24C36[2][B] uut/u_fra_div/divider_copy_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C36[2][B] uut/u_fra_div/divider_copy_Z[0]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[0]
1.588 0.011 tHld 1 R24C36[2][B] uut/u_fra_div/divider_copy_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack 0.678
Data Arrival Time 2.266
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[13]
To uut/u_fra_div/divider_copy_Z[12]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C42[2][A] uut/u_fra_div/divider_copy_Z[13]/CLK
1.778 0.201 tC2Q RF 3 R24C42[2][A] uut/u_fra_div/divider_copy_Z[13]/Q
1.902 0.124 tNET FF 1 R24C42[2][B] uut/u_fra_div/divider_copy_6_cZ[12]/I1
2.266 0.364 tINS FF 1 R24C42[2][B] uut/u_fra_div/divider_copy_6_cZ[12]/F
2.266 0.000 tNET FF 1 R24C42[2][B] uut/u_fra_div/divider_copy_Z[12]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C42[2][B] uut/u_fra_div/divider_copy_Z[12]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[12]
1.588 0.011 tHld 1 R24C42[2][B] uut/u_fra_div/divider_copy_Z[12]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.364, 52.866%; route: 0.124, 17.941%; tC2Q: 0.201, 29.193%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack 0.678
Data Arrival Time 2.266
Data Required Time 1.588
From uut/u_fra_div/divider_copy_Z[9]
To uut/u_fra_div/divider_copy_Z[8]
Launch Clk DEFAULT_CLK:[R]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C32[2][A] uut/u_fra_div/divider_copy_Z[9]/CLK
1.778 0.201 tC2Q RF 3 R24C32[2][A] uut/u_fra_div/divider_copy_Z[9]/Q
1.902 0.124 tNET FF 1 R24C32[2][B] uut/u_fra_div/divider_copy_6_cZ[8]/I1
2.266 0.364 tINS FF 1 R24C32[2][B] uut/u_fra_div/divider_copy_6_cZ[8]/F
2.266 0.000 tNET FF 1 R24C32[2][B] uut/u_fra_div/divider_copy_Z[8]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R24C32[2][B] uut/u_fra_div/divider_copy_Z[8]/CLK
1.577 0.000 tUnc uut/u_fra_div/divider_copy_Z[8]
1.588 0.011 tHld 1 R24C32[2][B] uut/u_fra_div/divider_copy_Z[8]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay cell: 0.364, 52.866%; route: 0.124, 17.941%; tC2Q: 0.201, 29.193%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648 -0.035 tSu 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/trigger_seq_start_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z/CLK
11.683 -0.200 tUnc u_la0_top/trigger_seq_start_Z
11.648 -0.035 tSu 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648 -0.035 tSu 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648 -0.035 tSu 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648 -0.035 tSu 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648 -0.035 tSu 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648 -0.035 tSu 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 -0.035 tSu 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648 -0.035 tSu 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648 -0.035 tSu 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648 -0.035 tSu 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648 -0.035 tSu 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648 -0.035 tSu 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648 -0.035 tSu 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648 -0.035 tSu 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648 -0.035 tSu 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648 -0.035 tSu 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 -0.035 tSu 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648 -0.035 tSu 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648 -0.035 tSu 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683 -0.200 tUnc u_la0_top/genblk1.u_ao_match_0/match_sep
11.648 -0.035 tSu 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648 -0.035 tSu 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648 -0.035 tSu 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648 -0.035 tSu 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack 2.019
Data Arrival Time 9.629
Data Required Time 11.648
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.688 0.688 tINS FF 164 IOT48[A] clk_ibuf/O
6.916 1.228 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
7.148 0.232 tC2Q FF 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
9.629 2.482 tNET FF 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
10.682 0.683 tINS RR 164 IOT48[A] clk_ibuf/O
11.883 1.201 tNET RR 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648 -0.035 tSu 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew -0.033
Setup Relationship 5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.482, 91.451%; tC2Q: 0.232, 8.549%
Required Clock Path Delay cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788 0.011 tHld 1 R6C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
1.788 0.011 tHld 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788 0.011 tHld 1 R8C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788 0.011 tHld 1 R12C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788 0.011 tHld 1 R2C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788 0.011 tHld 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788 0.011 tHld 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788 0.011 tHld 1 R4C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788 0.011 tHld 1 R4C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788 0.011 tHld 1 R7C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788 0.011 tHld 1 R12C11[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788 0.011 tHld 1 R12C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788 0.011 tHld 1 R12C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788 0.011 tHld 1 R4C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788 0.011 tHld 1 R4C2[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788 0.011 tHld 1 R9C10[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788 0.011 tHld 1 R8C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788 0.011 tHld 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788 0.011 tHld 1 R9C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788 0.011 tHld 1 R9C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788 0.011 tHld 1 R9C10[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788 0.011 tHld 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788 0.011 tHld 1 R3C2[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
1.777 0.200 tUnc u_la0_top/genblk1.u_ao_match_0/match_sep
1.788 0.011 tHld 1 R2C6[0][B] u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack 6.611
Data Arrival Time 8.399
Data Required Time 1.788
From u_la0_top/rst_ao_Z
To u_la0_top/trigger_seq_start_Z
Launch Clk DEFAULT_CLK:[F]
Latch Clk DEFAULT_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF 1 IOT48[A] clk_ibuf/I
5.677 0.678 tINS FF 164 IOT48[A] clk_ibuf/O
6.590 0.913 tNET FF 1 R2C11[2][B] u_la0_top/rst_ao_Z/CLK
6.792 0.202 tC2Q FR 43 R2C11[2][B] u_la0_top/rst_ao_Z/Q
8.399 1.607 tNET RR 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 DEFAULT_CLK(clock)
0.000 0.000 tCL RR 1 IOT48[A] clk_ibuf/I
0.675 0.675 tINS RR 164 IOT48[A] clk_ibuf/O
1.577 0.902 tNET RR 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z/CLK
1.777 0.200 tUnc u_la0_top/trigger_seq_start_Z
1.788 0.011 tHld 1 R7C11[0][A] u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 0
Arrival Clock Path Delay cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.607, 88.832%; tC2Q: 0.202, 11.168%
Required Clock Path Delay cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/quotient[0]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/quotient[0]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/quotient[0]/CLK

MPW2

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/quotient[13]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/quotient[13]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/quotient[13]/CLK

MPW3

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/quotient[9]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/quotient[9]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/quotient[9]/CLK

MPW4

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/quotient[1]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/quotient[1]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/quotient[1]/CLK

MPW5

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/divider_copy_Z[9]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/divider_copy_Z[9]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/divider_copy_Z[9]/CLK

MPW6

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/dividend_copy_Z[14]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/dividend_copy_Z[14]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/dividend_copy_Z[14]/CLK

MPW7

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: u_la0_top/u_ao_mem_ctrl/data_reg_Z[5]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF u_la0_top/u_ao_mem_ctrl/data_reg_Z[5]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR u_la0_top/u_ao_mem_ctrl/data_reg_Z[5]/CLK

MPW8

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: u_la0_top/u_ao_mem_ctrl/data_reg_Z[6]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF u_la0_top/u_ao_mem_ctrl/data_reg_Z[6]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR u_la0_top/u_ao_mem_ctrl/data_reg_Z[6]/CLK

MPW9

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: uut/u_fra_div/dividend_copy_Z[13]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF uut/u_fra_div/dividend_copy_Z[13]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR uut/u_fra_div/dividend_copy_Z[13]/CLK

MPW10

MPW Summary:

Slack: 3.662
Actual Width: 4.662
Required Width: 1.000
Type: Low Pulse Width
Clock: DEFAULT_CLK
Objects: u_la0_top/u_ao_mem_ctrl/data_reg_Z[7]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 DEFAULT_CLK(clock)
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
6.916 1.228 tNET FF u_la0_top/u_ao_mem_ctrl/data_reg_Z[7]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 DEFAULT_CLK(clock)
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.577 0.902 tNET RR u_la0_top/u_ao_mem_ctrl/data_reg_Z[7]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
73 complete_c 6.316 2.012
68 clk_c 3.019 1.228
32 un1_dividend_copy_cry_27_0_RNIVNRF 3.019 1.294
29 N_239_i 6.547 1.102
17 bi[2] 6.325 1.791
8 quotient_5_0_a2_2[12] 6.159 1.163
8 done_0_sqmuxa_0_a2_2 5.683 1.316
7 N_271 7.963 1.097
6 bi[0] 6.199 1.484
6 bi[1] 6.394 1.481

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R9C53 0.292
R2C49 0.222
R24C53 0.222
R24C52 0.181
R24C61 0.181
R3C45 0.167
R3C46 0.167
R24C42 0.167
R24C45 0.167
R2C50 0.153

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command