#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
#install: D:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-042

# Fri Sep 28 15:23:56 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v" (library work)
@I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\define.v" (library work)
@I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\static_macro_define.v" (library work)
@I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\parameter.v" (library work)
@I::"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\qdiv.v" (library work)
Verilog syntax check successful!
Selecting top level module fra_div
Running optimization stage 1 on \(qdiv)/(fra_div)_16s_3s .......
@N:CG364 : div_wrap.v(3) | Synthesizing module fra_div in library work.
Running optimization stage 1 on fra_div .......
Running optimization stage 2 on fra_div .......
Running optimization stage 2 on \(qdiv)/(fra_div)_16s_3s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 28 15:23:57 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level
@N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 28 15:23:57 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 28 15:23:57 2018

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Database state : E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level
@N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 28 15:23:58 2018

###########################################################]


Premap Report



# Fri Sep 28 15:23:59 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  Fra_div_scck.rpt
Printing clock  summary report in "E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\rev_1\Fra_div_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

@N:MF974 :  | Total number of latches (multibit) processed = 0  
@N:MF975 :  | Total number of latches (bit blasted) processed = 0  
@N:MF976 :  | Total number of (multibit) opaque latches found = 0  
@N:MF977 :  | Total number of (bit blasted) opaque latches found = 0  

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)







Detailed report for transparent and observable latches in design:
Linked File:  Fra_div_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

syn_allowed_resources : blockrams=140  set on top level netlist fra_div

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start           Requested     Requested     Clock        Clock                     Clock
Level     Clock           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------
0 -       fra_div|clk     329.6 MHz     3.034         inferred     Autoconstr_clkgroup_0     68   
==================================================================================================



Clock Load Summary
***********************

                Clock     Source        Clock Pin             Non-clock Pin     Non-clock Pin
Clock           Load      Pin           Seq Example           Seq Example       Comb Example 
---------------------------------------------------------------------------------------------
fra_div|clk     68        clk(port)     u_fra_div.bi[0].C     -                 -            
=============================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 68 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 Unconstrained_port     68         ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\rev_1\Fra_div.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 192MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Sep 28 15:24:01 2018

###########################################################]


Map & Optimize Report



# Fri Sep 28 15:24:02 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: D:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-042

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "0000000000000000" on instance u_fra_div.dividend_copy[15:0]. 
@N:FX493 :  | Applying initial value "00000000000000000000000000000" on instance u_fra_div.divider_copy[28:0]. 
@N:FX493 :  | Applying initial value "1" on instance u_fra_div.done. 
@N:FX493 :  | Applying initial value "0000000000000000" on instance u_fra_div.quotient[15:0]. 
@N:FX493 :  | Applying initial value "010001" on instance u_fra_div.bi[5:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.95ns		 161 /        68
   2		0h:00m:01s		    -1.95ns		 161 /        68
   3		0h:00m:01s		    -1.44ns		 161 /        68

   4		0h:00m:01s		    -1.44ns		 160 /        68


   5		0h:00m:01s		    -1.44ns		 160 /        68

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 192MB)

Writing Analyst data base E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\rev_1\synwork\Fra_div_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 192MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 192MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

@W:MT420 :  | Found inferred clock fra_div|clk with period 4.06ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Sep 28 15:24:06 2018
#


Top view:               fra_div
Requested Frequency:    246.4 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.716

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
fra_div|clk        246.4 MHz     209.4 MHz     4.059         4.775         -0.716     inferred     Autoconstr_clkgroup_0
System             150.0 MHz     312.1 MHz     6.667         3.204         3.463      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------
System       fra_div|clk  |  4.059       3.463   |  No paths    -      |  No paths    -      |  No paths    -    
fra_div|clk  System       |  4.059       -0.180  |  No paths    -      |  No paths    -      |  No paths    -    
fra_div|clk  fra_div|clk  |  4.059       -0.716  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: fra_div|clk
====================================



Starting Points with Worst Slack
********************************

                               Starting                                              Arrival           
Instance                       Reference       Type     Pin     Net                  Time        Slack 
                               Clock                                                                   
-------------------------------------------------------------------------------------------------------
u_fra_div.dividend_copy[0]     fra_div|clk     DFFE     Q       dividend_copy[0]     0.243       -0.716
u_fra_div.divider_copy[0]      fra_div|clk     DFFE     Q       divider_copy[0]      0.243       -0.695
u_fra_div.dividend_copy[1]     fra_div|clk     DFFE     Q       dividend_copy[1]     0.243       -0.681
u_fra_div.divider_copy[1]      fra_div|clk     DFFE     Q       divider_copy[1]      0.243       -0.660
u_fra_div.dividend_copy[2]     fra_div|clk     DFFE     Q       dividend_copy[2]     0.243       -0.646
u_fra_div.divider_copy[2]      fra_div|clk     DFFE     Q       divider_copy[2]      0.243       -0.625
u_fra_div.dividend_copy[3]     fra_div|clk     DFFE     Q       dividend_copy[3]     0.243       -0.611
u_fra_div.divider_copy[3]      fra_div|clk     DFFE     Q       divider_copy[3]      0.243       -0.590
u_fra_div.dividend_copy[4]     fra_div|clk     DFFE     Q       dividend_copy[4]     0.243       -0.576
u_fra_div.divider_copy[4]      fra_div|clk     DFFE     Q       divider_copy[4]      0.243       -0.555
=======================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                            Required           
Instance                       Reference       Type     Pin     Net                Time         Slack 
                               Clock                                                                  
------------------------------------------------------------------------------------------------------
u_fra_div.quotient[15]         fra_div|clk     DFF      D       quotient_1[15]     3.998        -0.716
u_fra_div.dividend_copy[0]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[1]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[2]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[3]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[4]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[5]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[6]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[7]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
u_fra_div.dividend_copy[8]     fra_div|clk     DFFE     CE      un1_done9_i_0      3.998        -0.345
======================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      4.714
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.716

    Number of logic level(s):                30
    Starting point:                          u_fra_div.dividend_copy[0] / Q
    Ending point:                            u_fra_div.quotient[15] / D
    The start point is clocked by            fra_div|clk [rising] on pin CLK
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u_fra_div.dividend_copy[0]                       DFFE     Q        Out     0.243     0.243       -         
dividend_copy[0]                                 Net      -        -       0.535     -           2         
u_fra_div.un1_dividend_copy_cry_0_0              ALU      I1       In      -         0.778       -         
u_fra_div.un1_dividend_copy_cry_0_0              ALU      COUT     Out     0.570     1.348       -         
un1_dividend_copy_cry_0                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      CIN      In      -         1.348       -         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      COUT     Out     0.035     1.383       -         
un1_dividend_copy_cry_1                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      CIN      In      -         1.383       -         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      COUT     Out     0.035     1.418       -         
un1_dividend_copy_cry_2                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      CIN      In      -         1.418       -         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      COUT     Out     0.035     1.453       -         
un1_dividend_copy_cry_3                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      CIN      In      -         1.453       -         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      COUT     Out     0.035     1.488       -         
un1_dividend_copy_cry_4                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      CIN      In      -         1.488       -         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      COUT     Out     0.035     1.523       -         
un1_dividend_copy_cry_5                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      CIN      In      -         1.523       -         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      COUT     Out     0.035     1.558       -         
un1_dividend_copy_cry_6                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      CIN      In      -         1.558       -         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      COUT     Out     0.035     1.593       -         
un1_dividend_copy_cry_7                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      CIN      In      -         1.593       -         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      COUT     Out     0.035     1.628       -         
un1_dividend_copy_cry_8                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      CIN      In      -         1.628       -         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      COUT     Out     0.035     1.663       -         
un1_dividend_copy_cry_9                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      CIN      In      -         1.663       -         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      COUT     Out     0.035     1.698       -         
un1_dividend_copy_cry_10                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      CIN      In      -         1.698       -         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      COUT     Out     0.035     1.733       -         
un1_dividend_copy_cry_11                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      CIN      In      -         1.733       -         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      COUT     Out     0.035     1.768       -         
un1_dividend_copy_cry_12                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      CIN      In      -         1.768       -         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      COUT     Out     0.035     1.803       -         
un1_dividend_copy_cry_13                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      CIN      In      -         1.803       -         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      COUT     Out     0.035     1.838       -         
un1_dividend_copy_cry_14                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      CIN      In      -         1.838       -         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      COUT     Out     0.035     1.873       -         
un1_dividend_copy_cry_15                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      CIN      In      -         1.873       -         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      COUT     Out     0.035     1.908       -         
un1_dividend_copy_cry_16                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      CIN      In      -         1.908       -         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      COUT     Out     0.035     1.943       -         
un1_dividend_copy_cry_17                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      CIN      In      -         1.943       -         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      COUT     Out     0.035     1.978       -         
un1_dividend_copy_cry_18                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      CIN      In      -         1.978       -         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      COUT     Out     0.035     2.013       -         
un1_dividend_copy_cry_19                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      CIN      In      -         2.013       -         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      COUT     Out     0.035     2.048       -         
un1_dividend_copy_cry_20                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      CIN      In      -         2.048       -         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      COUT     Out     0.035     2.083       -         
un1_dividend_copy_cry_21                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      CIN      In      -         2.083       -         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      COUT     Out     0.035     2.118       -         
un1_dividend_copy_cry_22                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      CIN      In      -         2.118       -         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      COUT     Out     0.035     2.153       -         
un1_dividend_copy_cry_23                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      CIN      In      -         2.153       -         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      COUT     Out     0.035     2.188       -         
un1_dividend_copy_cry_24                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      CIN      In      -         2.188       -         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      COUT     Out     0.035     2.223       -         
un1_dividend_copy_cry_25                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      CIN      In      -         2.223       -         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      COUT     Out     0.035     2.258       -         
un1_dividend_copy_cry_26                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      CIN      In      -         2.258       -         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      COUT     Out     0.035     2.293       -         
un1_dividend_copy_cry_27                         Net      -        -       0.961     -           1         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     I3       In      -         3.254       -         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     F        Out     0.371     3.625       -         
un1_done9_i_0                                    Net      -        -       0.718     -           32        
u_fra_div.quotient_1[15]                         LUT4     I3       In      -         4.343       -         
u_fra_div.quotient_1[15]                         LUT4     F        Out     0.371     4.714       -         
quotient_1[15]                                   Net      -        -       0.000     -           1         
u_fra_div.quotient[15]                           DFF      D        In      -         4.714       -         
===========================================================================================================
Total path delay (propagation time + setup) of 4.775 is 2.561(53.6%) logic and 2.214(46.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      4.693
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.695

    Number of logic level(s):                30
    Starting point:                          u_fra_div.divider_copy[0] / Q
    Ending point:                            u_fra_div.quotient[15] / D
    The start point is clocked by            fra_div|clk [rising] on pin CLK
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u_fra_div.divider_copy[0]                        DFFE     Q        Out     0.243     0.243       -         
divider_copy[0]                                  Net      -        -       0.535     -           2         
u_fra_div.un1_dividend_copy_cry_0_0              ALU      I0       In      -         0.778       -         
u_fra_div.un1_dividend_copy_cry_0_0              ALU      COUT     Out     0.549     1.327       -         
un1_dividend_copy_cry_0                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      CIN      In      -         1.327       -         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      COUT     Out     0.035     1.362       -         
un1_dividend_copy_cry_1                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      CIN      In      -         1.362       -         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      COUT     Out     0.035     1.397       -         
un1_dividend_copy_cry_2                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      CIN      In      -         1.397       -         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      COUT     Out     0.035     1.432       -         
un1_dividend_copy_cry_3                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      CIN      In      -         1.432       -         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      COUT     Out     0.035     1.467       -         
un1_dividend_copy_cry_4                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      CIN      In      -         1.467       -         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      COUT     Out     0.035     1.502       -         
un1_dividend_copy_cry_5                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      CIN      In      -         1.502       -         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      COUT     Out     0.035     1.537       -         
un1_dividend_copy_cry_6                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      CIN      In      -         1.537       -         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      COUT     Out     0.035     1.572       -         
un1_dividend_copy_cry_7                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      CIN      In      -         1.572       -         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      COUT     Out     0.035     1.607       -         
un1_dividend_copy_cry_8                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      CIN      In      -         1.607       -         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      COUT     Out     0.035     1.642       -         
un1_dividend_copy_cry_9                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      CIN      In      -         1.642       -         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      COUT     Out     0.035     1.677       -         
un1_dividend_copy_cry_10                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      CIN      In      -         1.677       -         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      COUT     Out     0.035     1.712       -         
un1_dividend_copy_cry_11                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      CIN      In      -         1.712       -         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      COUT     Out     0.035     1.747       -         
un1_dividend_copy_cry_12                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      CIN      In      -         1.747       -         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      COUT     Out     0.035     1.782       -         
un1_dividend_copy_cry_13                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      CIN      In      -         1.782       -         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      COUT     Out     0.035     1.817       -         
un1_dividend_copy_cry_14                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      CIN      In      -         1.817       -         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      COUT     Out     0.035     1.852       -         
un1_dividend_copy_cry_15                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      CIN      In      -         1.852       -         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      COUT     Out     0.035     1.887       -         
un1_dividend_copy_cry_16                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      CIN      In      -         1.887       -         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      COUT     Out     0.035     1.922       -         
un1_dividend_copy_cry_17                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      CIN      In      -         1.922       -         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      COUT     Out     0.035     1.957       -         
un1_dividend_copy_cry_18                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      CIN      In      -         1.957       -         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      COUT     Out     0.035     1.992       -         
un1_dividend_copy_cry_19                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      CIN      In      -         1.992       -         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      COUT     Out     0.035     2.027       -         
un1_dividend_copy_cry_20                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      CIN      In      -         2.027       -         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      COUT     Out     0.035     2.062       -         
un1_dividend_copy_cry_21                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      CIN      In      -         2.062       -         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      COUT     Out     0.035     2.097       -         
un1_dividend_copy_cry_22                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      CIN      In      -         2.097       -         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      COUT     Out     0.035     2.132       -         
un1_dividend_copy_cry_23                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      CIN      In      -         2.132       -         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      COUT     Out     0.035     2.167       -         
un1_dividend_copy_cry_24                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      CIN      In      -         2.167       -         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      COUT     Out     0.035     2.202       -         
un1_dividend_copy_cry_25                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      CIN      In      -         2.202       -         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      COUT     Out     0.035     2.237       -         
un1_dividend_copy_cry_26                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      CIN      In      -         2.237       -         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      COUT     Out     0.035     2.272       -         
un1_dividend_copy_cry_27                         Net      -        -       0.961     -           1         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     I3       In      -         3.233       -         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     F        Out     0.371     3.604       -         
un1_done9_i_0                                    Net      -        -       0.718     -           32        
u_fra_div.quotient_1[15]                         LUT4     I3       In      -         4.322       -         
u_fra_div.quotient_1[15]                         LUT4     F        Out     0.371     4.693       -         
quotient_1[15]                                   Net      -        -       0.000     -           1         
u_fra_div.quotient[15]                           DFF      D        In      -         4.693       -         
===========================================================================================================
Total path delay (propagation time + setup) of 4.754 is 2.540(53.4%) logic and 2.214(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      4.679
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.681

    Number of logic level(s):                29
    Starting point:                          u_fra_div.dividend_copy[1] / Q
    Ending point:                            u_fra_div.quotient[15] / D
    The start point is clocked by            fra_div|clk [rising] on pin CLK
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u_fra_div.dividend_copy[1]                       DFFE     Q        Out     0.243     0.243       -         
dividend_copy[1]                                 Net      -        -       0.535     -           2         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      I1       In      -         0.778       -         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      COUT     Out     0.570     1.348       -         
un1_dividend_copy_cry_1                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      CIN      In      -         1.348       -         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      COUT     Out     0.035     1.383       -         
un1_dividend_copy_cry_2                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      CIN      In      -         1.383       -         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      COUT     Out     0.035     1.418       -         
un1_dividend_copy_cry_3                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      CIN      In      -         1.418       -         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      COUT     Out     0.035     1.453       -         
un1_dividend_copy_cry_4                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      CIN      In      -         1.453       -         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      COUT     Out     0.035     1.488       -         
un1_dividend_copy_cry_5                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      CIN      In      -         1.488       -         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      COUT     Out     0.035     1.523       -         
un1_dividend_copy_cry_6                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      CIN      In      -         1.523       -         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      COUT     Out     0.035     1.558       -         
un1_dividend_copy_cry_7                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      CIN      In      -         1.558       -         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      COUT     Out     0.035     1.593       -         
un1_dividend_copy_cry_8                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      CIN      In      -         1.593       -         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      COUT     Out     0.035     1.628       -         
un1_dividend_copy_cry_9                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      CIN      In      -         1.628       -         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      COUT     Out     0.035     1.663       -         
un1_dividend_copy_cry_10                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      CIN      In      -         1.663       -         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      COUT     Out     0.035     1.698       -         
un1_dividend_copy_cry_11                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      CIN      In      -         1.698       -         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      COUT     Out     0.035     1.733       -         
un1_dividend_copy_cry_12                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      CIN      In      -         1.733       -         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      COUT     Out     0.035     1.768       -         
un1_dividend_copy_cry_13                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      CIN      In      -         1.768       -         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      COUT     Out     0.035     1.803       -         
un1_dividend_copy_cry_14                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      CIN      In      -         1.803       -         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      COUT     Out     0.035     1.838       -         
un1_dividend_copy_cry_15                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      CIN      In      -         1.838       -         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      COUT     Out     0.035     1.873       -         
un1_dividend_copy_cry_16                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      CIN      In      -         1.873       -         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      COUT     Out     0.035     1.908       -         
un1_dividend_copy_cry_17                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      CIN      In      -         1.908       -         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      COUT     Out     0.035     1.943       -         
un1_dividend_copy_cry_18                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      CIN      In      -         1.943       -         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      COUT     Out     0.035     1.978       -         
un1_dividend_copy_cry_19                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      CIN      In      -         1.978       -         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      COUT     Out     0.035     2.013       -         
un1_dividend_copy_cry_20                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      CIN      In      -         2.013       -         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      COUT     Out     0.035     2.048       -         
un1_dividend_copy_cry_21                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      CIN      In      -         2.048       -         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      COUT     Out     0.035     2.083       -         
un1_dividend_copy_cry_22                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      CIN      In      -         2.083       -         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      COUT     Out     0.035     2.118       -         
un1_dividend_copy_cry_23                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      CIN      In      -         2.118       -         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      COUT     Out     0.035     2.153       -         
un1_dividend_copy_cry_24                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      CIN      In      -         2.153       -         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      COUT     Out     0.035     2.188       -         
un1_dividend_copy_cry_25                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      CIN      In      -         2.188       -         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      COUT     Out     0.035     2.223       -         
un1_dividend_copy_cry_26                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      CIN      In      -         2.223       -         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      COUT     Out     0.035     2.258       -         
un1_dividend_copy_cry_27                         Net      -        -       0.961     -           1         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     I3       In      -         3.219       -         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     F        Out     0.371     3.590       -         
un1_done9_i_0                                    Net      -        -       0.718     -           32        
u_fra_div.quotient_1[15]                         LUT4     I3       In      -         4.308       -         
u_fra_div.quotient_1[15]                         LUT4     F        Out     0.371     4.679       -         
quotient_1[15]                                   Net      -        -       0.000     -           1         
u_fra_div.quotient[15]                           DFF      D        In      -         4.679       -         
===========================================================================================================
Total path delay (propagation time + setup) of 4.740 is 2.526(53.3%) logic and 2.214(46.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      4.658
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.660

    Number of logic level(s):                29
    Starting point:                          u_fra_div.divider_copy[1] / Q
    Ending point:                            u_fra_div.quotient[15] / D
    The start point is clocked by            fra_div|clk [rising] on pin CLK
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u_fra_div.divider_copy[1]                        DFFE     Q        Out     0.243     0.243       -         
divider_copy[1]                                  Net      -        -       0.535     -           3         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      I0       In      -         0.778       -         
u_fra_div.un1_dividend_copy_cry_1_0              ALU      COUT     Out     0.549     1.327       -         
un1_dividend_copy_cry_1                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      CIN      In      -         1.327       -         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      COUT     Out     0.035     1.362       -         
un1_dividend_copy_cry_2                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      CIN      In      -         1.362       -         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      COUT     Out     0.035     1.397       -         
un1_dividend_copy_cry_3                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      CIN      In      -         1.397       -         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      COUT     Out     0.035     1.432       -         
un1_dividend_copy_cry_4                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      CIN      In      -         1.432       -         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      COUT     Out     0.035     1.467       -         
un1_dividend_copy_cry_5                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      CIN      In      -         1.467       -         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      COUT     Out     0.035     1.502       -         
un1_dividend_copy_cry_6                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      CIN      In      -         1.502       -         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      COUT     Out     0.035     1.537       -         
un1_dividend_copy_cry_7                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      CIN      In      -         1.537       -         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      COUT     Out     0.035     1.572       -         
un1_dividend_copy_cry_8                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      CIN      In      -         1.572       -         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      COUT     Out     0.035     1.607       -         
un1_dividend_copy_cry_9                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      CIN      In      -         1.607       -         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      COUT     Out     0.035     1.642       -         
un1_dividend_copy_cry_10                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      CIN      In      -         1.642       -         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      COUT     Out     0.035     1.677       -         
un1_dividend_copy_cry_11                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      CIN      In      -         1.677       -         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      COUT     Out     0.035     1.712       -         
un1_dividend_copy_cry_12                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      CIN      In      -         1.712       -         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      COUT     Out     0.035     1.747       -         
un1_dividend_copy_cry_13                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      CIN      In      -         1.747       -         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      COUT     Out     0.035     1.782       -         
un1_dividend_copy_cry_14                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      CIN      In      -         1.782       -         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      COUT     Out     0.035     1.817       -         
un1_dividend_copy_cry_15                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      CIN      In      -         1.817       -         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      COUT     Out     0.035     1.852       -         
un1_dividend_copy_cry_16                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      CIN      In      -         1.852       -         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      COUT     Out     0.035     1.887       -         
un1_dividend_copy_cry_17                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      CIN      In      -         1.887       -         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      COUT     Out     0.035     1.922       -         
un1_dividend_copy_cry_18                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      CIN      In      -         1.922       -         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      COUT     Out     0.035     1.957       -         
un1_dividend_copy_cry_19                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      CIN      In      -         1.957       -         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      COUT     Out     0.035     1.992       -         
un1_dividend_copy_cry_20                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      CIN      In      -         1.992       -         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      COUT     Out     0.035     2.027       -         
un1_dividend_copy_cry_21                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      CIN      In      -         2.027       -         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      COUT     Out     0.035     2.062       -         
un1_dividend_copy_cry_22                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      CIN      In      -         2.062       -         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      COUT     Out     0.035     2.097       -         
un1_dividend_copy_cry_23                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      CIN      In      -         2.097       -         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      COUT     Out     0.035     2.132       -         
un1_dividend_copy_cry_24                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      CIN      In      -         2.132       -         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      COUT     Out     0.035     2.167       -         
un1_dividend_copy_cry_25                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      CIN      In      -         2.167       -         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      COUT     Out     0.035     2.202       -         
un1_dividend_copy_cry_26                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      CIN      In      -         2.202       -         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      COUT     Out     0.035     2.237       -         
un1_dividend_copy_cry_27                         Net      -        -       0.961     -           1         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     I3       In      -         3.198       -         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     F        Out     0.371     3.569       -         
un1_done9_i_0                                    Net      -        -       0.718     -           32        
u_fra_div.quotient_1[15]                         LUT4     I3       In      -         4.287       -         
u_fra_div.quotient_1[15]                         LUT4     F        Out     0.371     4.658       -         
quotient_1[15]                                   Net      -        -       0.000     -           1         
u_fra_div.quotient[15]                           DFF      D        In      -         4.658       -         
===========================================================================================================
Total path delay (propagation time + setup) of 4.719 is 2.505(53.1%) logic and 2.214(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      4.644
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.646

    Number of logic level(s):                28
    Starting point:                          u_fra_div.dividend_copy[2] / Q
    Ending point:                            u_fra_div.quotient[15] / D
    The start point is clocked by            fra_div|clk [rising] on pin CLK
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u_fra_div.dividend_copy[2]                       DFFE     Q        Out     0.243     0.243       -         
dividend_copy[2]                                 Net      -        -       0.535     -           2         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      I1       In      -         0.778       -         
u_fra_div.un1_dividend_copy_cry_2_0              ALU      COUT     Out     0.570     1.348       -         
un1_dividend_copy_cry_2                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      CIN      In      -         1.348       -         
u_fra_div.un1_dividend_copy_cry_3_0              ALU      COUT     Out     0.035     1.383       -         
un1_dividend_copy_cry_3                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      CIN      In      -         1.383       -         
u_fra_div.un1_dividend_copy_cry_4_0              ALU      COUT     Out     0.035     1.418       -         
un1_dividend_copy_cry_4                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      CIN      In      -         1.418       -         
u_fra_div.un1_dividend_copy_cry_5_0              ALU      COUT     Out     0.035     1.453       -         
un1_dividend_copy_cry_5                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      CIN      In      -         1.453       -         
u_fra_div.un1_dividend_copy_cry_6_0              ALU      COUT     Out     0.035     1.488       -         
un1_dividend_copy_cry_6                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      CIN      In      -         1.488       -         
u_fra_div.un1_dividend_copy_cry_7_0              ALU      COUT     Out     0.035     1.523       -         
un1_dividend_copy_cry_7                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      CIN      In      -         1.523       -         
u_fra_div.un1_dividend_copy_cry_8_0              ALU      COUT     Out     0.035     1.558       -         
un1_dividend_copy_cry_8                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      CIN      In      -         1.558       -         
u_fra_div.un1_dividend_copy_cry_9_0              ALU      COUT     Out     0.035     1.593       -         
un1_dividend_copy_cry_9                          Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      CIN      In      -         1.593       -         
u_fra_div.un1_dividend_copy_cry_10_0             ALU      COUT     Out     0.035     1.628       -         
un1_dividend_copy_cry_10                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      CIN      In      -         1.628       -         
u_fra_div.un1_dividend_copy_cry_11_0             ALU      COUT     Out     0.035     1.663       -         
un1_dividend_copy_cry_11                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      CIN      In      -         1.663       -         
u_fra_div.un1_dividend_copy_cry_12_0             ALU      COUT     Out     0.035     1.698       -         
un1_dividend_copy_cry_12                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      CIN      In      -         1.698       -         
u_fra_div.un1_dividend_copy_cry_13_0             ALU      COUT     Out     0.035     1.733       -         
un1_dividend_copy_cry_13                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      CIN      In      -         1.733       -         
u_fra_div.un1_dividend_copy_cry_14_0             ALU      COUT     Out     0.035     1.768       -         
un1_dividend_copy_cry_14                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      CIN      In      -         1.768       -         
u_fra_div.un1_dividend_copy_cry_15_0             ALU      COUT     Out     0.035     1.803       -         
un1_dividend_copy_cry_15                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      CIN      In      -         1.803       -         
u_fra_div.un1_dividend_copy_cry_16_0             ALU      COUT     Out     0.035     1.838       -         
un1_dividend_copy_cry_16                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      CIN      In      -         1.838       -         
u_fra_div.un1_dividend_copy_cry_17_0             ALU      COUT     Out     0.035     1.873       -         
un1_dividend_copy_cry_17                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      CIN      In      -         1.873       -         
u_fra_div.un1_dividend_copy_cry_18_0             ALU      COUT     Out     0.035     1.908       -         
un1_dividend_copy_cry_18                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      CIN      In      -         1.908       -         
u_fra_div.un1_dividend_copy_cry_19_0             ALU      COUT     Out     0.035     1.943       -         
un1_dividend_copy_cry_19                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      CIN      In      -         1.943       -         
u_fra_div.un1_dividend_copy_cry_20_0             ALU      COUT     Out     0.035     1.978       -         
un1_dividend_copy_cry_20                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      CIN      In      -         1.978       -         
u_fra_div.un1_dividend_copy_cry_21_0             ALU      COUT     Out     0.035     2.013       -         
un1_dividend_copy_cry_21                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      CIN      In      -         2.013       -         
u_fra_div.un1_dividend_copy_cry_22_0             ALU      COUT     Out     0.035     2.048       -         
un1_dividend_copy_cry_22                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      CIN      In      -         2.048       -         
u_fra_div.un1_dividend_copy_cry_23_0             ALU      COUT     Out     0.035     2.083       -         
un1_dividend_copy_cry_23                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      CIN      In      -         2.083       -         
u_fra_div.un1_dividend_copy_cry_24_0             ALU      COUT     Out     0.035     2.118       -         
un1_dividend_copy_cry_24                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      CIN      In      -         2.118       -         
u_fra_div.un1_dividend_copy_cry_25_0             ALU      COUT     Out     0.035     2.153       -         
un1_dividend_copy_cry_25                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      CIN      In      -         2.153       -         
u_fra_div.un1_dividend_copy_cry_26_0             ALU      COUT     Out     0.035     2.188       -         
un1_dividend_copy_cry_26                         Net      -        -       0.000     -           1         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      CIN      In      -         2.188       -         
u_fra_div.un1_dividend_copy_cry_27_0             ALU      COUT     Out     0.035     2.223       -         
un1_dividend_copy_cry_27                         Net      -        -       0.961     -           1         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     I3       In      -         3.184       -         
u_fra_div.un1_dividend_copy_cry_27_0_RNIVNRF     LUT4     F        Out     0.371     3.555       -         
un1_done9_i_0                                    Net      -        -       0.718     -           32        
u_fra_div.quotient_1[15]                         LUT4     I3       In      -         4.273       -         
u_fra_div.quotient_1[15]                         LUT4     F        Out     0.371     4.644       -         
quotient_1[15]                                   Net      -        -       0.000     -           1         
u_fra_div.quotient[15]                           DFF      D        In      -         4.644       -         
===========================================================================================================
Total path delay (propagation time + setup) of 4.705 is 2.491(52.9%) logic and 2.214(47.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                              Starting                                  Arrival          
Instance                      Reference     Type     Pin     Net        Time        Slack
                              Clock                                                      
-----------------------------------------------------------------------------------------
u_fra_div.quotient_RNO[0]     System        INV      O       N_39_0     0.000       3.463
=========================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                   Required          
Instance                  Reference     Type      Pin     Net        Time         Slack
                          Clock                                                        
---------------------------------------------------------------------------------------
u_fra_div.quotient[0]     System        DFFRE     D       N_39_0     3.998        3.463
=======================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.059
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.998

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.463

    Number of logic level(s):                0
    Starting point:                          u_fra_div.quotient_RNO[0] / O
    Ending point:                            u_fra_div.quotient[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            fra_div|clk [rising] on pin CLK

Instance / Net                          Pin      Pin               Arrival     No. of    
Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
u_fra_div.quotient_RNO[0]     INV       O        Out     0.000     0.000       -         
N_39_0                        Net       -        -       0.535     -           1         
u_fra_div.quotient[0]         DFFRE     D        In      -         0.535       -         
=========================================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

---------------------------------------
Resource Usage Report for fra_div 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             50 uses
DFF             1 use
DFFE            45 uses
DFFR            4 uses
DFFRE           15 uses
DFFS            3 uses
GSR             1 use
INV             1 use
LUT2            37 uses
LUT3            32 uses
LUT4            20 uses

I/O Register bits:                  0
Register bits not including I/Os:   68 of 41040 (0%)
Total load per clock:
   fra_div|clk: 68

@S |Mapping Summary:
Total  LUTs: 89 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 192MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Fri Sep 28 15:24:06 2018

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