#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: D:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-042 # Fri Sep 28 15:23:56 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v" (library work) @I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\define.v" (library work) @I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\static_macro_define.v" (library work) @I:"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_16\project\src\Fra_div\temp\Divider\parameter.v" (library work) @I::"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\qdiv.v" (library work) Verilog syntax check successful! Selecting top level module fra_div Running optimization stage 1 on \(qdiv)/(fra_div)_16s_3s ....... @N:CG364 : div_wrap.v(3) | Synthesizing module fra_div in library work. Running optimization stage 1 on fra_div ....... Running optimization stage 2 on fra_div ....... Running optimization stage 2 on \(qdiv)/(fra_div)_16s_3s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 15:23:57 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level @N:NF107 : div_wrap.v(3) | Selected library: work cell: fra_div view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 15:23:57 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 15:23:57 2018 ###########################################################]