Timing Messages
Report Title | Gowin Timing Analysis Report |
Tool Version | v1.8.1.01Beta |
Series, Device, Package, Speed, Operating Conditions | GW2A, GW2A-55, PBGA484, 8, COMMERCIAL |
Design Name | top |
Design File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\impl\synthesize\rev_1\DIVIDER_WIDTH_31.vm |
Timing Constraint File | --- |
Timing Report File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\impl\pnr\DIVIDER_WIDTH_31.tr.html |
Created Time | Fri Sep 28 15:40:34 2018 |
Command Line | D:\Gowin\1.8\Pnr\bin\gowin.exe -do E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\impl\pnr\cmd.do |
Legal Announcement | Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C |
Hold Delay Model | Fast 1.05V 0C |
Numbers of Paths Analyzed | 826 |
Numbers of Endpoints Analyzed | 2217 |
Numbers of Falling Endpoints | 1 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 132.938(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
2 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
3 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_end_dly_Z/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
4 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
5 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
6 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
7 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
8 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
9 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
10 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
11 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
12 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
13 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
14 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
15 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
16 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
17 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
18 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
19 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
20 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
21 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
22 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
23 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
24 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
25 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.425 | uut/u_fra_div/quotient[6]/Q | uut/u_fra_div/quotient[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436 |
2 | 0.427 | uut/u_fra_div/done_1/Q | uut/u_fra_div/done_1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
3 | 0.427 | uut/u_fra_div/quotient[16]/Q | uut/u_fra_div/quotient[16]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
4 | 0.427 | uut/u_fra_div/quotient[24]/Q | uut/u_fra_div/quotient[24]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
5 | 0.427 | uut/u_fra_div/quotient[2]/Q | uut/u_fra_div/quotient[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
6 | 0.427 | uut/u_fra_div/quotient[8]/Q | uut/u_fra_div/quotient[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
7 | 0.427 | uut/u_fra_div/quotient[0]/Q | uut/u_fra_div/quotient[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
8 | 0.427 | uut/u_fra_div/quotient[26]/Q | uut/u_fra_div/quotient[26]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
9 | 0.427 | uut/u_fra_div/quotient[12]/Q | uut/u_fra_div/quotient[12]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
10 | 0.427 | uut/u_fra_div/quotient[14]/Q | uut/u_fra_div/quotient[14]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438 |
11 | 0.485 | uut/u_fra_div/done_1_rep1/Q | uut/u_fra_div/done_1_rep1/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496 |
12 | 0.485 | uut/u_fra_div/quotient[3]/Q | uut/u_fra_div/quotient[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496 |
13 | 0.485 | uut/u_fra_div/quotient[4]/Q | uut/u_fra_div/quotient[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496 |
14 | 0.485 | uut/u_fra_div/quotient[22]/Q | uut/u_fra_div/quotient[22]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496 |
15 | 0.539 | uut/u_fra_div/quotient[10]/Q | uut/u_fra_div/quotient[10]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
16 | 0.539 | uut/u_fra_div/quotient[20]/Q | uut/u_fra_div/quotient[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
17 | 0.539 | uut/u_fra_div/quotient[23]/Q | uut/u_fra_div/quotient[23]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
18 | 0.539 | uut/u_fra_div/quotient[11]/Q | uut/u_fra_div/quotient[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
19 | 0.539 | uut/u_fra_div/quotient[5]/Q | uut/u_fra_div/quotient[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
20 | 0.539 | uut/u_fra_div/quotient[28]/Q | uut/u_fra_div/quotient[28]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
21 | 0.539 | uut/u_fra_div/quotient[29]/Q | uut/u_fra_div/quotient[29]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.550 |
22 | 0.542 | uut/u_fra_div/divider_copy_Z[56]/Q | uut/u_fra_div/divider_copy_Z[55]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.553 |
23 | 0.544 | uut/u_fra_div/bi_Z[4]/Q | uut/u_fra_div/bi_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.555 |
24 | 0.546 | uut/u_fra_div/divider_copy_Z[40]/Q | uut/u_fra_div/divider_copy_Z[39]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.557 |
25 | 0.546 | uut/u_fra_div/divider_copy_Z[38]/Q | uut/u_fra_div/divider_copy_Z[37]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.557 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
2 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
3 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
4 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
5 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
6 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
7 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
8 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
9 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
10 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
11 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
12 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
13 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_end_dly_Z/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
14 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
15 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
16 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
17 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
18 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
19 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
20 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
21 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
22 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
23 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
24 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
25 | 1.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.984 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
2 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
3 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
4 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
5 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
6 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
7 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
8 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
9 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
10 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
11 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
12 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
13 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
14 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
15 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
16 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
17 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
18 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
19 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
20 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
21 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
22 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
23 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
24 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
25 | 6.760 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.958 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/quotient[29] |
2 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/quotient[27] |
3 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/quotient[23] |
4 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/quotient[15] |
5 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/bi_Z[5] |
6 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/divider_copy_Z[26] |
7 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/done_1 |
8 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | u_la0_top/u_ao_mem_ctrl/data_reg_Z[90] |
9 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | u_la0_top/u_ao_mem_ctrl/data_reg_Z[91] |
10 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_fra_div/dividend_copy_Z[1] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path2
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path3
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_end_dly_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_end_dly_Z | |||
11.648 | -0.035 | tSu | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path4
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
11.648 | -0.035 | tSu | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path5
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] | |||
11.648 | -0.035 | tSu | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path6
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path7
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
11.648 | -0.035 | tSu | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path8
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path9
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
11.648 | -0.035 | tSu | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path10
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path11
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_window_sel_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R13C11[0][B] | u_la0_top/capture_window_sel_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R13C11[0][B] | u_la0_top/capture_window_sel_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R13C11[0][B] | u_la0_top/capture_window_sel_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path12
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/internal_reg_start_dly_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C11[2][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C11[2][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/internal_reg_start_dly_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R12C11[2][B] | u_la0_top/internal_reg_start_dly_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path13
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] | |||
11.648 | -0.035 | tSu | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path14
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path15
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/internal_reg_force_triger_syn_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C12[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C12[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/internal_reg_force_triger_syn_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R3C12[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path16
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path17
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path18
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/internal_reg_force_triger_syn_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/internal_reg_force_triger_syn_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path19
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] | |||
11.648 | -0.035 | tSu | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path20
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_window_sel[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_window_sel[3] | |||
11.648 | -0.035 | tSu | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path21
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/genblk1.u_ao_match_0/match_sep |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
11.683 | -0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
11.648 | -0.035 | tSu | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path22
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path23
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] | |||
11.648 | -0.035 | tSu | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path24
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path25
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] | |||
11.648 | -0.035 | tSu | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.014 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[6] |
To | uut/u_fra_div/quotient[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C67[0][A] | uut/u_fra_div/quotient[6]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C67[0][A] | uut/u_fra_div/quotient[6]/Q |
1.782 | 0.002 | tNET | RR | 1 | R22C67[0][A] | uut/u_fra_div/quotient_5[6]/I1 |
2.014 | 0.232 | tINS | RF | 1 | R22C67[0][A] | uut/u_fra_div/quotient_5[6]/F |
2.014 | 0.000 | tNET | FF | 1 | R22C67[0][A] | uut/u_fra_div/quotient[6]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C67[0][A] | uut/u_fra_div/quotient[6]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[6] | |||
1.588 | 0.011 | tHld | 1 | R22C67[0][A] | uut/u_fra_div/quotient[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path2
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/done_1 |
To | uut/u_fra_div/done_1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C54[1][A] | uut/u_fra_div/done_1/CLK |
1.779 | 0.202 | tC2Q | RR | 40 | R22C54[1][A] | uut/u_fra_div/done_1/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C54[1][A] | uut/u_fra_div/done_1_1_cZ/I0 |
2.015 | 0.232 | tINS | RF | 1 | R22C54[1][A] | uut/u_fra_div/done_1_1_cZ/F |
2.015 | 0.000 | tNET | FF | 1 | R22C54[1][A] | uut/u_fra_div/done_1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C54[1][A] | uut/u_fra_div/done_1/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/done_1 | |||
1.588 | 0.011 | tHld | 1 | R22C54[1][A] | uut/u_fra_div/done_1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path3
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[16] |
To | uut/u_fra_div/quotient[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C65[1][A] | uut/u_fra_div/quotient[16]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C65[1][A] | uut/u_fra_div/quotient[16]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C65[1][A] | uut/u_fra_div/quotient_5[16]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C65[1][A] | uut/u_fra_div/quotient_5[16]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C65[1][A] | uut/u_fra_div/quotient[16]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C65[1][A] | uut/u_fra_div/quotient[16]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[16] | |||
1.588 | 0.011 | tHld | 1 | R22C65[1][A] | uut/u_fra_div/quotient[16] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path4
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[24] |
To | uut/u_fra_div/quotient[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C59[1][A] | uut/u_fra_div/quotient[24]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C59[1][A] | uut/u_fra_div/quotient[24]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C59[1][A] | uut/u_fra_div/quotient_5[24]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C59[1][A] | uut/u_fra_div/quotient_5[24]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C59[1][A] | uut/u_fra_div/quotient[24]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C59[1][A] | uut/u_fra_div/quotient[24]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[24] | |||
1.588 | 0.011 | tHld | 1 | R22C59[1][A] | uut/u_fra_div/quotient[24] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path5
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[2] |
To | uut/u_fra_div/quotient[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[1][A] | uut/u_fra_div/quotient[2]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C56[1][A] | uut/u_fra_div/quotient[2]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C56[1][A] | uut/u_fra_div/quotient_5[2]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C56[1][A] | uut/u_fra_div/quotient_5[2]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C56[1][A] | uut/u_fra_div/quotient[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[1][A] | uut/u_fra_div/quotient[2]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[2] | |||
1.588 | 0.011 | tHld | 1 | R22C56[1][A] | uut/u_fra_div/quotient[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path6
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[8] |
To | uut/u_fra_div/quotient[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C67[1][A] | uut/u_fra_div/quotient[8]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C67[1][A] | uut/u_fra_div/quotient[8]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C67[1][A] | uut/u_fra_div/quotient_5[8]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C67[1][A] | uut/u_fra_div/quotient_5[8]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C67[1][A] | uut/u_fra_div/quotient[8]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C67[1][A] | uut/u_fra_div/quotient[8]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[8] | |||
1.588 | 0.011 | tHld | 1 | R22C67[1][A] | uut/u_fra_div/quotient[8] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path7
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[0] |
To | uut/u_fra_div/quotient[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C57[1][A] | uut/u_fra_div/quotient[0]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C57[1][A] | uut/u_fra_div/quotient[0]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C57[1][A] | uut/u_fra_div/quotient_5[0]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C57[1][A] | uut/u_fra_div/quotient_5[0]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C57[1][A] | uut/u_fra_div/quotient[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C57[1][A] | uut/u_fra_div/quotient[0]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[0] | |||
1.588 | 0.011 | tHld | 1 | R22C57[1][A] | uut/u_fra_div/quotient[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path8
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[26] |
To | uut/u_fra_div/quotient[26] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C60[1][A] | uut/u_fra_div/quotient[26]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C60[1][A] | uut/u_fra_div/quotient[26]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C60[1][A] | uut/u_fra_div/quotient_5[26]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C60[1][A] | uut/u_fra_div/quotient_5[26]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C60[1][A] | uut/u_fra_div/quotient[26]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C60[1][A] | uut/u_fra_div/quotient[26]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[26] | |||
1.588 | 0.011 | tHld | 1 | R22C60[1][A] | uut/u_fra_div/quotient[26] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path9
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[12] |
To | uut/u_fra_div/quotient[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C66[0][A] | uut/u_fra_div/quotient[12]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C66[0][A] | uut/u_fra_div/quotient[12]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C66[0][A] | uut/u_fra_div/quotient_5[12]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C66[0][A] | uut/u_fra_div/quotient_5[12]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C66[0][A] | uut/u_fra_div/quotient[12]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C66[0][A] | uut/u_fra_div/quotient[12]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[12] | |||
1.588 | 0.011 | tHld | 1 | R22C66[0][A] | uut/u_fra_div/quotient[12] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path10
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.015 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[14] |
To | uut/u_fra_div/quotient[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C66[1][A] | uut/u_fra_div/quotient[14]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C66[1][A] | uut/u_fra_div/quotient[14]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C66[1][A] | uut/u_fra_div/quotient_5[14]/I1 |
2.015 | 0.232 | tINS | RF | 1 | R22C66[1][A] | uut/u_fra_div/quotient_5[14]/F |
2.015 | 0.000 | tNET | FF | 1 | R22C66[1][A] | uut/u_fra_div/quotient[14]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C66[1][A] | uut/u_fra_div/quotient[14]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[14] | |||
1.588 | 0.011 | tHld | 1 | R22C66[1][A] | uut/u_fra_div/quotient[14] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path11
Path Summary:
Slack | 0.485 |
Data Arrival Time | 2.073 |
Data Required Time | 1.588 |
From | uut/u_fra_div/done_1_rep1 |
To | uut/u_fra_div/done_1_rep1 |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C54[2][A] | uut/u_fra_div/done_1_rep1/CLK |
1.779 | 0.202 | tC2Q | RR | 35 | R22C54[2][A] | uut/u_fra_div/done_1_rep1/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C54[2][A] | uut/u_fra_div/done_1_1_rep1/I2 |
2.073 | 0.290 | tINS | RF | 1 | R22C54[2][A] | uut/u_fra_div/done_1_1_rep1/F |
2.073 | 0.000 | tNET | FF | 1 | R22C54[2][A] | uut/u_fra_div/done_1_rep1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C54[2][A] | uut/u_fra_div/done_1_rep1/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/done_1_rep1 | |||
1.588 | 0.011 | tHld | 1 | R22C54[2][A] | uut/u_fra_div/done_1_rep1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path12
Path Summary:
Slack | 0.485 |
Data Arrival Time | 2.073 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[3] |
To | uut/u_fra_div/quotient[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C57[2][A] | uut/u_fra_div/quotient[3]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C57[2][A] | uut/u_fra_div/quotient[3]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C57[2][A] | uut/u_fra_div/quotient_5[3]/I1 |
2.073 | 0.290 | tINS | RF | 1 | R22C57[2][A] | uut/u_fra_div/quotient_5[3]/F |
2.073 | 0.000 | tNET | FF | 1 | R22C57[2][A] | uut/u_fra_div/quotient[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C57[2][A] | uut/u_fra_div/quotient[3]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[3] | |||
1.588 | 0.011 | tHld | 1 | R22C57[2][A] | uut/u_fra_div/quotient[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path13
Path Summary:
Slack | 0.485 |
Data Arrival Time | 2.073 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[4] |
To | uut/u_fra_div/quotient[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[2][A] | uut/u_fra_div/quotient[4]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C56[2][A] | uut/u_fra_div/quotient[4]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C56[2][A] | uut/u_fra_div/quotient_5[4]/I1 |
2.073 | 0.290 | tINS | RF | 1 | R22C56[2][A] | uut/u_fra_div/quotient_5[4]/F |
2.073 | 0.000 | tNET | FF | 1 | R22C56[2][A] | uut/u_fra_div/quotient[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[2][A] | uut/u_fra_div/quotient[4]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[4] | |||
1.588 | 0.011 | tHld | 1 | R22C56[2][A] | uut/u_fra_div/quotient[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path14
Path Summary:
Slack | 0.485 |
Data Arrival Time | 2.073 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[22] |
To | uut/u_fra_div/quotient[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C60[2][A] | uut/u_fra_div/quotient[22]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R23C60[2][A] | uut/u_fra_div/quotient[22]/Q |
1.783 | 0.004 | tNET | RR | 1 | R23C60[2][A] | uut/u_fra_div/quotient_5[22]/I1 |
2.073 | 0.290 | tINS | RF | 1 | R23C60[2][A] | uut/u_fra_div/quotient_5[22]/F |
2.073 | 0.000 | tNET | FF | 1 | R23C60[2][A] | uut/u_fra_div/quotient[22]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C60[2][A] | uut/u_fra_div/quotient[22]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[22] | |||
1.588 | 0.011 | tHld | 1 | R23C60[2][A] | uut/u_fra_div/quotient[22] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path15
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[10] |
To | uut/u_fra_div/quotient[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C67[2][B] | uut/u_fra_div/quotient[10]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R23C67[2][B] | uut/u_fra_div/quotient[10]/Q |
1.783 | 0.004 | tNET | RR | 1 | R23C67[2][B] | uut/u_fra_div/quotient_5[10]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R23C67[2][B] | uut/u_fra_div/quotient_5[10]/F |
2.127 | 0.000 | tNET | FF | 1 | R23C67[2][B] | uut/u_fra_div/quotient[10]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C67[2][B] | uut/u_fra_div/quotient[10]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[10] | |||
1.588 | 0.011 | tHld | 1 | R23C67[2][B] | uut/u_fra_div/quotient[10] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path16
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[20] |
To | uut/u_fra_div/quotient[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C61[2][B] | uut/u_fra_div/quotient[20]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R23C61[2][B] | uut/u_fra_div/quotient[20]/Q |
1.783 | 0.004 | tNET | RR | 1 | R23C61[2][B] | uut/u_fra_div/quotient_5[20]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R23C61[2][B] | uut/u_fra_div/quotient_5[20]/F |
2.127 | 0.000 | tNET | FF | 1 | R23C61[2][B] | uut/u_fra_div/quotient[20]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C61[2][B] | uut/u_fra_div/quotient[20]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[20] | |||
1.588 | 0.011 | tHld | 1 | R23C61[2][B] | uut/u_fra_div/quotient[20] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path17
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[23] |
To | uut/u_fra_div/quotient[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C60[2][B] | uut/u_fra_div/quotient[23]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R23C60[2][B] | uut/u_fra_div/quotient[23]/Q |
1.783 | 0.004 | tNET | RR | 1 | R23C60[2][B] | uut/u_fra_div/quotient_5[23]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R23C60[2][B] | uut/u_fra_div/quotient_5[23]/F |
2.127 | 0.000 | tNET | FF | 1 | R23C60[2][B] | uut/u_fra_div/quotient[23]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C60[2][B] | uut/u_fra_div/quotient[23]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[23] | |||
1.588 | 0.011 | tHld | 1 | R23C60[2][B] | uut/u_fra_div/quotient[23] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path18
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[11] |
To | uut/u_fra_div/quotient[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C66[2][B] | uut/u_fra_div/quotient[11]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R23C66[2][B] | uut/u_fra_div/quotient[11]/Q |
1.783 | 0.004 | tNET | RR | 1 | R23C66[2][B] | uut/u_fra_div/quotient_5[11]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R23C66[2][B] | uut/u_fra_div/quotient_5[11]/F |
2.127 | 0.000 | tNET | FF | 1 | R23C66[2][B] | uut/u_fra_div/quotient[11]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R23C66[2][B] | uut/u_fra_div/quotient[11]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[11] | |||
1.588 | 0.011 | tHld | 1 | R23C66[2][B] | uut/u_fra_div/quotient[11] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path19
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[5] |
To | uut/u_fra_div/quotient[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[2][B] | uut/u_fra_div/quotient[5]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C56[2][B] | uut/u_fra_div/quotient[5]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C56[2][B] | uut/u_fra_div/quotient_5[5]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R22C56[2][B] | uut/u_fra_div/quotient_5[5]/F |
2.127 | 0.000 | tNET | FF | 1 | R22C56[2][B] | uut/u_fra_div/quotient[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C56[2][B] | uut/u_fra_div/quotient[5]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[5] | |||
1.588 | 0.011 | tHld | 1 | R22C56[2][B] | uut/u_fra_div/quotient[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path20
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[28] |
To | uut/u_fra_div/quotient[28] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C61[2][B] | uut/u_fra_div/quotient[28]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C61[2][B] | uut/u_fra_div/quotient[28]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C61[2][B] | uut/u_fra_div/quotient_5[28]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R22C61[2][B] | uut/u_fra_div/quotient_5[28]/F |
2.127 | 0.000 | tNET | FF | 1 | R22C61[2][B] | uut/u_fra_div/quotient[28]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C61[2][B] | uut/u_fra_div/quotient[28]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[28] | |||
1.588 | 0.011 | tHld | 1 | R22C61[2][B] | uut/u_fra_div/quotient[28] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path21
Path Summary:
Slack | 0.539 |
Data Arrival Time | 2.127 |
Data Required Time | 1.588 |
From | uut/u_fra_div/quotient[29] |
To | uut/u_fra_div/quotient[29] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C60[2][B] | uut/u_fra_div/quotient[29]/CLK |
1.779 | 0.202 | tC2Q | RR | 4 | R22C60[2][B] | uut/u_fra_div/quotient[29]/Q |
1.783 | 0.004 | tNET | RR | 1 | R22C60[2][B] | uut/u_fra_div/quotient_5[29]/I1 |
2.127 | 0.344 | tINS | RF | 1 | R22C60[2][B] | uut/u_fra_div/quotient_5[29]/F |
2.127 | 0.000 | tNET | FF | 1 | R22C60[2][B] | uut/u_fra_div/quotient[29]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C60[2][B] | uut/u_fra_div/quotient[29]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/quotient[29] | |||
1.588 | 0.011 | tHld | 1 | R22C60[2][B] | uut/u_fra_div/quotient[29] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path22
Path Summary:
Slack | 0.542 |
Data Arrival Time | 2.131 |
Data Required Time | 1.588 |
From | uut/u_fra_div/divider_copy_Z[56] |
To | uut/u_fra_div/divider_copy_Z[55] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C24[1][B] | uut/u_fra_div/divider_copy_Z[56]/CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R22C24[1][B] | uut/u_fra_div/divider_copy_Z[56]/Q |
1.899 | 0.120 | tNET | FF | 1 | R22C24[0][B] | uut/u_fra_div/divider_copy_6_cZ[55]/I1 |
2.131 | 0.232 | tINS | FF | 1 | R22C24[0][B] | uut/u_fra_div/divider_copy_6_cZ[55]/F |
2.131 | 0.000 | tNET | FF | 1 | R22C24[0][B] | uut/u_fra_div/divider_copy_Z[55]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C24[0][B] | uut/u_fra_div/divider_copy_Z[55]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/divider_copy_Z[55] | |||
1.588 | 0.011 | tHld | 1 | R22C24[0][B] | uut/u_fra_div/divider_copy_Z[55] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path23
Path Summary:
Slack | 0.544 |
Data Arrival Time | 2.132 |
Data Required Time | 1.588 |
From | uut/u_fra_div/bi_Z[4] |
To | uut/u_fra_div/bi_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C63[2][B] | uut/u_fra_div/bi_Z[4]/CLK |
1.779 | 0.202 | tC2Q | RR | 19 | R22C63[2][B] | uut/u_fra_div/bi_Z[4]/Q |
1.788 | 0.009 | tNET | RR | 2 | R22C63[2][B] | uut/u_fra_div/un1_bi_cry_4_0/I0 |
2.132 | 0.344 | tINS | RF | 1 | R22C63[2][B] | uut/u_fra_div/un1_bi_cry_4_0/SUM |
2.132 | 0.000 | tNET | FF | 1 | R22C63[2][B] | uut/u_fra_div/bi_Z[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C63[2][B] | uut/u_fra_div/bi_Z[4]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/bi_Z[4] | |||
1.588 | 0.011 | tHld | 1 | R22C63[2][B] | uut/u_fra_div/bi_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.344, 62.032%; route: 0.009, 1.543%; tC2Q: 0.202, 36.426% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path24
Path Summary:
Slack | 0.546 |
Data Arrival Time | 2.134 |
Data Required Time | 1.588 |
From | uut/u_fra_div/divider_copy_Z[40] |
To | uut/u_fra_div/divider_copy_Z[39] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C26[1][B] | uut/u_fra_div/divider_copy_Z[40]/CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R22C26[1][B] | uut/u_fra_div/divider_copy_Z[40]/Q |
1.902 | 0.124 | tNET | FF | 1 | R22C26[0][A] | uut/u_fra_div/divider_copy_6_cZ[39]/I1 |
2.134 | 0.232 | tINS | FF | 1 | R22C26[0][A] | uut/u_fra_div/divider_copy_6_cZ[39]/F |
2.134 | 0.000 | tNET | FF | 1 | R22C26[0][A] | uut/u_fra_div/divider_copy_Z[39]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C26[0][A] | uut/u_fra_div/divider_copy_Z[39]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/divider_copy_Z[39] | |||
1.588 | 0.011 | tHld | 1 | R22C26[0][A] | uut/u_fra_div/divider_copy_Z[39] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path25
Path Summary:
Slack | 0.546 |
Data Arrival Time | 2.134 |
Data Required Time | 1.588 |
From | uut/u_fra_div/divider_copy_Z[38] |
To | uut/u_fra_div/divider_copy_Z[37] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C27[1][B] | uut/u_fra_div/divider_copy_Z[38]/CLK |
1.778 | 0.201 | tC2Q | RF | 2 | R22C27[1][B] | uut/u_fra_div/divider_copy_Z[38]/Q |
1.902 | 0.124 | tNET | FF | 1 | R22C27[1][A] | uut/u_fra_div/divider_copy_6_cZ[37]/I1 |
2.134 | 0.232 | tINS | FF | 1 | R22C27[1][A] | uut/u_fra_div/divider_copy_6_cZ[37]/F |
2.134 | 0.000 | tNET | FF | 1 | R22C27[1][A] | uut/u_fra_div/divider_copy_Z[37]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R22C27[1][A] | uut/u_fra_div/divider_copy_Z[37]/CLK |
1.577 | 0.000 | tUnc | uut/u_fra_div/divider_copy_Z[37] | |||
1.588 | 0.011 | tHld | 1 | R22C27[1][A] | uut/u_fra_div/divider_copy_Z[37] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R12C10[0][B] | u_la0_top/triger_level_cnt_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path2
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/internal_reg_force_triger_syn_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/internal_reg_force_triger_syn_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R9C11[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path3
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_window_sel[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_window_sel[3] | |||
11.648 | -0.035 | tSu | 1 | R13C11[0][A] | u_la0_top/capture_window_sel[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path4
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] | |||
11.648 | -0.035 | tSu | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path5
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/genblk1.u_ao_match_0/match_sep |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
11.683 | -0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
11.648 | -0.035 | tSu | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path6
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path7
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] | |||
11.648 | -0.035 | tSu | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path8
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
11.648 | -0.035 | tSu | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path9
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
11.648 | -0.035 | tSu | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path10
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_window_sel_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R13C11[1][A] | u_la0_top/capture_window_sel_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R13C11[1][A] | u_la0_top/capture_window_sel_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R13C11[1][A] | u_la0_top/capture_window_sel_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path11
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] | |||
11.648 | -0.035 | tSu | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path12
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
11.648 | -0.035 | tSu | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path13
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_end_dly_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_end_dly_Z | |||
11.648 | -0.035 | tSu | 1 | R3C12[2][A] | u_la0_top/capture_end_dly_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path14
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[3] | |||
11.648 | -0.035 | tSu | 1 | R2C7[0][A] | u_la0_top/triger_level_cnt_Z[3] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path15
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R12C10[1][A] | u_la0_top/triger_level_cnt_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path16
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] | |||
11.648 | -0.035 | tSu | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path17
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/trigger_seq_start_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/trigger_seq_start_Z | |||
11.648 | -0.035 | tSu | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path18
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] | |||
11.648 | -0.035 | tSu | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path19
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] | |||
11.648 | -0.035 | tSu | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path20
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] | |||
11.648 | -0.035 | tSu | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path21
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/triger_level_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R2C4[0][A] | u_la0_top/triger_level_cnt_Z[2] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path22
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
11.648 | -0.035 | tSu | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path23
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path24
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/capture_window_sel_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R12C10[0][A] | u_la0_top/capture_window_sel_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R12C10[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK |
11.683 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[2] | |||
11.648 | -0.035 | tSu | 1 | R12C10[0][A] | u_la0_top/capture_window_sel_Z[2] |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Path25
Path Summary:
Slack | 1.748 |
Data Arrival Time | 9.900 |
Data Required Time | 11.648 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
7.148 | 0.232 | tC2Q | FF | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
9.900 | 2.752 | tNET | FF | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
11.883 | 1.201 | tNET | RR | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK |
11.683 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_loop_Z | |||
11.648 | -0.035 | tSu | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
1.788 | 0.011 | tHld | 1 | R3C5[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path2
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z | |||
1.788 | 0.011 | tHld | 1 | R2C4[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path3
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_loop_Z | |||
1.788 | 0.011 | tHld | 1 | R2C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path4
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] | |||
1.788 | 0.011 | tHld | 1 | R12C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path5
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
1.788 | 0.011 | tHld | 1 | R9C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path6
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
1.788 | 0.011 | tHld | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path7
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] | |||
1.788 | 0.011 | tHld | 1 | R3C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path8
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] | |||
1.788 | 0.011 | tHld | 1 | R3C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path9
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] | |||
1.788 | 0.011 | tHld | 1 | R2C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path10
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] | |||
1.788 | 0.011 | tHld | 1 | R4C12[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path11
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] | |||
1.788 | 0.011 | tHld | 1 | R3C12[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path12
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R12C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R12C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] | |||
1.788 | 0.011 | tHld | 1 | R12C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path13
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] | |||
1.788 | 0.011 | tHld | 1 | R12C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path14
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] | |||
1.788 | 0.011 | tHld | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path15
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] | |||
1.788 | 0.011 | tHld | 1 | R11C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path16
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] | |||
1.788 | 0.011 | tHld | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path17
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] | |||
1.788 | 0.011 | tHld | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path18
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] | |||
1.788 | 0.011 | tHld | 1 | R7C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path19
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] | |||
1.788 | 0.011 | tHld | 1 | R7C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path20
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
1.788 | 0.011 | tHld | 1 | R7C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path21
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
1.788 | 0.011 | tHld | 1 | R7C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path22
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] | |||
1.788 | 0.011 | tHld | 1 | R11C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path23
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK |
1.777 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] | |||
1.788 | 0.011 | tHld | 1 | R11C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path24
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/genblk1.u_ao_match_0/match_sep |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
1.777 | 0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
1.788 | 0.011 | tHld | 1 | R12C10[1][B] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Path25
Path Summary:
Slack | 6.760 |
Data Arrival Time | 8.548 |
Data Required Time | 1.788 |
From | u_la0_top/rst_ao_Z |
To | u_la0_top/trigger_seq_start_Z |
Launch Clk | DEFAULT_CLK:[F] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||||
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 275 | IOT48[A] | clk_ibuf/O |
6.590 | 0.913 | tNET | FF | 1 | R7C11[0][B] | u_la0_top/rst_ao_Z/CLK |
6.792 | 0.202 | tC2Q | FR | 43 | R7C11[0][B] | u_la0_top/rst_ao_Z/Q |
8.548 | 1.756 | tNET | RR | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 275 | IOT48[A] | clk_ibuf/O |
1.577 | 0.902 | tNET | RR | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z/CLK |
1.777 | 0.200 | tUnc | u_la0_top/trigger_seq_start_Z | |||
1.788 | 0.011 | tHld | 1 | R9C11[2][A] | u_la0_top/trigger_seq_start_Z |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | -5.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/quotient[29] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/quotient[29]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/quotient[29]/CLK |
MPW2
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/quotient[27] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/quotient[27]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/quotient[27]/CLK |
MPW3
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/quotient[23] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/quotient[23]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/quotient[23]/CLK |
MPW4
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/quotient[15] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/quotient[15]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/quotient[15]/CLK |
MPW5
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/bi_Z[5] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/bi_Z[5]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/bi_Z[5]/CLK |
MPW6
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/divider_copy_Z[26] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/divider_copy_Z[26]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/divider_copy_Z[26]/CLK |
MPW7
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/done_1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/done_1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/done_1/CLK |
MPW8
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[90] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]/CLK |
MPW9
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[91] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]/CLK |
MPW10
MPW Summary:
Slack: | 3.662 |
Actual Width: | 4.662 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | uut/u_fra_div/dividend_copy_Z[1] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
6.916 | 1.228 | tNET | FF | uut/u_fra_div/dividend_copy_Z[1]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.577 | 0.902 | tNET | RR | uut/u_fra_div/dividend_copy_Z[1]/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
131 | clk_c | 2.478 | 1.228 |
61 | un1_dividend_copy_cry_0_RNI5EK11[57] | 2.478 | 2.270 |
59 | un1_done7_cZ | 6.087 | 3.113 |
41 | done_rep2 | 7.659 | 1.304 |
39 | complete_c | 6.979 | 1.984 |
35 | done_rep1 | 7.112 | 1.889 |
34 | quotient_0_sqmuxa | 7.095 | 1.675 |
30 | bi[0] | 5.728 | 1.046 |
29 | bi[1] | 6.285 | 1.027 |
27 | bi[2] | 6.279 | 0.940 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R22C63 | 0.528 |
R22C52 | 0.389 |
R22C65 | 0.389 |
R22C64 | 0.375 |
R22C56 | 0.361 |
R22C41 | 0.333 |
R22C49 | 0.333 |
R22C50 | 0.319 |
R22C54 | 0.306 |
R22C61 | 0.306 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|