Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:02s - 2018/9/28
15:40:00
(premap)Complete 14 0 0 0m:01s 0m:02s 194MB 2018/9/28
15:40:04
(fpga_mapper)Complete 11 2 0 0m:07s 0m:08s 222MB 2018/9/28
15:40:12
Multi-srs Generator Complete2018/9/28
15:40:01

Area Summary
I/O ports (io_port) 108 Non I/O Register bits (non_io_reg) 531 (1%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 6 (140)
Block Multipliers (dsp_used) 0 (20) LUTs (total_luts) 467 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i221.0 MHz187.8 MHz-0.799
ao_top_0|control[0]184.9 MHz157.1 MHz-0.955
System150.0 MHz233.5 MHz2.384

Optimizations Summary
Combined Clock Conversion 2 / 0