Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\DVI_RX\data\dvi_rx_top.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\DVI_RX\data\dvi2rgb.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-6 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Tue Oct 24 09:48:39 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DVI_RX_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.319s, Peak memory usage = 35.746MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.746MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 35.746MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 35.746MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 35.746MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.746MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.746MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 35.746MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 35.746MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 35.746MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 35.746MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 35.746MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 51.449MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 51.449MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 51.449MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 51.449MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 42 |
I/O Buf | 38 |
    IBUF | 1 |
    OBUF | 33 |
    TLVDS_IBUF | 4 |
Register | 329 |
    DFF | 1 |
    DFFR | 2 |
    DFFRE | 11 |
    DFFC | 201 |
    DFFCE | 114 |
LUT | 631 |
    LUT2 | 62 |
    LUT3 | 202 |
    LUT4 | 367 |
ALU | 18 |
    ALU | 18 |
SSRAM | 1 |
    RAM16S4 | 1 |
INV | 3 |
    INV | 3 |
IOLOGIC | 6 |
    IDES10 | 3 |
    IODELAY | 3 |
CLOCK | 2 |
    CLKDIV | 1 |
    rPLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 658(634 LUT, 18 ALU, 1 RAM16) / 20736 | 4% |
Register | 329 / 16509 | 2% |
  --Register as Latch | 0 / 16509 | 0% |
  --Register as FF | 329 / 16509 | 2% |
BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_tmds_clk_p | Base | 13.468 | 74.3 | 0.000 | 6.734 | dvi2rgb_inst/u_HDMI_CK/I | ||
dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.3 | 0.000 | 1.347 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUT |
dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.3 | 0.000 | 1.347 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTP |
dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk | Generated | 13.468 | 74.3 | 0.000 | 6.734 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTD |
dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.7 | 0.000 | 4.040 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTD3 |
dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | Generated | 13.468 | 74.3 | 0.000 | 6.734 | dvi2rgb_inst/rPLL_inst/CLKOUTP | dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | dvi2rgb_inst/u_clkdiv5/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_tmds_clk_p | 74.3(MHz) | 357.1(MHz) | 4 | TOP |
2 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | 74.3(MHz) | 193.2(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 8.173 |
Data Arrival Time | 5.576 |
Data Required Time | 13.749 |
From | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0 |
To | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
Launch Clk | I_tmds_clk_p[R] |
Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_tmds_clk_p | |||
0.000 | 0.000 | tCL | RR | 1 | dvi2rgb_inst/u_HDMI_CK/I |
0.683 | 0.683 | tINS | RR | 16 | dvi2rgb_inst/u_HDMI_CK/O |
0.863 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s4/I1 |
1.887 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s4/F |
2.124 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s3/F |
2.878 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s5/I1 |
3.433 | 0.555 | tINS | FF | 13 | dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s5/F |
3.670 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s44/I3 |
4.041 | 0.371 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s44/F |
4.278 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s37/I2 |
4.731 | 0.453 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s37/F |
4.968 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s33/I3 |
5.339 | 0.371 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s33/F |
5.576 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
13.639 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.819 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/CLK |
13.784 | -0.035 | tUnc | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 | ||
13.749 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
Clock Skew: | -0.512 |
Setup Relationship: | 13.468 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.822, 59.876%; route: 1.659, 35.201%; tC2Q: 0.232, 4.923% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 8.292 |
Data Arrival Time | 5.491 |
Data Required Time | 13.784 |
From | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0 |
To | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0 |
Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 10 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I1 |
1.375 | 0.555 | tINS | FF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
1.612 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/I1 |
2.167 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/F |
2.404 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/I1 |
2.959 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/F |
3.196 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/I0 |
3.713 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/F |
3.950 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I1 |
4.504 | 0.555 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
4.741 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
5.312 | 0.570 | tINS | FR | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
5.491 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
13.639 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.819 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0/CLK |
13.784 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.307, 64.326%; route: 1.602, 31.161%; tC2Q: 0.232, 4.513% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:Slack | 8.292 |
Data Arrival Time | 5.491 |
Data Required Time | 13.784 |
From | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0 |
To | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0 |
Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 10 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I1 |
1.375 | 0.555 | tINS | FF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
1.612 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/I1 |
2.167 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/F |
2.404 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/I1 |
2.959 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/F |
3.196 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/I0 |
3.713 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/F |
3.950 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I1 |
4.504 | 0.555 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
4.741 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
5.312 | 0.570 | tINS | FR | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
5.491 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
13.639 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.819 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0/CLK |
13.784 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.307, 64.326%; route: 1.602, 31.161%; tC2Q: 0.232, 4.513% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:Slack | 8.292 |
Data Arrival Time | 5.491 |
Data Required Time | 13.784 |
From | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0 |
To | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0 |
Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 10 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I1 |
1.375 | 0.555 | tINS | FF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
1.612 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/I1 |
2.167 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/F |
2.404 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/I1 |
2.959 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/F |
3.196 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/I0 |
3.713 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/F |
3.950 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I1 |
4.504 | 0.555 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
4.741 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
5.312 | 0.570 | tINS | FR | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
5.491 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
13.639 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.819 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0/CLK |
13.784 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.307, 64.326%; route: 1.602, 31.161%; tC2Q: 0.232, 4.513% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:Slack | 8.292 |
Data Arrival Time | 5.491 |
Data Required Time | 13.784 |
From | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0 |
To | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0 |
Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 10 | dvi2rgb_inst/u_Data_Aligning_Auto/B_align_9_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I1 |
1.375 | 0.555 | tINS | FF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
1.612 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/I1 |
2.167 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s59/F |
2.404 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/I1 |
2.959 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s45/F |
3.196 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/I0 |
3.713 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n853_s38/F |
3.950 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I1 |
4.504 | 0.555 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
4.741 | 0.237 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
5.312 | 0.570 | tINS | FR | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
5.491 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
13.639 | 0.170 | tCL | RR | 319 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.819 | 0.180 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0/CLK |
13.784 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 3.307, 64.326%; route: 1.602, 31.161%; tC2Q: 0.232, 4.513% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |