Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_RX_RefDesign\project\impl\gwsynthesis\dk_video.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_RX_RefDesign\project\src\dk_video.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_RX_RefDesign\project\src\dk_video.sdc |
Version | V1.9.9 Beta-6 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Mon Oct 30 11:25:12 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 1402 |
Numbers of Endpoints Analyzed | 1258 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
I_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | I_clk | ||
I_tmds_clk_p | Base | 13.468 | 74.250 | 0.000 | 6.734 | I_tmds_clk_p | ||
rx0_pclk | Base | 13.468 | 74.250 | 0.000 | 6.734 | rx0_pclk | ||
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk | Generated | 13.468 | 74.250 | 0.000 | 6.734 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.750 | 0.000 | 4.040 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT | rx0_pclk | DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUT |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT | rx0_pclk | DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTP |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.387 | 185.625 | 0.000 | 2.694 | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT | rx0_pclk | DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.750 | 0.000 | 4.040 | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT | rx0_pclk | DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_clk | 50.000(MHz) | 202.579(MHz) | 2 | TOP |
2 | I_tmds_clk_p | 74.250(MHz) | 330.890(MHz) | 4 | TOP |
3 | rx0_pclk | 74.250(MHz) | 126.512(MHz) | 10 | TOP |
No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
I_clk | Setup | 0.000 | 0 |
I_clk | Hold | 0.000 | 0 |
I_tmds_clk_p | Setup | 0.000 | 0 |
I_tmds_clk_p | Hold | 0.000 | 0 |
rx0_pclk | Setup | 0.000 | 0 |
rx0_pclk | Hold | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
DVI_TX_Top_inst/rgb2dvi_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.564 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 7.869 |
2 | 6.047 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 7.386 |
3 | 6.056 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 7.377 |
4 | 6.060 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 7.373 |
5 | 6.512 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.921 |
6 | 6.517 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.916 |
7 | 6.546 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.887 |
8 | 6.588 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.845 |
9 | 6.796 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.637 |
10 | 6.807 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.626 |
11 | 6.820 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.613 |
12 | 6.820 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.613 |
13 | 6.820 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.613 |
14 | 6.820 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0/CE | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.613 |
15 | 6.864 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_11_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.569 |
16 | 6.875 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.558 |
17 | 6.957 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.476 |
18 | 7.019 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.414 |
19 | 7.023 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.410 |
20 | 7.023 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.410 |
21 | 7.051 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.382 |
22 | 7.052 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.381 |
23 | 7.052 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.381 |
24 | 7.115 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.318 |
25 | 7.134 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 13.468 | 0.000 | 6.299 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.333 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[6] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.451 |
2 | 0.344 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[9] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
3 | 0.344 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[7] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
4 | 0.344 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[4] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
5 | 0.425 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
6 | 0.425 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
7 | 0.425 | run_cnt_3_s0/Q | run_cnt_3_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
8 | 0.425 | run_cnt_5_s0/Q | run_cnt_5_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
9 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
10 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
11 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
12 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
13 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
14 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.436 |
15 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/D | I_tmds_clk_p:[R] | I_tmds_clk_p:[R] | 0.000 | 0.000 | 0.436 |
16 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/D | I_tmds_clk_p:[R] | I_tmds_clk_p:[R] | 0.000 | 0.000 | 0.436 |
17 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/D | I_tmds_clk_p:[R] | I_tmds_clk_p:[R] | 0.000 | 0.000 | 0.436 |
18 | 0.425 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/D | I_tmds_clk_p:[R] | I_tmds_clk_p:[R] | 0.000 | 0.000 | 0.436 |
19 | 0.427 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/D | I_tmds_clk_p:[R] | I_tmds_clk_p:[R] | 0.000 | 0.000 | 0.438 |
20 | 0.427 | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/Q | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.438 |
21 | 0.427 | run_cnt_6_s0/Q | run_cnt_6_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.438 |
22 | 0.427 | run_cnt_18_s0/Q | run_cnt_18_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.438 |
23 | 0.427 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.438 |
24 | 0.427 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.438 |
25 | 0.427 | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/Q | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/D | rx0_pclk:[R] | rx0_pclk:[R] | 0.000 | 0.000 | 0.438 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0 |
2 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0 |
3 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0 |
4 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0 |
5 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0 |
6 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_4_s0 |
7 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0 |
8 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2 |
9 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2 |
10 | 4.916 | 5.916 | 1.000 | Low Pulse Width | I_tmds_clk_p | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.564 |
Data Arrival Time | 8.113 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q |
1.077 | 0.602 | tNET | FF | 1 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/I1 |
1.632 | 0.555 | tINS | FF | 4 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/F |
1.888 | 0.256 | tNET | FF | 1 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I0 |
2.443 | 0.555 | tINS | FF | 3 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.865 | 0.422 | tNET | FF | 1 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.382 | 0.517 | tINS | FF | 3 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
4.043 | 0.660 | tNET | FF | 1 | R29C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/I1 |
4.613 | 0.570 | tINS | FR | 4 | R29C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/F |
4.789 | 0.176 | tNET | RR | 2 | R29C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/I1 |
5.160 | 0.371 | tINS | RF | 1 | R29C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/COUT |
5.160 | 0.000 | tNET | FF | 2 | R29C37[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/CIN |
5.195 | 0.035 | tINS | FF | 1 | R29C37[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT |
5.195 | 0.000 | tNET | FF | 2 | R29C37[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN |
5.665 | 0.470 | tINS | FF | 1 | R29C37[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM |
6.078 | 0.413 | tNET | FF | 1 | R27C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s5/I3 |
6.627 | 0.549 | tINS | FR | 1 | R27C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s5/F |
6.629 | 0.001 | tNET | RR | 1 | R27C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0 |
7.146 | 0.517 | tINS | RF | 1 | R27C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F |
7.543 | 0.397 | tNET | FF | 1 | R27C36[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1 |
8.113 | 0.570 | tINS | FR | 1 | R27C36[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F |
8.113 | 0.000 | tNET | RR | 1 | R27C36[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C36[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C36[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.709, 59.842%; route: 2.928, 37.210%; tC2Q: 0.232, 2.948% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 6.047 |
Data Arrival Time | 7.629 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q |
1.077 | 0.602 | tNET | FF | 1 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/I1 |
1.632 | 0.555 | tINS | FF | 4 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/F |
1.888 | 0.256 | tNET | FF | 1 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I0 |
2.443 | 0.555 | tINS | FF | 3 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.865 | 0.422 | tNET | FF | 1 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.382 | 0.517 | tINS | FF | 3 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
4.043 | 0.660 | tNET | FF | 1 | R29C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/I1 |
4.598 | 0.555 | tINS | FF | 4 | R29C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/F |
5.008 | 0.410 | tNET | FF | 2 | R30C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n134_s/I1 |
5.379 | 0.371 | tINS | FF | 1 | R30C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n134_s/COUT |
5.379 | 0.000 | tNET | FF | 2 | R30C37[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n133_s/CIN |
5.849 | 0.470 | tINS | FF | 2 | R30C37[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n133_s/SUM |
6.509 | 0.660 | tNET | FF | 1 | R27C39[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2/I0 |
7.079 | 0.570 | tINS | FR | 1 | R27C39[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2/F |
7.080 | 0.001 | tNET | RR | 1 | R27C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/I0 |
7.629 | 0.549 | tINS | RR | 1 | R27C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/F |
7.629 | 0.000 | tNET | RR | 1 | R27C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.142, 56.079%; route: 3.012, 40.780%; tC2Q: 0.232, 3.141% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 6.056 |
Data Arrival Time | 7.620 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/I0 |
3.916 | 0.555 | tINS | FF | 4 | R18C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/F |
4.419 | 0.503 | tNET | FF | 2 | R20C38[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0/I1 |
4.790 | 0.371 | tINS | FF | 1 | R20C38[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0/COUT |
4.790 | 0.000 | tNET | FF | 2 | R20C38[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0/CIN |
5.260 | 0.470 | tINS | FF | 2 | R20C38[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0/SUM |
5.435 | 0.175 | tNET | FF | 1 | R21C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3 |
5.984 | 0.549 | tINS | FR | 1 | R21C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F |
6.156 | 0.172 | tNET | RR | 1 | R21C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2/I0 |
6.609 | 0.453 | tINS | RF | 1 | R21C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2/F |
7.249 | 0.640 | tNET | FF | 1 | R18C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I0 |
7.620 | 0.371 | tINS | FF | 1 | R18C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F |
7.620 | 0.000 | tNET | FF | 1 | R18C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R18C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
13.676 | -0.035 | tSu | 1 | R18C37[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.046, 54.850%; route: 3.099, 42.005%; tC2Q: 0.232, 3.145% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 6.060 |
Data Arrival Time | 7.617 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q |
0.651 | 0.176 | tNET | FF | 1 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/I0 |
1.206 | 0.555 | tINS | FF | 2 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/F |
1.628 | 0.422 | tNET | FF | 1 | R24C35[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s6/I3 |
2.177 | 0.549 | tINS | FR | 3 | R24C35[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s6/F |
2.351 | 0.174 | tNET | RR | 1 | R24C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16/I2 |
2.906 | 0.555 | tINS | RF | 5 | R24C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16/F |
3.490 | 0.584 | tNET | FF | 1 | R24C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3 |
3.861 | 0.371 | tINS | FF | 4 | R24C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F |
4.267 | 0.406 | tNET | FF | 2 | R24C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1 |
4.638 | 0.371 | tINS | FF | 1 | R24C39[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/COUT |
4.638 | 0.000 | tNET | FF | 2 | R24C39[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/CIN |
5.108 | 0.470 | tINS | FF | 2 | R24C39[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM |
5.267 | 0.159 | tNET | FF | 1 | R24C39[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s5/I2 |
5.784 | 0.517 | tINS | FF | 1 | R24C39[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s5/F |
6.197 | 0.413 | tNET | FF | 1 | R24C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0 |
6.650 | 0.453 | tINS | FF | 1 | R24C38[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F |
7.047 | 0.397 | tNET | FF | 1 | R25C38[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1 |
7.617 | 0.570 | tINS | FR | 1 | R25C38[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F |
7.617 | 0.000 | tNET | RR | 1 | R25C38[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R25C38[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
13.676 | -0.035 | tSu | 1 | R25C38[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.411, 59.823%; route: 2.730, 37.031%; tC2Q: 0.232, 3.146% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 6.512 |
Data Arrival Time | 7.165 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/I2 |
6.063 | 0.555 | tINS | FF | 1 | R21C37[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/F |
6.703 | 0.640 | tNET | FF | 1 | R18C37[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I1 |
7.165 | 0.462 | tINS | FR | 1 | R18C37[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F |
7.165 | 0.000 | tNET | RR | 1 | R18C37[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R18C37[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK |
13.676 | -0.035 | tSu | 1 | R18C37[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.366, 48.632%; route: 3.323, 48.016%; tC2Q: 0.232, 3.352% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 6.517 |
Data Arrival Time | 7.159 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q |
1.077 | 0.602 | tNET | FF | 1 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/I1 |
1.632 | 0.555 | tINS | FF | 4 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/F |
1.888 | 0.256 | tNET | FF | 1 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I0 |
2.443 | 0.555 | tINS | FF | 3 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.865 | 0.422 | tNET | FF | 1 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.382 | 0.517 | tINS | FF | 3 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
4.052 | 0.669 | tNET | FF | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/I3 |
4.601 | 0.549 | tINS | FR | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/F |
4.602 | 0.001 | tNET | RR | 1 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/I0 |
5.157 | 0.555 | tINS | RF | 8 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/F |
5.847 | 0.690 | tNET | FF | 1 | R27C38[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3/I2 |
6.417 | 0.570 | tINS | FR | 1 | R27C38[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3/F |
6.589 | 0.172 | tNET | RR | 1 | R27C39[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I1 |
7.159 | 0.570 | tINS | RR | 1 | R27C39[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F |
7.159 | 0.000 | tNET | RR | 1 | R27C39[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C39[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C39[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.871, 55.972%; route: 2.813, 40.673%; tC2Q: 0.232, 3.355% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 6.546 |
Data Arrival Time | 7.131 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q |
1.077 | 0.602 | tNET | FF | 1 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/I1 |
1.632 | 0.555 | tINS | FF | 4 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/F |
1.888 | 0.256 | tNET | FF | 1 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I0 |
2.443 | 0.555 | tINS | FF | 3 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.865 | 0.422 | tNET | FF | 1 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.382 | 0.517 | tINS | FF | 3 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
4.052 | 0.669 | tNET | FF | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/I3 |
4.601 | 0.549 | tINS | FR | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/F |
4.602 | 0.001 | tNET | RR | 1 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/I0 |
5.157 | 0.555 | tINS | RF | 8 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/F |
5.593 | 0.436 | tNET | FF | 1 | R29C38[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0/I2 |
6.148 | 0.555 | tINS | FF | 1 | R29C38[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0/F |
6.561 | 0.413 | tNET | FF | 1 | R30C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2/I1 |
7.131 | 0.570 | tINS | FR | 1 | R30C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2/F |
7.131 | 0.000 | tNET | RR | 1 | R30C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R30C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/CLK |
13.676 | -0.035 | tSu | 1 | R30C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.856, 55.986%; route: 2.799, 40.645%; tC2Q: 0.232, 3.368% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 6.588 |
Data Arrival Time | 7.088 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
6.191 | 0.665 | tNET | FF | 1 | R26C24[3][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s4/I3 |
6.761 | 0.570 | tINS | FR | 1 | R26C24[3][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s4/F |
7.088 | 0.328 | tNET | RR | 1 | R25C24[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R25C24[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK |
13.676 | -0.035 | tSu | 1 | R25C24[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.059, 44.689%; route: 3.554, 51.922%; tC2Q: 0.232, 3.389% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 6.796 |
Data Arrival Time | 6.880 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
6.053 | 0.527 | tNET | FF | 1 | R26C25[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s3/I0 |
6.380 | 0.327 | tINS | FR | 3 | R26C25[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s3/F |
6.880 | 0.500 | tNET | RR | 1 | R25C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R25C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CLK |
13.676 | -0.035 | tSu | 1 | R25C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.816, 42.430%; route: 3.589, 54.074%; tC2Q: 0.232, 3.496% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 6.807 |
Data Arrival Time | 6.869 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/I2 |
6.063 | 0.555 | tINS | FF | 5 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/F |
6.498 | 0.435 | tNET | FF | 1 | R20C35[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1/I1 |
6.869 | 0.371 | tINS | FF | 1 | R20C35[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1/F |
6.869 | 0.000 | tNET | FF | 1 | R20C35[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R20C35[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0/CLK |
13.676 | -0.035 | tSu | 1 | R20C35[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.275, 49.426%; route: 3.119, 47.073%; tC2Q: 0.232, 3.501% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 6.820 |
Data Arrival Time | 6.857 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
5.948 | 0.422 | tNET | FF | 1 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
6.497 | 0.549 | tINS | FR | 4 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
6.857 | 0.360 | tNET | RR | 1 | R27C22[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C22[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C22[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.038, 45.937%; route: 3.343, 50.555%; tC2Q: 0.232, 3.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 6.820 |
Data Arrival Time | 6.857 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
5.948 | 0.422 | tNET | FF | 1 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
6.497 | 0.549 | tINS | FR | 4 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
6.857 | 0.360 | tNET | RR | 1 | R27C22[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C22[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C22[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.038, 45.937%; route: 3.343, 50.555%; tC2Q: 0.232, 3.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 6.820 |
Data Arrival Time | 6.857 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
5.948 | 0.422 | tNET | FF | 1 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
6.497 | 0.549 | tINS | FR | 4 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
6.857 | 0.360 | tNET | RR | 1 | R27C22[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C22[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C22[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.038, 45.937%; route: 3.343, 50.555%; tC2Q: 0.232, 3.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 6.820 |
Data Arrival Time | 6.857 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C18[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_10_s0/Q |
1.622 | 1.147 | tNET | FF | 1 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/I2 |
2.139 | 0.517 | tINS | FF | 5 | R27C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s20/F |
2.808 | 0.669 | tNET | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/I2 |
3.261 | 0.453 | tINS | FF | 1 | R30C20[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s70/F |
3.416 | 0.154 | tNET | FF | 1 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/I1 |
3.933 | 0.517 | tINS | FF | 2 | R30C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s53/F |
4.351 | 0.419 | tNET | FF | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/I0 |
4.900 | 0.549 | tINS | FR | 1 | R27C20[3][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s24/F |
5.073 | 0.172 | tNET | RR | 1 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/I0 |
5.526 | 0.453 | tINS | RF | 3 | R27C21[2][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s8/F |
5.948 | 0.422 | tNET | FF | 1 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/I1 |
6.497 | 0.549 | tINS | FR | 4 | R26C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s6/F |
6.857 | 0.360 | tNET | RR | 1 | R27C22[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C22[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C22[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.038, 45.937%; route: 3.343, 50.555%; tC2Q: 0.232, 3.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 6.864 |
Data Arrival Time | 6.812 |
Data Required Time | 13.676 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_11_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R12C19[0][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 10 | R12C19[0][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/B_align_11_s0/Q |
1.469 | 0.994 | tNET | FF | 1 | R29C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s17/I1 |
2.024 | 0.555 | tINS | FF | 7 | R29C19[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s17/F |
2.596 | 0.572 | tNET | FF | 1 | R30C21[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s13/I2 |
3.113 | 0.517 | tINS | FF | 2 | R30C21[1][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s13/F |
3.773 | 0.660 | tNET | FF | 1 | R27C20[0][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s55/I0 |
4.322 | 0.549 | tINS | FR | 1 | R27C20[0][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s55/F |
4.324 | 0.001 | tNET | RR | 1 | R27C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s40/I3 |
4.879 | 0.555 | tINS | RF | 1 | R27C20[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s40/F |
5.292 | 0.413 | tNET | FF | 1 | R27C21[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s34/I3 |
5.745 | 0.453 | tINS | FF | 1 | R27C21[2][B] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s34/F |
6.263 | 0.518 | tNET | FF | 1 | R26C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s33/I0 |
6.812 | 0.549 | tINS | FR | 1 | R26C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n853_s33/F |
6.812 | 0.000 | tNET | RR | 1 | R26C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R26C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/CLK |
13.676 | -0.035 | tSu | 1 | R26C25[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.178, 48.381%; route: 3.159, 48.087%; tC2Q: 0.232, 3.532% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 6.875 |
Data Arrival Time | 6.802 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R27C33[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/Q |
1.077 | 0.602 | tNET | FF | 1 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/I1 |
1.632 | 0.555 | tINS | FF | 4 | R29C34[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14/F |
1.888 | 0.256 | tNET | FF | 1 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I0 |
2.443 | 0.555 | tINS | FF | 3 | R27C34[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.865 | 0.422 | tNET | FF | 1 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.382 | 0.517 | tINS | FF | 3 | R27C35[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
4.052 | 0.669 | tNET | FF | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/I3 |
4.601 | 0.549 | tINS | FR | 1 | R30C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1/F |
4.602 | 0.001 | tNET | RR | 1 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/I0 |
5.157 | 0.555 | tINS | RF | 8 | R30C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/F |
5.598 | 0.441 | tNET | FF | 1 | R27C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1/I1 |
6.147 | 0.549 | tINS | FR | 1 | R27C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1/F |
6.147 | 0.000 | tNET | RR | 1 | R27C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0/I0 |
6.252 | 0.105 | tINS | RR | 1 | R27C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0/O |
6.431 | 0.178 | tNET | RR | 1 | R27C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0/I0 |
6.802 | 0.371 | tINS | RF | 1 | R27C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0/F |
6.802 | 0.000 | tNET | FF | 1 | R27C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R27C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/CLK |
13.676 | -0.035 | tSu | 1 | R27C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.756, 57.271%; route: 2.570, 39.191%; tC2Q: 0.232, 3.538% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 6.957 |
Data Arrival Time | 6.720 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/I2 |
6.078 | 0.570 | tINS | FR | 5 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/F |
6.258 | 0.180 | tNET | RR | 1 | R21C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1/I1 |
6.720 | 0.462 | tINS | RR | 1 | R21C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1/F |
6.720 | 0.000 | tNET | RR | 1 | R21C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R21C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0/CLK |
13.676 | -0.035 | tSu | 1 | R21C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.381, 52.205%; route: 2.863, 44.213%; tC2Q: 0.232, 3.582% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 7.019 |
Data Arrival Time | 6.657 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.342 | 0.504 | tNET | FF | 1 | R20C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1/I1 |
5.912 | 0.570 | tINS | FR | 1 | R20C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1/F |
5.912 | 0.000 | tNET | RR | 1 | R20C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0/I0 |
6.017 | 0.105 | tINS | RR | 1 | R20C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0/O |
6.195 | 0.178 | tNET | RR | 1 | R20C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0/I0 |
6.657 | 0.462 | tINS | RR | 1 | R20C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0/F |
6.657 | 0.000 | tNET | RR | 1 | R20C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R20C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/CLK |
13.676 | -0.035 | tSu | 1 | R20C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.486, 54.350%; route: 2.696, 42.033%; tC2Q: 0.232, 3.617% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 7.023 |
Data Arrival Time | 6.653 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/I2 |
6.078 | 0.570 | tINS | FR | 5 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/F |
6.083 | 0.005 | tNET | RR | 1 | R21C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0/I2 |
6.653 | 0.570 | tINS | RR | 1 | R21C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0/F |
6.653 | 0.000 | tNET | RR | 1 | R21C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R21C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0/CLK |
13.676 | -0.035 | tSu | 1 | R21C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.489, 54.430%; route: 2.689, 41.950%; tC2Q: 0.232, 3.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 7.023 |
Data Arrival Time | 6.653 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/I2 |
6.078 | 0.570 | tINS | FR | 5 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/F |
6.083 | 0.005 | tNET | RR | 1 | R21C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1/I2 |
6.653 | 0.570 | tINS | RR | 1 | R21C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1/F |
6.653 | 0.000 | tNET | RR | 1 | R21C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R21C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0/CLK |
13.676 | -0.035 | tSu | 1 | R21C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.489, 54.430%; route: 2.689, 41.950%; tC2Q: 0.232, 3.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 7.051 |
Data Arrival Time | 6.626 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/I2 |
6.078 | 0.570 | tINS | FR | 5 | R21C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3/F |
6.255 | 0.176 | tNET | RR | 1 | R20C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0/I1 |
6.626 | 0.371 | tINS | RF | 1 | R20C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0/F |
6.626 | 0.000 | tNET | FF | 1 | R20C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R20C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0/CLK |
13.676 | -0.035 | tSu | 1 | R20C36[0][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.290, 51.550%; route: 2.860, 44.815%; tC2Q: 0.232, 3.635% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 7.052 |
Data Arrival Time | 6.625 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/I2 |
6.078 | 0.570 | tINS | FR | 2 | R21C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/F |
6.254 | 0.176 | tNET | RR | 1 | R22C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0/I2 |
6.625 | 0.371 | tINS | RF | 1 | R22C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0/F |
6.625 | 0.000 | tNET | FF | 1 | R22C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R22C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/CLK |
13.676 | -0.035 | tSu | 1 | R22C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.290, 51.556%; route: 2.859, 44.808%; tC2Q: 0.232, 3.636% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 7.052 |
Data Arrival Time | 6.625 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 6 | R20C34[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
1.138 | 0.662 | tNET | FF | 1 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I1 |
1.591 | 0.453 | tINS | FF | 2 | R18C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F |
1.844 | 0.253 | tNET | FF | 1 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I3 |
2.215 | 0.371 | tINS | FF | 5 | R20C35[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
2.477 | 0.263 | tNET | FF | 1 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I0 |
2.930 | 0.453 | tINS | FF | 4 | R18C35[0][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F |
3.361 | 0.430 | tNET | FF | 1 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
3.916 | 0.555 | tINS | FF | 2 | R18C36[2][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
4.321 | 0.405 | tNET | FF | 1 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
4.838 | 0.517 | tINS | FF | 8 | R18C38[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
5.508 | 0.670 | tNET | FF | 1 | R21C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/I2 |
6.078 | 0.570 | tINS | FR | 2 | R21C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/F |
6.254 | 0.176 | tNET | RR | 1 | R22C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0/I1 |
6.625 | 0.371 | tINS | RF | 1 | R22C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0/F |
6.625 | 0.000 | tNET | FF | 1 | R22C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R22C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/CLK |
13.676 | -0.035 | tSu | 1 | R22C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.290, 51.556%; route: 2.859, 44.808%; tC2Q: 0.232, 3.636% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 7.115 |
Data Arrival Time | 6.562 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q |
0.651 | 0.176 | tNET | FF | 1 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/I0 |
1.221 | 0.570 | tINS | FR | 2 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/F |
1.397 | 0.176 | tNET | RR | 1 | R23C35[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16/I3 |
1.952 | 0.555 | tINS | RF | 4 | R23C35[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16/F |
2.619 | 0.667 | tNET | FF | 1 | R24C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2 |
3.072 | 0.453 | tINS | FF | 1 | R24C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
3.562 | 0.490 | tNET | FF | 1 | R23C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I1 |
3.933 | 0.371 | tINS | FF | 2 | R23C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F |
4.113 | 0.179 | tNET | FF | 1 | R23C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0/I0 |
4.668 | 0.555 | tINS | FF | 7 | R23C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0/F |
5.256 | 0.589 | tNET | FF | 1 | R25C36[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/I0 |
5.773 | 0.517 | tINS | FF | 2 | R25C36[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/F |
6.191 | 0.418 | tNET | FF | 1 | R24C34[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0/I1 |
6.562 | 0.371 | tINS | FF | 1 | R24C34[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0/F |
6.562 | 0.000 | tNET | FF | 1 | R24C34[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R24C34[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLK |
13.676 | -0.035 | tSu | 1 | R24C34[2][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.392, 53.684%; route: 2.694, 42.644%; tC2Q: 0.232, 3.672% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 7.134 |
Data Arrival Time | 6.543 |
Data Required Time | 13.676 |
From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 |
To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R23C36[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/Q |
0.651 | 0.176 | tNET | FF | 1 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/I0 |
1.221 | 0.570 | tINS | FR | 2 | R23C36[3][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5/F |
1.397 | 0.176 | tNET | RR | 1 | R23C35[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16/I3 |
1.952 | 0.555 | tINS | RF | 4 | R23C35[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16/F |
2.619 | 0.667 | tNET | FF | 1 | R24C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2 |
3.072 | 0.453 | tINS | FF | 1 | R24C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
3.562 | 0.490 | tNET | FF | 1 | R23C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I1 |
3.933 | 0.371 | tINS | FF | 2 | R23C36[1][B] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F |
4.113 | 0.179 | tNET | FF | 1 | R23C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0/I0 |
4.683 | 0.570 | tINS | FR | 7 | R23C37[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0/F |
4.861 | 0.178 | tNET | RR | 1 | R23C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I0 |
5.416 | 0.555 | tINS | RF | 6 | R23C36[3][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F |
6.081 | 0.665 | tNET | FF | 1 | R22C33[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0/I0 |
6.543 | 0.462 | tINS | FR | 1 | R22C33[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0/F |
6.543 | 0.000 | tNET | RR | 1 | R22C33[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.468 | 13.468 | active clock edge time | ||||
13.468 | 0.000 | rx0_pclk | ||||
13.468 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
13.711 | 0.243 | tNET | RR | 1 | R22C33[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLK |
13.676 | -0.035 | tSu | 1 | R22C33[1][A] | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.468 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.536, 56.134%; route: 2.531, 40.183%; tC2Q: 0.232, 3.683% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.333 |
Data Arrival Time | 1.311 |
Data Required Time | 0.978 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C32[0][B] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R30C32[0][B] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/Q |
1.311 | 0.249 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/CLK |
0.978 | 0.118 | tHld | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path2
Path Summary:
Slack | 0.344 |
Data Arrival Time | 1.322 |
Data Required Time | 0.978 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C31[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R30C31[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/CLK |
0.978 | 0.118 | tHld | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 0.344 |
Data Arrival Time | 1.322 |
Data Required Time | 0.978 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C32[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R30C32[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/CLK |
0.978 | 0.118 | tHld | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path4
Path Summary:
Slack | 0.344 |
Data Arrival Time | 1.322 |
Data Required Time | 0.978 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C32[2][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R30C32[2][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/AD[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s/CLK |
0.978 | 0.118 | tHld | 1 | BSRAM_R28[8] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/edid_ram_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path5
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/Q |
1.064 | 0.002 | tNET | RR | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n1258_s1/I1 |
1.296 | 0.232 | tINS | RF | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n1258_s1/F |
1.296 | 0.000 | tNET | FF | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R32C27[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/nstate_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path6
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 5 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/Q |
1.064 | 0.002 | tNET | RR | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n657_s2/I1 |
1.296 | 0.232 | tINS | RF | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n657_s2/F |
1.296 | 0.000 | tNET | FF | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R31C34[1][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path7
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | run_cnt_3_s0 |
To | run_cnt_3_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C39[0][A] | run_cnt_3_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R32C39[0][A] | run_cnt_3_s0/Q |
1.064 | 0.002 | tNET | RR | 1 | R32C39[0][A] | n69_s2/I2 |
1.296 | 0.232 | tINS | RF | 1 | R32C39[0][A] | n69_s2/F |
1.296 | 0.000 | tNET | FF | 1 | R32C39[0][A] | run_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C39[0][A] | run_cnt_3_s0/CLK |
0.871 | 0.011 | tHld | 1 | R32C39[0][A] | run_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | run_cnt_5_s0 |
To | run_cnt_5_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C36[0][A] | run_cnt_5_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 4 | R32C36[0][A] | run_cnt_5_s0/Q |
1.064 | 0.002 | tNET | RR | 1 | R32C36[0][A] | n67_s4/I0 |
1.296 | 0.232 | tINS | RF | 1 | R32C36[0][A] | n67_s4/F |
1.296 | 0.000 | tNET | FF | 1 | R32C36[0][A] | run_cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C36[0][A] | run_cnt_5_s0/CLK |
0.871 | 0.011 | tHld | 1 | R32C36[0][A] | run_cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path9
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/n90_s8/I0 |
0.621 | 0.232 | tINS | RF | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/n90_s8/F |
0.621 | 0.000 | tNET | FF | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4/CLK |
0.195 | 0.011 | tHld | 1 | R22C31[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl0_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1376_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1376_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1/CLK |
0.195 | 0.011 | tHld | 1 | R25C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1256_s3/I1 |
0.621 | 0.232 | tINS | RF | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1256_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R23C29[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/g_code_clk_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1510_s1/I1 |
0.621 | 0.232 | tINS | RF | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1510_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C23[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1508_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1508_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C30[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1496_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1496_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C26[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.164 |
Data Required Time | 1.739 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2 |
Launch Clk | I_tmds_clk_p:[R] |
Latch Clk | I_tmds_clk_p:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/CLK |
1.930 | 0.202 | tC2Q | RR | 3 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/Q |
1.932 | 0.002 | tNET | RR | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s10/I0 |
2.164 | 0.232 | tINS | RF | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s10/F |
2.164 | 0.000 | tNET | FF | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/CLK |
1.739 | 0.011 | tHld | 1 | R21C26[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Path16
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.164 |
Data Required Time | 1.739 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0 |
Launch Clk | I_tmds_clk_p:[R] |
Latch Clk | I_tmds_clk_p:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/CLK |
1.930 | 0.202 | tC2Q | RR | 3 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/Q |
1.932 | 0.002 | tNET | RR | 2 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1778_s/I1 |
2.164 | 0.232 | tINS | RF | 1 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1778_s/SUM |
2.164 | 0.000 | tNET | FF | 1 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/CLK |
1.739 | 0.011 | tHld | 1 | R21C23[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Path17
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.164 |
Data Required Time | 1.739 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0 |
Launch Clk | I_tmds_clk_p:[R] |
Latch Clk | I_tmds_clk_p:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/CLK |
1.930 | 0.202 | tC2Q | RR | 3 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/Q |
1.932 | 0.002 | tNET | RR | 2 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1774_s/I1 |
2.164 | 0.232 | tINS | RF | 1 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1774_s/SUM |
2.164 | 0.000 | tNET | FF | 1 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0/CLK |
1.739 | 0.011 | tHld | 1 | R21C24[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Path18
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.164 |
Data Required Time | 1.739 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0 |
Launch Clk | I_tmds_clk_p:[R] |
Latch Clk | I_tmds_clk_p:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK |
1.930 | 0.202 | tC2Q | RR | 3 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/Q |
1.932 | 0.002 | tNET | RR | 2 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1772_s/I1 |
2.164 | 0.232 | tINS | RF | 1 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1772_s/SUM |
2.164 | 0.000 | tNET | FF | 1 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK |
1.739 | 0.011 | tHld | 1 | R21C24[1][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Path19
Path Summary:
Slack | 0.427 |
Data Arrival Time | 2.166 |
Data Required Time | 1.739 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2 |
Launch Clk | I_tmds_clk_p:[R] |
Latch Clk | I_tmds_clk_p:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/CLK |
1.930 | 0.202 | tC2Q | RR | 4 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/Q |
1.934 | 0.004 | tNET | RR | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1780_s3/I0 |
2.166 | 0.232 | tINS | RF | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1780_s3/F |
2.166 | 0.000 | tNET | FF | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_tmds_clk_p | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
0.675 | 0.675 | tINS | RR | 16 | IOT22 | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
1.728 | 1.053 | tNET | RR | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/CLK |
1.739 | 0.011 | tHld | 1 | R21C25[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 39.091%; route: 1.053, 60.909% |
Path20
Path Summary:
Slack | 0.427 |
Data Arrival Time | 1.297 |
Data Required Time | 0.871 |
From | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0 |
To | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 3 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/Q |
1.065 | 0.004 | tNET | RR | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n640_s4/I1 |
1.297 | 0.232 | tINS | RF | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/n640_s4/F |
1.297 | 0.000 | tNET | FF | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0/CLK |
0.871 | 0.011 | tHld | 1 | R32C30[0][A] | EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 0.427 |
Data Arrival Time | 1.297 |
Data Required Time | 0.871 |
From | run_cnt_6_s0 |
To | run_cnt_6_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R33C37[1][A] | run_cnt_6_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 4 | R33C37[1][A] | run_cnt_6_s0/Q |
1.065 | 0.004 | tNET | RR | 1 | R33C37[1][A] | n66_s2/I2 |
1.297 | 0.232 | tINS | RF | 1 | R33C37[1][A] | n66_s2/F |
1.297 | 0.000 | tNET | FF | 1 | R33C37[1][A] | run_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R33C37[1][A] | run_cnt_6_s0/CLK |
0.871 | 0.011 | tHld | 1 | R33C37[1][A] | run_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 0.427 |
Data Arrival Time | 1.297 |
Data Required Time | 0.871 |
From | run_cnt_18_s0 |
To | run_cnt_18_s0 |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R33C37[0][A] | run_cnt_18_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 5 | R33C37[0][A] | run_cnt_18_s0/Q |
1.065 | 0.004 | tNET | RR | 1 | R33C37[0][A] | n54_s2/I2 |
1.297 | 0.232 | tINS | RF | 1 | R33C37[0][A] | n54_s2/F |
1.297 | 0.000 | tNET | FF | 1 | R33C37[0][A] | run_cnt_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR27[A] | I_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 108 | IOR27[A] | I_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R33C37[0][A] | run_cnt_18_s0/CLK |
0.871 | 0.011 | tHld | 1 | R33C37[0][A] | run_cnt_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/Q |
0.390 | 0.004 | tNET | RR | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2096_s4/I2 |
0.622 | 0.232 | tINS | RF | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2096_s4/F |
0.622 | 0.000 | tNET | FF | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3/CLK |
0.195 | 0.011 | tHld | 1 | R26C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/Q |
0.390 | 0.004 | tNET | RR | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2094_s1/I2 |
0.622 | 0.232 | tINS | RF | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2094_s1/F |
0.622 | 0.000 | tNET | FF | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R25C27[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1 |
To | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1 |
Launch Clk | rx0_pclk:[R] |
Latch Clk | rx0_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/Q |
0.390 | 0.004 | tNET | RR | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2091_s1/I2 |
0.622 | 0.232 | tINS | RF | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2091_s1/F |
0.622 | 0.000 | tNET | FF | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx0_pclk | ||||
0.000 | 0.000 | tCL | RR | 396 | TOPSIDE[0] | DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1/CLK |
0.195 | 0.011 | tHld | 1 | R25C28[0][A] | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0/CLK |
MPW2
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0/CLK |
MPW3
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/CLK |
MPW4
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK |
MPW5
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0/CLK |
MPW6
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_4_s0/CLK |
MPW7
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0/CLK |
MPW8
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s2/CLK |
MPW9
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_d1_0_s2/CLK |
MPW10
MPW Summary:
Slack: | 4.916 |
Actual Width: | 5.916 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_tmds_clk_p |
Objects: | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.734 | 0.000 | active clock edge time | ||
6.734 | 0.000 | I_tmds_clk_p | ||
6.734 | 0.000 | tCL | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
7.422 | 0.688 | tINS | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
9.280 | 1.859 | tNET | FF | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
13.468 | 0.000 | active clock edge time | ||
13.468 | 0.000 | I_tmds_clk_p | ||
13.468 | 0.000 | tCL | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I |
14.144 | 0.675 | tINS | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O |
15.196 | 1.053 | tNET | RR | DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
396 | rx0_pclk | 5.564 | 0.261 |
108 | I_clk_d | 15.064 | 0.261 |
72 | align_cnt[1] | 7.462 | 1.280 |
68 | b_chk_cnt_2_13 | 8.764 | 1.857 |
66 | align_cnt[0] | 7.530 | 1.354 |
56 | Align_sta[1] | 8.764 | 1.665 |
42 | de_d | 11.371 | 1.281 |
42 | align_cnt[3] | 7.975 | 0.972 |
37 | align_cnt[2] | 8.050 | 1.190 |
33 | data_0_8 | 9.336 | 1.109 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R27C22 | 90.28% |
R22C32 | 83.33% |
R21C31 | 81.94% |
R20C32 | 80.56% |
R21C24 | 79.17% |
R32C19 | 79.17% |
R29C23 | 77.78% |
R32C31 | 77.78% |
R12C18 | 76.39% |
R32C36 | 76.39% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add |
TC_CLOCK | Actived | create_clock -name I_tmds_clk_p -period 13.468 -waveform {0 6.734} [get_ports {I_tmds_clk_p}] -add |
TC_CLOCK | Actived | create_clock -name rx0_pclk -period 13.468 -waveform {0 6.734} [get_nets {rx0_pclk}] -add |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {I_tmds_clk_p}] -group [get_clocks {rx0_pclk}] |