Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\EDID_PROM\data\edid_prom_top.v
D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\EDID_PROM\data\i2c_slave_wrapper.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Tue Oct 24 09:49:57 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module EDID_PROM_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.245s, Peak memory usage = 35.906MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.906MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 35.906MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.906MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 35.906MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.906MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 35.906MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.906MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 35.906MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 35.906MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.906MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.906MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 50.336MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 50.336MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 50.336MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 50.336MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 3
    IOBUF 1
Register 81
    DFF 3
    DFFE 32
    DFFR 4
    DFFP 4
    DFFC 8
    DFFCE 30
LUT 178
    LUT2 27
    LUT3 37
    LUT4 114
INV 2
    INV 2
BSRAM 1
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 180(180 LUT, 0 ALU) / 20736 <1%
Register 81 / 16509 <1%
  --Register as Latch 0 / 16509 0%
  --Register as FF 81 / 16509 <1%
BSRAM 1 / 46 3%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 10.000 100.0 0.000 5.000 I_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 100.0(MHz) 275.2(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0
To i2c_slave_wrapper_inst/u_i2c_slave/ack_flag_s2
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 82 I_clk_ibuf/O
0.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK
1.095 0.232 tC2Q RF 10 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q
1.332 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n640_s7/I1
1.887 0.555 tINS FF 7 i2c_slave_wrapper_inst/u_i2c_slave/n640_s7/F
2.124 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n2063_s6/I1
2.679 0.555 tINS FF 3 i2c_slave_wrapper_inst/u_i2c_slave/n2063_s6/F
2.916 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1118_s21/I1
3.471 0.555 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1118_s21/F
3.708 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1118_s20/I0
4.225 0.517 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1118_s20/F
4.462 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/ack_flag_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 82 I_clk_ibuf/O
10.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/ack_flag_s2/CLK
10.828 -0.035 tSu 1 i2c_slave_wrapper_inst/u_i2c_slave/ack_flag_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
To i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 82 I_clk_ibuf/O
0.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK
1.095 0.232 tC2Q RF 6 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q
1.332 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/I1
1.887 0.555 tINS FF 5 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/F
2.124 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/I0
2.641 0.517 tINS FF 2 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/F
2.878 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/I1
3.433 0.555 tINS FF 4 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/F
3.670 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1112_s34/I1
4.225 0.555 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1112_s34/F
4.462 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 82 I_clk_ibuf/O
10.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0/CLK
10.828 -0.035 tSu 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
To i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 82 I_clk_ibuf/O
0.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK
1.095 0.232 tC2Q RF 6 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q
1.332 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/I1
1.887 0.555 tINS FF 5 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/F
2.124 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/I0
2.641 0.517 tINS FF 2 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/F
2.878 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/I1
3.433 0.555 tINS FF 4 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/F
3.670 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1110_s34/I1
4.225 0.555 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1110_s34/F
4.462 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 82 I_clk_ibuf/O
10.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK
10.828 -0.035 tSu 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
To i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 82 I_clk_ibuf/O
0.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK
1.095 0.232 tC2Q RF 6 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q
1.332 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/I1
1.887 0.555 tINS FF 5 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/F
2.124 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/I0
2.641 0.517 tINS FF 2 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/F
2.878 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/I1
3.433 0.555 tINS FF 4 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/F
3.670 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1108_s34/I1
4.225 0.555 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1108_s34/F
4.462 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 82 I_clk_ibuf/O
10.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK
10.828 -0.035 tSu 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0
To i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 82 I_clk_ibuf/O
0.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK
1.095 0.232 tC2Q RF 6 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q
1.332 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/I1
1.887 0.555 tINS FF 5 i2c_slave_wrapper_inst/u_i2c_slave/n1104_s25/F
2.124 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/I0
2.641 0.517 tINS FF 2 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s10/F
2.878 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/I1
3.433 0.555 tINS FF 4 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s45/F
3.670 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s43/I1
4.225 0.555 tINS FF 1 i2c_slave_wrapper_inst/u_i2c_slave/n1106_s43/F
4.462 0.237 tNET FF 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 82 I_clk_ibuf/O
10.863 0.180 tNET RR 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0/CLK
10.828 -0.035 tSu 1 i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%