Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\DVI_TX\data\dvi_tx_top.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\DVI_TX\data\rgb2dvi.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-6 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Tue Oct 24 09:48:19 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DVI_TX_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 35.828MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 35.828MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.828MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.828MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 35.828MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.828MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 35.828MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.828MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 35.828MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 35.828MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 35.828MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 35.828MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 52.406MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 52.406MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 52.406MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 52.406MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 37 |
I/O Buf | 33 |
    IBUF | 29 |
    TLVDS_OBUF | 4 |
Register | 73 |
    DFFP | 3 |
    DFFC | 70 |
LUT | 215 |
    LUT2 | 30 |
    LUT3 | 54 |
    LUT4 | 131 |
ALU | 69 |
    ALU | 69 |
INV | 3 |
    INV | 3 |
IOLOGIC | 4 |
    OSER10 | 4 |
CLOCK | 1 |
    rPLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 287(218 LUT, 69 ALU) / 20736 | 2% |
Register | 73 / 16509 | <1% |
  --Register as Latch | 0 / 16509 | 0% |
  --Register as FF | 73 / 16509 | <1% |
BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_rgb_clk | Base | 13.468 | 74.3 | 0.000 | 6.734 | I_rgb_clk_ibuf/I | ||
rgb2dvi_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.3 | 0.000 | 1.347 | I_rgb_clk_ibuf/I | I_rgb_clk | rgb2dvi_inst/rpll_inst/CLKOUT |
rgb2dvi_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.3 | 0.000 | 1.347 | I_rgb_clk_ibuf/I | I_rgb_clk | rgb2dvi_inst/rpll_inst/CLKOUTP |
rgb2dvi_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.387 | 185.6 | 0.000 | 2.694 | I_rgb_clk_ibuf/I | I_rgb_clk | rgb2dvi_inst/rpll_inst/CLKOUTD |
rgb2dvi_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.7 | 0.000 | 4.040 | I_rgb_clk_ibuf/I | I_rgb_clk | rgb2dvi_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_rgb_clk | 74.3(MHz) | 139.9(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 6.321 |
Data Arrival Time | 7.975 |
Data Required Time | 14.296 |
From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 |
To | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
Launch Clk | I_rgb_clk[R] |
Latch Clk | I_rgb_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_rgb_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1 |
1.887 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F |
2.124 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I1 |
2.679 | 0.555 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.916 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.433 | 0.517 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
3.670 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/I1 |
4.225 | 0.555 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/F |
4.462 | 0.237 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/I1 |
5.032 | 0.570 | tINS | FR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/COUT |
5.032 | 0.000 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/CIN |
5.502 | 0.470 | tINS | RF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/SUM |
5.739 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s5/I2 |
6.192 | 0.453 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s5/F |
6.429 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0 |
6.946 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F |
7.183 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1 |
7.738 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F |
7.975 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | I_rgb_clk | |||
13.468 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
14.151 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
14.331 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
14.296 | -0.035 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.747, 66.746%; route: 2.133, 29.992%; tC2Q: 0.232, 3.262% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 6.359 |
Data Arrival Time | 7.937 |
Data Required Time | 14.296 |
From | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 |
To | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
Launch Clk | I_rgb_clk[R] |
Latch Clk | I_rgb_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_rgb_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 20 | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/I1 |
1.887 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/F |
2.124 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I0 |
2.641 | 0.517 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F |
2.878 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16/I0 |
3.395 | 0.517 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16/F |
3.632 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/I1 |
4.187 | 0.555 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/F |
4.424 | 0.237 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/I1 |
4.994 | 0.570 | tINS | FR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/COUT |
4.994 | 0.000 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/CIN |
5.464 | 0.470 | tINS | RF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM |
5.701 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s5/I2 |
6.154 | 0.453 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s5/F |
6.391 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0 |
6.908 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F |
7.145 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1 |
7.700 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F |
7.937 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | I_rgb_clk | |||
13.468 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
14.151 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
14.331 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
14.296 | -0.035 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.709, 66.567%; route: 2.133, 30.153%; tC2Q: 0.232, 3.280% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.505 |
Data Arrival Time | 7.790 |
Data Required Time | 14.296 |
From | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 |
To | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
Launch Clk | I_rgb_clk[R] |
Latch Clk | I_rgb_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_rgb_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/I1 |
1.887 | 0.555 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/F |
2.124 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17/I1 |
2.679 | 0.555 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17/F |
2.916 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17/I0 |
3.433 | 0.517 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17/F |
3.670 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/I2 |
4.122 | 0.453 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/F |
4.359 | 0.237 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/I1 |
4.930 | 0.570 | tINS | FR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/COUT |
4.930 | 0.000 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/CIN |
5.399 | 0.470 | tINS | RF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/SUM |
5.636 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s5/I3 |
6.007 | 0.371 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s5/F |
6.244 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0 |
6.761 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F |
6.998 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1 |
7.553 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F |
7.790 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | I_rgb_clk | |||
13.468 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
14.151 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
14.331 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
14.296 | -0.035 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.563, 65.863%; route: 2.133, 30.788%; tC2Q: 0.232, 3.349% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.742 |
Data Arrival Time | 7.554 |
Data Required Time | 14.296 |
From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 |
To | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
Launch Clk | I_rgb_clk[R] |
Latch Clk | I_rgb_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_rgb_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1 |
1.887 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F |
2.124 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/I1 |
2.679 | 0.555 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16/F |
2.916 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/I0 |
3.433 | 0.517 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2/F |
3.670 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/I1 |
4.225 | 0.555 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s14/F |
4.462 | 0.237 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/I1 |
5.016 | 0.555 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/SUM |
5.253 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4/I0 |
5.771 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4/F |
6.008 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2/I1 |
6.563 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2/F |
6.799 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/I0 |
7.317 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/F |
7.554 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | I_rgb_clk | |||
13.468 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
14.151 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
14.331 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK |
14.296 | -0.035 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.326, 64.654%; route: 2.133, 31.879%; tC2Q: 0.232, 3.467% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.780 |
Data Arrival Time | 7.516 |
Data Required Time | 14.296 |
From | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 |
To | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
Launch Clk | I_rgb_clk[R] |
Latch Clk | I_rgb_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_rgb_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 20 | rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/I1 |
1.887 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/F |
2.124 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I0 |
2.641 | 0.517 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F |
2.878 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16/I0 |
3.395 | 0.517 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16/F |
3.632 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/I1 |
4.187 | 0.555 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s14/F |
4.424 | 0.237 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/I1 |
4.978 | 0.555 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/SUM |
5.215 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4/I0 |
5.733 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4/F |
5.970 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/I1 |
6.524 | 0.555 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/F |
6.761 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I0 |
7.279 | 0.517 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F |
7.516 | 0.237 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
13.468 | 0.000 | I_rgb_clk | |||
13.468 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
14.151 | 0.683 | tINS | RR | 78 | I_rgb_clk_ibuf/O |
14.331 | 0.180 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK |
14.296 | -0.035 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 13.468 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.288, 64.452%; route: 2.133, 32.061%; tC2Q: 0.232, 3.487% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |