#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Wed Jun 26 14:50:33 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v" (library work) @I:"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\top_define.vh" (library work) @I:"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\static_macro_define.vh" (library work) @I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp" (library work) @N:CG346 : I2C_MASTER.vp(491) | Read full_case directive. @N:CG347 : I2C_MASTER.vp(491) | Read a parallel_case directive. @N:CG346 : I2C_MASTER.vp(495) | Read full_case directive. @N:CG347 : I2C_MASTER.vp(495) | Read a parallel_case directive. @W:CG286 : I2C_MASTER.vp(495) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive. @N:CG346 : I2C_MASTER.vp(804) | Read full_case directive. @N:CG347 : I2C_MASTER.vp(804) | Read a parallel_case directive. Verilog syntax check successful! Selecting top level module I2C_MASTER_Top Running optimization stage 1 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top ....... Running optimization stage 1 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top ....... Running optimization stage 1 on \~i2c_master.I2C_MASTER_Top ....... @N:CG364 : I2C_MASTER_TOP.v(4) | Synthesizing module I2C_MASTER_Top in library work. Running optimization stage 1 on I2C_MASTER_Top ....... Running optimization stage 2 on I2C_MASTER_Top ....... Running optimization stage 2 on \~i2c_master.I2C_MASTER_Top ....... Running optimization stage 2 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top ....... Extracted state machine for register c_state State machine has 18 reachable states with original encodings of: 00000000000000000 00000000000000001 00000000000000010 00000000000000100 00000000000001000 00000000000010000 00000000000100000 00000000001000000 00000000010000000 00000000100000000 00000001000000000 00000010000000000 00000100000000000 00001000000000000 00010000000000000 00100000000000000 01000000000000000 10000000000000000 Running optimization stage 2 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top ....... Extracted state machine for register c_state State machine has 6 reachable states with original encodings of: 00000 00001 00010 00100 01000 10000 For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 75MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 26 14:50:33 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level @N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 26 14:50:34 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jun 26 14:50:34 2019 ###########################################################]