Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDID_PROM\data\edid_prom_top.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDID_PROM\data\i2c_slave_wrapper.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Fri Mar 22 16:51:09 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | EDID_PROM_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 83.352MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 83.352MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 83.352MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 83.352MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 83.352MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 83.352MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 83.352MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 83.352MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 83.352MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 83.352MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 83.352MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 83.352MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.896s, Peak memory usage = 112.168MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 112.168MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 112.168MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 112.168MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 22 |
I/O Buf | 22 |
    IBUF | 21 |
    IOBUF | 1 |
Register | 70 |
    DFF | 2 |
    DFFE | 24 |
    DFFR | 3 |
    DFFP | 4 |
    DFFC | 8 |
    DFFCE | 29 |
LUT | 162 |
    LUT2 | 15 |
    LUT3 | 38 |
    LUT4 | 109 |
INV | 2 |
    INV | 2 |
BSRAM | 1 |
    SDPB | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 164(164 LUT, 0 ALU) / 20736 | <1% |
Register | 70 / 16509 | <1% |
  --Register as Latch | 0 / 16509 | 0% |
  --Register as FF | 70 / 16509 | <1% |
BSRAM | 1 / 46 | 3% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_mema_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_mema_clk_ibuf/I | ||
I_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_clk | 100.000(MHz) | 205.888(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.143 |
Data Arrival Time | 5.182 |
Data Required Time | 10.325 |
From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
To | i2c_slave_wrapper_inst/u_i2c_slave/slave_addr_flag_s2 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
1.621 | 0.555 | tINS | FF | 9 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s6/I1 |
2.650 | 0.555 | tINS | FF | 3 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s6/F |
3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s0/I1 |
3.679 | 0.555 | tINS | FF | 3 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s0/F |
4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1121_s11/I1 |
4.708 | 0.555 | tINS | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1121_s11/F |
5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/slave_addr_flag_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/slave_addr_flag_s2/CLK |
10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/slave_addr_flag_s2 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.220, 46.039%; route: 2.370, 49.150%; tC2Q: 0.232, 4.811% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:Slack | 5.143 |
Data Arrival Time | 5.182 |
Data Required Time | 10.325 |
From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
To | i2c_slave_wrapper_inst/u_i2c_slave/cstate_0_s1 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
1.621 | 0.555 | tINS | FF | 9 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s6/I1 |
2.650 | 0.555 | tINS | FF | 3 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s6/F |
3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s0/I1 |
3.679 | 0.555 | tINS | FF | 3 | i2c_slave_wrapper_inst/u_i2c_slave/n2079_s0/F |
4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1109_s9/I1 |
4.708 | 0.555 | tINS | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1109_s9/F |
5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/cstate_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/cstate_0_s1/CLK |
10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/cstate_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.220, 46.039%; route: 2.370, 49.150%; tC2Q: 0.232, 4.811% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:Slack | 5.181 |
Data Arrival Time | 5.144 |
Data Required Time | 10.325 |
From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0 |
To | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/I1 |
1.621 | 0.555 | tINS | FF | 5 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/F |
2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/I0 |
2.612 | 0.517 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/F |
3.086 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/I1 |
3.641 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/F |
4.115 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s43/I1 |
4.670 | 0.555 | tINS | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s43/F |
5.144 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0/CLK |
10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.182, 45.610%; route: 2.370, 49.541%; tC2Q: 0.232, 4.849% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:Slack | 5.181 |
Data Arrival Time | 5.144 |
Data Required Time | 10.325 |
From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0 |
To | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/I1 |
1.621 | 0.555 | tINS | FF | 5 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/F |
2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/I0 |
2.612 | 0.517 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/F |
3.086 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/I1 |
3.641 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/F |
4.115 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1119_s34/I1 |
4.670 | 0.555 | tINS | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1119_s34/F |
5.144 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0/CLK |
10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.182, 45.610%; route: 2.370, 49.541%; tC2Q: 0.232, 4.849% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:Slack | 5.181 |
Data Arrival Time | 5.144 |
Data Required Time | 10.325 |
From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0 |
To | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_2_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/I1 |
1.621 | 0.555 | tINS | FF | 5 | i2c_slave_wrapper_inst/u_i2c_slave/n1111_s25/F |
2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/I0 |
2.612 | 0.517 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_3_s11/F |
3.086 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/I1 |
3.641 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/n1113_s45/F |
4.115 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1117_s34/I1 |
4.670 | 0.555 | tINS | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n1117_s34/F |
5.144 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.182, 45.610%; route: 2.370, 49.541%; tC2Q: 0.232, 4.849% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |