#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
#OS: Windows 7 6.1
#Hostname: Desktop-2019KKU

# Wed Jun 26 14:50:33 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v" (library work)
@I:"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\top_define.vh" (library work)
@I:"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\static_macro_define.vh" (library work)
@I::"D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp" (library work)
@N:CG346 : I2C_MASTER.vp(491) | Read full_case directive.
@N:CG347 : I2C_MASTER.vp(491) | Read a parallel_case directive.
@N:CG346 : I2C_MASTER.vp(495) | Read full_case directive.
@N:CG347 : I2C_MASTER.vp(495) | Read a parallel_case directive.
@W:CG286 : I2C_MASTER.vp(495) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
@N:CG346 : I2C_MASTER.vp(804) | Read full_case directive.
@N:CG347 : I2C_MASTER.vp(804) | Read a parallel_case directive.
Verilog syntax check successful!
Selecting top level module I2C_MASTER_Top
Running optimization stage 1 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top  .......
Running optimization stage 1 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top  .......
Running optimization stage 1 on \~i2c_master.I2C_MASTER_Top  .......
@N:CG364 : I2C_MASTER_TOP.v(4) | Synthesizing module I2C_MASTER_Top in library work.
Running optimization stage 1 on I2C_MASTER_Top .......
Running optimization stage 2 on I2C_MASTER_Top .......
Running optimization stage 2 on \~i2c_master.I2C_MASTER_Top  .......
Running optimization stage 2 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top  .......
Extracted state machine for register c_state
State machine has 18 reachable states with original encodings of:
   00000000000000000
   00000000000000001
   00000000000000010
   00000000000000100
   00000000000001000
   00000000000010000
   00000000000100000
   00000000001000000
   00000000010000000
   00000000100000000
   00000001000000000
   00000010000000000
   00000100000000000
   00001000000000000
   00010000000000000
   00100000000000000
   01000000000000000
   10000000000000000
Running optimization stage 2 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top  .......
Extracted state machine for register c_state
State machine has 6 reachable states with original encodings of:
   00000
   00001
   00010
   00100
   01000
   10000

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 75MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 26 14:50:33 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level
@N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 26 14:50:34 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 26 14:50:34 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level
@N:NF107 : i2c_master_top.v(4) | Selected library: work cell: I2C_MASTER_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 26 14:50:35 2019

###########################################################]


Premap Report



# Wed Jun 26 14:50:35 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
@L: C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master_scck.rpt 
Printing clock  summary report in "C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
Encoding state machine c_state[5:0] (in view: work.\\\~I2C_Master_Byte_Ctrl\.I2C_MASTER_Top\ (verilog))
original code -> new code
   00000 -> 000001
   00001 -> 000010
   00010 -> 000100
   00100 -> 001000
   01000 -> 010000
   10000 -> 100000
Encoding state machine c_state[17:0] (in view: work.\\\~I2C_Master_Bit_Ctrl\.I2C_MASTER_Top\ (verilog))
original code -> new code
   00000000000000000 -> 000000000000000001
   00000000000000001 -> 000000000000000010
   00000000000000010 -> 000000000000000100
   00000000000000100 -> 000000000000001000
   00000000000001000 -> 000000000000010000
   00000000000010000 -> 000000000000100000
   00000000000100000 -> 000000000001000000
   00000000001000000 -> 000000000010000000
   00000000010000000 -> 000000000100000000
   00000000100000000 -> 000000001000000000
   00000001000000000 -> 000000010000000000
   00000010000000000 -> 000000100000000000
   00000100000000000 -> 000001000000000000
   00001000000000000 -> 000010000000000000
   00010000000000000 -> 000100000000000000
   00100000000000000 -> 001000000000000000
   01000000000000000 -> 010000000000000000
   10000000000000000 -> 100000000000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)



Clock Summary
******************

          Start                    Requested     Requested     Clock        Clock                     Clock
Level     Clock                    Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------
0 -       I2C_MASTER_Top|I_CLK     170.6 MHz     5.863         inferred     Autoconstr_clkgroup_0     127  
===========================================================================================================



Clock Load Summary
***********************

                         Clock     Source          Clock Pin                Non-clock Pin     Non-clock Pin
Clock                    Load      Pin             Seq Example              Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------
I2C_MASTER_Top|I_CLK     127       I_CLK(port)     u_i2c_master.rxack.C     -                 -            
===========================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 127 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       I_CLK               Unconstrained_port     127        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 106MB peak: 192MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 26 14:50:37 2019

###########################################################]


Map & Optimize Report



# Wed Jun 26 14:50:37 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: D:\GOWIN SW\test_version\Gowin_V1.9.1.01Beta_31814_0625\SynplifyPro
OS: Windows 6.1

Hostname: Desktop-2019KKU

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.20ns		 197 /       127
   2		0h:00m:01s		    -2.20ns		 191 /       127
Timing driven replication report
Added 5 Registers via timing driven replication
Added 5 LUTs via timing driven replication

   3		0h:00m:01s		    -2.20ns		 196 /       132
   4		0h:00m:01s		    -1.75ns		 198 /       132
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication


   5		0h:00m:01s		    -2.00ns		 199 /       133

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 195MB)

Writing Analyst data base C:\Users\Desktop\Desktop\IP release\IP_release_190620\IP_release_190508\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_GUI\Gowin_I2C_Master_refDesign\gw_i2c_master\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\i2c_master_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 195MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 195MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 195MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 195MB)

@W:MT420 :  | Found inferred clock I2C_MASTER_Top|I_CLK with period 6.48ns. Please declare a user-defined clock on port I_CLK. 


##### START OF TIMING REPORT #####[
# Timing report written on Wed Jun 26 14:50:41 2019
#


Top view:               I2C_MASTER_Top
Requested Frequency:    154.4 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.143

                         Requested      Estimated     Requested     Estimated                Clock        Clock                
Starting Clock           Frequency      Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------
I2C_MASTER_Top|I_CLK     154.4 MHz      131.2 MHz     6.477         7.620         -1.143     inferred     Autoconstr_clkgroup_0
System                   1152.2 MHz     979.4 MHz     0.868         1.021         -0.153     system       system_clkgroup      
===============================================================================================================================





Clock Relationships
*******************

Clocks                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------
System                System                |  0.868       -0.153  |  No paths    -      |  No paths    -      |  No paths    -    
System                I2C_MASTER_Top|I_CLK  |  6.477       5.323   |  No paths    -      |  No paths    -      |  No paths    -    
I2C_MASTER_Top|I_CLK  System                |  6.477       5.089   |  No paths    -      |  No paths    -      |  No paths    -    
I2C_MASTER_Top|I_CLK  I2C_MASTER_Top|I_CLK  |  6.477       -1.143  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: I2C_MASTER_Top|I_CLK
====================================



Starting Points with Worst Slack
********************************

                                            Starting                                                  Arrival           
Instance                                    Reference                Type      Pin     Net            Time        Slack 
                                            Clock                                                                       
------------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[13]        0.367       -1.143
u_i2c_master.bit_controller.cnt[9]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[9]         0.367       -1.076
u_i2c_master.bit_controller.cnt[12]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[12]        0.367       -1.076
u_i2c_master.bit_controller.cnt[8]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[8]         0.367       -1.009
u_i2c_master.byte_controller.c_state[2]     I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[2]     0.367       -0.888
u_i2c_master.bit_controller.cnt[1]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[1]         0.367       -0.866
u_i2c_master.bit_controller.cnt[14]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[14]        0.367       -0.866
u_i2c_master.byte_controller.c_state[1]     I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[1]     0.367       -0.821
u_i2c_master.bit_controller.cnt[0]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[0]         0.367       -0.799
u_i2c_master.bit_controller.cnt[10]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[10]        0.367       -0.799
========================================================================================================================


Ending Points with Worst Slack
******************************

                                       Starting                                            Required           
Instance                               Reference                Type      Pin     Net      Time         Slack 
                                       Clock                                                                  
--------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[0]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[1]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[2]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[3]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[4]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[5]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[6]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[7]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[8]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
u_i2c_master.bit_controller.cnt[9]     I2C_MASTER_Top|I_CLK     DFFCE     CE      cnte     6.344        -1.143
==============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      7.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.143

    Number of logic level(s):                3
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[0] / CE
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]       DFFCE     Q        Out     0.367     0.367       -         
cnt[13]                                   Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      I1       In      -         1.388       -         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      F        Out     1.099     2.487       -         
un1_cnt_9                                 Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.cntlde_1      LUT4      I1       In      -         3.508       -         
u_i2c_master.bit_controller.cntlde_1      LUT4      F        Out     1.099     4.607       -         
cntlde_1                                  Net       -        -       0.766     -           1         
u_i2c_master.bit_controller.cntlde        LUT4      I0       In      -         5.373       -         
u_i2c_master.bit_controller.cntlde        LUT4      F        Out     1.032     6.405       -         
cnte                                      Net       -        -       1.082     -           16        
u_i2c_master.bit_controller.cnt[0]        DFFCE     CE       In      -         7.487       -         
=====================================================================================================
Total path delay (propagation time + setup) of 7.620 is 3.730(49.0%) logic and 3.890(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      7.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.143

    Number of logic level(s):                3
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[1] / CE
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]       DFFCE     Q        Out     0.367     0.367       -         
cnt[13]                                   Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      I1       In      -         1.388       -         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      F        Out     1.099     2.487       -         
un1_cnt_9                                 Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.cntlde_1      LUT4      I1       In      -         3.508       -         
u_i2c_master.bit_controller.cntlde_1      LUT4      F        Out     1.099     4.607       -         
cntlde_1                                  Net       -        -       0.766     -           1         
u_i2c_master.bit_controller.cntlde        LUT4      I0       In      -         5.373       -         
u_i2c_master.bit_controller.cntlde        LUT4      F        Out     1.032     6.405       -         
cnte                                      Net       -        -       1.082     -           16        
u_i2c_master.bit_controller.cnt[1]        DFFCE     CE       In      -         7.487       -         
=====================================================================================================
Total path delay (propagation time + setup) of 7.620 is 3.730(49.0%) logic and 3.890(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      7.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.143

    Number of logic level(s):                3
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[2] / CE
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]       DFFCE     Q        Out     0.367     0.367       -         
cnt[13]                                   Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      I1       In      -         1.388       -         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      F        Out     1.099     2.487       -         
un1_cnt_9                                 Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.cntlde_1      LUT4      I1       In      -         3.508       -         
u_i2c_master.bit_controller.cntlde_1      LUT4      F        Out     1.099     4.607       -         
cntlde_1                                  Net       -        -       0.766     -           1         
u_i2c_master.bit_controller.cntlde        LUT4      I0       In      -         5.373       -         
u_i2c_master.bit_controller.cntlde        LUT4      F        Out     1.032     6.405       -         
cnte                                      Net       -        -       1.082     -           16        
u_i2c_master.bit_controller.cnt[2]        DFFCE     CE       In      -         7.487       -         
=====================================================================================================
Total path delay (propagation time + setup) of 7.620 is 3.730(49.0%) logic and 3.890(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      7.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.143

    Number of logic level(s):                3
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[3] / CE
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]       DFFCE     Q        Out     0.367     0.367       -         
cnt[13]                                   Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      I1       In      -         1.388       -         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      F        Out     1.099     2.487       -         
un1_cnt_9                                 Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.cntlde_1      LUT4      I1       In      -         3.508       -         
u_i2c_master.bit_controller.cntlde_1      LUT4      F        Out     1.099     4.607       -         
cntlde_1                                  Net       -        -       0.766     -           1         
u_i2c_master.bit_controller.cntlde        LUT4      I0       In      -         5.373       -         
u_i2c_master.bit_controller.cntlde        LUT4      F        Out     1.032     6.405       -         
cnte                                      Net       -        -       1.082     -           16        
u_i2c_master.bit_controller.cnt[3]        DFFCE     CE       In      -         7.487       -         
=====================================================================================================
Total path delay (propagation time + setup) of 7.620 is 3.730(49.0%) logic and 3.890(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      7.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.143

    Number of logic level(s):                3
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[4] / CE
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]       DFFCE     Q        Out     0.367     0.367       -         
cnt[13]                                   Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      I1       In      -         1.388       -         
u_i2c_master.bit_controller.un1_cnt_9     LUT4      F        Out     1.099     2.487       -         
un1_cnt_9                                 Net       -        -       1.021     -           2         
u_i2c_master.bit_controller.cntlde_1      LUT4      I1       In      -         3.508       -         
u_i2c_master.bit_controller.cntlde_1      LUT4      F        Out     1.099     4.607       -         
cntlde_1                                  Net       -        -       0.766     -           1         
u_i2c_master.bit_controller.cntlde        LUT4      I0       In      -         5.373       -         
u_i2c_master.bit_controller.cntlde        LUT4      F        Out     1.032     6.405       -         
cnte                                      Net       -        -       1.082     -           16        
u_i2c_master.bit_controller.cnt[4]        DFFCE     CE       In      -         7.487       -         
=====================================================================================================
Total path delay (propagation time + setup) of 7.620 is 3.730(49.0%) logic and 3.890(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                               Starting                                            Arrival           
Instance                                       Reference     Type     Pin     Net                  Time        Slack 
                                               Clock                                                                 
---------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.scl_padoen_o_i     System        INV      O       un1_scl_padoen_o     0.000       -0.153
u_i2c_master.bit_controller.sda_padoen_o_i     System        INV      O       un1_sda_padoen_o     0.000       -0.153
u_i2c_master.I_RESETN_i                        System        INV      O       I_RESETN_i           0.000       5.323 
=====================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                               Required           
Instance                                    Reference     Type     Pin        Net                  Time         Slack 
                                            Clock                                                                     
----------------------------------------------------------------------------------------------------------------------
un1_scl_padoen_o_i                          System        INV      I          un1_scl_padoen_o     0.868        -0.153
un1_sda_padoen_o_i                          System        INV      I          un1_sda_padoen_o     0.868        -0.153
u_i2c_master.bit_controller.c_state[0]      System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.byte_controller.c_state[0]     System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.bit_controller.clk_en          System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.bit_controller.dSCL            System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.bit_controller.dSDA            System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.bit_controller.sSCL            System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
u_i2c_master.bit_controller.sSDA            System        DFFP     PRESET     I_RESETN_i           6.344        5.323 
======================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      0.868
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.868

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.153

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.bit_controller.scl_padoen_o_i / O
    Ending point:                            un1_scl_padoen_o_i / I
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.scl_padoen_o_i     INV      O        Out     0.000     0.000       -         
un1_scl_padoen_o                               Net      -        -       1.021     -           1         
un1_scl_padoen_o_i                             INV      I        In      -         1.021       -         
=========================================================================================================
Total path delay (propagation time + setup) of 1.021 is 0.000(0.0%) logic and 1.021(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.868
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.868

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.153

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.bit_controller.sda_padoen_o_i / O
    Ending point:                            un1_sda_padoen_o_i / I
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.sda_padoen_o_i     INV      O        Out     0.000     0.000       -         
un1_sda_padoen_o                               Net      -        -       1.021     -           1         
un1_sda_padoen_o_i                             INV      I        In      -         1.021       -         
=========================================================================================================
Total path delay (propagation time + setup) of 1.021 is 0.000(0.0%) logic and 1.021(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.323

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_i / O
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                       Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_i                    INV      O          Out     0.000     0.000       -         
I_RESETN_i                                 Net      -          -       1.021     -           132       
u_i2c_master.bit_controller.c_state[0]     DFFP     PRESET     In      -         1.021       -         
=======================================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.323

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_i / O
    Ending point:                            u_i2c_master.bit_controller.clk_en / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                  Pin        Pin               Arrival     No. of    
Name                                   Type     Name       Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_i                INV      O          Out     0.000     0.000       -         
I_RESETN_i                             Net      -          -       1.021     -           132       
u_i2c_master.bit_controller.clk_en     DFFP     PRESET     In      -         1.021       -         
===================================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.477
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.344

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.323

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_i / O
    Ending point:                            u_i2c_master.bit_controller.dSCL / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                Pin        Pin               Arrival     No. of    
Name                                 Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_i              INV      O          Out     0.000     0.000       -         
I_RESETN_i                           Net      -          -       1.021     -           132       
u_i2c_master.bit_controller.dSCL     DFFP     PRESET     In      -         1.021       -         
=================================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 195MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 195MB)

---------------------------------------
Resource Usage Report for I2C_MASTER_Top 

Mapping to part: gw1n_4blqfp144-6
Cell usage:
ALU             16 uses
DFF             1 use
DFFC            43 uses
DFFCE           80 uses
DFFP            7 uses
DFFPE           2 uses
GSR             1 use
INV             5 uses
MUX2_LUT5       10 uses
MUX2_LUT6       1 use
LUT2            16 uses
LUT3            44 uses
LUT4            121 uses

I/O ports: 29
I/O primitives: 2
IOBUF          2 uses

I/O Register bits:                  0
Register bits not including I/Os:   133 of 3456 (3%)
Total load per clock:
   I2C_MASTER_Top|I_CLK: 133

@S |Mapping Summary:
Total  LUTs: 181 (3%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 195MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Wed Jun 26 14:50:41 2019

###########################################################]