Project Settings
Project Name I2C_MASTER Device Name rev_1: GOWIN-GW1N : GW1N_4B
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 14 1 0 - 00m:01s - 2019/6/26
14:50:34
(premap)Complete 9 0 0 0m:01s 0m:01s 192MB 2019/6/26
14:50:37
(fpga_mapper)Complete 11 1 0 0m:03s 0m:03s 195MB 2019/6/26
14:50:41
Multi-srs Generator Complete2019/6/26
14:50:35

Area Summary
I/O ports (io_port) 29 Non I/O Register bits (non_io_reg) 133 (3%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 0 (10)
Block Multipliers (dsp_used) 0 (8) LUTs (total_luts) 181 (3%)

Timing Summary
Clock NameReq FreqEst FreqSlack
I2C_MASTER_Top|I_CLK154.4 MHz131.2 MHz-1.143
System1152.2 MHz979.4 MHz-0.153

Optimizations Summary
Combined Clock Conversion 1 / 0