Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.8Beta |
| Part Number | GW1NS-UX2CLQ144C5/I4 |
| Device | GW1NS-2C |
| Created Time | Wed Jul 14 15:21:32 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 44.016MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 44.016MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 44.016MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 44.016MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 44.016MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.016MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.016MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 44.016MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.016MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 44.016MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.016MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 44.016MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 57.531MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 57.531MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.706s, Peak memory usage = 57.531MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 5s, Peak memory usage = 57.531MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 257 |
| I/O Buf | 257 |
| IBUF | 87 |
| OBUF | 152 |
| IOBUF | 18 |
| Register | 449 |
| DFF | 1 |
| DFFE | 1 |
| DFFP | 7 |
| DFFPE | 31 |
| DFFC | 104 |
| DFFCE | 302 |
| DFFNCE | 3 |
| LUT | 665 |
| LUT2 | 84 |
| LUT3 | 202 |
| LUT4 | 379 |
| ALU | 17 |
| ALU | 17 |
| INV | 20 |
| INV | 20 |
| BSRAM | 4 |
| SP | 4 |
| CLOCK | 4 |
| CLKDIV | 2 |
| DQCE | 1 |
| OSCF | 1 |
| User Flash | 1 |
| FLASH128K | 1 |
| MCU | 1 |
| ADC | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 702(685 LUTs, 17 ALUs) / 1728 | 41% |
| Register | 449 / 1548 | 29% |
| --Register as Latch | 0 / 1548 | 0% |
| --Register as FF | 449 / 1548 | 29% |
| BSRAM | 4 / 4 | 100% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | DEFAULT_CLK | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | 50.0(MHz) | 53.5(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.662 |
| Data Arrival Time | 9.892 |
| Data Required Time | 10.554 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
| Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0/CLK |
| 1.481 | 0.573 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0/Q |
| 2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n1007_s1/I1 |
| 3.455 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n1007_s1/F |
| 4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s4/I1 |
| 5.429 | 1.374 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s4/F |
| 6.029 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
| 7.402 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
| 8.002 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I0 |
| 9.292 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F |
| 9.892 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK |
| 10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
| Clock Skew: | 0.146 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 2
Path Summary:| Slack | 0.662 |
| Data Arrival Time | 9.892 |
| Data Required Time | 10.554 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
| Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0/CLK |
| 1.481 | 0.573 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpha_s0/Q |
| 2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n1007_s1/I1 |
| 3.455 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n1007_s1/F |
| 4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s4/I1 |
| 5.429 | 1.374 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s4/F |
| 6.029 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
| 7.402 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
| 8.002 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0 |
| 9.292 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F |
| 9.892 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK |
| 10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
| Clock Skew: | 0.146 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 3
Path Summary:| Slack | 1.253 |
| Data Arrival Time | 9.301 |
| Data Required Time | 10.554 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_3_s1 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_3_s1/CLK |
| 1.481 | 0.573 | tC2Q | RF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_3_s1/Q |
| 2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/wait_one_tick_done_s5/I1 |
| 3.455 | 1.374 | tINS | FF | 3 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/wait_one_tick_done_s5/F |
| 4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/I1 |
| 5.429 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/F |
| 6.029 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/I0 |
| 7.319 | 1.290 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/F |
| 7.919 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s13/I3 |
| 8.701 | 0.782 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s13/F |
| 9.301 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| Clock Skew: | 0.146 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
| Arrival Data Path Delay: | cell: 4.820, 57.430%; route: 3.000, 35.744%; tC2Q: 0.573, 6.826% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 4
Path Summary:| Slack | 2.952 |
| Data Arrival Time | 17.456 |
| Data Required Time | 20.408 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
| Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 11.627 | 0.573 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
| 12.227 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I1 |
| 13.601 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
| 14.201 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I2 |
| 15.229 | 1.028 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
| 15.829 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/I2 |
| 16.856 | 1.028 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/F |
| 17.456 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 20.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 20.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/CLK |
| 20.408 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
| Clock Skew: | -0.146 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
| Arrival Data Path Delay: | cell: 3.429, 53.561%; route: 2.400, 37.490%; tC2Q: 0.573, 8.949% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
Path 5
Path Summary:| Slack | 3.197 |
| Data Arrival Time | 17.211 |
| Data Required Time | 20.408 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
| Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 11.627 | 0.573 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
| 12.227 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I1 |
| 13.601 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
| 14.201 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I2 |
| 15.229 | 1.028 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
| 15.829 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/I3 |
| 16.611 | 0.782 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/F |
| 17.211 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 20.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
| 20.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/CLK |
| 20.408 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
| Clock Skew: | -0.146 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
| Arrival Data Path Delay: | cell: 3.184, 51.712%; route: 2.400, 38.982%; tC2Q: 0.573, 9.306% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |