Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.8Beta |
Part Number | GW1NSE-UX2CLQ144C5/I4 |
Device | GW1NSE-2C |
Created Time | Wed Jul 14 16:01:41 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.082MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 44.082MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 44.082MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 44.082MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 44.082MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.082MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.082MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 44.082MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.082MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 44.082MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.082MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 44.082MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 57.836MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 57.836MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 57.836MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 57.836MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 248 |
I/O Buf | 248 |
    IBUF | 78 |
    OBUF | 152 |
    IOBUF | 18 |
Register | 441 |
    DFF | 1 |
    DFFE | 1 |
    DFFP | 7 |
    DFFPE | 31 |
    DFFC | 99 |
    DFFCE | 299 |
    DFFNCE | 3 |
LUT | 646 |
    LUT2 | 83 |
    LUT3 | 165 |
    LUT4 | 398 |
ALU | 18 |
    ALU | 18 |
INV | 20 |
    INV | 20 |
BSRAM | 4 |
    SP | 4 |
CLOCK | 2 |
    CLKDIV | 1 |
    DQCE | 1 |
User Flash | 1 |
    FLASH128K | 1 |
MCU | 1 |
ADC | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 684(666 LUTs, 18 ALUs) / 1728 | 40% |
Register | 441 / 1533 | 29% |
  --Register as Latch | 0 / 1533 | 0% |
  --Register as FF | 441 / 1533 | 29% |
BSRAM | 4 / 4 | 100% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | DEFAULT_CLK | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | 50.0(MHz) | 54.0(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.746 |
Data Arrival Time | 9.809 |
Data Required Time | 10.554 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/CLK |
1.481 | 0.573 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/Q |
2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/I1 |
3.455 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/F |
4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/I0 |
5.345 | 1.290 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/F |
5.945 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
7.319 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
7.919 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I0 |
9.209 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F |
9.809 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK |
10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
Clock Skew: | 0.146 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Arrival Data Path Delay: | cell: 5.327, 59.857%; route: 3.000, 33.706%; tC2Q: 0.573, 6.437% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 2
Path Summary:Slack | 0.746 |
Data Arrival Time | 9.809 |
Data Required Time | 10.554 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/CLK |
1.481 | 0.573 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/Q |
2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/I1 |
3.455 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/F |
4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/I0 |
5.345 | 1.290 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/F |
5.945 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1 |
7.319 | 1.374 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F |
7.919 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0 |
9.209 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F |
9.809 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK |
10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
Clock Skew: | 0.146 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Arrival Data Path Delay: | cell: 5.327, 59.857%; route: 3.000, 33.706%; tC2Q: 0.573, 6.437% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 3
Path Summary:Slack | 1.008 |
Data Arrival Time | 9.546 |
Data Required Time | 10.554 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
0.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
0.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/CLK |
1.481 | 0.573 | tC2Q | RF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/Q |
2.081 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/I1 |
3.455 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/F |
4.055 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/I0 |
5.345 | 1.290 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s16/F |
5.945 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/I2 |
6.972 | 1.028 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/F |
7.572 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I1 |
8.946 | 1.374 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F |
9.546 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
10.554 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
Clock Skew: | 0.146 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Arrival Data Path Delay: | cell: 5.065, 58.636%; route: 3.000, 34.731%; tC2Q: 0.573, 6.633% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.454, 100.000% |
Path 4
Path Summary:Slack | 2.690 |
Data Arrival Time | 17.719 |
Data Required Time | 20.408 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
11.627 | 0.573 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
12.227 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I0 |
13.517 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
14.117 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I1 |
15.491 | 1.374 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
16.091 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/I2 |
17.119 | 1.028 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/F |
17.719 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
20.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
20.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/CLK |
20.408 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
Clock Skew: | -0.146 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
Arrival Data Path Delay: | cell: 3.691, 55.389%; route: 2.400, 36.014%; tC2Q: 0.573, 8.597% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
Path 5
Path Summary:Slack | 2.935 |
Data Arrival Time | 17.474 |
Data Required Time | 20.408 |
From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
Launch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R] |
Latch Clk | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
10.454 | 0.454 | tCL | FF | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
11.054 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
11.627 | 0.573 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
12.227 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I0 |
13.517 | 1.290 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
14.117 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I1 |
15.491 | 1.374 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
16.091 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/I3 |
16.874 | 0.782 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/F |
17.474 | 0.600 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk | |||
20.454 | 0.454 | tCL | RR | 448 | Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT |
20.908 | 0.454 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/CLK |
20.408 | -0.500 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
Clock Skew: | -0.146 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |
Arrival Data Path Delay: | cell: 3.446, 53.687%; route: 2.400, 37.388%; tC2Q: 0.573, 8.925% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.600, 100.000% |