Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\PSRAM\data\psram_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8Beta
Part Number GW1NSR-LX2CQN48PC5/I4
Device GW1NSR-2C
Created Time Wed Jul 14 16:16:04 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PSRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 40.426MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 40.426MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 40.426MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 40.426MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 40.426MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 40.426MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 40.426MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 40.426MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.426MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 40.426MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 40.426MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 40.426MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.027MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 55.027MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 55.027MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.027MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 98
Embedded Port 13
I/O Buf 110
    IBUF 63
    OBUF 37
    IOBUF 9
    ELVDS_OBUF 1
Register 387
    DFFP 2
    DFFPE 4
    DFFC 235
    DFFCE 146
LUT 619
    LUT2 223
    LUT3 138
    LUT4 258
ALU 31
    ALU 31
SSRAM 9
    RAM16SDP4 9
INV 4
    INV 4
IOLOGIC 28
    IDES4 8
    OSER4 11
    IODELAY 9
CLOCK 3
    DLL 1
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 708(623 LUTs, 31 ALUs, 9 SSRAMs) / 1728 41%
Register 387 / 1437 27%
  --Register as Latch 0 / 1437 0%
  --Register as FF 387 / 1437 27%
BSRAM 0 / 4 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 96.5(MHz) 6 TOP
2 u_psram_top/clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 100.7(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.359
Data Arrival Time 11.540
Data Required Time 11.181
From u_psram_top/u_psram_sync/flag_0_s0
To u_psram_top/u_psram_sync/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
1.227 1.227 tINS RR 31 clk_ibuf/O
1.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/flag_0_s0/CLK
2.254 0.573 tC2Q RF 11 u_psram_top/u_psram_sync/flag_0_s0/Q
2.854 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s15/I1
4.228 1.374 tINS FF 2 u_psram_top/u_psram_sync/n316_s15/F
4.828 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s14/I1
6.202 1.374 tINS FF 1 u_psram_top/u_psram_sync/n316_s14/F
6.802 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s3/I3
7.584 0.782 tINS FF 1 u_psram_top/u_psram_sync/n390_s3/F
8.184 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s2/I3
8.967 0.782 tINS FF 3 u_psram_top/u_psram_sync/n390_s2/F
9.567 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s1/I1
10.940 1.374 tINS FF 1 u_psram_top/u_psram_sync/n390_s1/F
11.540 0.600 tNET FF 1 u_psram_top/u_psram_sync/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
11.227 1.227 tINS RR 31 clk_ibuf/O
11.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/count_0_s0/CLK
11.181 -0.500 tSu 1 u_psram_top/u_psram_sync/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 5.686, 57.675%; route: 3.600, 36.514%; tC2Q: 0.573, 5.811%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 2

Path Summary:
Slack -0.258
Data Arrival Time 11.439
Data Required Time 11.181
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_14_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
1.227 1.227 tINS RR 31 clk_ibuf/O
1.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
2.254 0.573 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
2.854 0.600 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
4.228 1.374 tINS FF 4 u_psram_top/u_psram_sync/n47_s2/F
4.828 0.600 tNET FF 1 u_psram_top/u_psram_sync/n43_s2/I2
5.855 1.028 tINS FF 4 u_psram_top/u_psram_sync/n43_s2/F
6.455 0.600 tNET FF 1 u_psram_top/u_psram_sync/n42_s2/I1
7.829 1.374 tINS FF 3 u_psram_top/u_psram_sync/n42_s2/F
8.429 0.600 tNET FF 1 u_psram_top/u_psram_sync/n37_s2/I2
9.457 1.028 tINS FF 2 u_psram_top/u_psram_sync/n37_s2/F
10.057 0.600 tNET FF 1 u_psram_top/u_psram_sync/n37_s5/I3
10.839 0.782 tINS FF 1 u_psram_top/u_psram_sync/n37_s5/F
11.439 0.600 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_14_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
11.227 1.227 tINS RR 31 clk_ibuf/O
11.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_14_s3/CLK
11.181 -0.500 tSu 1 u_psram_top/u_psram_sync/lock_cnt_14_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 5.585, 57.236%; route: 3.600, 36.893%; tC2Q: 0.573, 5.871%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 3

Path Summary:
Slack -0.258
Data Arrival Time 11.439
Data Required Time 11.181
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_15_s4
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
1.227 1.227 tINS RR 31 clk_ibuf/O
1.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
2.254 0.573 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
2.854 0.600 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
4.228 1.374 tINS FF 4 u_psram_top/u_psram_sync/n47_s2/F
4.828 0.600 tNET FF 1 u_psram_top/u_psram_sync/n43_s2/I2
5.855 1.028 tINS FF 4 u_psram_top/u_psram_sync/n43_s2/F
6.455 0.600 tNET FF 1 u_psram_top/u_psram_sync/n42_s2/I1
7.829 1.374 tINS FF 3 u_psram_top/u_psram_sync/n42_s2/F
8.429 0.600 tNET FF 1 u_psram_top/u_psram_sync/n37_s2/I2
9.457 1.028 tINS FF 2 u_psram_top/u_psram_sync/n37_s2/F
10.057 0.600 tNET FF 1 u_psram_top/u_psram_sync/n36_s4/I3
10.839 0.782 tINS FF 1 u_psram_top/u_psram_sync/n36_s4/F
11.439 0.600 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_15_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
11.227 1.227 tINS RR 31 clk_ibuf/O
11.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_15_s4/CLK
11.181 -0.500 tSu 1 u_psram_top/u_psram_sync/lock_cnt_15_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 5.585, 57.236%; route: 3.600, 36.893%; tC2Q: 0.573, 5.871%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 4

Path Summary:
Slack -0.013
Data Arrival Time 11.194
Data Required Time 11.181
From u_psram_top/u_psram_sync/flag_0_s0
To u_psram_top/u_psram_sync/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
1.227 1.227 tINS RR 31 clk_ibuf/O
1.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/flag_0_s0/CLK
2.254 0.573 tC2Q RF 11 u_psram_top/u_psram_sync/flag_0_s0/Q
2.854 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s15/I1
4.228 1.374 tINS FF 2 u_psram_top/u_psram_sync/n316_s15/F
4.828 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s14/I1
6.202 1.374 tINS FF 1 u_psram_top/u_psram_sync/n316_s14/F
6.802 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s3/I3
7.584 0.782 tINS FF 1 u_psram_top/u_psram_sync/n390_s3/F
8.184 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s2/I3
8.967 0.782 tINS FF 3 u_psram_top/u_psram_sync/n390_s2/F
9.567 0.600 tNET FF 1 u_psram_top/u_psram_sync/n389_s1/I2
10.594 1.028 tINS FF 1 u_psram_top/u_psram_sync/n389_s1/F
11.194 0.600 tNET FF 1 u_psram_top/u_psram_sync/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
11.227 1.227 tINS RR 31 clk_ibuf/O
11.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/count_1_s0/CLK
11.181 -0.500 tSu 1 u_psram_top/u_psram_sync/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 5.340, 56.134%; route: 3.600, 37.843%; tC2Q: 0.573, 6.023%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 5

Path Summary:
Slack 0.232
Data Arrival Time 10.949
Data Required Time 11.181
From u_psram_top/u_psram_sync/flag_0_s0
To u_psram_top/u_psram_sync/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
1.227 1.227 tINS RR 31 clk_ibuf/O
1.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/flag_0_s0/CLK
2.254 0.573 tC2Q RF 11 u_psram_top/u_psram_sync/flag_0_s0/Q
2.854 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s15/I1
4.228 1.374 tINS FF 2 u_psram_top/u_psram_sync/n316_s15/F
4.828 0.600 tNET FF 1 u_psram_top/u_psram_sync/n316_s14/I1
6.202 1.374 tINS FF 1 u_psram_top/u_psram_sync/n316_s14/F
6.802 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s3/I3
7.584 0.782 tINS FF 1 u_psram_top/u_psram_sync/n390_s3/F
8.184 0.600 tNET FF 1 u_psram_top/u_psram_sync/n390_s2/I3
8.967 0.782 tINS FF 3 u_psram_top/u_psram_sync/n390_s2/F
9.567 0.600 tNET FF 1 u_psram_top/u_psram_sync/n388_s1/I3
10.349 0.782 tINS FF 1 u_psram_top/u_psram_sync/n388_s1/F
10.949 0.600 tNET FF 1 u_psram_top/u_psram_sync/count_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
11.227 1.227 tINS RR 31 clk_ibuf/O
11.681 0.454 tNET RR 1 u_psram_top/u_psram_sync/count_2_s0/CLK
11.181 -0.500 tSu 1 u_psram_top/u_psram_sync/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 5.095, 54.974%; route: 3.600, 38.844%; tC2Q: 0.573, 6.182%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%