#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
#OS: Linux 
#Hostname: JINAN9100.sdgowin.com

# Tue Jul 30 08:55:41 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:16:24

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:16:24

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/generic/gw1ns.v" (library work)
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/GOWIN_EMPU/data/gowin_empu.v" (library work)
@I:"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/GOWIN_EMPU/data/gowin_empu.v":"/home/liukai/gowin_empu/src/gowin_empu/temp/gw_empu/config.v" (library work)
@I:"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/GOWIN_EMPU/data/gowin_empu.v":"/home/liukai/gowin_empu/src/gowin_empu/temp/gw_empu/gowin_empu_name.v" (library work)
@W:CG1337 : gowin_empu.v(1423) | Net master_pse11 is not declared.
@N:CG347 : gowin_empu.v(4335) | Read a parallel_case directive.
@W:CS141 : gowin_empu.v(4544) | Unrecognized synthesis directive enum_state. Verify the correct directive name.
@N:CG346 : gowin_empu.v(4575) | Read full_case directive.
@N:CG347 : gowin_empu.v(4575) | Read a parallel_case directive.
@W:CS141 : gowin_empu.v(4770) | Unrecognized synthesis directive enum_state. Verify the correct directive name.
@N:CG346 : gowin_empu.v(4967) | Read full_case directive.
@N:CG347 : gowin_empu.v(4967) | Read a parallel_case directive.
@N:CG346 : gowin_empu.v(4971) | Read full_case directive.
@N:CG347 : gowin_empu.v(4971) | Read a parallel_case directive.
@W:CG286 : gowin_empu.v(4971) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
@I::"/share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/GOWIN_EMPU/data/gowin_empu_top.v" (library work)
Verilog syntax check successful!
Selecting top level module Gowin_EMPU_Top
Running optimization stage 1 on GSR .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on GW_CLKDIV .......
Running optimization stage 1 on MCU .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on GW_GPIO .......
Running optimization stage 1 on DQCE .......
Running optimization stage 1 on FLASH128K .......
Running optimization stage 1 on gw_rom_flash_15s_32s .......
Running optimization stage 1 on GW_FLASH .......
Running optimization stage 1 on SP .......
Running optimization stage 1 on GW_SRAM4 .......
Running optimization stage 1 on GW_CLKDIV_ADC .......
Running optimization stage 1 on OSCF .......
Running optimization stage 1 on GW_OSC .......
Running optimization stage 1 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 1 on gw_int_apb2_decoder_8s .......
Running optimization stage 1 on ADC .......
Running optimization stage 1 on gw_cmsdk_apb2_adc .......
Running optimization stage 1 on i2c_master_bit_ctrl .......
Running optimization stage 1 on i2c_master_byte_ctrl .......
Running optimization stage 1 on gw_apb_i2c .......
Running optimization stage 1 on SPI_Z2 .......
Running optimization stage 1 on gw_cmsdk_apb2_spi .......
Running optimization stage 1 on cmsdk_apb_uart .......
Running optimization stage 1 on gw_peripherals_interconnect_12s .......
Running optimization stage 1 on \~Gowin_EMPU.Gowin_EMPU_Top  .......
@N:CG364 : gowin_empu_top.v(3) | Synthesizing module Gowin_EMPU_Top in library work.
Running optimization stage 1 on Gowin_EMPU_Top .......
Running optimization stage 2 on Gowin_EMPU_Top .......
Running optimization stage 2 on \~Gowin_EMPU.Gowin_EMPU_Top  .......
Running optimization stage 2 on gw_peripherals_interconnect_12s .......
Running optimization stage 2 on cmsdk_apb_uart .......
Running optimization stage 2 on gw_cmsdk_apb2_spi .......
Running optimization stage 2 on SPI_Z2 .......
Running optimization stage 2 on gw_apb_i2c .......
Running optimization stage 2 on i2c_master_byte_ctrl .......
Extracted state machine for register c_state
State machine has 6 reachable states with original encodings of:
   00000
   00001
   00010
   00100
   01000
   10000
Running optimization stage 2 on i2c_master_bit_ctrl .......
Extracted state machine for register c_state
State machine has 18 reachable states with original encodings of:
   000000000000000000
   000000000000000001
   000000000000000010
   000000000000000100
   000000000000001000
   000000000000010000
   000000000000100000
   000000000001000000
   000000000010000000
   000000000100000000
   000000001000000000
   000000010000000000
   000000100000000000
   000001000000000000
   000010000000000000
   000100000000000000
   001000000000000000
   010000000000000000
Running optimization stage 2 on gw_cmsdk_apb2_adc .......
Running optimization stage 2 on ADC .......
Running optimization stage 2 on gw_int_apb2_decoder_8s .......
Running optimization stage 2 on gw_cmsdk_apb2_slave_mux_Z1 .......
Running optimization stage 2 on GW_OSC .......
Running optimization stage 2 on OSCF .......
Running optimization stage 2 on GW_CLKDIV_ADC .......
Running optimization stage 2 on GW_SRAM4 .......
Running optimization stage 2 on SP .......
Running optimization stage 2 on GW_FLASH .......
Running optimization stage 2 on gw_rom_flash_15s_32s .......
Running optimization stage 2 on FLASH128K .......
Running optimization stage 2 on DQCE .......
Running optimization stage 2 on GW_GPIO .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on MCU .......
Running optimization stage 2 on GW_CLKDIV .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Jul 30 08:55:42 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:16:24

@N: :  | Running in 64-bit mode 
@N:NF107 : gowin_empu_top.v(3) | Selected library: work cell: Gowin_EMPU_Top view verilog as top level
@N:NF107 : gowin_empu_top.v(3) | Selected library: work cell: Gowin_EMPU_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Jul 30 08:55:43 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Jul 30 08:55:43 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:16:24

@N: :  | Running in 64-bit mode 
@N:NF107 : gowin_empu_top.v(3) | Selected library: work cell: Gowin_EMPU_Top view verilog as top level
@N:NF107 : gowin_empu_top.v(3) | Selected library: work cell: Gowin_EMPU_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Jul 30 08:55:44 2019

###########################################################]


Premap Report



# Tue Jul 30 08:55:44 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1312R, Built Mar 13 2019 02:07:26


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  gowin_empu_scck.rpt
Printing clock  summary report in "/home/liukai/gowin_empu/src/gowin_empu/temp/gw_empu/rev_1/gowin_empu_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 106MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 120MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)



Clock Summary
******************

          Start                                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                                   Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------------------------
0 -       System                                  247.0 MHz     4.049         system       system_clkgroup           0    
                                                                                                                          
0 -       GW_CLKDIV|clkout_inferred_clock         100.0 MHz     10.000        inferred     Autoconstr_clkgroup_0     440  
                                                                                                                          
0 -       GW_CLKDIV_ADC|clkout_inferred_clock     197.3 MHz     5.070         inferred     Autoconstr_clkgroup_1     8    
==========================================================================================================================



Clock Load Summary
***********************

                                        Clock     Source                                                    Clock Pin                                                                              Non-clock Pin     Non-clock Pin                                                                              
Clock                                   Load      Pin                                                       Seq Example                                                                            Seq Example       Comb Example                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                  0         -                                                         -                                                                                      -                 -                                                                                          
                                                                                                                                                                                                                                                                                                                
GW_CLKDIV|clkout_inferred_clock         440       Gowin_EMPU_inst.sysclk.clkdiv_inst.CLKOUT(CLKDIV)         Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.rx_shift_buf[6:0].C     -                 Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.un1_CLK_I.I[0](inv)
                                                                                                                                                                                                                                                                                                                
GW_CLKDIV_ADC|clkout_inferred_clock     8         Gowin_EMPU_inst.adc_clkdiv.clkdiv_inst.CLKOUT(CLKDIV)     Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.soc_once.C           -                 -                                                                                          
================================================================================================================================================================================================================================================================================================================


@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /home/liukai/gowin_empu/src/gowin_empu/temp/gw_empu/rev_1/gowin_empu.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 196MB)

Encoding state machine c_state[17:0] (in view: work.i2c_master_bit_ctrl(verilog))
original code -> new code
   000000000000000000 -> 000000000000000001
   000000000000000001 -> 000000000000000010
   000000000000000010 -> 000000000000000100
   000000000000000100 -> 000000000000001000
   000000000000001000 -> 000000000000010000
   000000000000010000 -> 000000000000100000
   000000000000100000 -> 000000000001000000
   000000000001000000 -> 000000000010000000
   000000000010000000 -> 000000000100000000
   000000000100000000 -> 000000001000000000
   000000001000000000 -> 000000010000000000
   000000010000000000 -> 000000100000000000
   000000100000000000 -> 000001000000000000
   000001000000000000 -> 000010000000000000
   000010000000000000 -> 000100000000000000
   000100000000000000 -> 001000000000000000
   001000000000000000 -> 010000000000000000
   010000000000000000 -> 100000000000000000
Encoding state machine c_state[5:0] (in view: work.i2c_master_byte_ctrl(verilog))
original code -> new code
   00000 -> 000001
   00001 -> 000010
   00010 -> 000100
   00100 -> 001000
   01000 -> 010000
   10000 -> 100000

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 196MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 196MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 196MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Jul 30 08:55:47 2019

###########################################################]


Map & Optimize Report



# Tue Jul 30 08:55:47 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: /share/gwsw/gowin_new/trunk/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: JINAN9100.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1312R, Built Mar 13 2019 02:07:26


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 194MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)

Encoding state machine c_state[5:0] (in view: work.i2c_master_byte_ctrl(verilog))
original code -> new code
   00000 -> 000001
   00001 -> 000010
   00010 -> 000100
   00100 -> 001000
   01000 -> 010000
   10000 -> 100000
Encoding state machine c_state[17:0] (in view: work.i2c_master_bit_ctrl(verilog))
original code -> new code
   000000000000000000 -> 000000000000000001
   000000000000000001 -> 000000000000000010
   000000000000000010 -> 000000000000000100
   000000000000000100 -> 000000000000001000
   000000000000001000 -> 000000000000010000
   000000000000010000 -> 000000000000100000
   000000000000100000 -> 000000000001000000
   000000000001000000 -> 000000000010000000
   000000000010000000 -> 000000000100000000
   000000000100000000 -> 000000001000000000
   000000001000000000 -> 000000010000000000
   000000010000000000 -> 000000100000000000
   000000100000000000 -> 000001000000000000
   000001000000000000 -> 000010000000000000
   000010000000000000 -> 000100000000000000
   000100000000000000 -> 001000000000000000
   001000000000000000 -> 010000000000000000
   010000000000000000 -> 100000000000000000

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 208MB peak: 209MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 209MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 201MB peak: 209MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 203MB peak: 209MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 204MB peak: 209MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 205MB peak: 209MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 204MB peak: 209MB)


Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 204MB peak: 209MB)


Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 219MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -3.34ns		 703 /       440
   2		0h:00m:04s		    -3.34ns		 702 /       440
   3		0h:00m:04s		    -3.34ns		 700 /       440
   4		0h:00m:04s		    -3.34ns		 700 /       440
   5		0h:00m:04s		    -3.34ns		 700 /       440
   6		0h:00m:04s		    -3.34ns		 700 /       440
Timing driven replication report
Added 0 Registers via timing driven replication
Added 1 LUTs via timing driven replication

   7		0h:00m:05s		    -3.09ns		 712 /       440
   8		0h:00m:05s		    -3.09ns		 712 /       440
   9		0h:00m:05s		    -3.09ns		 714 /       440
  10		0h:00m:05s		    -3.09ns		 716 /       440
  11		0h:00m:05s		    -3.09ns		 717 /       440


  12		0h:00m:05s		    -3.09ns		 718 /       440
  13		0h:00m:05s		    -3.09ns		 720 /       440
  14		0h:00m:05s		    -3.09ns		 720 /       440
  15		0h:00m:05s		    -3.09ns		 720 /       440
  16		0h:00m:06s		    -3.09ns		 720 /       440

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 217MB peak: 219MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 217MB peak: 219MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 444 clock pin(s) of sequential element(s)
0 instances converted, 444 sequential instances remain driven by gated/generated clocks

====================================================================================================================================== Gated/Generated Clocks =======================================================================================================================================
Clock Tree ID     Driving Element                            Drive Element Type     Fanout     Sample Instance                                                                         Explanation                                                                                                   
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        Gowin_EMPU_inst.sysclk.clkdiv_inst         CLKDIV                 436        Gowin_EMPU_inst.u_flash_wrap.rom_haddr_test[7]                                          Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
ClockId0002        Gowin_EMPU_inst.adc_clkdiv.clkdiv_inst     CLKDIV                 8          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[0]     Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
=====================================================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 143MB peak: 219MB)

Writing Analyst data base /home/liukai/gowin_empu/src/gowin_empu/temp/gw_empu/rev_1/synwork/gowin_empu_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 215MB peak: 219MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 215MB peak: 219MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 213MB peak: 219MB)


Start final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 213MB peak: 219MB)

@W:MT246 : gowin_empu.v(399) | Blackbox MCU is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(2299) | Blackbox ADC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(5150) | Blackbox OSCF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(1160) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(785) | Blackbox DQCE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(865) | Blackbox FLASH128K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock GW_CLKDIV|clkout_inferred_clock with period 9.37ns. Please declare a user-defined clock on net Gowin_EMPU_inst.sysclk.fclk. 
@W:MT420 :  | Found inferred clock GW_CLKDIV_ADC|clkout_inferred_clock with period 4.12ns. Please declare a user-defined clock on net Gowin_EMPU_inst.adc_clkdiv.adc_clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Jul 30 08:55:57 2019
#


Top view:               Gowin_EMPU_Top
Requested Frequency:    106.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -3.567

                                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                          Frequency     Frequency     Period        Period        Slack      Type         Group                
---------------------------------------------------------------------------------------------------------------------------------------------
GW_CLKDIV_ADC|clkout_inferred_clock     242.5 MHz     206.1 MHz     4.123         4.851         -0.728     inferred     Autoconstr_clkgroup_1
GW_CLKDIV|clkout_inferred_clock         106.7 MHz     60.6 MHz      9.373         16.507        -3.567     inferred     Autoconstr_clkgroup_0
System                                  161.0 MHz     136.8 MHz     6.212         7.309         -1.096     system       system_clkgroup      
=============================================================================================================================================





Clock Relationships
*******************

Clocks                                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise  
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                             Ending                               |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                               System                               |  6.212       -1.096  |  No paths    -      |  No paths    -       |  No paths    -     
System                               GW_CLKDIV|clkout_inferred_clock      |  9.373       -0.660  |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV|clkout_inferred_clock      System                               |  9.373       2.689   |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV|clkout_inferred_clock      GW_CLKDIV|clkout_inferred_clock      |  9.373       -1.654  |  No paths    -      |  4.686       -3.567  |  4.686       -0.819
GW_CLKDIV|clkout_inferred_clock      GW_CLKDIV_ADC|clkout_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV_ADC|clkout_inferred_clock  System                               |  4.123       2.735   |  No paths    -      |  No paths    -       |  No paths    -     
GW_CLKDIV_ADC|clkout_inferred_clock  GW_CLKDIV_ADC|clkout_inferred_clock  |  4.123       -0.728  |  No paths    -      |  No paths    -       |  No paths    -     
===================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_CLKDIV_ADC|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                        Starting                                                                       Arrival           
Instance                                                                                Reference                               Type     Pin     Net                   Time        Slack 
                                                                                        Clock                                                                                            
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[3]     0.367       -0.728
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[2]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[2]     0.367       -0.660
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[4]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[4]     0.367       -0.451
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[1]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[1]     0.367       -0.334
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[0]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[0]     0.367       -0.294
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[5]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[5]     0.367       -0.194
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       count_sampling[6]     0.367       -0.194
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.soc_once              GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     Q       soc_once              0.367       2.735 
=========================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                        Starting                                                                                 Required           
Instance                                                                                Reference                               Type     Pin     Net                             Time         Slack 
                                                                                        Clock                                                                                                       
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[5]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       count_sampling_3[5]             3.990        -0.728
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       count_sampling_3[6]             3.990        -0.728
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[4]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       un1_count_sampling_2_axbxc4     3.990        -0.422
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.soc_once              GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       soc_once5                       3.990        -0.355
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[0]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       un1_count_sampling_2_axbxc0     3.990        -0.145
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       un1_count_sampling_2_axbxc3     3.990        -0.145
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[1]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       un1_count_sampling_2_axbxc1     3.990        1.442 
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[2]     GW_CLKDIV_ADC|clkout_inferred_clock     DFFC     D       un1_count_sampling_2_axbxc2     3.990        1.442 
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.u_S55NLLAD2A          GW_CLKDIV_ADC|clkout_inferred_clock     ADC      SOC     soc_once                        4.123        2.735 
====================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.123
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.990

    - Propagation time:                      4.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.728

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[5] / D
    The start point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                   Pin      Pin               Arrival     No. of    
Name                                                                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]                DFFC          Q        Out     0.367     0.367       -         
count_sampling[3]                                                                                  Net           -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1_0_0     LUT4          I1       In      -         1.449       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1_0_0     LUT4          F        Out     1.099     2.548       -         
count_sampling_0_N_2L1_1_0_0                                                                       Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1_0       MUX2_LUT5     I0       In      -         2.548       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1_0       MUX2_LUT5     O        Out     0.150     2.698       -         
count_sampling_0_N_2L1_1_0                                                                         Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1         MUX2_LUT6     I0       In      -         2.698       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_1         MUX2_LUT6     O        Out     0.177     2.875       -         
count_sampling_0_1_0[5]                                                                            Net           -        -       1.021     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[5]              LUT4          I2       In      -         3.896       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[5]              LUT4          F        Out     0.822     4.718       -         
count_sampling_3[5]                                                                                Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[5]                DFFC          D        In      -         4.718       -         
==================================================================================================================================================================
Total path delay (propagation time + setup) of 4.851 is 2.748(56.6%) logic and 2.103(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.123
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.990

    - Propagation time:                      4.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.728

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6] / D
    The start point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                   Pin      Pin               Arrival     No. of    
Name                                                                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]                DFFC          Q        Out     0.367     0.367       -         
count_sampling[3]                                                                                  Net           -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0_1     LUT4          I1       In      -         1.449       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0_1     LUT4          F        Out     1.099     2.548       -         
count_sampling_0_N_2L1_2_0_1                                                                       Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0       MUX2_LUT5     I1       In      -         2.548       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0       MUX2_LUT5     O        Out     0.150     2.698       -         
count_sampling_0_N_2L1_2_0                                                                         Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     I0       In      -         2.698       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     O        Out     0.177     2.875       -         
count_sampling_0_N_2L1_2                                                                           Net           -        -       1.021     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          I2       In      -         3.896       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          F        Out     0.822     4.718       -         
count_sampling_3[6]                                                                                Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]                DFFC          D        In      -         4.718       -         
==================================================================================================================================================================
Total path delay (propagation time + setup) of 4.851 is 2.748(56.6%) logic and 2.103(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.123
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.990

    - Propagation time:                      4.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.728

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6] / D
    The start point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                   Pin      Pin               Arrival     No. of    
Name                                                                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]                DFFC          Q        Out     0.367     0.367       -         
count_sampling[3]                                                                                  Net           -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0_0     LUT4          I1       In      -         1.449       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0_0     LUT4          F        Out     1.099     2.548       -         
count_sampling_0_N_2L1_2_0_0                                                                       Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0       MUX2_LUT5     I0       In      -         2.548       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_0       MUX2_LUT5     O        Out     0.150     2.698       -         
count_sampling_0_N_2L1_2_0                                                                         Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     I0       In      -         2.698       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     O        Out     0.177     2.875       -         
count_sampling_0_N_2L1_2                                                                           Net           -        -       1.021     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          I2       In      -         3.896       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          F        Out     0.822     4.718       -         
count_sampling_3[6]                                                                                Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]                DFFC          D        In      -         4.718       -         
==================================================================================================================================================================
Total path delay (propagation time + setup) of 4.851 is 2.748(56.6%) logic and 2.103(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.123
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.990

    - Propagation time:                      4.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.728

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6] / D
    The start point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                   Pin      Pin               Arrival     No. of    
Name                                                                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]                DFFC          Q        Out     0.367     0.367       -         
count_sampling[3]                                                                                  Net           -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1_1     LUT4          I1       In      -         1.449       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1_1     LUT4          F        Out     1.099     2.548       -         
count_sampling_0_N_2L1_2_1_1                                                                       Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1       MUX2_LUT5     I1       In      -         2.548       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1       MUX2_LUT5     O        Out     0.150     2.698       -         
count_sampling_0_N_2L1_2_1                                                                         Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     I1       In      -         2.698       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     O        Out     0.177     2.875       -         
count_sampling_0_N_2L1_2                                                                           Net           -        -       1.021     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          I2       In      -         3.896       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          F        Out     0.822     4.718       -         
count_sampling_3[6]                                                                                Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]                DFFC          D        In      -         4.718       -         
==================================================================================================================================================================
Total path delay (propagation time + setup) of 4.851 is 2.748(56.6%) logic and 2.103(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.123
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.990

    - Propagation time:                      4.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.728

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6] / D
    The start point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV_ADC|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                   Pin      Pin               Arrival     No. of    
Name                                                                                               Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[3]                DFFC          Q        Out     0.367     0.367       -         
count_sampling[3]                                                                                  Net           -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1_0     LUT4          I1       In      -         1.449       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1_0     LUT4          F        Out     1.099     2.548       -         
count_sampling_0_N_2L1_2_1_0                                                                       Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1       MUX2_LUT5     I0       In      -         2.548       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2_1       MUX2_LUT5     O        Out     0.150     2.698       -         
count_sampling_0_N_2L1_2_1                                                                         Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     I1       In      -         2.698       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0_N_2L1_2         MUX2_LUT6     O        Out     0.177     2.875       -         
count_sampling_0_N_2L1_2                                                                           Net           -        -       1.021     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          I2       In      -         3.896       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling_0[6]              LUT4          F        Out     0.822     4.718       -         
count_sampling_3[6]                                                                                Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_adc.count_sampling[6]                DFFC          D        In      -         4.718       -         
==================================================================================================================================================================
Total path delay (propagation time + setup) of 4.851 is 2.748(56.6%) logic and 2.103(43.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: GW_CLKDIV|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                  Starting                                                               Arrival           
Instance                                                                                          Reference                           Type      Pin     Net              Time        Slack 
                                                                                                  Clock                                                                                    
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[2]      GW_CLKDIV|clkout_inferred_clock     DFFC      Q       data_cnt[2]      0.367       -3.567
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[1]      GW_CLKDIV|clkout_inferred_clock     DFFC      Q       data_cnt[1]      0.367       -3.500
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[0]     GW_CLKDIV|clkout_inferred_clock     DFFC      Q       clock_cnt[0]     0.367       -3.500
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_sel[0]              GW_CLKDIV|clkout_inferred_clock     DFFCE     Q       clock_sel[0]     0.367       -3.433
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[3]      GW_CLKDIV|clkout_inferred_clock     DFFC      Q       data_cnt[3]      0.367       -3.290
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[2]     GW_CLKDIV|clkout_inferred_clock     DFFC      Q       clock_cnt[2]     0.367       -3.223
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[4]      GW_CLKDIV|clkout_inferred_clock     DFFC      Q       data_cnt[4]      0.367       -3.221
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[0]      GW_CLKDIV|clkout_inferred_clock     DFFC      Q       data_cnt[0]      0.367       -3.061
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[3]     GW_CLKDIV|clkout_inferred_clock     DFFC      Q       clock_cnt[3]     0.367       -3.027
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[1]     GW_CLKDIV|clkout_inferred_clock     DFFC      Q       clock_cnt[1]     0.367       -2.966
===========================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                 Starting                                                                         Required           
Instance                                                                                         Reference                           Type       Pin     Net                       Time         Slack 
                                                                                                 Clock                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     D       n_status_7[0]             4.553        -3.567
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[2]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     D       n_status_7[2]             4.553        -3.218
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     CE      n_status_1_sqmuxa_1_i     4.553        -2.460
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[1]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     CE      n_status_1_sqmuxa_1_i     4.553        -2.460
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[2]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     CE      n_status_1_sqmuxa_1_i     4.553        -2.460
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[1]     GW_CLKDIV|clkout_inferred_clock     DFFNCE     D       n_status_7[1]             4.553        -2.047
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.reg_baud_cntr_i[0]                GW_CLKDIV|clkout_inferred_clock     DFFCE      D       reg_baud_cntr_i_lm[0]     9.240        -1.654
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.reg_baud_cntr_i[1]                GW_CLKDIV|clkout_inferred_clock     DFFCE      D       reg_baud_cntr_i_lm[1]     9.240        -1.654
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.reg_baud_cntr_i[2]                GW_CLKDIV|clkout_inferred_clock     DFFCE      D       reg_baud_cntr_i_lm[2]     9.240        -1.654
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.reg_baud_cntr_i[3]                GW_CLKDIV|clkout_inferred_clock     DFFCE      D       reg_baud_cntr_i_lm[3]     9.240        -1.654
=====================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.686
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.553

    - Propagation time:                      8.121
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -3.567

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[2] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0] / D
    The start point is clocked by            GW_CLKDIV|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|clkout_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                        Type          Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[2]                DFFC          Q        Out     0.367     0.367       -         
data_cnt[2]                                                                                                 Net           -        -       1.021     -           6         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          I1       In      -         1.388       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          F        Out     1.099     2.487       -         
data_cnt17_2_4_1                                                                                            Net           -        -       1.021     -           2         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_0           LUT4          I2       In      -         3.508       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_0           LUT4          F        Out     0.822     4.330       -         
data_cnt17_2_4_0                                                                                            Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     I0       In      -         4.330       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     O        Out     0.150     4.480       -         
data_cnt17_2_4                                                                                              Net           -        -       1.021     -           4         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          I2       In      -         5.501       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          F        Out     0.822     6.323       -         
m12_a0                                                                                                      Net           -        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          I0       In      -         7.089       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          F        Out     1.032     8.121       -         
n_status_7[0]                                                                                               Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]                DFFNCE        D        In      -         8.121       -         
===========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.254 is 4.425(53.6%) logic and 3.829(46.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.686
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.553

    - Propagation time:                      8.121
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -3.567

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[2] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0] / D
    The start point is clocked by            GW_CLKDIV|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|clkout_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                        Type          Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[2]                DFFC          Q        Out     0.367     0.367       -         
data_cnt[2]                                                                                                 Net           -        -       1.021     -           6         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          I1       In      -         1.388       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          F        Out     1.099     2.487       -         
data_cnt17_2_4_1                                                                                            Net           -        -       1.021     -           2         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_3           LUT4          I2       In      -         3.508       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_3           LUT4          F        Out     0.822     4.330       -         
data_cnt17_2_4_3                                                                                            Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     I1       In      -         4.330       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     O        Out     0.150     4.480       -         
data_cnt17_2_4                                                                                              Net           -        -       1.021     -           4         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          I2       In      -         5.501       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          F        Out     0.822     6.323       -         
m12_a0                                                                                                      Net           -        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          I0       In      -         7.089       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          F        Out     1.032     8.121       -         
n_status_7[0]                                                                                               Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]                DFFNCE        D        In      -         8.121       -         
===========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.254 is 4.425(53.6%) logic and 3.829(46.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.686
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.553

    - Propagation time:                      8.053
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.500

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[1] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0] / D
    The start point is clocked by            GW_CLKDIV|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|clkout_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                        Type          Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[1]                DFFC          Q        Out     0.367     0.367       -         
data_cnt[1]                                                                                                 Net           -        -       1.021     -           10        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          I0       In      -         1.388       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          F        Out     1.032     2.420       -         
data_cnt17_2_4_1                                                                                            Net           -        -       1.021     -           2         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_0           LUT4          I2       In      -         3.441       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_0           LUT4          F        Out     0.822     4.263       -         
data_cnt17_2_4_0                                                                                            Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     I0       In      -         4.263       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     O        Out     0.150     4.413       -         
data_cnt17_2_4                                                                                              Net           -        -       1.021     -           4         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          I2       In      -         5.434       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          F        Out     0.822     6.256       -         
m12_a0                                                                                                      Net           -        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          I0       In      -         7.022       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          F        Out     1.032     8.053       -         
n_status_7[0]                                                                                               Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]                DFFNCE        D        In      -         8.053       -         
===========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.186 is 4.358(53.2%) logic and 3.829(46.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.686
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.553

    - Propagation time:                      8.053
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.500

    Number of logic level(s):                5
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[1] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0] / D
    The start point is clocked by            GW_CLKDIV|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|clkout_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                        Type          Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt[1]                DFFC          Q        Out     0.367     0.367       -         
data_cnt[1]                                                                                                 Net           -        -       1.021     -           10        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          I0       In      -         1.388       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_1           LUT3          F        Out     1.032     2.420       -         
data_cnt17_2_4_1                                                                                            Net           -        -       1.021     -           2         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_3           LUT4          I2       In      -         3.441       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4_3           LUT4          F        Out     0.822     4.263       -         
data_cnt17_2_4_3                                                                                            Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     I1       In      -         4.263       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.data_cnt17_2_4             MUX2_LUT5     O        Out     0.150     4.413       -         
data_cnt17_2_4                                                                                              Net           -        -       1.021     -           4         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          I2       In      -         5.434       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a0     LUT4          F        Out     0.822     6.256       -         
m12_a0                                                                                                      Net           -        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          I0       In      -         7.022       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3          F        Out     1.032     8.053       -         
n_status_7[0]                                                                                               Net           -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]                DFFNCE        D        In      -         8.053       -         
===========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.186 is 4.358(53.2%) logic and 3.829(46.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.686
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.553

    - Propagation time:                      8.053
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.500

    Number of logic level(s):                4
    Starting point:                          Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[0] / Q
    Ending point:                            Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0] / D
    The start point is clocked by            GW_CLKDIV|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|clkout_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                                        Type       Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.clock_cnt[0]               DFFC       Q        Out     0.367     0.367       -         
clock_cnt[0]                                                                                                Net        -        -       1.021     -           3         
Gowin_EMPU_inst.G_10_N_2L1_0                                                                                LUT4       I1       In      -         1.388       -         
Gowin_EMPU_inst.G_10_N_2L1_0                                                                                LUT4       F        Out     1.099     2.487       -         
G_10_N_2L1_0                                                                                                Net        -        -       0.766     -           1         
Gowin_EMPU_inst.G_10                                                                                        LUT4       I0       In      -         3.253       -         
Gowin_EMPU_inst.G_10                                                                                        LUT4       F        Out     1.032     4.285       -         
u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status24                                 Net        -        -       1.082     -           14        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a1     LUT4       I2       In      -         5.367       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_a1     LUT4       F        Out     0.822     6.189       -         
m12_a1                                                                                                      Net        -        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3       I1       In      -         6.954       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status_7_2_0_.m12_0      LUT3       F        Out     1.099     8.053       -         
n_status_7[0]                                                                                               Net        -        -       0.000     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.genblk1\.n_status[0]                DFFNCE     D        In      -         8.053       -         
========================================================================================================================================================================
Total path delay (propagation time + setup) of 8.186 is 4.552(55.6%) logic and 3.634(44.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                              Starting                                                                  Arrival           
Instance                      Reference     Type     Pin                      Net                       Time        Slack 
                              Clock                                                                                       
--------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[9]      apbtargexp2_paddr[9]      0.000       -1.096
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[8]      apbtargexp2_paddr[8]      0.000       -1.029
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[5]      apbtargexp2_paddr[5]      0.000       -0.968
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[11]     apbtargexp2_paddr[11]     0.000       -0.907
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[2]      apbtargexp2_paddr[2]      0.000       -0.901
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[10]     apbtargexp2_paddr[10]     0.000       -0.840
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PSEL          apbtargexp2_psel          0.000       -0.752
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[6]      apbtargexp2_paddr[6]      0.000       -0.691
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[3]      apbtargexp2_paddr[3]      0.000       -0.660
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[7]      apbtargexp2_paddr[7]      0.000       -0.495
==========================================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                                    Required           
Instance                      Reference     Type     Pin                       Net                        Time         Slack 
                              Clock                                                                                          
-----------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[1]      apbtargexp2_prdata[1]      6.212        -1.096
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[3]      apbtargexp2_prdata[3]      6.212        -1.096
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[5]      apbtargexp2_prdata[5]      6.212        -1.096
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[8]      apbtargexp2_prdata[8]      6.212        -1.096
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[9]      apbtargexp2_prdata[9]      6.212        -0.968
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[13]     apbtargexp2_prdata[13]     6.212        -0.968
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[10]     N_13_i                     6.212        -0.758
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[12]     N_29_i                     6.212        -0.758
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[15]     N_52_i                     6.212        -0.758
Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[19]     apbtargexp2_prdata[19]     6.212        -0.752
=============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.212
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.212

    - Propagation time:                      7.309
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.096

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[9]
    Ending point:                            Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[1]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                      Pin                      Pin               Arrival     No. of    
Name                                                                                       Type     Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PADDR[9]      Out     0.000     0.000       -         
apbtargexp2_paddr[9]                                                                       Net      -                        -       1.143     -           24        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     I1                       In      -         1.143       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     F                        Out     1.099     2.242       -         
N_59                                                                                       Net      -                        -       1.082     -           13        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[1]     LUT4     I1                       In      -         3.324       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[1]     LUT4     F                        Out     1.099     4.423       -         
PRDATA_0_a1[1]                                                                             Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[1]          LUT4     I1                       In      -         5.189       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[1]          LUT4     F                        Out     1.099     6.288       -         
apbtargexp2_prdata[1]                                                                      Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PRDATA[1]     In      -         7.309       -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 7.309 is 3.297(45.1%) logic and 4.012(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.212
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.212

    - Propagation time:                      7.309
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.096

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[9]
    Ending point:                            Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[8]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                          Pin                      Pin               Arrival     No. of    
Name                                                                                           Type     Name                     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top                                                                      MCU      APBTARGEXP2PADDR[9]      Out     0.000     0.000       -         
apbtargexp2_paddr[9]                                                                           Net      -                        -       1.143     -           24        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0           LUT2     I1                       In      -         1.143       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0           LUT2     F                        Out     1.099     2.242       -         
N_59                                                                                           Net      -                        -       1.082     -           13        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a2_1_0[8]     LUT4     I1                       In      -         3.324       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a2_1_0[8]     LUT4     F                        Out     1.099     4.423       -         
PRDATA_0_1_0[8]                                                                                Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0[8]            LUT4     I1                       In      -         5.189       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0[8]            LUT4     F                        Out     1.099     6.288       -         
apbtargexp2_prdata[8]                                                                          Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.u_mcu_top                                                                      MCU      APBTARGEXP2PRDATA[8]     In      -         7.309       -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 7.309 is 3.297(45.1%) logic and 4.012(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.212
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.212

    - Propagation time:                      7.309
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.096

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[9]
    Ending point:                            Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                      Pin                      Pin               Arrival     No. of    
Name                                                                                       Type     Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PADDR[9]      Out     0.000     0.000       -         
apbtargexp2_paddr[9]                                                                       Net      -                        -       1.143     -           24        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     I1                       In      -         1.143       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     F                        Out     1.099     2.242       -         
N_59                                                                                       Net      -                        -       1.082     -           13        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[3]     LUT4     I1                       In      -         3.324       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[3]     LUT4     F                        Out     1.099     4.423       -         
PRDATA_0_a1[3]                                                                             Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[3]          LUT4     I1                       In      -         5.189       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[3]          LUT4     F                        Out     1.099     6.288       -         
apbtargexp2_prdata[3]                                                                      Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PRDATA[3]     In      -         7.309       -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 7.309 is 3.297(45.1%) logic and 4.012(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.212
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.212

    - Propagation time:                      7.309
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.096

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[9]
    Ending point:                            Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[5]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                      Pin                      Pin               Arrival     No. of    
Name                                                                                       Type     Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PADDR[9]      Out     0.000     0.000       -         
apbtargexp2_paddr[9]                                                                       Net      -                        -       1.143     -           24        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     I1                       In      -         1.143       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     F                        Out     1.099     2.242       -         
N_59                                                                                       Net      -                        -       1.082     -           13        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[5]     LUT4     I1                       In      -         3.324       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[5]     LUT4     F                        Out     1.099     4.423       -         
PRDATA_0_a1[5]                                                                             Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[5]          LUT4     I1                       In      -         5.189       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[5]          LUT4     F                        Out     1.099     6.288       -         
apbtargexp2_prdata[5]                                                                      Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PRDATA[5]     In      -         7.309       -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 7.309 is 3.297(45.1%) logic and 4.012(54.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.212
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         6.212

    - Propagation time:                      7.242
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.029

    Number of logic level(s):                3
    Starting point:                          Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[8]
    Ending point:                            Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[1]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                      Pin                      Pin               Arrival     No. of    
Name                                                                                       Type     Name                     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PADDR[8]      Out     0.000     0.000       -         
apbtargexp2_paddr[8]                                                                       Net      -                        -       1.143     -           28        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     I0                       In      -         1.143       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PSEL3_i_o3_0       LUT2     F                        Out     1.032     2.175       -         
N_59                                                                                       Net      -                        -       1.082     -           13        
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[1]     LUT4     I1                       In      -         3.257       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA_0_a1[1]     LUT4     F                        Out     1.099     4.356       -         
PRDATA_0_a1[1]                                                                             Net      -                        -       0.766     -           1         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[1]          LUT4     I1                       In      -         5.122       -         
Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.PRDATA[1]          LUT4     F                        Out     1.099     6.221       -         
apbtargexp2_prdata[1]                                                                      Net      -                        -       1.021     -           1         
Gowin_EMPU_inst.u_mcu_top                                                                  MCU      APBTARGEXP2PRDATA[1]     In      -         7.242       -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 7.242 is 3.230(44.6%) logic and 4.012(55.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 214MB peak: 219MB)


Finished timing report (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 214MB peak: 219MB)

---------------------------------------
Resource Usage Report for Gowin_EMPU_Top 

Mapping to part: gw1ns_2clqfp144-6
Cell usage:
ADC             1 use
ALU             51 uses
CLKDIV          2 uses
DFF             1 use
DFFC            128 uses
DFFCE           267 uses
DFFE            1 use
DFFNCE          3 uses
DFFP            10 uses
DFFPE           30 uses
DLNCE           1 use
DQCE            1 use
FLASH128K       1 use
GSR             2 uses
INV             21 uses
MCU             1 use
MUX2_LUT5       8 uses
MUX2_LUT6       2 uses
OSCF            1 use
SP              4 uses
LUT2            75 uses
LUT3            196 uses
LUT4            381 uses

I/O ports: 38
I/O primitives: 38
IBUF           8 uses
IOBUF          18 uses
OBUF           12 uses

I/O Register bits:                  0
Register bits not including I/Os:   440 of 1296 (33%)

RAM/ROM usage summary
Block Rams : 4 of 4 (100%)

Total load per clock:

@S |Mapping Summary:
Total  LUTs: 652 (37%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 46MB peak: 219MB)

Process took 0h:00m:10s realtime, 0h:00m:10s cputime
# Tue Jul 30 08:55:57 2019

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