Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM\data\psram_code.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW1NSR-LV4CMG64PC7/I6 |
Device | GW1NSR-4C |
Created Time | Fri Feb 26 14:45:22 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | PSRAM_Memory_Interface_Top |
Synthesis Process | Running parser: Actual time = 0h 0m 1s, CPU time = 0h 0m 1s, Peak memory usage = 44.168MB Running netlist conversion: Actual time = 0h 0m 0.023s, CPU time = 0h 0m 0.031s, Peak memory usage = 44.168MB Running device independent optimization: Optimizing Phase 0: Actual time = 0h 0m 0.089s, CPU time = 0h 0m 0.093s, Peak memory usage = 44.168MB Optimizing Phase 1: Actual time = 0h 0m 0.079s, CPU time = 0h 0m 0.078s, Peak memory usage = 44.168MB Optimizing Phase 2: Actual time = 0h 0m 0.13s, CPU time = 0h 0m 0.125s, Peak memory usage = 44.168MB Running inference: Inferring Phase 0: Actual time = 0h 0m 0.034s, CPU time = 0h 0m 0.031s, Peak memory usage = 44.168MB Inferring Phase 1: Actual time = 0h 0m 0.003s, CPU time = 0h 0m 0.015s, Peak memory usage = 44.168MB Inferring Phase 2: Actual time = 0h 0m 0.015s, CPU time = 0h 0m 0.015s, Peak memory usage = 44.168MB Inferring Phase 3: Actual time = 0h 0m 0.005s, CPU time = 0h 0m 0s, Peak memory usage = 44.168MB Running technical mapping: Tech-Mapping Phase 0: Actual time = 0h 0m 0.147s, CPU time = 0h 0m 0.14s, Peak memory usage = 44.168MB Tech-Mapping Phase 1: Actual time = 0h 0m 0.029s, CPU time = 0h 0m 0.031s, Peak memory usage = 44.168MB Tech-Mapping Phase 2: Actual time = 0h 0m 0.024s, CPU time = 0h 0m 0.031s, Peak memory usage = 44.168MB Tech-Mapping Phase 3: Actual time = 0h 0m 2s, CPU time = 0h 0m 2s, Peak memory usage = 59.371MB Tech-Mapping Phase 4: Actual time = 0h 0m 0.259s, CPU time = 0h 0m 0.25s, Peak memory usage = 59.371MB Generate netlist file: Actual time = 0h 0m 0.05s, CPU time = 0h 0m 0.046s, Peak memory usage = 59.371MB |
Total Time and Memory Usage | Actual time = 0h 0m 3s, CPU time = 0h 0m 3s, Peak memory usage = 59.371MB |
Resource
Resource Usage Summary
I/O Port | 166 |
Emedded Port | 26 |
I/O Buf | 191 |
    IBUF | 99 |
    OBUF | 73 |
    IOBUF | 18 |
    ELVDS_OBUF | 1 |
Register | 1130 |
    DFFE | 464 |
    DFFRE | 112 |
    DFFP | 2 |
    DFFPE | 8 |
    DFFC | 323 |
    DFFCE | 221 |
LUT | 1292 |
    LUT2 | 236 |
    LUT3 | 638 |
    LUT4 | 418 |
ALU | 46 |
    ALU | 46 |
INV | 5 |
    INV | 5 |
IOLOGIC | 58 |
    IDES4 | 16 |
    OSER4 | 23 |
    IODELAY | 19 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Logic | 1343(1297 LUTs, 46 ALUs) / 4608 | 29% |
Register | 1130 / 3702 | 31% |
  --Register as Latch | 0 / 3702 | 0% |
  --Register as FF | 1130 / 3702 | 31% |
BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 150.7(MHz) | 6 | TOP |
2 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 287.3(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.36 |
Data Arrival Time | 7.34 |
Data Required Time | 10.7 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_12_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
3.676 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s3/F |
4.032 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
4.846 | 0.814 | tINS | FF | 2 | u_psram_top/u_psram_sync/n43_s2/F |
5.202 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
5.811 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
6.167 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s5/I1 |
6.981 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n39_s5/F |
7.337 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3 |
Clock Skew: | 0 |
Setup Relationship: | 10 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Arrival Data Path Delay: | cell: 3.87, 61%; route: 2.13, 33.7%; tC2Q: 0.34, 5.36% |
Required Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Path 2
Path Summary:Slack | 3.36 |
Data Arrival Time | 7.34 |
Data Required Time | 10.7 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_13_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
3.676 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s3/F |
4.032 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
4.846 | 0.814 | tINS | FF | 2 | u_psram_top/u_psram_sync/n43_s2/F |
5.202 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
5.811 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
6.167 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n38_s1/I1 |
6.981 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n38_s1/F |
7.337 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1 |
Clock Skew: | 0 |
Setup Relationship: | 10 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Arrival Data Path Delay: | cell: 3.87, 61%; route: 2.13, 33.7%; tC2Q: 0.34, 5.36% |
Required Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Path 3
Path Summary:Slack | 3.41 |
Data Arrival Time | 7.29 |
Data Required Time | 10.7 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_14_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
3.676 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s3/F |
4.032 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
4.846 | 0.814 | tINS | FF | 2 | u_psram_top/u_psram_sync/n43_s2/F |
5.202 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
5.811 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
6.167 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n37_s1/I0 |
6.931 | 0.765 | tINS | FF | 1 | u_psram_top/u_psram_sync/n37_s1/F |
7.287 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1 |
Clock Skew: | 0 |
Setup Relationship: | 10 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Arrival Data Path Delay: | cell: 3.82, 60.7%; route: 2.13, 33.9%; tC2Q: 0.34, 5.4% |
Required Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Path 4
Path Summary:Slack | 3.57 |
Data Arrival Time | 7.13 |
Data Required Time | 10.7 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_15_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
3.676 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s3/F |
4.032 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
4.846 | 0.814 | tINS | FF | 2 | u_psram_top/u_psram_sync/n43_s2/F |
5.202 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
5.811 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
6.167 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n36_s1/I2 |
6.776 | 0.609 | tINS | FF | 1 | u_psram_top/u_psram_sync/n36_s1/F |
7.132 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_15_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_15_s1/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_15_s1 |
Clock Skew: | 0 |
Setup Relationship: | 10 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Arrival Data Path Delay: | cell: 3.66, 59.7%; route: 2.13, 34.8%; tC2Q: 0.34, 5.54% |
Required Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Path 5
Path Summary:Slack | 3.71 |
Data Arrival Time | 6.99 |
Data Required Time | 10.7 |
From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
To | u_psram_top/u_psram_sync/flag_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n283_s17/I1 |
2.506 | 0.814 | tINS | FF | 3 | u_psram_top/u_psram_sync/n283_s17/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n338_s13/I2 |
3.471 | 0.609 | tINS | FF | 5 | u_psram_top/u_psram_sync/n338_s13/F |
3.827 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n294_s13/I1 |
4.641 | 0.814 | tINS | FF | 3 | u_psram_top/u_psram_sync/n294_s13/F |
4.997 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n349_s7/I3 |
5.461 | 0.464 | tINS | FF | 2 | u_psram_top/u_psram_sync/n349_s7/F |
5.816 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/n360_s6/I1 |
6.631 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n360_s6/F |
6.986 | 0.356 | tNET | FF | 1 | u_psram_top/u_psram_sync/flag_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_top/u_psram_sync/flag_0_s0/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/flag_0_s0 |
Clock Skew: | 0 |
Setup Relationship: | 10 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |
Arrival Data Path Delay: | cell: 3.52, 58.7%; route: 2.13, 35.6%; tC2Q: 0.34, 5.67% |
Required Clock Path Delay: | cell: 0.728, 73%; route: 0.269, 27% |