Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Fri Feb 26 15:07:26 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    Actual time = 0h 0m 1s, CPU time = 0h 0m 1s, Peak memory usage = 39.520MB
Running netlist conversion:
    Actual time = 0h 0m 0.012s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.520MB
Running device independent optimization:
    Optimizing Phase 0: Actual time = 0h 0m 0.019s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.520MB
    Optimizing Phase 1: Actual time = 0h 0m 0.009s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.520MB
    Optimizing Phase 2: Actual time = 0h 0m 0.013s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.520MB
Running inference:
    Inferring Phase 0: Actual time = 0h 0m 0.003s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
    Inferring Phase 1: Actual time = 0h 0m 0s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
    Inferring Phase 2: Actual time = 0h 0m 0.002s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
    Inferring Phase 3: Actual time = 0h 0m 0s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
Running technical mapping:
    Tech-Mapping Phase 0: Actual time = 0h 0m 0.01s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.520MB
    Tech-Mapping Phase 1: Actual time = 0h 0m 0.004s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
    Tech-Mapping Phase 2: Actual time = 0h 0m 0.003s, CPU time = 0h 0m 0s, Peak memory usage = 39.520MB
    Tech-Mapping Phase 3: Actual time = 0h 0m 0.447s, CPU time = 0h 0m 0.421s, Peak memory usage = 52.844MB
    Tech-Mapping Phase 4: Actual time = 0h 0m 0.035s, CPU time = 0h 0m 0.031s, Peak memory usage = 52.844MB
Generate netlist file:
    Actual time = 0h 0m 0.016s, CPU time = 0h 0m 0.015s, Peak memory usage = 52.844MB
Total Time and Memory Usage Actual time = 0h 0m 1s, CPU time = 0h 0m 1s, Peak memory usage = 52.844MB

Resource

Resource Usage Summary

I/O Port 136
I/O Buf 136
    IBUF 41
    OBUF 95
Register 116
    DFFP 2
    DFFPE 2
    DFFC 46
    DFFCE 49
    DFFNCE 16
    DLNCE 1
LUT 140
    LUT2 29
    LUT3 58
    LUT4 53
INV 3
    INV 3
BSRAM 8
    SP 8
User Flash 1
    FLASH256K 1
EMCU 1

Resource Utilization Summary

Logic 143(143 LUTs, 0 ALUs) / 4608 3%
Register 116 / 3573 3%
  --Register as Latch 1 / 3573 1%
  --Register as FF 115 / 3573 3%
BSRAM 8 / 10 80%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 10.000 100.0 0.000 5.000 sys_clk_ibuf/I
reset_n Base 10.000 100.0 0.000 5.000 reset_n_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 100.0(MHz) 89.9(MHz) 5 TOP
2 reset_n 100.0(MHz) 325.7(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.564
Data Arrival Time 6.32
Data Required Time 5.76
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 123 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_0_s0/CLK
1.336 0.340 tC2Q RF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_sel_0_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s6/I1
2.506 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s6/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n403_s3/I1
3.676 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n403_s3/F
4.032 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s14/I1
4.846 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s14/F
5.202 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n324_s12/I0
5.967 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n324_s12/F
6.322 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 123 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_s3
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 3.21, 60.2%; route: 1.78, 33.4%; tC2Q: 0.34, 6.38%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%

Path 2

Path Summary:
Slack -0.514
Data Arrival Time 6.27
Data Required Time 5.76
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 123 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0/CLK
1.336 0.340 tC2Q RF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s5/I1
2.506 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s5/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s8/I0
3.627 0.765 tINS FF 8 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s8/F
3.982 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s13/I1
4.797 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s13/F
5.152 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s12/I0
5.917 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s12/F
6.273 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 123 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_s3
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 3.16, 59.9%; route: 1.78, 33.7%; tC2Q: 0.34, 6.44%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%

Path 3

Path Summary:
Slack -0.514
Data Arrival Time 6.27
Data Required Time 5.76
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 123 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0/CLK
1.336 0.340 tC2Q RF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s5/I1
2.506 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s5/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s8/I0
3.627 0.765 tINS FF 8 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_s8/F
3.982 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s13/I1
4.797 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_s13/F
5.152 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n325_s13/I0
5.917 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n325_s13/F
6.273 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 123 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_s3
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 3.16, 59.9%; route: 1.78, 33.7%; tC2Q: 0.34, 6.44%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%

Path 4

Path Summary:
Slack 0.967
Data Arrival Time 4.79
Data Required Time 5.76
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 123 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n87_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n87_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n73_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n73_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n141_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n141_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 123 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 2.03, 53.6%; route: 1.42, 37.5%; tC2Q: 0.34, 8.95%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%

Path 5

Path Summary:
Slack 0.967
Data Arrival Time 4.79
Data Required Time 5.76
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 123 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n87_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n87_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n73_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n73_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n140_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n140_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 123 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 2.03, 53.6%; route: 1.42, 37.5%; tC2Q: 0.34, 8.95%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%