Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Fri Feb 26 15:07:52 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module HyperRAM_Memory_Interface_Top
Synthesis Process Running parser:
    Actual time = 0h 0m 1s, CPU time = 0h 0m 1s, Peak memory usage = 39.773MB
Running netlist conversion:
    Actual time = 0h 0m 0.013s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.773MB
Running device independent optimization:
    Optimizing Phase 0: Actual time = 0h 0m 0.049s, CPU time = 0h 0m 0.046s, Peak memory usage = 39.773MB
    Optimizing Phase 1: Actual time = 0h 0m 0.039s, CPU time = 0h 0m 0.046s, Peak memory usage = 39.773MB
    Optimizing Phase 2: Actual time = 0h 0m 0.058s, CPU time = 0h 0m 0.046s, Peak memory usage = 39.773MB
Running inference:
    Inferring Phase 0: Actual time = 0h 0m 0.017s, CPU time = 0h 0m 0.031s, Peak memory usage = 39.773MB
    Inferring Phase 1: Actual time = 0h 0m 0.002s, CPU time = 0h 0m 0s, Peak memory usage = 39.773MB
    Inferring Phase 2: Actual time = 0h 0m 0.01s, CPU time = 0h 0m 0s, Peak memory usage = 39.773MB
    Inferring Phase 3: Actual time = 0h 0m 0.002s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.773MB
Running technical mapping:
    Tech-Mapping Phase 0: Actual time = 0h 0m 0.088s, CPU time = 0h 0m 0.078s, Peak memory usage = 39.773MB
    Tech-Mapping Phase 1: Actual time = 0h 0m 0.017s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.773MB
    Tech-Mapping Phase 2: Actual time = 0h 0m 0.014s, CPU time = 0h 0m 0.015s, Peak memory usage = 39.773MB
    Tech-Mapping Phase 3: Actual time = 0h 0m 1s, CPU time = 0h 0m 1s, Peak memory usage = 54.727MB
    Tech-Mapping Phase 4: Actual time = 0h 0m 0.148s, CPU time = 0h 0m 0.125s, Peak memory usage = 54.727MB
Generate netlist file:
    Actual time = 0h 0m 0.031s, CPU time = 0h 0m 0.015s, Peak memory usage = 54.727MB
Total Time and Memory Usage Actual time = 0h 0m 2s, CPU time = 0h 0m 2s, Peak memory usage = 54.727MB

Resource

Resource Usage Summary

I/O Port 99
Emedded Port 13
I/O Buf 112
    IBUF 64
    OBUF 39
    IOBUF 9
Register 677
    DFFE 208
    DFFRE 80
    DFFP 3
    DFFPE 3
    DFFC 229
    DFFCE 154
LUT 740
    LUT2 168
    LUT3 349
    LUT4 223
ALU 31
    ALU 31
INV 7
    INV 7
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Logic 778(747 LUTs, 31 ALUs) / 4608 17%
Register 677 / 3612 19%
  --Register as Latch 0 / 3612 0%
  --Register as FF 677 / 3612 19%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 182.9(MHz) 5 TOP
2 u_hpram_top/clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 287.3(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.18
Data Arrival Time 1.69
Data Required Time 5.87
From u_hpram_top/u_hpram_sync/cs_memsync_4_s0
To u_hpram_top/u_dqce_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK
1.336 0.340 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q
1.692 0.356 tNET FF 1 u_hpram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.729 0.729 tINS FF 1 memory_clk_ibuf/O
6.085 0.356 tNET FF 3 u_hpram_top/u_dqce_clk_x2p/CLKIN
6.055 -0.030 tUnc u_hpram_top/u_dqce_clk_x2p
5.867 -0.188 tSu 1 u_hpram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.0885
Setup Relationship: 5
Logic Level: 1
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 0, 0%; route: 0.356, 51.2%; tC2Q: 0.34, 48.8%
Required Clock Path Delay: cell: 0.729, 67.2%; route: 0.356, 32.8%

Path 2

Path Summary:
Slack 4.53
Data Arrival Time 6.17
Data Required Time 10.7
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.336 0.340 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
1.692 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s17/I1
2.506 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n315_s17/F
2.862 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I2
3.471 0.609 tINS FF 5 u_hpram_top/u_hpram_sync/n315_s13/F
3.827 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s2/I1
4.641 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n389_s2/F
4.997 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s1/I1
5.811 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n389_s1/F
6.167 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/count_0_s0/CLK
10.700 -0.296 tSu 1 u_hpram_top/u_hpram_sync/count_0_s0
Path Statistics:
Clock Skew: 0
Setup Relationship: 10
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 3.05, 59%; route: 1.78, 34.4%; tC2Q: 0.34, 6.57%
Required Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%

Path 3

Path Summary:
Slack 4.73
Data Arrival Time 5.97
Data Required Time 10.7
From u_hpram_top/u_hpram_sync/cs_memsync_0_s0
To u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
1.336 0.340 tC2Q RF 9 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q
1.692 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
2.506 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s11/F
2.862 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s9/I1
3.676 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s9/F
4.032 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s13/I0
4.797 0.765 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s13/F
5.152 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s12/I3
5.616 0.464 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s12/F
5.972 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/CLK
10.700 -0.296 tSu 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Path Statistics:
Clock Skew: 0
Setup Relationship: 10
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 2.86, 57.4%; route: 1.78, 35.7%; tC2Q: 0.34, 6.83%
Required Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%

Path 4

Path Summary:
Slack 4.73
Data Arrival Time 5.97
Data Required Time 10.7
From u_hpram_top/u_hpram_sync/cs_memsync_0_s0
To u_hpram_top/u_hpram_sync/flag_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
1.336 0.340 tC2Q RF 9 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q
1.692 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
2.506 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s11/F
2.862 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s9/I1
3.676 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s9/F
4.032 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s8/I0
4.797 0.765 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s8/F
5.152 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s5/I3
5.616 0.464 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s5/F
5.972 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/flag_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/flag_1_s0/CLK
10.700 -0.296 tSu 1 u_hpram_top/u_hpram_sync/flag_1_s0
Path Statistics:
Clock Skew: 0
Setup Relationship: 10
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 2.86, 57.4%; route: 1.78, 35.7%; tC2Q: 0.34, 6.83%
Required Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%

Path 5

Path Summary:
Slack 4.74
Data Arrival Time 5.96
Data Required Time 10.7
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.336 0.340 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
1.692 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s17/I1
2.506 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n315_s17/F
2.862 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I2
3.471 0.609 tINS FF 5 u_hpram_top/u_hpram_sync/n315_s13/F
3.827 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s2/I1
4.641 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/n389_s2/F
4.997 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/n388_s1/I2
5.606 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n388_s1/F
5.961 0.356 tNET FF 1 u_hpram_top/u_hpram_sync/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_hpram_top/u_hpram_sync/count_1_s0/CLK
10.700 -0.296 tSu 1 u_hpram_top/u_hpram_sync/count_1_s0
Path Statistics:
Clock Skew: 0
Setup Relationship: 10
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%
Arrival Data Path Delay: cell: 2.85, 57.3%; route: 1.78, 35.8%; tC2Q: 0.34, 6.84%
Required Clock Path Delay: cell: 0.728, 73%; route: 0.269, 27%