Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.5.01Beta
Created Time Mon Apr 13 16:53:28 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: Gowin_EMPU_Top
Part Number: GW1NSE-UX2CLQ144C5/I4

Resource

Resource Usage Summary

I/OPORT Usage: 248
I/OBUF Usage: 248
    IBUF 78
    OBUF 152
    IOBUF 18
REG Usage: 429
    DFF 1
    DFFE 1
    DFFP 8
    DFFPE 31
    DFFC 77
    DFFCE 307
    DFFNCE 3
    DLCE 1
LUT Usage: 659
    LUT2 90
    LUT3 223
    LUT4 346
ALU Usage: 20
    ALU 20
INV Usage: 22
    INV 22
BSRAM Usage: 4
    SP 4
CLOCK Usage: 2
    CLKDIV 1
    DQCE 1

Resource Utilization Summary

Target Device: GW1NSE-2C-LQFP144
CFU Logics 701(681 LUTs, 20 ALUs) / 1728 41%
Registers 429 / 1536 28%
BSRAMs 4 / 4 100%
DSP Macros 0 / (0*2) -


Timing

Clock Summary:

Clock Type Frequency Period Rise Fall Source Master Object
Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk Generated 50.0 MHz 20.000 0.000 10.000 DEFAULT_CLK
DEFAULT_CLK Base 100.0 MHz 10.000 0.000 5.000

Timing Report:

Top View: Gowin_EMPU_Top
Requested Frequency: 50.0 MHz
Paths Requested: 5
Constraint File(ignored):
All time values displayed in nanoseconds(ns).

Performance Summary:

Worst Slack in Design: 1.510
Start Clock Slack Requested Frequency Estimated Frequency Requested Period Estimated Period Clock Type
Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk 1.510 50.0 MHz 54.1 MHz 20.000 18.490 Generated

Detail Timing Paths Information

Path information for path number 1 : 
Clock Skew: 0.140
Setup Relationship: 10.000
Slack(critical): 0.755
Data Arrival Time: 9.141
Data Required Time: 9.896
Number of Logic Level: 5
Starting Point: Gowin_EMPU_inst/sysclk/clkdiv_inst
Ending Point: Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_ins6622
The Start Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[falling]
The End Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
\Gowin_EMPU_inst/sysclk/clkdiv_inst CLKDIV CLKOUT Out 0.000 0.000 -
master_pclk Net - - 0.436 - 435
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC CLK In - 0.436 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC Q Out 0.550 0.986 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_clock_cnt[3] Net - - 0.576 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 I1 In - 1.562 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 F Out 1.319 2.880 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n202 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n708_ins7115 LUT4 I1 In - 3.456 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n708_ins7115 LUT4 F Out 1.319 4.775 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n708 Net - - 0.576 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7152 LUT4 I1 In - 5.351 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7152 LUT4 F Out 1.319 6.670 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n326 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins6869 LUT4 I1 In - 7.246 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins6869 LUT4 F Out 1.319 8.565 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n326_37 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_ins6622 DFFNCE D In - 9.141 -

Total Path Delay: 9.141
Logic Delay: 5.825(63.7%)
Route Delay: 3.316(36.3%)


Path information for path number 2 : 
Clock Skew: 0.281
Setup Relationship: 10.000
Slack(non-critical): 0.916
Data Arrival Time: 8.980
Data Required Time: 9.896
Number of Logic Level: 5
Starting Point: Gowin_EMPU_inst/sysclk/clkdiv_inst
Ending Point: Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_ins6620
The Start Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[falling]
The End Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
\Gowin_EMPU_inst/sysclk/clkdiv_inst CLKDIV CLKOUT Out 0.000 0.000 -
master_pclk Net - - 0.436 - 435
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC CLK In - 0.436 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC Q Out 0.550 0.986 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_clock_cnt[3] Net - - 0.576 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 I1 In - 1.562 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 F Out 1.319 2.880 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n202 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n554_ins7350 LUT4 I0 In - 3.456 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n554_ins7350 LUT4 F Out 1.238 4.695 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n554 Net - - 0.576 - 5
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7153 LUT4 I1 In - 5.271 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7153 LUT4 F Out 1.319 6.590 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n326_43 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n324_ins7365 LUT4 I0 In - 7.166 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n324_ins7365 LUT4 F Out 1.238 8.404 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n324 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_2_ins6620 DFFNCE D In - 8.980 -

Total Path Delay: 8.980
Logic Delay: 5.664(63.1%)
Route Delay: 3.316(36.9%)


Path information for path number 3 : 
Clock Skew: 0.421
Setup Relationship: 10.000
Slack(non-critical): 1.655
Data Arrival Time: 8.241
Data Required Time: 9.896
Number of Logic Level: 5
Starting Point: Gowin_EMPU_inst/sysclk/clkdiv_inst
Ending Point: Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins6621
The Start Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[falling]
The End Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
\Gowin_EMPU_inst/sysclk/clkdiv_inst CLKDIV CLKOUT Out 0.000 0.000 -
master_pclk Net - - 0.436 - 435
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC CLK In - 0.436 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC Q Out 0.550 0.986 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_clock_cnt[3] Net - - 0.576 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 I1 In - 1.562 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 F Out 1.319 2.880 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n202 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7111 LUT3 I1 In - 3.456 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7111 LUT3 F Out 1.319 4.775 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n202_9 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7151 LUT4 I2 In - 5.351 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n326_ins7151 LUT4 F Out 0.986 6.338 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n326_39 Net - - 0.576 - 6
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n325_ins6898 LUT4 I3 In - 6.914 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n325_ins6898 LUT4 F Out 0.751 7.665 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n325 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins6621 DFFNCE D In - 8.241 -

Total Path Delay: 8.241
Logic Delay: 4.925(59.8%)
Route Delay: 3.316(40.2%)


Path information for path number 4 : 
Clock Skew: 0.281
Setup Relationship: 10.000
Slack(non-critical): 3.269
Data Arrival Time: 16.486
Data Required Time: 19.756
Number of Logic Level: 4
Starting Point: Gowin_EMPU_inst/sysclk/clkdiv_inst
Ending Point: Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/tx_shift_data_0_ins5735
The Start Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[rising]
The End Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[falling]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
\Gowin_EMPU_inst/sysclk/clkdiv_inst CLKDIV CLKOUT Out 0.000 10.000 -
master_pclk Net - - 0.576 - 435
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins6621 DFFNCE CLK In - 10.576 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins6621 DFFNCE Q Out 0.550 11.126 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n_status[1] Net - - 0.576 - 5
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n246_ins7113 LUT3 I1 In - 11.702 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n246_ins7113 LUT3 F Out 1.319 13.021 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n246 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n459_ins6794 LUT4 I3 In - 13.597 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n459_ins6794 LUT4 F Out 0.751 14.348 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n459 Net - - 0.576 - 10
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n506_ins6796 LUT4 I2 In - 14.924 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n506_ins6796 LUT4 F Out 0.986 15.910 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n506 Net - - 0.576 - 1
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/tx_shift_data_0_ins5735 DFFCE D In - 16.486 -

Total Path Delay: 6.486
Logic Delay: 3.606(55.6%)
Route Delay: 2.880(44.4%)


Path information for path number 5 : 
Clock Skew: 0.421
Setup Relationship: 10.000
Slack(non-critical): 3.386
Data Arrival Time: 6.938
Data Required Time: 10.324
Number of Logic Level: 4
Starting Point: Gowin_EMPU_inst/sysclk/clkdiv_inst
Ending Point: Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_ins6622
The Start Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[falling]
The End Point Is Clocked By: Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
\Gowin_EMPU_inst/sysclk/clkdiv_inst CLKDIV CLKOUT Out 0.000 0.000 -
master_pclk Net - - 0.436 - 435
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC CLK In - 0.436 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/clock_cnt_3_ins5326 DFFC Q Out 0.550 0.986 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_clock_cnt[3] Net - - 0.576 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 I1 In - 1.562 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n202_ins7278 LUT4 F Out 1.319 2.880 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n202 Net - - 0.576 - 4
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n554_ins7350 LUT4 I0 In - 3.456 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n554_ins7350 LUT4 F Out 1.238 4.695 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n554 Net - - 0.576 - 5
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins7352 LUT4 I0 In - 5.271 -
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_1_ins7352 LUT4 F Out 1.231 6.502 -
Gowin_EMPU_inst_u_gw_peripherals_interconnect_u_gw_cmsdk_apb2_spi_u_spi_n_status_1 Net - - 0.436 - 3
\Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/u_spi/n_status_0_ins6622 DFFNCE CE In - 6.938 -

Total Path Delay: 6.938
Logic Delay: 4.338(62.5%)
Route Delay: 2.599(37.5%)


Message

Info (EXT0100) : Run analyzation & elaboration
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu\src\gowin_empu\temp\gw_empu\config.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:2998)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:2998)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu\src\gowin_empu\temp\gw_empu\gowin_empu_name.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:11)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:2998)
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu\src\gowin_empu\temp\gw_empu\gowin_empu_name.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v:1)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v:1)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu\src\gowin_empu\temp\gw_empu\config.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v:2)
Info (EXT1018) : Compiling module 'Gowin_EMPU_Top'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v:3)
Warning (EXT1927) : Port '**' remains unconnected for this instance(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT2435) : Port '**' is not connected on this instance(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT3002) : Net '**' does not have a driver(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT3002) : Net '**' does not have a driver(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT2371) : Delay control is not supported for synthesis(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT2371) : Delay control is not supported for synthesis(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1173) : Full_case directive is effective : might cause synthesis - simulation differences(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT3013) : Input port '**' is not connected on this instance(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (EXT3053) : Input port '**' remains unconnected for this instance(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (EXT0101) : Current top module is "Gowin_EMPU_Top"
Info (CVT0001) : Run conversion
Info (DIO0001) : Run device independent optimization
Info (DIO0006) : Register and gate optimizing before inferencing
Warning (DIO0003) : Register "count_sampling[6]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[5]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[4]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[3]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[2]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[1]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "count_sampling[0]" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Warning (DIO0003) : Register "soc_once" CLK pin dangling,the register will be replaced by GND(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v:0)
Info (DSP0001) : DSP inferencing
Info (RAM0001) : RAM inferencing
Info (ATO0001) : Adder tree reduction
Info (ATO0002) : Rebuild ALU instances from adder tree nodes
Info (DIO0001) : Run device independent optimization
Info (DIO0007) : Register and gate optimizing before mapping
Info (MAP0001) : Run tech-mapping
Info (MAP0003) : Run logic optimization
Info (DIO0001) : Run device independent optimization
Info (SYN0009) : Write post-map netlist to file: D:\user-bak\Users\root\Desktop\gowin_empu\src\gowin_empu\temp\gw_empu\gowin_empu.vg

Summary

Total Warnings: 26
Total Informations: 42

Synthesis completed successfully!
Process took 0h:0m:6s realtime, 0h:0m:6s cputime
Memory peak: 56.7MB