Project Settings
Project Name gowin_empu_ahb_psram Device Name rev_1: GOWIN-GW1NSR : GW1NSR_2C
Implementation Name rev_1 Top Module Gowin_EMPU_Template
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 19 113 0 - 00m:06s - 2020/4/23
15:15:00
(premap)Complete 6 0 0 0m:03s 0m:04s 231MB 2020/4/23
15:15:08
(fpga_mapper)Complete 13 14 0 0m:09s 0m:09s 242MB 2020/4/23
15:15:18
Multi-srs Generator Complete00m:01s2020/4/23
15:15:02

Area Summary
I/O ports (io_port) 18 Non I/O Register bits (non_io_reg) 940 (87%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 4 (4) LUTs (total_luts) 1247 (72%)

Timing Summary
Clock NameReq FreqEst FreqSlack
GW_CLKDIV|master_hclk_inferred_clock75.7 MHz34.1 MHz-8.046
SPI|inv_4467_1_O_inferred_clock100.0 MHzNANA
_~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0]91.3 MHzNANA
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock91.3 MHz77.6 MHz-1.934
_~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock100.0 MHzNANA
_~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0]91.3 MHzNANA
System109.3 MHz92.9 MHz-1.614

Optimizations Summary
Combined Clock Conversion 2 / 4