#Build: Synplify Pro (R) P-2019.09G-1, Build 284R, Feb 28 2020
#install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-029

# Thu Apr 23 15:14:54 2020

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q3p1, Build 317R, Built Apr  1 2020 10:50:36

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q3p1, Build 317R, Built Apr  1 2020 10:50:36

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro\lib\generic\gw1ns.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\psram_memory_interface.v" (library work)
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(361) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(362) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(361) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(376) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(362) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(377) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(361) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(376) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(391) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(362) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(377) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(392) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(361) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(376) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(391) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(406) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(362) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(377) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(392) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(407) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(331) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(346) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(361) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(376) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(391) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(406) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(421) | Duplicate defparam HWL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(332) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(347) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(362) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(377) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(392) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(407) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(422) | Duplicate defparam TXCLK_POL found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2941) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2941) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2950) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2941) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2950) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2959) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2941) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2950) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2959) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2968) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2923) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2932) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2941) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2950) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2959) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2968) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(2977) | Duplicate defparam C_STATIC_DLY found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4260) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4260) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4268) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4260) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4268) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4284) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4260) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4268) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4284) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4292) | Duplicate defparam INIT found ! Previously declared here.
@W:CG1347 : psram_memory_interface.v(4252) | Duplicate defparam INIT found ! Previously declared here.

Only the first 100 messages of id 'CG1347' are reported. To see all messages use 'report_messages -log D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\impl\synthesize\rev_1\synlog\gowin_empu_ahb_psram_compiler.srr -id CG1347' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG1347} -count unlimited' in the Tcl shell.
@I::"D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\gowin_empu\gowin_empu.v" (library work)
@I::"D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\gowin_ahb_psram.v" (library work)
@I::"D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\gowin_empu_template.v" (library work)
Verilog syntax check successful!
Selecting top level module Gowin_EMPU_Template
@N:CG364 : gw1ns.v(101) | Synthesizing module LUT2 in library work.
Running optimization stage 1 on LUT2 .......
@N:CG364 : gw1ns.v(2359) | Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on DLL .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on ELVDS_OBUF .......
Running optimization stage 1 on OBUF .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on OSER4 .......
Running optimization stage 1 on IDES4 .......
Running optimization stage 1 on RAM16SDP4 .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_Top  .......
Running optimization stage 1 on \~psram_wd.PSRAM_Memory_Interface_Top  .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on \~psram_init.PSRAM_Memory_Interface_Top  .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on DL .......
Running optimization stage 1 on \~psram_sync.PSRAM_Memory_Interface_Top  .......
Running optimization stage 1 on \~psram_top.PSRAM_Memory_Interface_Top  .......
@N:CG364 : psram_memory_interface.v(8709) | Synthesizing module PSRAM_Memory_Interface_Top in library work.
Running optimization stage 1 on PSRAM_Memory_Interface_Top .......
@W:CL168 : psram_memory_interface.v(8972) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : gowin_ahb_psram.v(5) | Synthesizing module Gowin_AHB_PSRAM_Top in library work.
Running optimization stage 1 on Gowin_AHB_PSRAM_Top .......
@W:CL271 : gowin_ahb_psram.v(47) | Pruning unused bits 1 to 0 of ahb_address[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@A:CL282 : gowin_ahb_psram.v(274) | Feedback mux created for signal reg_data_out3[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : gowin_ahb_psram.v(274) | Feedback mux created for signal reg_data_out2[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : gowin_ahb_psram.v(274) | Feedback mux created for signal reg_data_out1[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : gowin_ahb_psram.v(274) | Feedback mux created for signal reg_data_out0[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : gowin_ahb_psram.v(76) | Feedback mux created for signal reg_cmd_en. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
Running optimization stage 1 on MCU .......
Running optimization stage 1 on GW_CLKDIV .......
Running optimization stage 1 on DQCE .......
Running optimization stage 1 on FLASH128K .......
Running optimization stage 1 on gw_rom_flash .......
Running optimization stage 1 on GW_FLASH .......
Running optimization stage 1 on SP .......
Running optimization stage 1 on GW_SRAM4 .......
Running optimization stage 1 on ADC .......
Running optimization stage 1 on gw_cmsdk_apb2_adc .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on cmsdk_apb_uart .......
Running optimization stage 1 on gw_cmsdk_apb2_slave_mux .......
Running optimization stage 1 on DLCE .......
Running optimization stage 1 on DFFNCE .......
Running optimization stage 1 on SPI .......
Running optimization stage 1 on gw_cmsdk_apb2_spi .......
Running optimization stage 1 on gw_peripherals_interconnect .......
Running optimization stage 1 on \~Gowin_EMPU.Gowin_EMPU_Top  .......
@N:CG364 : gowin_empu.v(5514) | Synthesizing module Gowin_EMPU_Top in library work.
Running optimization stage 1 on Gowin_EMPU_Top .......
@W:CL168 : gowin_empu.v(5602) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : gowin_empu.v(5599) | Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : gowin_empu_template.v(2) | Synthesizing module Gowin_EMPU_Template in library work.
@W:CG781 : gowin_empu_template.v(61) | Input AHB_HMASTLOCK on instance u_Gowin_AHB_PSRAM_Top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : gowin_empu_template.v(62) | Input AHB_HMASTER on instance u_Gowin_AHB_PSRAM_Top is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : gowin_empu_template.v(48) | Removing wire master_exresp, as there is no assignment to it.
@W:CG360 : gowin_empu_template.v(49) | Removing wire master_hruser, as there is no assignment to it.
Running optimization stage 1 on Gowin_EMPU_Template .......
Running optimization stage 2 on Gowin_EMPU_Template .......
@W:CL156 : gowin_empu_template.v(48) | *Input master_exresp to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : gowin_empu_template.v(49) | *Input master_hruser[2:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on Gowin_EMPU_Top .......
Running optimization stage 2 on \~Gowin_EMPU.Gowin_EMPU_Top  .......
Running optimization stage 2 on gw_peripherals_interconnect .......
Running optimization stage 2 on gw_cmsdk_apb2_spi .......
Running optimization stage 2 on SPI .......
Running optimization stage 2 on DFFNCE .......
Running optimization stage 2 on DLCE .......
Running optimization stage 2 on gw_cmsdk_apb2_slave_mux .......
Running optimization stage 2 on cmsdk_apb_uart .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on gw_cmsdk_apb2_adc .......
Running optimization stage 2 on ADC .......
Running optimization stage 2 on GW_SRAM4 .......
Running optimization stage 2 on SP .......
Running optimization stage 2 on GW_FLASH .......
Running optimization stage 2 on gw_rom_flash .......
Running optimization stage 2 on FLASH128K .......
Running optimization stage 2 on DQCE .......
Running optimization stage 2 on GW_CLKDIV .......
Running optimization stage 2 on MCU .......
Running optimization stage 2 on Gowin_AHB_PSRAM_Top .......
@N:CL135 : gowin_ahb_psram.v(337) | Found sequential shift fall_edge_rd_valid1 with address depth of 3 words and data bit width of 1.
@N:CL201 : gowin_ahb_psram.v(274) | Trying to extract state machine for register rd_state.
Extracted state machine for register rd_state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N:CL201 : gowin_ahb_psram.v(220) | Trying to extract state machine for register wr_state.
Extracted state machine for register wr_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL247 : gowin_ahb_psram.v(11) | Input port bit 0 of AHB_HTRANS[1:0] is unused

@W:CL246 : gowin_ahb_psram.v(18) | Input port bits 31 to 12 of AHB_HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : gowin_ahb_psram.v(18) | Input port bits 1 to 0 of AHB_HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : gowin_ahb_psram.v(12) | Input AHB_HBURST is unused.
@N:CL159 : gowin_ahb_psram.v(13) | Input AHB_HPROT is unused.
@N:CL159 : gowin_ahb_psram.v(14) | Input AHB_HSIZE is unused.
@N:CL159 : gowin_ahb_psram.v(16) | Input AHB_HMASTLOCK is unused.
@N:CL159 : gowin_ahb_psram.v(17) | Input AHB_HMASTER is unused.
Running optimization stage 2 on PSRAM_Memory_Interface_Top .......
Running optimization stage 2 on \~psram_top.PSRAM_Memory_Interface_Top  .......
Running optimization stage 2 on \~psram_sync.PSRAM_Memory_Interface_Top  .......
Running optimization stage 2 on DL .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on \~psram_init.PSRAM_Memory_Interface_Top  .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on \~psram_wd.PSRAM_Memory_Interface_Top  .......
Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_Top  .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on RAM16SDP4 .......
Running optimization stage 2 on IDES4 .......
Running optimization stage 2 on OSER4 .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on OBUF .......
Running optimization stage 2 on ELVDS_OBUF .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on DLL .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on LUT2 .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 108MB peak: 108MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Thu Apr 23 15:14:59 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr 23 15:15:00 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  gowin_empu_ahb_psram_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:05s realtime, 0h:00m:03s cputime

Process completed successfully.
# Thu Apr 23 15:15:00 2020

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr 23 15:15:02 2020

###########################################################]


Premap Report



# Thu Apr 23 15:15:04 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1564R, Built Mar  4 2020 10:56:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  gowin_empu_ahb_psram_scck.rpt
See clock summary report "D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\impl\synthesize\rev_1\gowin_empu_ahb_psram_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 148MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0

Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)



Clock Summary
******************

          Start                                                                   Requested     Requested     Clock                                                                             Clock                     Clock
Level     Clock                                                                   Frequency     Period        Type                                                                              Group                     Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                                  211.6 MHz     4.725         system                                                                            system_clkgroup           0    
                                                                                                                                                                                                                               
0 -       _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock          152.8 MHz     6.546         inferred                                                                          Autoconstr_clkgroup_2     528  
1 .         _~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0]     152.8 MHz     6.546         derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_2     8    
1 .         _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0]          152.8 MHz     6.546         derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_2     1    
                                                                                                                                                                                                                               
0 -       GW_CLKDIV|master_hclk_inferred_clock                                    106.0 MHz     9.434         inferred                                                                          Autoconstr_clkgroup_0     446  
                                                                                                                                                                                                                               
0 -       _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock          100.0 MHz     10.000        inferred                                                                          Autoconstr_clkgroup_3     19   
                                                                                                                                                                                                                               
0 -       SPI|inv_4467_1_O_inferred_clock                                         100.0 MHz     10.000        inferred                                                                          Autoconstr_clkgroup_1     1    
===============================================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                      Clock     Source                                                                                                         Clock Pin                                                                                                                        Non-clock Pin                                                                                                                                     Non-clock Pin
Clock                                                                 Load      Pin                                                                                                            Seq Example                                                                                                                      Seq Example                                                                                                                                       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                0         -                                                                                                              -                                                                                                                                -                                                                                                                                                 -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock        528       u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.clkdiv.CLKOUT(CLKDIV)                           u_Gowin_AHB_PSRAM_Top.cross_reg_cmd1.C                                                                                           u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.\\iserdes_gen\[0\]\.u_ides4.PCLK     -            
_~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0]     8         u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.VALUE_0_ins3685.Q(DFFC)            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\dq_iodelay_gen0\[0\]\.\[0\]\.iodelay.VALUE           -                                                                                                                                                 -            
_~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0]          1         u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.step_0_ins3271.Q(DFFCE)              u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\ck_delay\[0\]\.iodelay.VALUE                         -                                                                                                                                                 -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               
GW_CLKDIV|master_hclk_inferred_clock                                  446       u_Gowin_EMPU_Top.Gowin_EMPU_inst.sysclk.clkdiv_inst.CLKOUT(CLKDIV)                                             u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.dw04_cs_ins3986.CLK                     -                                                                                                                                                 -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               
_~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock        19        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_dqce_clk_x2p.CLKOUT(DHCEN)                    u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.mask_oser4.FCLK     -                                                                                                                                                 -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               
SPI|inv_4467_1_O_inferred_clock                                       1         u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.inv_4467_1.O(INV)     u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467.G                   -                                                                                                                                                 -            
===============================================================================================================================================================================================================================================================================================================================================================================================================================================================================================


@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\impl\synthesize\rev_1\gowin_empu_ahb_psram.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB)

Encoding state machine rd_state[4:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog))
original code -> new code
   000 -> 000
   001 -> 001
   010 -> 010
   011 -> 011
   100 -> 100
Encoding state machine wr_state[3:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : gowin_ahb_psram.v(220) | There are no possible illegal states for state machine wr_state[3:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog)); safe FSM implementation is not required.

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 230MB peak: 230MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 231MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Thu Apr 23 15:15:08 2020

###########################################################]


Map & Optimize Report



# Thu Apr 23 15:15:08 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.09G-1
Install: D:\Gowin\Gowin_V1.9.5.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-029

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1564R, Built Mar  4 2020 10:56:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 231MB peak: 231MB)

Encoding state machine rd_state[4:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog))
original code -> new code
   000 -> 000
   001 -> 001
   010 -> 010
   011 -> 011
   100 -> 100
Encoding state machine wr_state[3:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : gowin_ahb_psram.v(220) | There are no possible illegal states for state machine wr_state[3:0] (in view: work.Gowin_AHB_PSRAM_Top(verilog)); safe FSM implementation is not required.

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 240MB peak: 240MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 241MB peak: 241MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 241MB peak: 241MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 241MB peak: 241MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 241MB peak: 241MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 241MB peak: 241MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 241MB peak: 241MB)


Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 241MB peak: 241MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 242MB peak: 242MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -7.83ns		1251 /       311
   2		0h:00m:04s		    -7.83ns		1250 /       311

   3		0h:00m:04s		    -7.83ns		1250 /       311

   4		0h:00m:04s		    -7.83ns		1250 /       311

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 242MB peak: 242MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@W:MT453 :  | clock period is too long for clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock, changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 242MB peak: 242MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 984 clock pin(s) of sequential element(s)
0 instances converted, 984 sequential instances remain driven by gated/generated clocks

================================================================================================================== Non-Gated/Non-Generated Clocks ==================================================================================================================
Clock Tree ID     Driving Element                                                                                 Drive Element Type     Fanout     Sample Instance                                                                                                 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0005        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.VALUE_0_ins3685     DFFC                   8          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\dq_iodelay_gen0\[0\]\.\[0\]\.iodelay
ClockId0006        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.step_0_ins3271        DFFCE                  1          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\ck_delay\[0\]\.iodelay              
====================================================================================================================================================================================================================================================================
======================================================================================================================================================================================= Gated/Generated Clocks =======================================================================================================================================================================================
Clock Tree ID     Driving Element                                                                                         Drive Element Type     Fanout     Sample Instance                                                                                                             Explanation                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.clkdiv                                   CLKDIV                 516        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_28_ins3232                                         Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
ClockId0002        u_Gowin_EMPU_Top.Gowin_EMPU_inst.sysclk.clkdiv_inst                                                     CLKDIV                 448        u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_flash_wrap.rom_haddr_test_14_ins3900                                                     Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
ClockId0003        u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_dqce_clk_x2p                           DHCEN                  19         u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.mask_oser4     No gated clock conversion method for cell cell:GOWIN.OSER4                                                    
ClockId0004        u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.inv_4467_1     INV                    1          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467                Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements
======================================================================================================================================================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 160MB peak: 242MB)

Writing Analyst data base D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\impl\synthesize\rev_1\synwork\gowin_empu_ahb_psram_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 239MB peak: 242MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 240MB peak: 242MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 240MB peak: 242MB)


Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 235MB peak: 242MB)

@W:MT246 : gowin_empu.v(5348) | Blackbox MCU is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(452) | Blackbox ADC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(91) | Blackbox DQCE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(50) | Blackbox FLASH128K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : gowin_empu.v(19) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : psram_memory_interface.v(7825) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : psram_memory_interface.v(7813) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock GW_CLKDIV|master_hclk_inferred_clock with period 13.21ns. Please declare a user-defined clock on net u_Gowin_EMPU_Top.Gowin_EMPU_inst.sysclk.master_hclk. 
@W:MT420 :  | Found inferred clock SPI|inv_4467_1_O_inferred_clock with period 10.00ns. Please declare a user-defined clock on net u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.inv_4467_1_O. 
@W:MT420 :  | Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock with period 10.96ns. Please declare a user-defined clock on net u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.clk_out. 
@W:MT420 :  | Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock with period 10.00ns. Please declare a user-defined clock on net u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.clk_x2p. 
@N:MT615 :  | Found clock _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] with period 10.96ns  
@N:MT615 :  | Found clock _~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0] with period 10.96ns  


##### START OF TIMING REPORT #####[
# Timing report written on Thu Apr 23 15:15:18 2020
#


Top view:               Gowin_EMPU_Template
Requested Frequency:    75.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -8.046

                                                                      Requested     Estimated     Requested     Estimated                Clock                                                                             Clock                
Starting Clock                                                        Frequency     Frequency     Period        Period        Slack      Type                                                                              Group                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
GW_CLKDIV|master_hclk_inferred_clock                                  75.7 MHz      34.1 MHz      13.214        29.307        -8.046     inferred                                                                          Autoconstr_clkgroup_0
SPI|inv_4467_1_O_inferred_clock                                       100.0 MHz     NA            10.000        NA            NA         inferred                                                                          Autoconstr_clkgroup_1
_~psram_init_PSRAM_Memory_Interface_Top_|VALUE_2_derived_clock[0]     91.3 MHz      NA            10.958        NA            NA         derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_2
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock        91.3 MHz      77.6 MHz      10.958        12.892        -1.934     inferred                                                                          Autoconstr_clkgroup_2
_~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock        100.0 MHz     NA            10.000        NA            NA         inferred                                                                          Autoconstr_clkgroup_3
_~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0]          91.3 MHz      NA            10.958        NA            NA         derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock)     Autoconstr_clkgroup_2
System                                                                109.3 MHz     92.9 MHz      9.148         10.762        -1.614     system                                                                            system_clkgroup      
================================================================================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                        Ending                                                          |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                          System                                                          |  9.148       -1.614  |  No paths    -      |  No paths    -       |  No paths    -    
System                                                          GW_CLKDIV|master_hclk_inferred_clock                            |  13.214      3.038   |  No paths    -      |  No paths    -       |  No paths    -    
System                                                          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  10.958      3.518   |  No paths    -      |  No paths    -       |  No paths    -    
GW_CLKDIV|master_hclk_inferred_clock                            System                                                          |  13.214      -2.207  |  No paths    -      |  No paths    -       |  No paths    -    
GW_CLKDIV|master_hclk_inferred_clock                            GW_CLKDIV|master_hclk_inferred_clock                            |  13.214      -2.332  |  No paths    -      |  6.607       -8.046  |  6.607       0.919
GW_CLKDIV|master_hclk_inferred_clock                            SPI|inv_4467_1_O_inferred_clock                                 |  No paths    -       |  No paths    -      |  Diff grp    -       |  No paths    -    
GW_CLKDIV|master_hclk_inferred_clock                            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -    
SPI|inv_4467_1_O_inferred_clock                                 GW_CLKDIV|master_hclk_inferred_clock                            |  Diff grp    -       |  No paths    -      |  Diff grp    -       |  No paths    -    
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  System                                                          |  10.958      0.294   |  No paths    -      |  No paths    -       |  No paths    -    
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  GW_CLKDIV|master_hclk_inferred_clock                            |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -    
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  |  10.958      -1.934  |  No paths    -      |  No paths    -       |  No paths    -    
_~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock  _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -    
========================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_CLKDIV|master_hclk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                                    Starting                                                                      Arrival           
Instance                                                                                                            Reference                                Type      Pin     Net                Time        Slack 
                                                                                                                    Clock                                                                                           
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       clock_polarity     0.440       -8.046
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4065        GW_CLKDIV|master_hclk_inferred_clock     DFFC      Q       SCLK_MASTER        0.440       -4.169
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4066        GW_CLKDIV|master_hclk_inferred_clock     DFFP      Q       SCLK_MASTER_7      0.440       -4.089
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_1_ins4208         GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       data_cnt[1]        0.440       -4.089
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_0_ins4211         GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       data_cnt[0]        0.440       -4.008
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_2_ins4205         GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       data_cnt[2]        0.440       -3.756
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_sel_0_ins4022        GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       clock_sel[0]       0.440       -3.521
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_cnt_0_ins4046        GW_CLKDIV|master_hclk_inferred_clock     DFFC      Q       clock_cnt[0]       0.440       -3.441
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_3_ins4202         GW_CLKDIV|master_hclk_inferred_clock     DFFCE     Q       data_cnt[3]        0.440       -3.369
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_cnt_3_ins4043        GW_CLKDIV|master_hclk_inferred_clock     DFFC      Q       clock_cnt[3]       0.440       -3.295
====================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                 Starting                                                                   Required           
Instance                                                                                                         Reference                                Type       Pin     Net            Time         Slack 
                                                                                                                 Clock                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467     GW_CLKDIV|master_hclk_inferred_clock     DLCE       D       n623           -3.837       -8.046
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_0_ins4690      GW_CLKDIV|master_hclk_inferred_clock     DFFNCE     D       n326           6.447        -8.046
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_2_ins4688      GW_CLKDIV|master_hclk_inferred_clock     DFFNCE     D       n324           6.447        -8.046
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_1_ins4689      GW_CLKDIV|master_hclk_inferred_clock     DFFNCE     D       n325           6.447        -7.966
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_0_ins4211      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_1_ins4208      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_2_ins4205      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_3_ins4202      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_4_ins4199      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_5_ins4196      GW_CLKDIV|master_hclk_inferred_clock     DFFCE      CE      data_cnt_5     13.055       -2.332
===============================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.607
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.447

    - Propagation time:                      14.494
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -8.046

    Number of logic level(s):                6
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020 / Q
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_2_ins4688 / D
    The start point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     DFFCE      Q        Out     0.440     0.440       -         
clock_polarity                                                                                                      Net        -        -       1.225     -           7         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       I1       In      -         1.666       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       F        Out     1.319     2.984       -         
n623                                                                                                                Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       D        In      -         4.210       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       Q        Out     0.440     4.650       -         
SCLK_MASTER_17                                                                                                      Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       I2       In      -         5.875       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       F        Out     0.986     6.862       -         
n202_11                                                                                                             Net        -        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       I1       In      -         8.087       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       F        Out     1.319     9.406       -         
n326_47                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_5_ins4949         LUT4       I1       In      -         10.631      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_5_ins4949         LUT4       F        Out     1.319     11.950      -         
data_cnt_5_21                                                                                                       Net        -        -       1.225     -           4         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n324_ins4830               LUT2       I1       In      -         13.175      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n324_ins4830               LUT2       F        Out     1.319     14.494      -         
n324                                                                                                                Net        -        -       0.000     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_2_ins4688         DFFNCE     D        In      -         14.494      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 14.653 is 7.302(49.8%) logic and 7.351(50.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.607
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.447

    - Propagation time:                      14.494
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -8.046

    Number of logic level(s):                6
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020 / Q
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_0_ins4690 / D
    The start point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     DFFCE      Q        Out     0.440     0.440       -         
clock_polarity                                                                                                      Net        -        -       1.225     -           7         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       I1       In      -         1.666       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       F        Out     1.319     2.984       -         
n623                                                                                                                Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       D        In      -         4.210       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       Q        Out     0.440     4.650       -         
SCLK_MASTER_17                                                                                                      Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       I2       In      -         5.875       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       F        Out     0.986     6.862       -         
n202_11                                                                                                             Net        -        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       I1       In      -         8.087       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       F        Out     1.319     9.406       -         
n326_47                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       I1       In      -         10.631      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       F        Out     1.319     11.950      -         
n326_39                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4804               LUT4       I1       In      -         13.175      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4804               LUT4       F        Out     1.319     14.494      -         
n326                                                                                                                Net        -        -       0.000     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_0_ins4690         DFFNCE     D        In      -         14.494      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 14.653 is 7.302(49.8%) logic and 7.351(50.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.607
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.447

    - Propagation time:                      14.413
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.966

    Number of logic level(s):                6
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020 / Q
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_1_ins4689 / D
    The start point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     DFFCE      Q        Out     0.440     0.440       -         
clock_polarity                                                                                                      Net        -        -       1.225     -           7         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       I1       In      -         1.666       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       F        Out     1.319     2.984       -         
n623                                                                                                                Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       D        In      -         4.210       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       Q        Out     0.440     4.650       -         
SCLK_MASTER_17                                                                                                      Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       I2       In      -         5.875       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       F        Out     0.986     6.862       -         
n202_11                                                                                                             Net        -        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       I1       In      -         8.087       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4984               LUT4       F        Out     1.319     9.406       -         
n326_47                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       I1       In      -         10.631      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       F        Out     1.319     11.950      -         
n326_39                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n325_ins4820               LUT4       I0       In      -         13.175      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n325_ins4820               LUT4       F        Out     1.238     14.413      -         
n325                                                                                                                Net        -        -       0.000     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_1_ins4689         DFFNCE     D        In      -         14.413      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 14.573 is 7.222(49.6%) logic and 7.351(50.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.607
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.447

    - Propagation time:                      14.081
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.633

    Number of logic level(s):                6
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020 / Q
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_2_ins4688 / D
    The start point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     DFFCE      Q        Out     0.440     0.440       -         
clock_polarity                                                                                                      Net        -        -       1.225     -           7         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       I1       In      -         1.666       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       F        Out     1.319     2.984       -         
n623                                                                                                                Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       D        In      -         4.210       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       Q        Out     0.440     4.650       -         
SCLK_MASTER_17                                                                                                      Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       I2       In      -         5.875       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       F        Out     0.986     6.862       -         
n202_11                                                                                                             Net        -        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4985               LUT4       I0       In      -         8.087       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4985               LUT4       F        Out     1.238     9.325       -         
n326_49                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_5_ins4949         LUT4       I2       In      -         10.550      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.data_cnt_5_ins4949         LUT4       F        Out     0.986     11.537      -         
data_cnt_5_21                                                                                                       Net        -        -       1.225     -           4         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n324_ins4830               LUT2       I1       In      -         12.762      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n324_ins4830               LUT2       F        Out     1.319     14.081      -         
n324                                                                                                                Net        -        -       0.000     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_2_ins4688         DFFNCE     D        In      -         14.081      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 14.240 is 6.889(48.4%) logic and 7.351(51.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.607
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.447

    - Propagation time:                      14.081
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.633

    Number of logic level(s):                6
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020 / Q
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_0_ins4690 / D
    The start point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_CLKDIV|master_hclk_inferred_clock [falling] on pin CLK

Instance / Net                                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.clock_polarity_ins4020     DFFCE      Q        Out     0.440     0.440       -         
clock_polarity                                                                                                      Net        -        -       1.225     -           7         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       I1       In      -         1.666       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n623_ins4747               LUT2       F        Out     1.319     2.984       -         
n623                                                                                                                Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       D        In      -         4.210       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.SCLK_MASTER_ins4467        DLCE       Q        Out     0.440     4.650       -         
SCLK_MASTER_17                                                                                                      Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       I2       In      -         5.875       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n202_ins4904               LUT3       F        Out     0.986     6.862       -         
n202_11                                                                                                             Net        -        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4985               LUT4       I0       In      -         8.087       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4985               LUT4       F        Out     1.238     9.325       -         
n326_49                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       I2       In      -         10.550      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4938               LUT4       F        Out     0.986     11.537      -         
n326_39                                                                                                             Net        -        -       1.225     -           2         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4804               LUT4       I1       In      -         12.762      -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n326_ins4804               LUT4       F        Out     1.319     14.081      -         
n326                                                                                                                Net        -        -       0.000     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n_status_0_ins4690         DFFNCE     D        In      -         14.081      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 14.240 is 6.889(48.4%) logic and 7.351(51.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                                                          Starting                                                                                                   Arrival           
Instance                                                                                                                  Reference                                                          Type      Pin     Net                   Time        Slack 
                                                                                                                          Clock                                                                                                                        
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_dd0_0_ins3696                      _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       init_calib_dd0[0]     0.440       -1.934
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_ddd_0_ins3756                      _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       init_calib_ddd[0]     0.440       -1.853
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_21_ins3239                                       _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d_1[21]       0.440       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_d2_ins3766                         _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       init_calib            0.440       -1.697
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_15_ins3245                                       _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d_1[15]       0.440       -1.681
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_28_ins3232                                       _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d_1[28]       0.440       -1.681
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_d_0_ins3702                        _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       init_calib_d[0]       0.440       -1.675
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_18_ins3242                                       _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFC      Q       rd_data_d_1[18]       0.440       -1.600
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.wr_ptr_1_ins4167     _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       wr_ptr[1]             0.440       -1.509
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.wr_ptr_0_ins4171     _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     Q       wr_ptr[0]             0.440       -1.429
=======================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                                  Starting                                                                                              Required           
Instance                                                                                                                          Reference                                                          Type      Pin     Net              Time         Slack 
                                                                                                                                  Clock                                                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_0_ins3818     _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      wr_ptr_1         10.798       -1.934
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins3815     _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      wr_ptr_1         10.798       -1.934
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_ins4220          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_1_ins4217          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_2_ins4214          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_3_ins4211          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_4_ins4208          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_ins4205          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_6_ins4202          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_7_ins4199          _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock     DFFCE     CE      check_cnt_10     10.798       -1.761
===========================================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.958
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.798

    - Propagation time:                      12.732
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.934

    Number of logic level(s):                5
    Starting point:                          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_dd0_0_ins3696 / Q
    Ending point:                            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_0_ins3818 / CE
    The start point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_dd0_0_ins3696                                  DFFCE     Q        Out     0.440     0.440       -         
init_calib_dd0[0]                                                                                                                     Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      I1       In      -         1.666       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      F        Out     1.319     2.984       -         
wr_en_9                                                                                                                               Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      I2       In      -         4.210       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      F        Out     0.986     5.196       -         
CA_63                                                                                                                                 Net       -        -       1.372     -           26        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      I3       In      -         6.568       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      F        Out     0.751     7.319       -         
wr_en                                                                                                                                 Net       -        -       1.225     -           5         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      I3       In      -         8.544       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      F        Out     0.751     9.295       -         
wr_data_ctrl                                                                                                                          Net       -        -       1.225     -           10        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      I2       In      -         10.520      -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      F        Out     0.986     11.507      -         
wr_ptr_1                                                                                                                              Net       -        -       1.225     -           2         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_0_ins3818         DFFCE     CE       In      -         12.732      -         
=================================================================================================================================================================================================
Total path delay (propagation time + setup) of 12.892 is 5.394(41.8%) logic and 7.498(58.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.958
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.798

    - Propagation time:                      12.732
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.934

    Number of logic level(s):                5
    Starting point:                          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_dd0_0_ins3696 / Q
    Ending point:                            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins3815 / CE
    The start point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_dd0_0_ins3696                                  DFFCE     Q        Out     0.440     0.440       -         
init_calib_dd0[0]                                                                                                                     Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      I1       In      -         1.666       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      F        Out     1.319     2.984       -         
wr_en_9                                                                                                                               Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      I2       In      -         4.210       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      F        Out     0.986     5.196       -         
CA_63                                                                                                                                 Net       -        -       1.372     -           26        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      I3       In      -         6.568       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      F        Out     0.751     7.319       -         
wr_en                                                                                                                                 Net       -        -       1.225     -           5         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      I3       In      -         8.544       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      F        Out     0.751     9.295       -         
wr_data_ctrl                                                                                                                          Net       -        -       1.225     -           10        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      I2       In      -         10.520      -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      F        Out     0.986     11.507      -         
wr_ptr_1                                                                                                                              Net       -        -       1.225     -           2         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins3815         DFFCE     CE       In      -         12.732      -         
=================================================================================================================================================================================================
Total path delay (propagation time + setup) of 12.892 is 5.394(41.8%) logic and 7.498(58.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.958
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.798

    - Propagation time:                      12.652
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.853

    Number of logic level(s):                5
    Starting point:                          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_ddd_0_ins3756 / Q
    Ending point:                            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_0_ins3818 / CE
    The start point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_ddd_0_ins3756                                  DFFCE     Q        Out     0.440     0.440       -         
init_calib_ddd[0]                                                                                                                     Net       -        -       1.225     -           3         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      I0       In      -         1.666       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      F        Out     1.238     2.904       -         
wr_en_9                                                                                                                               Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      I2       In      -         4.129       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      F        Out     0.986     5.116       -         
CA_63                                                                                                                                 Net       -        -       1.372     -           26        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      I3       In      -         6.487       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      F        Out     0.751     7.238       -         
wr_en                                                                                                                                 Net       -        -       1.225     -           5         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      I3       In      -         8.464       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      F        Out     0.751     9.215       -         
wr_data_ctrl                                                                                                                          Net       -        -       1.225     -           10        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      I2       In      -         10.440      -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      F        Out     0.986     11.426      -         
wr_ptr_1                                                                                                                              Net       -        -       1.225     -           2         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_0_ins3818         DFFCE     CE       In      -         12.652      -         
=================================================================================================================================================================================================
Total path delay (propagation time + setup) of 12.811 is 5.314(41.5%) logic and 7.498(58.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.958
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.798

    - Propagation time:                      12.652
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.853

    Number of logic level(s):                5
    Starting point:                          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_ddd_0_ins3756 / Q
    Ending point:                            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins3815 / CE
    The start point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                                  Pin      Pin               Arrival     No. of    
Name                                                                                                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.init_calib_ddd_0_ins3756                                  DFFCE     Q        Out     0.440     0.440       -         
init_calib_ddd[0]                                                                                                                     Net       -        -       1.225     -           3         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      I0       In      -         1.666       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins6246            LUT3      F        Out     1.238     2.904       -         
wr_en_9                                                                                                                               Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      I2       In      -         4.129       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.CA_63_ins5821            LUT3      F        Out     0.986     5.116       -         
CA_63                                                                                                                                 Net       -        -       1.372     -           26        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      I3       In      -         6.487       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_en_ins5817            LUT4      F        Out     0.751     7.238       -         
wr_en                                                                                                                                 Net       -        -       1.225     -           5         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      I3       In      -         8.464       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_data_ctrl_ins5819     LUT4      F        Out     0.751     9.215       -         
wr_data_ctrl                                                                                                                          Net       -        -       1.225     -           10        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      I2       In      -         10.440      -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins5904         LUT3      F        Out     0.986     11.426      -         
wr_ptr_1                                                                                                                              Net       -        -       1.225     -           2         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_wd.\\data_lane_gen\[0\]\.u_psram_lane.wr_ptr_1_ins3815         DFFCE     CE       In      -         12.652      -         
=================================================================================================================================================================================================
Total path delay (propagation time + setup) of 12.811 is 5.314(41.5%) logic and 7.498(58.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.958
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.798

    - Propagation time:                      12.559
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.761

    Number of logic level(s):                5
    Starting point:                          u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_21_ins3239 / Q
    Ending point:                            u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_ins4220 / CE
    The start point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                          Pin      Pin               Arrival     No. of    
Name                                                                                                                          Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.rd_data_d_21_ins3239                                           DFFC      Q        Out     0.440     0.440       -         
rd_data_d_1[21]                                                                                                               Net       -        -       1.225     -           4         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6398     LUT4      I1       In      -         1.666       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6398     LUT4      F        Out     1.319     2.984       -         
check_cnt_10_53                                                                                                               Net       -        -       0.919     -           1         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6377     LUT2      I1       In      -         3.903       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6377     LUT2      F        Out     1.319     5.222       -         
check_cnt_10_29                                                                                                               Net       -        -       1.225     -           2         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6385     LUT4      I0       In      -         6.447       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6385     LUT4      F        Out     1.238     7.686       -         
check_cnt_10_45                                                                                                               Net       -        -       0.919     -           1         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6315     LUT4      I2       In      -         8.605       -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins6315     LUT4      F        Out     0.986     9.591       -         
check_cnt_10_25                                                                                                               Net       -        -       0.919     -           1         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins5919     LUT4      I3       In      -         10.510      -         
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_10_ins5919     LUT4      F        Out     0.751     11.261      -         
check_cnt_10                                                                                                                  Net       -        -       1.298     -           11        
u_Gowin_AHB_PSRAM_Top.u_PSRAM_Memory_Interface_Top.u_psram_top.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_ins4220      DFFCE     CE       In      -         12.559      -         
=========================================================================================================================================================================================
Total path delay (propagation time + setup) of 12.719 is 6.214(48.9%) logic and 6.505(51.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                               Starting                                                                  Arrival           
Instance                                       Reference     Type     Pin                      Net                       Time        Slack 
                                               Clock                                                                                       
-------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[11]     apbtargexp2_paddr[11]     0.000       -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[10]     apbtargexp2_paddr[10]     0.000       -1.534
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[9]      apbtargexp2_paddr[9]      0.000       -1.282
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[3]      apbtargexp2_paddr[3]      0.000       -1.257
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[2]      apbtargexp2_paddr[2]      0.000       -1.250
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PSEL          apbtargexp2_psel          0.000       -1.047
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[4]      apbtargexp2_paddr[4]      0.000       -0.852
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[6]      apbtargexp2_paddr[6]      0.000       0.792 
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[5]      apbtargexp2_paddr[5]      0.000       0.873 
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PADDR[8]      apbtargexp2_paddr[8]      0.000       1.010 
===========================================================================================================================================


Ending Points with Worst Slack
******************************

                                               Starting                                                  Required           
Instance                                       Reference     Type     Pin                       Net      Time         Slack 
                                               Clock                                                                        
----------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[0]      n388     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[1]      n389     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[2]      n390     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[3]      n391     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[4]      n392     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[5]      n393     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[6]      n394     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[7]      n395     9.148        -1.614
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[16]     n372     9.148        -1.257
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top     System        MCU      APBTARGEXP2PRDATA[17]     n373     9.148        -1.257
============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      9.148
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.148

    - Propagation time:                      10.762
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                4
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[0]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                     Pin                      Pin               Arrival     No. of    
Name                                                                                                      Type     Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                     Net      -                        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     I1                       In      -         1.225       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     F                        Out     1.319     2.544       -         
read_enable_9                                                                                             Net      -                        -       1.225     -           6         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     I1                       In      -         3.769       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     F                        Out     1.319     5.088       -         
n21                                                                                                       Net      -                        -       1.225     -           9         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n388_ins4878     LUT4     I1                       In      -         6.313       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n388_ins4878     LUT4     F                        Out     1.319     7.632       -         
n388_9                                                                                                    Net      -                        -       0.919     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n388_ins4707     LUT3     I2                       In      -         8.551       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n388_ins4707     LUT3     F                        Out     0.986     9.537       -         
n388                                                                                                      Net      -                        -       1.225     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PRDATA[0]     In      -         10.762      -         
====================================================================================================================================================================================
Total path delay (propagation time + setup) of 10.762 is 4.943(45.9%) logic and 5.820(54.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      9.148
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.148

    - Propagation time:                      10.762
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                4
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[7]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                     Pin                      Pin               Arrival     No. of    
Name                                                                                                      Type     Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                     Net      -                        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     I1                       In      -         1.225       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     F                        Out     1.319     2.544       -         
read_enable_9                                                                                             Net      -                        -       1.225     -           6         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     I1                       In      -         3.769       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     F                        Out     1.319     5.088       -         
n21                                                                                                       Net      -                        -       1.225     -           9         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n395_ins4885     LUT4     I1                       In      -         6.313       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n395_ins4885     LUT4     F                        Out     1.319     7.632       -         
n395_9                                                                                                    Net      -                        -       0.919     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n395_ins4714     LUT3     I2                       In      -         8.551       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n395_ins4714     LUT3     F                        Out     0.986     9.537       -         
n395                                                                                                      Net      -                        -       1.225     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PRDATA[7]     In      -         10.762      -         
====================================================================================================================================================================================
Total path delay (propagation time + setup) of 10.762 is 4.943(45.9%) logic and 5.820(54.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      9.148
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.148

    - Propagation time:                      10.762
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                4
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[6]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                     Pin                      Pin               Arrival     No. of    
Name                                                                                                      Type     Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                     Net      -                        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     I1                       In      -         1.225       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     F                        Out     1.319     2.544       -         
read_enable_9                                                                                             Net      -                        -       1.225     -           6         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     I1                       In      -         3.769       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     F                        Out     1.319     5.088       -         
n21                                                                                                       Net      -                        -       1.225     -           9         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n394_ins4884     LUT4     I1                       In      -         6.313       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n394_ins4884     LUT4     F                        Out     1.319     7.632       -         
n394_9                                                                                                    Net      -                        -       0.919     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n394_ins4713     LUT3     I2                       In      -         8.551       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n394_ins4713     LUT3     F                        Out     0.986     9.537       -         
n394                                                                                                      Net      -                        -       1.225     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PRDATA[6]     In      -         10.762      -         
====================================================================================================================================================================================
Total path delay (propagation time + setup) of 10.762 is 4.943(45.9%) logic and 5.820(54.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      9.148
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.148

    - Propagation time:                      10.762
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                4
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[5]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                     Pin                      Pin               Arrival     No. of    
Name                                                                                                      Type     Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                     Net      -                        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     I1                       In      -         1.225       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     F                        Out     1.319     2.544       -         
read_enable_9                                                                                             Net      -                        -       1.225     -           6         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     I1                       In      -         3.769       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     F                        Out     1.319     5.088       -         
n21                                                                                                       Net      -                        -       1.225     -           9         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n393_ins4883     LUT4     I1                       In      -         6.313       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n393_ins4883     LUT4     F                        Out     1.319     7.632       -         
n393_9                                                                                                    Net      -                        -       0.919     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n393_ins4712     LUT3     I2                       In      -         8.551       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n393_ins4712     LUT3     F                        Out     0.986     9.537       -         
n393                                                                                                      Net      -                        -       1.225     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PRDATA[5]     In      -         10.762      -         
====================================================================================================================================================================================
Total path delay (propagation time + setup) of 10.762 is 4.943(45.9%) logic and 5.820(54.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      9.148
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.148

    - Propagation time:                      10.762
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                4
    Starting point:                          u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PADDR[11]
    Ending point:                            u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top / APBTARGEXP2PRDATA[4]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                     Pin                      Pin               Arrival     No. of    
Name                                                                                                      Type     Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PADDR[11]     Out     0.000     0.000       -         
apbtargexp2_paddr[11]                                                                                     Net      -                        -       1.225     -           3         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     I1                       In      -         1.225       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_apb_uart_es.read_enable_ins4909       LUT4     F                        Out     1.319     2.544       -         
read_enable_9                                                                                             Net      -                        -       1.225     -           6         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     I1                       In      -         3.769       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_spi.u_spi.n21_ins4894      LUT2     F                        Out     1.319     5.088       -         
n21                                                                                                       Net      -                        -       1.225     -           9         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n392_ins4882     LUT4     I1                       In      -         6.313       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n392_ins4882     LUT4     F                        Out     1.319     7.632       -         
n392_9                                                                                                    Net      -                        -       0.919     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n392_ins4711     LUT3     I2                       In      -         8.551       -         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_gw_peripherals_interconnect.u_gw_cmsdk_apb2_slave_mux.n392_ins4711     LUT3     F                        Out     0.986     9.537       -         
n392                                                                                                      Net      -                        -       1.225     -           1         
u_Gowin_EMPU_Top.Gowin_EMPU_inst.u_mcu_top                                                                MCU      APBTARGEXP2PRDATA[4]     In      -         10.762      -         
====================================================================================================================================================================================
Total path delay (propagation time + setup) of 10.762 is 4.943(45.9%) logic and 5.820(54.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 236MB peak: 242MB)


Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 236MB peak: 242MB)

---------------------------------------
Resource Usage Report for Gowin_EMPU_Template 

Mapping to part: gw1nsr_2cqfn48-5
Cell usage:
ADC             1 use
ALU             51 uses
CLKDIV          2 uses
DFFC            276 uses
DFFCE           518 uses
DFFE            129 uses
DFFNCE          3 uses
DFFP            4 uses
DFFPE           10 uses
DHCEN           1 use
DL              8 uses
DLCE            1 use
DLL             1 use
DQCE            1 use
FLASH128K       1 use
GSR             2 uses
IDES4           8 uses
INV             17 uses
IODELAY         9 uses
MCU             1 use
MUX2_LUT5       36 uses
OSER4           11 uses
RAM16SDP4       9 uses
SP              4 uses
LUT1            1 use
LUT2            303 uses
LUT3            337 uses
LUT4            606 uses

I/O ports: 18
I/O primitives: 17
ELVDS_OBUF     1 use
IBUF           3 uses
IOBUF          9 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   940 of 1080 (87%)

RAM/ROM usage summary
Block Rams : 4 of 4 (100%)

Total load per clock:
   GW_CLKDIV|master_hclk_inferred_clock: 451

@S |Mapping Summary:
Total  LUTs: 1247 (72%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 79MB peak: 242MB)

Process took 0h:00m:09s realtime, 0h:00m:09s cputime
# Thu Apr 23 15:15:18 2020

###########################################################]