Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.5.01Beta
Created Time Thu Apr 23 15:46:54 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: PSRAM_Memory_Interface_Top
Part Number: GW1NSR-LX2CQN48PC5/I4

Resource

Resource Usage Summary

I/OPORT Usage: 98
Emedded PORT Usage: 13
I/OBUF Usage: 110
    IBUF 63
    OBUF 37
    IOBUF 9
    ELVDS_OBUF 1
REG Usage: 395
    DFFP 2
    DFFPE 4
    DFFC 205
    DFFCE 176
    DL 8
LUT Usage: 610
    LUT2 235
    LUT3 130
    LUT4 245
ALU Usage: 31
    ALU 31
SSRAM Usage: 9
    RAM16SDP4 9
INV Usage: 9
    INV 9
IOLOGIC Usage: 28
    IDES4 8
    OSER4 11
    IODELAY 9
CLOCK Usage: 2
    DLL 1
    CLKDIV 1

Resource Utilization Summary

Target Device: GW1NSR-2C-QFN48
CFU Logics 704(619 LUTs, 31 ALUs, 9 SSRAMs) / 1728 41%
Registers 395 / 1437 27%
BSRAMs 0 / 4 0%
DSP Macros 0 / (0*2) -


Timing

Clock Summary:

Clock Type Frequency Period Rise Fall Source Master Object
u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 50.0 MHz 20.000 0.000 10.000 DEFAULT_CLK
DEFAULT_CLK Base 100.0 MHz 10.000 0.000 5.000

Timing Report:

Top View: PSRAM_Memory_Interface_Top
Requested Frequency: 50.0 MHz
Paths Requested: 5
Constraint File(ignored):
All time values displayed in nanoseconds(ns).

Performance Summary:

Worst Slack in Design: 10.188
Start Clock Slack Requested Frequency Estimated Frequency Requested Period Estimated Period Clock Type
u_psram_top/clkdiv/CLKOUT.default_gen_clk 10.188 50.0 MHz 101.9 MHz 20.000 9.812 Generated

Detail Timing Paths Information

Path information for path number 1 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(critical): -0.948
Data Arrival Time: 11.646
Data Required Time: 10.698
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_ins4318
Ending Point: u_psram_top/u_psram_sync/lock_cnt_14_ins4279
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf2989 IBUF I In - 0.000 -
clk_ibuf2989 IBUF O Out 0.943 0.943 -
clk Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE Q Out 0.550 1.928 -
u_psram_top_u_psram_sync_lock_cnt[1] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 F Out 1.319 3.823 -
u_psram_top_u_psram_sync_n48 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 I2 In - 4.399 -
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 F Out 0.986 5.385 -
u_psram_top_u_psram_sync_n46 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 I1 In - 5.961 -
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 F Out 1.319 7.280 -
u_psram_top_u_psram_sync_n43 Net - - 0.576 - 6
\u_psram_top/u_psram_sync/n37_ins6359 LUT3 I1 In - 7.856 -
\u_psram_top/u_psram_sync/n37_ins6359 LUT3 F Out 1.319 9.175 -
u_psram_top_u_psram_sync_n37 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n37_ins6491 LUT4 I1 In - 9.751 -
\u_psram_top/u_psram_sync/n37_ins6491 LUT4 F Out 1.319 11.070 -
u_psram_top_u_psram_sync_n37_17 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_14_ins4279 DFFCE D In - 11.646 -

Total Path Delay: 11.646
Logic Delay: 7.754(66.6%)
Route Delay: 3.892(33.4%)


Path information for path number 2 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.867
Data Arrival Time: 11.565
Data Required Time: 10.698
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_ins4318
Ending Point: u_psram_top/u_psram_sync/lock_cnt_11_ins4288
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf2989 IBUF I In - 0.000 -
clk_ibuf2989 IBUF O Out 0.943 0.943 -
clk Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE Q Out 0.550 1.928 -
u_psram_top_u_psram_sync_lock_cnt[1] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 F Out 1.319 3.823 -
u_psram_top_u_psram_sync_n48 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 I2 In - 4.399 -
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 F Out 0.986 5.385 -
u_psram_top_u_psram_sync_n46 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 I1 In - 5.961 -
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 F Out 1.319 7.280 -
u_psram_top_u_psram_sync_n43 Net - - 0.576 - 6
\u_psram_top/u_psram_sync/n40_ins6518 LUT4 I0 In - 7.856 -
\u_psram_top/u_psram_sync/n40_ins6518 LUT4 F Out 1.238 9.095 -
u_psram_top_u_psram_sync_n40 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n40_ins6492 LUT4 I1 In - 9.671 -
\u_psram_top/u_psram_sync/n40_ins6492 LUT4 F Out 1.319 10.989 -
u_psram_top_u_psram_sync_n40_23 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_11_ins4288 DFFCE D In - 11.565 -

Total Path Delay: 11.565
Logic Delay: 7.674(66.4%)
Route Delay: 3.892(33.6%)


Path information for path number 3 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.867
Data Arrival Time: 11.565
Data Required Time: 10.698
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_ins4318
Ending Point: u_psram_top/u_psram_sync/lock_cnt_12_ins4285
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf2989 IBUF I In - 0.000 -
clk_ibuf2989 IBUF O Out 0.943 0.943 -
clk Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE Q Out 0.550 1.928 -
u_psram_top_u_psram_sync_lock_cnt[1] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 F Out 1.319 3.823 -
u_psram_top_u_psram_sync_n48 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 I2 In - 4.399 -
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 F Out 0.986 5.385 -
u_psram_top_u_psram_sync_n46 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 I1 In - 5.961 -
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 F Out 1.319 7.280 -
u_psram_top_u_psram_sync_n43 Net - - 0.576 - 6
\u_psram_top/u_psram_sync/n40_ins6518 LUT4 I0 In - 7.856 -
\u_psram_top/u_psram_sync/n40_ins6518 LUT4 F Out 1.238 9.095 -
u_psram_top_u_psram_sync_n40 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n39_ins6062 LUT4 I1 In - 9.671 -
\u_psram_top/u_psram_sync/n39_ins6062 LUT4 F Out 1.319 10.989 -
u_psram_top_u_psram_sync_n39 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_12_ins4285 DFFCE D In - 11.565 -

Total Path Delay: 11.565
Logic Delay: 7.674(66.4%)
Route Delay: 3.892(33.6%)


Path information for path number 4 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): -0.380
Data Arrival Time: 11.078
Data Required Time: 10.698
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/lock_cnt_1_ins4318
Ending Point: u_psram_top/u_psram_sync/lock_cnt_15_ins4276
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf2989 IBUF I In - 0.000 -
clk_ibuf2989 IBUF O Out 0.943 0.943 -
clk Net - - 0.436 - 31
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE CLK In - 1.378 -
\u_psram_top/u_psram_sync/lock_cnt_1_ins4318 DFFCE Q Out 0.550 1.928 -
u_psram_top_u_psram_sync_lock_cnt[1] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n48_ins6352 LUT3 F Out 1.319 3.823 -
u_psram_top_u_psram_sync_n48 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 I2 In - 4.399 -
\u_psram_top/u_psram_sync/n46_ins6353 LUT3 F Out 0.986 5.385 -
u_psram_top_u_psram_sync_n46 Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 I1 In - 5.961 -
\u_psram_top/u_psram_sync/n43_ins6420 LUT4 F Out 1.319 7.280 -
u_psram_top_u_psram_sync_n43 Net - - 0.576 - 6
\u_psram_top/u_psram_sync/n37_ins6359 LUT3 I1 In - 7.856 -
\u_psram_top/u_psram_sync/n37_ins6359 LUT3 F Out 1.319 9.175 -
u_psram_top_u_psram_sync_n37 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n36_ins6490 LUT4 I3 In - 9.751 -
\u_psram_top/u_psram_sync/n36_ins6490 LUT4 F Out 0.751 10.502 -
u_psram_top_u_psram_sync_n36 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/lock_cnt_15_ins4276 DFFCE D In - 11.078 -

Total Path Delay: 11.078
Logic Delay: 7.187(64.9%)
Route Delay: 3.892(35.1%)


Path information for path number 5 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 0.423
Data Arrival Time: 10.275
Data Required Time: 10.698
Number of Logic Level: 6
Starting Point: u_psram_top/u_psram_sync/count_2_ins3795
Ending Point: u_psram_top/u_psram_sync/count_0_ins3797
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
clk_ibuf2989 IBUF I In - 0.000 -
clk_ibuf2989 IBUF O Out 0.943 0.943 -
clk Net - - 0.436 - 31
\u_psram_top/u_psram_sync/count_2_ins3795 DFFC CLK In - 1.378 -
\u_psram_top/u_psram_sync/count_2_ins3795 DFFC Q Out 0.550 1.928 -
u_psram_top_u_psram_sync_count[2] Net - - 0.576 - 4
\u_psram_top/u_psram_sync/n285_ins6387 LUT2 I1 In - 2.504 -
\u_psram_top/u_psram_sync/n285_ins6387 LUT2 F Out 1.319 3.823 -
u_psram_top_u_psram_sync_n285 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n327_ins6392 LUT4 I3 In - 4.399 -
\u_psram_top/u_psram_sync/n327_ins6392 LUT4 F Out 0.751 5.150 -
u_psram_top_u_psram_sync_n327 Net - - 0.576 - 2
\u_psram_top/u_psram_sync/n414_ins6394 LUT4 I3 In - 5.726 -
\u_psram_top/u_psram_sync/n414_ins6394 LUT4 F Out 0.751 6.477 -
u_psram_top_u_psram_sync_n414 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/n414_ins6350 LUT4 I3 In - 7.053 -
\u_psram_top/u_psram_sync/n414_ins6350 LUT4 F Out 0.751 7.805 -
u_psram_top_u_psram_sync_n414_13 Net - - 0.576 - 3
\u_psram_top/u_psram_sync/n414_ins6047 LUT2 I1 In - 8.381 -
\u_psram_top/u_psram_sync/n414_ins6047 LUT2 F Out 1.319 9.699 -
u_psram_top_u_psram_sync_n414_11 Net - - 0.576 - 1
\u_psram_top/u_psram_sync/count_0_ins3797 DFFC D In - 10.275 -

Total Path Delay: 10.275
Logic Delay: 6.384(62.1%)
Route Delay: 3.892(37.9%)


Message

Info (EXT0100) : Run analyzation & elaboration
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v'
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:2)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:3)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:3)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:29)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:29)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:30)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:30)
Info (EXT1482) : Analyzing Verilog file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:34)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:14)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:36)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:34)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:14)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:36)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:34)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:34)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:14)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:36)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_define.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:34)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:2)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Info (EXT1328) : Analyzing included file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_local_param.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:14)
Info (EXT2320) : Back to file 'D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:1437)
Warning (EXT1212) : Block identifier is required on this block(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module 'PSRAM_Memory_Interface_Top'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v:5)
Warning (EXT1927) : Port '**' remains unconnected for this instance(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT1018) : Compiling module '**'(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Warning (EXT3002) : Net '**' does not have a driver(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (EXT0101) : Current top module is "PSRAM_Memory_Interface_Top"
Warning (NLT0001) : Sweep user defined dangling instance "u_psram_top\u_psram_wd\rwds_iodelay_gen[0].iodelay_rwds"(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Warning (NLT0001) : Sweep user defined dangling instance "u_psram_top\u_psram_wd\data_lane_gen[0].u_psram_lane\u_rwds_ides4"(D:\Gowin\Gowin_V1.9.5.01Beta\IDE\ipcore\PSRAM\data\psram_code.v:0)
Info (CVT0001) : Run conversion
Info (DIO0001) : Run device independent optimization
Info (DIO0006) : Register and gate optimizing before inferencing
Info (DSP0001) : DSP inferencing
Info (RAM0001) : RAM inferencing
Info (ATO0001) : Adder tree reduction
Info (ATO0002) : Rebuild ALU instances from adder tree nodes
Info (DIO0001) : Run device independent optimization
Info (DIO0007) : Register and gate optimizing before mapping
Info (MAP0001) : Run tech-mapping
Info (MAP0003) : Run logic optimization
Info (DIO0001) : Run device independent optimization
Info (SYN0009) : Write post-map netlist to file: D:\user-bak\Users\root\Desktop\gowin_empu_ahb_psram\src\psram_memory_interface\temp\PSRAM\psram_memory_interface.vg

Summary

Total Warnings: 8
Total Informations: 67

Synthesis completed successfully!
Process took 0h:0m:7s realtime, 0h:0m:5s cputime
Memory peak: 54.5MB