<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_REG_IF\project\impl\synthesize\rev_1\synlog\FLASH608K_REG_IF_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>tb|clk</data>
<data>158.2 MHz</data>
<data>134.5 MHz</data>
<data>-1.115</data>
</row>
<row>
<data>System</data>
<data>100.0 MHz</data>
<data>204.3 MHz</data>
<data>5.106</data>
</row>
</report_table>
