
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v" (library work)
@W: CG1337 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":38:7:38:15|Net key_write is not declared.
@W: CG1337 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":39:7:39:14|Net key_read is not declared.
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v" (library work)
Verilog syntax check successful!
Selecting top level module tb
@N: CG364 :"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v":1864:7:1864:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on DFF .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFS .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on ER_UFM .......
Running optimization stage 1 on WR_UFM .......
Running optimization stage 1 on RD_UFM .......
Running optimization stage 1 on FLASH256K .......
Running optimization stage 1 on GW_USER_FLASH_256K .......
Running optimization stage 1 on Flash_Ctroller_256K .......
Running optimization stage 1 on Wishbone_Master_Top_256K .......
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":9412:7:9412:32|Synthesizing module Gowin_Flash_Controller_Top in library work.
Running optimization stage 1 on Gowin_Flash_Controller_Top .......
@W: CL168 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":9456:6:9456:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":4:7:4:8|Synthesizing module tb in library work.
Running optimization stage 1 on tb .......
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_adr_i[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_adr_i[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 31 to 28 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bit 20 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 1 to 0 of wb_reg_adr_i[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on tb .......
@N: CL201 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Trying to extract state machine for register i.
Extracted state machine for register i
State machine has 29 reachable states with original encodings of:
   00000000
   00000001
   00000010
   00000011
   00000100
   00000101
   00000110
   00000111
   00001000
   00001001
   00001010
   00001011
   00001100
   00001101
   00001110
   00001111
   00010000
   00010001
   00010010
   00010011
   00010100
   00010101
   00010110
   00010111
   00011000
   00011001
   00011010
   00011011
   00011100
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 19 to 3 of wb_reg_dat_i[19:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 27 to 22 of wb_reg_dat_i[27:21]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on Gowin_Flash_Controller_Top .......
Running optimization stage 2 on Wishbone_Master_Top_256K .......
Running optimization stage 2 on Flash_Ctroller_256K .......
Running optimization stage 2 on GW_USER_FLASH_256K .......
Running optimization stage 2 on FLASH256K .......
Running optimization stage 2 on RD_UFM .......
Running optimization stage 2 on WR_UFM .......
Running optimization stage 2 on ER_UFM .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on DFFS .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on DFF .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\impl\synthesize\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 98MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:11:15 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:11:15 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\impl\synthesize\rev_1\synwork\FLASH256K_WB_IF_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 19MB peak: 19MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Tue Oct 22 17:11:15 2019

###########################################################]
