# Tue Oct 22 17:09:04 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 218MB peak: 218MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.60ns		 426 /        51
   2		0h:00m:01s		    -2.60ns		 426 /        51

   3		0h:00m:01s		    -2.60ns		 426 /        51

   4		0h:00m:01s		    -2.60ns		 426 /        51

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 225MB)

Writing Analyst data base C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_REG_IF\project\impl\synthesize\rev_1\synwork\FLASH256K_REG_IF_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 228MB)

@W: MT246 :"c:\users\qinfei\desktop\gowin_flash_controller\flash256k_reg_if\project\src\gowin_flash_controller\gowin_flash_controller.v":5615:12:5615:21|Blackbox FLASH256K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock tb|clk with period 6.32ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing report written on Tue Oct 22 17:09:08 2019
#


Top view:               tb
Requested Frequency:    158.2 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.115

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
tb|clk             158.2 MHz     134.5 MHz     6.321         7.436         -1.115     inferred     Autoconstr_clkgroup_0
System             100.0 MHz     206.9 MHz     10.000        4.833         5.167      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
System    tb|clk  |  6.321       5.167   |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk    System  |  6.321       4.933   |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk    tb|clk  |  6.321       -1.115  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: tb|clk
====================================



Starting Points with Worst Slack
********************************

                                                                                    Starting                                         Arrival           
Instance                                                                            Reference     Type     Pin     Net               Time        Slack 
                                                                                    Clock                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\]      tb|clk        DFFC     Q       erase_cnt[1]      0.367       -1.115
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[5\]      tb|clk        DFFC     Q       erase_cnt[5]      0.367       -1.058
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[0\]      tb|clk        DFFC     Q       erase_cnt[0]      0.367       -1.048
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[4\]      tb|clk        DFFC     Q       erase_cnt[4]      0.367       -0.991
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[2\]      tb|clk        DFFC     Q       erase_cnt[2]      0.367       -0.838
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[6\]      tb|clk        DFFC     Q       erase_cnt[6]      0.367       -0.781
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[9\]      tb|clk        DFFC     Q       erase_cnt[9]      0.367       -0.773
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[13\]     tb|clk        DFFC     Q       erase_cnt[13]     0.367       -0.716
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[8\]      tb|clk        DFFC     Q       erase_cnt[8]      0.367       -0.706
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[17\]     tb|clk        DFFC     Q       erase_cnt[17]     0.367       -0.659
=======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                    Starting                                            Required           
Instance                                                                            Reference     Type     Pin     Net                  Time         Slack 
                                                                                    Clock                                                                  
-----------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\]     tb|clk        DFFC     D       erase_cnt_lm[18]     6.188        -1.115
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[17\]     tb|clk        DFFC     D       erase_cnt_lm[17]     6.188        -1.058
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[16\]     tb|clk        DFFC     D       erase_cnt_lm[16]     6.188        -1.001
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[15\]     tb|clk        DFFC     D       erase_cnt_lm[15]     6.188        -0.944
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[14\]     tb|clk        DFFC     D       erase_cnt_lm[14]     6.188        -0.887
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[22\]     tb|clk        DFFC     D       erase_cnt_lm[22]     6.188        -0.887
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[13\]     tb|clk        DFFC     D       erase_cnt_lm[13]     6.188        -0.830
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[21\]     tb|clk        DFFC     D       erase_cnt_lm[21]     6.188        -0.830
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[12\]     tb|clk        DFFC     D       erase_cnt_lm[12]     6.188        -0.773
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[20\]     tb|clk        DFFC     D       erase_cnt_lm[20]     6.188        -0.773
===========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      7.303
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.115

    Number of logic level(s):                15
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\] / Q
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\]                DFFC     Q        Out     0.367     0.367       -         
erase_cnt[1]                                                                                  Net      -        -       1.021     -           4         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     I1       In      -         1.388       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     F        Out     1.099     2.487       -         
erase_cnt_qxu_par_0[0]                                                                        Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      I0       In      -         3.508       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      COUT     Out     0.958     4.466       -         
erase_cnt_qxu_par_1_COUT[0]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      CIN      In      -         4.466       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      COUT     Out     0.057     4.523       -         
erase_cnt_qxu_par_1_COUT[4]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      CIN      In      -         4.523       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      COUT     Out     0.057     4.580       -         
erase_cnt_cry[8]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      CIN      In      -         4.580       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      COUT     Out     0.057     4.637       -         
erase_cnt_cry[9]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      CIN      In      -         4.637       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      COUT     Out     0.057     4.694       -         
erase_cnt_cry[10]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      CIN      In      -         4.694       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      COUT     Out     0.057     4.751       -         
erase_cnt_cry[11]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      CIN      In      -         4.751       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      COUT     Out     0.057     4.808       -         
erase_cnt_cry[12]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      CIN      In      -         4.808       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      COUT     Out     0.057     4.865       -         
erase_cnt_cry[13]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      CIN      In      -         4.865       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      COUT     Out     0.057     4.922       -         
erase_cnt_cry[14]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      CIN      In      -         4.922       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      COUT     Out     0.057     4.979       -         
erase_cnt_cry[15]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      CIN      In      -         4.979       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      COUT     Out     0.057     5.036       -         
erase_cnt_cry[16]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      CIN      In      -         5.036       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      COUT     Out     0.057     5.093       -         
erase_cnt_cry[17]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      CIN      In      -         5.093       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      SUM      Out     0.563     5.656       -         
erase_cnt_s[18]                                                                               Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     I3       In      -         6.677       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     F        Out     0.626     7.303       -         
erase_cnt_lm[18]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\]               DFFC     D        In      -         7.303       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 7.436 is 4.373(58.8%) logic and 3.063(41.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      7.246
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.058

    Number of logic level(s):                14
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[5\] / Q
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[5\]                DFFC     Q        Out     0.367     0.367       -         
erase_cnt[5]                                                                                  Net      -        -       1.021     -           4         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[4\]     LUT4     I1       In      -         1.388       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[4\]     LUT4     F        Out     1.099     2.487       -         
erase_cnt_qxu_par_0[4]                                                                        Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      I0       In      -         3.508       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      COUT     Out     0.958     4.466       -         
erase_cnt_qxu_par_1_COUT[4]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      CIN      In      -         4.466       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      COUT     Out     0.057     4.523       -         
erase_cnt_cry[8]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      CIN      In      -         4.523       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      COUT     Out     0.057     4.580       -         
erase_cnt_cry[9]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      CIN      In      -         4.580       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      COUT     Out     0.057     4.637       -         
erase_cnt_cry[10]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      CIN      In      -         4.637       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      COUT     Out     0.057     4.694       -         
erase_cnt_cry[11]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      CIN      In      -         4.694       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      COUT     Out     0.057     4.751       -         
erase_cnt_cry[12]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      CIN      In      -         4.751       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      COUT     Out     0.057     4.808       -         
erase_cnt_cry[13]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      CIN      In      -         4.808       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      COUT     Out     0.057     4.865       -         
erase_cnt_cry[14]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      CIN      In      -         4.865       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      COUT     Out     0.057     4.922       -         
erase_cnt_cry[15]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      CIN      In      -         4.922       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      COUT     Out     0.057     4.979       -         
erase_cnt_cry[16]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      CIN      In      -         4.979       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      COUT     Out     0.057     5.036       -         
erase_cnt_cry[17]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      CIN      In      -         5.036       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      SUM      Out     0.563     5.599       -         
erase_cnt_s[18]                                                                               Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     I3       In      -         6.620       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     F        Out     0.626     7.246       -         
erase_cnt_lm[18]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\]               DFFC     D        In      -         7.246       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 7.379 is 4.316(58.5%) logic and 3.063(41.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      7.246
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.058

    Number of logic level(s):                14
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\] / Q
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[17\] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\]                DFFC     Q        Out     0.367     0.367       -         
erase_cnt[1]                                                                                  Net      -        -       1.021     -           4         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     I1       In      -         1.388       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     F        Out     1.099     2.487       -         
erase_cnt_qxu_par_0[0]                                                                        Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      I0       In      -         3.508       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      COUT     Out     0.958     4.466       -         
erase_cnt_qxu_par_1_COUT[0]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      CIN      In      -         4.466       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      COUT     Out     0.057     4.523       -         
erase_cnt_qxu_par_1_COUT[4]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      CIN      In      -         4.523       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      COUT     Out     0.057     4.580       -         
erase_cnt_cry[8]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      CIN      In      -         4.580       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      COUT     Out     0.057     4.637       -         
erase_cnt_cry[9]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      CIN      In      -         4.637       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      COUT     Out     0.057     4.694       -         
erase_cnt_cry[10]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      CIN      In      -         4.694       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      COUT     Out     0.057     4.751       -         
erase_cnt_cry[11]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      CIN      In      -         4.751       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      COUT     Out     0.057     4.808       -         
erase_cnt_cry[12]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      CIN      In      -         4.808       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      COUT     Out     0.057     4.865       -         
erase_cnt_cry[13]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      CIN      In      -         4.865       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      COUT     Out     0.057     4.922       -         
erase_cnt_cry[14]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      CIN      In      -         4.922       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      COUT     Out     0.057     4.979       -         
erase_cnt_cry[15]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      CIN      In      -         4.979       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      COUT     Out     0.057     5.036       -         
erase_cnt_cry[16]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      CIN      In      -         5.036       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      SUM      Out     0.563     5.599       -         
erase_cnt_s[17]                                                                               Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[17\]            LUT4     I3       In      -         6.620       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[17\]            LUT4     F        Out     0.626     7.246       -         
erase_cnt_lm[17]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[17\]               DFFC     D        In      -         7.246       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 7.379 is 4.316(58.5%) logic and 3.063(41.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      7.236
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.048

    Number of logic level(s):                15
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[0\] / Q
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[0\]                DFFC     Q        Out     0.367     0.367       -         
erase_cnt[0]                                                                                  Net      -        -       1.021     -           3         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     I0       In      -         1.388       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     F        Out     1.032     2.420       -         
erase_cnt_qxu_par_0[0]                                                                        Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      I0       In      -         3.441       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      COUT     Out     0.958     4.399       -         
erase_cnt_qxu_par_1_COUT[0]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      CIN      In      -         4.399       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      COUT     Out     0.057     4.456       -         
erase_cnt_qxu_par_1_COUT[4]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      CIN      In      -         4.456       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      COUT     Out     0.057     4.513       -         
erase_cnt_cry[8]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      CIN      In      -         4.513       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      COUT     Out     0.057     4.570       -         
erase_cnt_cry[9]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      CIN      In      -         4.570       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      COUT     Out     0.057     4.627       -         
erase_cnt_cry[10]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      CIN      In      -         4.627       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      COUT     Out     0.057     4.684       -         
erase_cnt_cry[11]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      CIN      In      -         4.684       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      COUT     Out     0.057     4.741       -         
erase_cnt_cry[12]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      CIN      In      -         4.741       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      COUT     Out     0.057     4.798       -         
erase_cnt_cry[13]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      CIN      In      -         4.798       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      COUT     Out     0.057     4.855       -         
erase_cnt_cry[14]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      CIN      In      -         4.855       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      COUT     Out     0.057     4.912       -         
erase_cnt_cry[15]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      CIN      In      -         4.912       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      COUT     Out     0.057     4.969       -         
erase_cnt_cry[16]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      CIN      In      -         4.969       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[17\]           ALU      COUT     Out     0.057     5.026       -         
erase_cnt_cry[17]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      CIN      In      -         5.026       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_s_0\[18\]             ALU      SUM      Out     0.563     5.589       -         
erase_cnt_s[18]                                                                               Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     I3       In      -         6.610       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[18\]            LUT4     F        Out     0.626     7.236       -         
erase_cnt_lm[18]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[18\]               DFFC     D        In      -         7.236       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 7.369 is 4.306(58.4%) logic and 3.063(41.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      7.189
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.001

    Number of logic level(s):                13
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\] / Q
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[16\] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                         Pin      Pin               Arrival     No. of    
Name                                                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[1\]                DFFC     Q        Out     0.367     0.367       -         
erase_cnt[1]                                                                                  Net      -        -       1.021     -           4         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     I1       In      -         1.388       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_0_cZ\[0\]     LUT4     F        Out     1.099     2.487       -         
erase_cnt_qxu_par_0[0]                                                                        Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      I0       In      -         3.508       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[0\]        ALU      COUT     Out     0.958     4.466       -         
erase_cnt_qxu_par_1_COUT[0]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      CIN      In      -         4.466       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_qxu_par_1\[4\]        ALU      COUT     Out     0.057     4.523       -         
erase_cnt_qxu_par_1_COUT[4]                                                                   Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      CIN      In      -         4.523       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[8\]            ALU      COUT     Out     0.057     4.580       -         
erase_cnt_cry[8]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      CIN      In      -         4.580       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[9\]            ALU      COUT     Out     0.057     4.637       -         
erase_cnt_cry[9]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      CIN      In      -         4.637       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[10\]           ALU      COUT     Out     0.057     4.694       -         
erase_cnt_cry[10]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      CIN      In      -         4.694       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[11\]           ALU      COUT     Out     0.057     4.751       -         
erase_cnt_cry[11]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      CIN      In      -         4.751       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[12\]           ALU      COUT     Out     0.057     4.808       -         
erase_cnt_cry[12]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      CIN      In      -         4.808       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[13\]           ALU      COUT     Out     0.057     4.865       -         
erase_cnt_cry[13]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      CIN      In      -         4.865       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[14\]           ALU      COUT     Out     0.057     4.922       -         
erase_cnt_cry[14]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      CIN      In      -         4.922       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[15\]           ALU      COUT     Out     0.057     4.979       -         
erase_cnt_cry[15]                                                                             Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      CIN      In      -         4.979       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_cry_0\[16\]           ALU      SUM      Out     0.563     5.542       -         
erase_cnt_s[16]                                                                               Net      -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[16\]            LUT4     I3       In      -         6.563       -         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_lm_0\[16\]            LUT4     F        Out     0.626     7.189       -         
erase_cnt_lm[16]                                                                              Net      -        -       0.000     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_ER_UFM.\\erase_cnt_Z\[16\]               DFFC     D        In      -         7.189       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 7.322 is 4.259(58.2%) logic and 3.063(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                                       Starting                                                   Arrival          
Instance                                                                               Reference     Type          Pin         Net                Time        Slack
                                                                                       Clock                                                                       
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\state_UFM_i_cZ\[0\]               System        INV           O           state_UFM_i[0]     0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[0]     DOUT[0]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[1]     DOUT[1]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[2]     DOUT[2]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[3]     DOUT[3]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[4]     DOUT[4]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[5]     DOUT[5]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[6]     DOUT[6]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[7]     DOUT[7]            0.000       5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.u_GW_USER_FLASH_256K.flash_inst     System        FLASH256K     DOUT[8]     DOUT[8]            0.000       5.167
===================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                        Starting                                    Required          
Instance                                                                Reference     Type      Pin     Net         Time         Slack
                                                                        Clock                                                         
--------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[0\]     System        DFFCE     D       DOUT[0]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[1\]     System        DFFCE     D       DOUT[1]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[2\]     System        DFFCE     D       DOUT[2]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[3\]     System        DFFCE     D       DOUT[3]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[4\]     System        DFFCE     D       DOUT[4]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[5\]     System        DFFCE     D       DOUT[5]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[6\]     System        DFFCE     D       DOUT[6]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[7\]     System        DFFCE     D       DOUT[7]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[8\]     System        DFFCE     D       DOUT[8]     6.188        5.167
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\comp_data\[9\]     System        DFFCE     D       DOUT[9]     6.188        5.167
======================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.188

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.167

    Number of logic level(s):                0
    Starting point:                          u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\state_UFM_i_cZ\[0\] / O
    Ending point:                            u_gowin_flash_controller_top.u_Flash_Ctroller_256K.Done_signal_reg / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                         Pin      Pin               Arrival     No. of    
Name                                                                         Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.\\state_UFM_i_cZ\[0\]     INV       O        Out     0.000     0.000       -         
state_UFM_i[0]                                                               Net       -        -       1.021     -           1         
u_gowin_flash_controller_top.u_Flash_Ctroller_256K.Done_signal_reg           DFFCE     D        In      -         1.021       -         
========================================================================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 228MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 228MB)

---------------------------------------
Resource Usage Report for tb 

Mapping to part: gw1n_4lqfp144-6
Cell usage:
ALU             123 uses
DFFC            299 uses
DFFCE           81 uses
DFFE            33 uses
DFFP            5 uses
FLASH256K       1 use
GSR             1 use
INV             3 uses
LUT2            82 uses
LUT3            105 uses
LUT4            238 uses

I/O ports: 36
I/O primitives: 36
IBUF           4 uses
OBUF           32 uses

I/O Register bits:                  0
Register bits not including I/Os:   418 of 3456 (12%)
Total load per clock:
   tb|clk: 418

@S |Mapping Summary:
Total  LUTs: 425 (9%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 74MB peak: 228MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Oct 22 17:09:09 2019

###########################################################]
