Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH64KZ_REG_IF\project\impl\synthesize\rev_1\FLASH64KZ_REG_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH64KZ_REG_IF\project\src\FLASH64KZ_REG_IF.cst
Timing Constraint File | ---
GOWIN version | V1.9.2.01Beta
Part Number | GW1NZ-ZV1FN32C5/I4
Created Time | Tue Oct 22 17:02:22 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 852
Numbers of Endpoints Analyzed | 783
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 100.153(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.015 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.305
2 | 0.504 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.816
3 | 0.516 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.804
4 | 0.935 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.385
5 | 0.937 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.383
6 | 0.959 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.361
7 | 1.005 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.315
8 | 1.083 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.237
9 | 1.138 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.182
10 | 1.140 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.180
11 | 1.216 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.104
12 | 1.363 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.957
13 | 1.377 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.943
14 | 1.428 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.892
15 | 1.532 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.788
16 | 1.556 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.764
17 | 1.563 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.757
18 | 1.578 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.742
19 | 1.589 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.731
20 | 1.594 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.726
21 | 1.668 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.652
22 | 1.692 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.628
23 | 1.728 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.592
24 | 1.767 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/nhv_cnt_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.553
25 | 1.787 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.533

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.687 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.687
2 | 0.688 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/xe_tmp/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.688
3 | 0.689 | i_Z[3]/Q | i_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.689
4 | 0.849 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.849
5 | 0.849 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.849
6 | 0.849 | erase_reg_Z/Q | erase_reg_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.849
7 | 0.849 | i_Z[5]/Q | i_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.849
8 | 0.851 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.851
9 | 0.851 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.851
10 | 0.851 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.851
11 | 0.851 | i_Z[2]/Q | i_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.851
12 | 0.851 | i_Z[9]/Q | i_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.851
13 | 0.852 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.852
14 | 0.852 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.852
15 | 0.852 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.852
16 | 0.853 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853
17 | 0.855 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.855
18 | 0.855 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.855
19 | 0.863 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.863
20 | 1.009 | i_Z[7]/Q | i_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.009
21 | 1.015 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_busy_tmp/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.015
22 | 1.057 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/comp_data[7]/Q | rdata_reg[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.057
23 | 1.070 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.070
24 | 1.070 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.070
25 | 1.079 | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.079

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | i_Z[0]
2 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | key1_temp2_Z
3 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | i_Z[9]
4 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | i_Z[1]
5 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wdata_Z[2]
6 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wyaddr_Z[2]
7 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/ERASE_Z
8 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[4]
9 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[3]
10 | 2.738 | 4.238 | 1.500 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/w_command_Z

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.015
Data Arrival Time | 12.540
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
8.786 | 0.068 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/COUT
8.786 | 0.000 | tNET | FF | 2 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/CIN
8.855 | 0.068 | tINS | FF | 1 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/COUT
8.855 | 0.000 | tNET | FF | 2 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/CIN
8.923 | 0.068 | tINS | FF | 1 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/COUT
8.923 | 0.000 | tNET | FF | 2 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/CIN
8.992 | 0.068 | tINS | FF | 1 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/COUT
8.992 | 0.000 | tNET | FF | 2 | R5C19[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[17]/CIN
9.060 | 0.068 | tINS | FF | 1 | R5C19[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[17]/COUT
9.060 | 0.000 | tNET | FF | 2 | R5C19[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_s_0[18]/CIN
9.736 | 0.676 | tINS | FF | 1 | R5C19[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_s_0[18]/SUM
11.302 | 1.566 | tNET | FF | 1 | R3C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[18]/I3
12.540 | 1.238 | tINS | FF | 1 | R3C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[18]/F
12.540 | 0.000 | tNET | FF | 1 | R3C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R3C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]
12.556 | -0.480 | tSu |  | 1 | R3C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[18]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 5.125, 55.082%; route: 3.629, 39.007%; tC2Q: 0.550, 5.911%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path2

Path Summary:

Slack | 0.504
Data Arrival Time | 12.051
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.341 | 1.555 | tNET | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/I1
6.579 | 1.238 | tINS | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/F
7.564 | 0.985 | tNET | FF | 2 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/I0
8.818 | 1.254 | tINS | FF | 1 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/COUT
8.818 | 0.000 | tNET | FF | 2 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/CIN
8.886 | 0.068 | tINS | FF | 1 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/COUT
8.886 | 0.000 | tNET | FF | 2 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/CIN
8.955 | 0.068 | tINS | FF | 1 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/COUT
8.955 | 0.000 | tNET | FF | 2 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/CIN
9.023 | 0.068 | tINS | FF | 1 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/COUT
9.023 | 0.000 | tNET | FF | 2 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/CIN
9.092 | 0.068 | tINS | FF | 1 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/COUT
9.092 | 0.000 | tNET | FF | 2 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/CIN
9.767 | 0.676 | tINS | FF | 1 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/SUM
10.732 | 0.965 | tNET | FF | 1 | R4C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[20]/I3
12.051 | 1.319 | tINS | FF | 1 | R4C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[20]/F
12.051 | 0.000 | tNET | FF | 1 | R4C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]
12.556 | -0.480 | tSu |  | 1 | R4C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.760, 54.000%; route: 3.505, 39.761%; tC2Q: 0.550, 6.239%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path3

Path Summary:

Slack | 0.516
Data Arrival Time | 12.039
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.341 | 1.555 | tNET | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/I1
6.579 | 1.238 | tINS | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/F
7.564 | 0.985 | tNET | FF | 2 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/I0
8.818 | 1.254 | tINS | FF | 1 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/COUT
8.818 | 0.000 | tNET | FF | 2 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/CIN
8.886 | 0.068 | tINS | FF | 1 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/COUT
8.886 | 0.000 | tNET | FF | 2 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/CIN
8.955 | 0.068 | tINS | FF | 1 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/COUT
8.955 | 0.000 | tNET | FF | 2 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/CIN
9.023 | 0.068 | tINS | FF | 1 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/COUT
9.023 | 0.000 | tNET | FF | 2 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/CIN
9.092 | 0.068 | tINS | FF | 1 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/COUT
9.092 | 0.000 | tNET | FF | 2 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/CIN
9.160 | 0.068 | tINS | FF | 1 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/COUT
9.160 | 0.000 | tNET | FF | 2 | R2C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[21]/CIN
9.836 | 0.676 | tINS | FF | 1 | R2C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[21]/SUM
10.801 | 0.965 | tNET | FF | 1 | R4C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[21]/I3
12.039 | 1.238 | tINS | FF | 1 | R4C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[21]/F
12.039 | 0.000 | tNET | FF | 1 | R4C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]
12.556 | -0.480 | tSu |  | 1 | R4C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.748, 53.938%; route: 3.505, 39.815%; tC2Q: 0.550, 6.248%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path4

Path Summary:

Slack | 0.935
Data Arrival Time | 11.620
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.341 | 1.555 | tNET | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/I1
6.579 | 1.238 | tINS | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/F
7.564 | 0.985 | tNET | FF | 2 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/I0
8.818 | 1.254 | tINS | FF | 1 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/COUT
8.818 | 0.000 | tNET | FF | 2 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/CIN
8.886 | 0.068 | tINS | FF | 1 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/COUT
8.886 | 0.000 | tNET | FF | 2 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/CIN
8.955 | 0.068 | tINS | FF | 1 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/COUT
8.955 | 0.000 | tNET | FF | 2 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/CIN
9.023 | 0.068 | tINS | FF | 1 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/COUT
9.023 | 0.000 | tNET | FF | 2 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/CIN
9.092 | 0.068 | tINS | FF | 1 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/COUT
9.092 | 0.000 | tNET | FF | 2 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/CIN
9.160 | 0.068 | tINS | FF | 1 | R2C17[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[20]/COUT
9.160 | 0.000 | tNET | FF | 2 | R2C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[21]/CIN
9.228 | 0.068 | tINS | FF | 1 | R2C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[21]/COUT
9.228 | 0.000 | tNET | FF | 2 | R2C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_s_0[22]/CIN
9.904 | 0.676 | tINS | FF | 1 | R2C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_s_0[22]/SUM
10.869 | 0.965 | tNET | FF | 1 | R4C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[22]/I3
11.620 | 0.751 | tINS | FF | 1 | R4C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[22]/F
11.620 | 0.000 | tNET | FF | 1 | R4C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]
12.556 | -0.480 | tSu |  | 1 | R4C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.330, 51.637%; route: 3.505, 41.804%; tC2Q: 0.550, 6.560%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path5

Path Summary:

Slack | 0.937
Data Arrival Time | 11.619
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
8.786 | 0.068 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/COUT
8.786 | 0.000 | tNET | FF | 2 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/CIN
8.855 | 0.068 | tINS | FF | 1 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/COUT
8.855 | 0.000 | tNET | FF | 2 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/CIN
8.923 | 0.068 | tINS | FF | 1 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/COUT
8.923 | 0.000 | tNET | FF | 2 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/CIN
8.992 | 0.068 | tINS | FF | 1 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/COUT
8.992 | 0.000 | tNET | FF | 2 | R5C19[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[17]/CIN
9.667 | 0.676 | tINS | FF | 1 | R5C19[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[17]/SUM
10.632 | 0.965 | tNET | FF | 1 | R3C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[17]/I3
11.619 | 0.986 | tINS | FF | 1 | R3C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[17]/F
11.619 | 0.000 | tNET | FF | 1 | R3C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R3C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]
12.556 | -0.480 | tSu |  | 1 | R3C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[17]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.805, 57.316%; route: 3.028, 36.123%; tC2Q: 0.550, 6.561%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path6

Path Summary:

Slack | 0.959
Data Arrival Time | 11.597
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
9.394 | 0.676 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/SUM
10.359 | 0.965 | tNET | FF | 1 | R4C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[13]/I3
11.597 | 1.238 | tINS | FF | 1 | R4C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[13]/F
11.597 | 0.000 | tNET | FF | 1 | R4C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]
12.556 | -0.480 | tSu |  | 1 | R4C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[13]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.783, 57.206%; route: 3.028, 36.217%; tC2Q: 0.550, 6.578%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path7

Path Summary:

Slack | 1.005
Data Arrival Time | 11.550
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
8.786 | 0.068 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/COUT
8.786 | 0.000 | tNET | FF | 2 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/CIN
8.855 | 0.068 | tINS | FF | 1 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/COUT
8.855 | 0.000 | tNET | FF | 2 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/CIN
8.923 | 0.068 | tINS | FF | 1 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/COUT
8.923 | 0.000 | tNET | FF | 2 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/CIN
9.599 | 0.676 | tINS | FF | 1 | R5C19[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[16]/SUM
10.564 | 0.965 | tNET | FF | 1 | R4C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[16]/I3
11.550 | 0.986 | tINS | FF | 1 | R4C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[16]/F
11.550 | 0.000 | tNET | FF | 1 | R4C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]
12.556 | -0.480 | tSu |  | 1 | R4C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[16]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.736, 56.965%; route: 3.028, 36.420%; tC2Q: 0.550, 6.615%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path8

Path Summary:

Slack | 1.083
Data Arrival Time | 11.472
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
9.188 | 0.676 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/SUM
10.154 | 0.965 | tNET | FF | 1 | R4C16[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[10]/I3
11.472 | 1.319 | tINS | FF | 1 | R4C16[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[10]/F
11.472 | 0.000 | tNET | FF | 1 | R4C16[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C16[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]
12.556 | -0.480 | tSu |  | 1 | R4C16[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.658, 56.557%; route: 3.028, 36.765%; tC2Q: 0.550, 6.677%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path9

Path Summary:

Slack | 1.138
Data Arrival Time | 11.418
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
9.120 | 0.676 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/SUM
10.667 | 1.547 | tNET | FF | 1 | R2C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[9]/I3
11.418 | 0.751 | tINS | FF | 1 | R2C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[9]/F
11.418 | 0.000 | tNET | FF | 1 | R2C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R2C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]
12.556 | -0.480 | tSu |  | 1 | R2C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.022, 49.161%; route: 3.610, 44.117%; tC2Q: 0.550, 6.722%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path10

Path Summary:

Slack | 1.140
Data Arrival Time | 11.415
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.341 | 1.555 | tNET | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/I1
6.579 | 1.238 | tINS | FF | 1 | R4C16[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cp_cZ[4]/F
7.564 | 0.985 | tNET | FF | 2 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/I0
8.818 | 1.254 | tINS | FF | 1 | R2C16[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_cp_0[4]/COUT
8.818 | 0.000 | tNET | FF | 2 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/CIN
8.886 | 0.068 | tINS | FF | 1 | R2C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[8]/COUT
8.886 | 0.000 | tNET | FF | 2 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/CIN
8.955 | 0.068 | tINS | FF | 1 | R2C16[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[12]/COUT
8.955 | 0.000 | tNET | FF | 2 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/CIN
9.023 | 0.068 | tINS | FF | 1 | R2C17[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[16]/COUT
9.023 | 0.000 | tNET | FF | 2 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/CIN
9.699 | 0.676 | tINS | FF | 1 | R2C17[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[19]/SUM
10.664 | 0.965 | tNET | FF | 1 | R2C15[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[19]/I3
11.415 | 0.751 | tINS | FF | 1 | R2C15[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[19]/F
11.415 | 0.000 | tNET | FF | 1 | R2C15[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R2C15[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]
12.556 | -0.480 | tSu |  | 1 | R2C15[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[19]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.124, 50.424%; route: 3.505, 42.852%; tC2Q: 0.550, 6.724%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path11

Path Summary:

Slack | 1.216
Data Arrival Time | 11.340
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q
5.555 | 1.770 | tNET | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/I2
6.794 | 1.238 | tINS | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/F
6.800 | 0.007 | tNET | FF | 1 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/I3
8.039 | 1.238 | tINS | FF | 12 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/F
10.021 | 1.982 | tNET | FF | 1 | R9C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_i_i_cZ/I1
11.340 | 1.319 | tINS | FF | 1 | R9C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_i_i_cZ/F
11.340 | 0.000 | tNET | FF | 1 | R9C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R9C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp
12.556 | -0.480 | tSu |  | 1 | R9C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.796, 46.837%; route: 3.758, 46.377%; tC2Q: 0.550, 6.787%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path12

Path Summary:

Slack | 1.363
Data Arrival Time | 11.193
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q
5.939 | 2.153 | tNET | FF | 2 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/I0
7.193 | 1.254 | tINS | FF | 1 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/COUT
7.193 | 0.000 | tNET | FF | 2 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/CIN
7.261 | 0.068 | tINS | FF | 1 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/COUT
7.261 | 0.000 | tNET | FF | 2 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/CIN
7.330 | 0.068 | tINS | FF | 1 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/COUT
7.330 | 0.000 | tNET | FF | 2 | R3C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[4]/CIN
7.398 | 0.068 | tINS | FF | 1 | R3C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[4]/COUT
7.398 | 0.000 | tNET | FF | 2 | R3C11[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[5]/CIN
7.466 | 0.068 | tINS | FF | 1 | R3C11[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[5]/COUT
7.466 | 0.000 | tNET | FF | 2 | R3C11[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[6]/CIN
7.535 | 0.068 | tINS | FF | 1 | R3C11[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[6]/COUT
7.535 | 0.000 | tNET | FF | 2 | R3C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[7]/CIN
8.210 | 0.676 | tINS | FF | 1 | R3C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[7]/SUM
9.955 | 1.744 | tNET | FF | 1 | R8C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[7]/I1
11.193 | 1.238 | tINS | FF | 1 | R8C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[7]/F
11.193 | 0.000 | tNET | FF | 1 | R8C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R8C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]
12.556 | -0.480 | tSu |  | 1 | R8C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.510, 44.111%; route: 3.897, 48.977%; tC2Q: 0.550, 6.912%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path13

Path Summary:

Slack | 1.377
Data Arrival Time | 11.178
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
8.786 | 0.068 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/COUT
8.786 | 0.000 | tNET | FF | 2 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/CIN
9.462 | 0.676 | tINS | FF | 1 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/SUM
10.427 | 0.965 | tNET | FF | 1 | R2C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[14]/I3
11.178 | 0.751 | tINS | FF | 1 | R2C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[14]/F
11.178 | 0.000 | tNET | FF | 1 | R2C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R2C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]
12.556 | -0.480 | tSu |  | 1 | R2C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.364, 54.949%; route: 3.028, 38.126%; tC2Q: 0.550, 6.925%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path14

Path Summary:

Slack | 1.428
Data Arrival Time | 11.128
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q
5.555 | 1.770 | tNET | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/I2
6.794 | 1.238 | tINS | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/F
6.800 | 0.007 | tNET | FF | 1 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/I3
8.039 | 1.238 | tINS | FF | 12 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/F
9.809 | 1.770 | tNET | FF | 1 | R9C11[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[2]/I0
11.128 | 1.319 | tINS | FF | 1 | R9C11[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[2]/F
11.128 | 0.000 | tNET | FF | 1 | R9C11[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R9C11[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]
12.556 | -0.480 | tSu |  | 1 | R9C11[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.796, 48.093%; route: 3.547, 44.939%; tC2Q: 0.550, 6.969%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path15

Path Summary:

Slack | 1.532
Data Arrival Time | 11.024
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
9.283 | 0.634 | tINS | FR | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/SUM
9.786 | 0.503 | tNET | RR | 1 | R4C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[12]/I3
11.024 | 1.238 | tINS | RF | 1 | R4C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[12]/F
11.024 | 0.000 | tNET | FF | 1 | R4C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]
12.556 | -0.480 | tSu |  | 1 | R4C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.673, 59.996%; route: 2.566, 32.942%; tC2Q: 0.550, 7.062%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path16

Path Summary:

Slack | 1.556
Data Arrival Time | 11.000
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q
5.939 | 2.153 | tNET | FF | 2 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/I0
7.193 | 1.254 | tINS | FF | 1 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/COUT
7.193 | 0.000 | tNET | FF | 2 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/CIN
7.261 | 0.068 | tINS | FF | 1 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/COUT
7.261 | 0.000 | tNET | FF | 2 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/CIN
7.937 | 0.676 | tINS | FF | 1 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/SUM
9.681 | 1.744 | tNET | FF | 1 | R8C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[3]/I1
11.000 | 1.319 | tINS | FF | 1 | R8C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[3]/F
11.000 | 0.000 | tNET | FF | 1 | R8C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R8C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]
12.556 | -0.480 | tSu |  | 1 | R8C11[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.317, 42.720%; route: 3.897, 50.196%; tC2Q: 0.550, 7.084%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path17

Path Summary:

Slack | 1.563
Data Arrival Time | 10.993
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
9.257 | 0.676 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/SUM
10.242 | 0.985 | tNET | FF | 1 | R5C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[11]/I3
10.993 | 0.751 | tINS | FF | 1 | R5C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[11]/F
10.993 | 0.000 | tNET | FF | 1 | R5C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R5C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]
12.556 | -0.480 | tSu |  | 1 | R5C16[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[11]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.159, 53.617%; route: 3.048, 39.293%; tC2Q: 0.550, 7.090%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path18

Path Summary:

Slack | 1.578
Data Arrival Time | 10.977
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/I1
6.619 | 1.273 | tINS | FR | 1 | R5C16[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_0_cZ[4]/F
7.122 | 0.503 | tNET | RR | 2 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/I0
8.376 | 1.254 | tINS | RF | 1 | R5C17[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_qxu_par_1[4]/COUT
8.376 | 0.000 | tNET | FF | 2 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/CIN
8.444 | 0.068 | tINS | FF | 1 | R5C17[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[8]/COUT
8.444 | 0.000 | tNET | FF | 2 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/CIN
8.513 | 0.068 | tINS | FF | 1 | R5C17[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[9]/COUT
8.513 | 0.000 | tNET | FF | 2 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/CIN
8.581 | 0.068 | tINS | FF | 1 | R5C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[10]/COUT
8.581 | 0.000 | tNET | FF | 2 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/CIN
8.650 | 0.068 | tINS | FF | 1 | R5C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[11]/COUT
8.650 | 0.000 | tNET | FF | 2 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/CIN
8.718 | 0.068 | tINS | FF | 1 | R5C18[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[12]/COUT
8.718 | 0.000 | tNET | FF | 2 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/CIN
8.786 | 0.068 | tINS | FF | 1 | R5C18[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[13]/COUT
8.786 | 0.000 | tNET | FF | 2 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/CIN
8.855 | 0.068 | tINS | FF | 1 | R5C18[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[14]/COUT
8.855 | 0.000 | tNET | FF | 2 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/CIN
9.488 | 0.634 | tINS | FR | 1 | R5C18[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_cry_0[15]/SUM
9.991 | 0.503 | tNET | RR | 1 | R4C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[15]/I3
10.977 | 0.986 | tINS | RF | 1 | R4C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[15]/F
10.977 | 0.000 | tNET | FF | 1 | R4C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]
12.556 | -0.480 | tSu |  | 1 | R4C18[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 4.626, 59.755%; route: 2.566, 33.141%; tC2Q: 0.550, 7.104%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path19

Path Summary:

Slack | 1.589
Data Arrival Time | 10.967
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/Q
5.346 | 1.560 | tNET | FF | 1 | R5C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state23_11_cZ/I0
6.665 | 1.319 | tINS | FF | 1 | R5C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state23_11_cZ/F
6.671 | 0.007 | tNET | FF | 1 | R5C16[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state23_19_cZ/I1
7.990 | 1.319 | tINS | FF | 25 | R5C16[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state23_19_cZ/F
9.648 | 1.658 | tNET | FF | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[5]/I1
10.967 | 1.319 | tINS | FF | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_lm_0[5]/F
10.967 | 0.000 | tNET | FF | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]
12.556 | -0.480 | tSu |  | 1 | R2C18[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.956, 51.174%; route: 3.225, 41.712%; tC2Q: 0.550, 7.114%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path20

Path Summary:

Slack | 1.594
Data Arrival Time | 10.961
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q
5.555 | 1.770 | tNET | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/I2
6.794 | 1.238 | tINS | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/F
6.800 | 0.007 | tNET | FF | 1 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/I3
8.039 | 1.238 | tINS | FF | 12 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/F
9.642 | 1.604 | tNET | FF | 1 | R5C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[0]/I0
10.961 | 1.319 | tINS | FF | 1 | R5C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[0]/F
10.961 | 0.000 | tNET | FF | 1 | R5C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R5C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]
12.556 | -0.480 | tSu |  | 1 | R5C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.796, 49.130%; route: 3.380, 43.750%; tC2Q: 0.550, 7.119%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path21

Path Summary:

Slack | 1.668
Data Arrival Time | 10.887
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[1]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[1]/Q
5.553 | 1.767 | tNET | FF | 2 | R4C12[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[1]/I0
6.807 | 1.254 | tINS | FF | 1 | R4C12[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[1]/COUT
6.807 | 0.000 | tNET | FF | 2 | R4C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[2]/CIN
6.875 | 0.068 | tINS | FF | 1 | R4C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[2]/COUT
6.875 | 0.000 | tNET | FF | 2 | R4C12[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[3]/CIN
6.944 | 0.068 | tINS | FF | 1 | R4C12[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[3]/COUT
6.944 | 0.000 | tNET | FF | 2 | R4C13[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[4]/CIN
7.012 | 0.068 | tINS | FF | 1 | R4C13[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[4]/COUT
7.012 | 0.000 | tNET | FF | 2 | R4C13[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[5]/CIN
7.081 | 0.068 | tINS | FF | 1 | R4C13[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[5]/COUT
7.081 | 0.000 | tNET | FF | 2 | R4C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[6]/CIN
7.149 | 0.068 | tINS | FF | 1 | R4C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_cry_0[6]/COUT
7.149 | 0.000 | tNET | FF | 2 | R4C13[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_s_0[7]/CIN
7.825 | 0.676 | tINS | FF | 1 | R4C13[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_s_0[7]/SUM
9.569 | 1.744 | tNET | FF | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_lm_0[7]/I0
10.887 | 1.319 | tINS | FF | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_lm_0[7]/F
10.887 | 0.000 | tNET | FF | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]
12.556 | -0.480 | tSu |  | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/nvs_cnt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.590, 46.923%; route: 3.511, 45.890%; tC2Q: 0.550, 7.188%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path22

Path Summary:

Slack | 1.692
Data Arrival Time | 10.864
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q
5.555 | 1.770 | tNET | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/I2
6.794 | 1.238 | tINS | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/F
6.800 | 0.007 | tNET | FF | 1 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/I3
8.039 | 1.238 | tINS | FF | 12 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/F
9.625 | 1.587 | tNET | FF | 1 | R2C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[4]/I0
10.864 | 1.238 | tINS | FF | 1 | R2C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[4]/F
10.864 | 0.000 | tNET | FF | 1 | R2C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R2C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]
12.556 | -0.480 | tSu |  | 1 | R2C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.715, 48.705%; route: 3.363, 44.085%; tC2Q: 0.550, 7.210%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path23

Path Summary:

Slack | 1.728
Data Arrival Time | 10.828
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R8C11[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[1]/Q
5.939 | 2.153 | tNET | FF | 2 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/I0
7.193 | 1.254 | tINS | FF | 1 | R3C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[1]/COUT
7.193 | 0.000 | tNET | FF | 2 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/CIN
7.261 | 0.068 | tINS | FF | 1 | R3C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[2]/COUT
7.261 | 0.000 | tNET | FF | 2 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/CIN
7.330 | 0.068 | tINS | FF | 1 | R3C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[3]/COUT
7.330 | 0.000 | tNET | FF | 2 | R3C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[4]/CIN
7.398 | 0.068 | tINS | FF | 1 | R3C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[4]/COUT
7.398 | 0.000 | tNET | FF | 2 | R3C11[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[5]/CIN
7.466 | 0.068 | tINS | FF | 1 | R3C11[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[5]/COUT
7.466 | 0.000 | tNET | FF | 2 | R3C11[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[6]/CIN
8.142 | 0.676 | tINS | FF | 1 | R3C11[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_cry_0[6]/SUM
9.509 | 1.367 | tNET | FF | 1 | R7C10[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[6]/I1
10.828 | 1.319 | tINS | FF | 1 | R7C10[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_lm_0[6]/F
10.828 | 0.000 | tNET | FF | 1 | R7C10[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R7C10[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]
12.556 | -0.480 | tSu |  | 1 | R7C10[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_cnt_Z[6]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.522, 46.391%; route: 3.520, 46.365%; tC2Q: 0.550, 7.244%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path24

Path Summary:

Slack | 1.767
Data Arrival Time | 10.789
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/nhv_cnt_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R10C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/nhv_cnt_Z[2]/CLK
3.786 | 0.550 | tC2Q | RF | 4 | R10C16[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/nhv_cnt_Z[2]/Q
4.969 | 1.184 | tNET | FF | 1 | R9C15[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i_a2_1/I0
6.243 | 1.273 | tINS | FR | 1 | R9C15[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i_a2_1/F
6.745 | 0.503 | tNET | RR | 1 | R8C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i_a2/I2
7.984 | 1.238 | tINS | RF | 1 | R8C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i_a2/F
9.550 | 1.566 | tNET | FF | 1 | R4C15[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i/I0
10.789 | 1.238 | tINS | FF | 1 | R4C15[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m65_0_i/F
10.789 | 0.000 | tNET | FF | 1 | R4C15[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R4C15[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]
12.556 | -0.480 | tSu |  | 1 | R4C15[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.750, 49.650%; route: 3.253, 43.068%; tC2Q: 0.550, 7.282%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Path25

Path Summary:

Slack | 1.787
Data Arrival Time | 10.769
Data Required Time | 12.556
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
3.236 | 2.293 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/CLK
3.786 | 0.550 | tC2Q | RF | 2 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[7]/Q
5.555 | 1.770 | tNET | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/I2
6.794 | 1.238 | tINS | FF | 1 | R3C12[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2_4_cZ/F
6.800 | 0.007 | tNET | FF | 1 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/I3
8.039 | 1.238 | tINS | FF | 12 | R3C12[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/prog_tmp_3_0_a5_i_o2/F
9.450 | 1.412 | tNET | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[8]/I0
10.769 | 1.319 | tINS | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_lm_0[8]/F
10.769 | 0.000 | tNET | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
10.943 | 0.943 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
13.236 | 2.293 | tNET | RR | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]/CLK
13.036 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]
12.556 | -0.480 | tSu |  | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/pgh_cnt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%
Arrival Data Path Delay | cell: 3.796, 50.384%; route: 3.188, 42.315%; tC2Q: 0.550, 7.301%
Required Clock Path Delay | cell: 0.943, 29.131%; route: 2.293, 70.869%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.687
Data Arrival Time | 3.220
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[1]/CLK
2.933 | 0.400 | tC2Q | RR | 13 | R5C14[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[1]/Q
3.220 | 0.287 | tNET | RR | 1 | R5C14[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z
2.533 | 0.000 | tHld |  | 1 | R5C14[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_command_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.287, 41.734%; tC2Q: 0.400, 58.266%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path2

Path Summary:

Slack | 0.688
Data Arrival Time | 3.221
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/xe_tmp
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/xe_tmp/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R7C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/xe_tmp/Q
3.221 | 0.288 | tNET | RR | 1 | R7C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z
2.533 | 0.000 | tHld |  | 1 | R7C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/r_busy_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.288, 41.854%; tC2Q: 0.400, 58.146%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path3

Path Summary:

Slack | 0.689
Data Arrival Time | 3.223
Data Required Time | 2.533
From | i_Z[3]
To | i_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[0][B] | i_Z[3]/CLK
2.933 | 0.400 | tC2Q | RR | 6 | R3C19[0][B] | i_Z[3]/Q
3.223 | 0.289 | tNET | RR | 1 | R3C19[2][A] | i_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[2][A] | i_Z[4]/CLK
2.533 | 0.000 | tUnc |  |  |  | i_Z[4]
2.533 | 0.000 | tHld |  | 1 | R3C19[2][A] | i_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.289, 41.973%; tC2Q: 0.400, 58.027%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path4

Path Summary:

Slack | 0.849
Data Arrival Time | 3.383
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/CLK
2.933 | 0.400 | tC2Q | RR | 2 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/Q
2.936 | 0.003 | tNET | RR | 1 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_1_sqmuxa_0_a4_0_a2/I0
3.383 | 0.446 | tINS | RF | 2 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_1_sqmuxa_0_a4_0_a2/F
3.383 | 0.000 | tNET | FF | 1 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z
2.533 | 0.000 | tHld |  | 1 | R8C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/pws_cnt_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.565%; route: 0.003, 0.334%; tC2Q: 0.400, 47.101%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path5

Path Summary:

Slack | 0.849
Data Arrival Time | 3.383
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/CLK
2.933 | 0.400 | tC2Q | RR | 2 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/Q
2.936 | 0.003 | tNET | RR | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/N_30_i_cZ/I2
3.383 | 0.446 | tINS | RF | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/N_30_i_cZ/F
3.383 | 0.000 | tNET | FF | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]
2.533 | 0.000 | tHld |  | 1 | R4C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/wait_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.565%; route: 0.003, 0.334%; tC2Q: 0.400, 47.101%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path6

Path Summary:

Slack | 0.849
Data Arrival Time | 3.383
Data Required Time | 2.533
From | erase_reg_Z
To | erase_reg_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C19[0][A] | erase_reg_Z/CLK
2.933 | 0.400 | tC2Q | RR | 46 | R2C19[0][A] | erase_reg_Z/Q
2.936 | 0.003 | tNET | RR | 1 | R2C19[0][A] | erase_reg_3_f0_0_0/I0
3.383 | 0.446 | tINS | RF | 1 | R2C19[0][A] | erase_reg_3_f0_0_0/F
3.383 | 0.000 | tNET | FF | 1 | R2C19[0][A] | erase_reg_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C19[0][A] | erase_reg_Z/CLK
2.533 | 0.000 | tUnc |  |  |  | erase_reg_Z
2.533 | 0.000 | tHld |  | 1 | R2C19[0][A] | erase_reg_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.565%; route: 0.003, 0.334%; tC2Q: 0.400, 47.101%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path7

Path Summary:

Slack | 0.849
Data Arrival Time | 3.383
Data Required Time | 2.533
From | i_Z[5]
To | i_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[1][A] | i_Z[5]/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R3C19[1][A] | i_Z[5]/Q
2.936 | 0.003 | tNET | RR | 1 | R3C19[1][A] | i_ns_0[5]/I2
3.383 | 0.446 | tINS | RF | 1 | R3C19[1][A] | i_ns_0[5]/F
3.383 | 0.000 | tNET | FF | 1 | R3C19[1][A] | i_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[1][A] | i_Z[5]/CLK
2.533 | 0.000 | tUnc |  |  |  | i_Z[5]
2.533 | 0.000 | tHld |  | 1 | R3C19[1][A] | i_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.565%; route: 0.003, 0.334%; tC2Q: 0.400, 47.101%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path8

Path Summary:

Slack | 0.851
Data Arrival Time | 3.384
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/Q
2.938 | 0.004 | tNET | RR | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_0[4]/I3
3.384 | 0.446 | tINS | RF | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_0[4]/F
3.384 | 0.000 | tNET | FF | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]
2.533 | 0.000 | tHld |  | 1 | R9C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.478%; route: 0.004, 0.500%; tC2Q: 0.400, 47.023%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path9

Path Summary:

Slack | 0.851
Data Arrival Time | 3.384
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/CLK
2.933 | 0.400 | tC2Q | RR | 3 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/Q
2.938 | 0.004 | tNET | RR | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt_4_a4_0_a2[0]/I0
3.384 | 0.446 | tINS | RF | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt_4_a4_0_a2[0]/F
3.384 | 0.000 | tNET | FF | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]
2.533 | 0.000 | tHld |  | 1 | R9C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/end_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.478%; route: 0.004, 0.500%; tC2Q: 0.400, 47.023%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path10

Path Summary:

Slack | 0.851
Data Arrival Time | 3.384
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/CLK
2.933 | 0.400 | tC2Q | RR | 12 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/Q
2.938 | 0.004 | tNET | RR | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m27_i_i/I3
3.384 | 0.446 | tINS | RF | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m27_i_i/F
3.384 | 0.000 | tNET | FF | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]
2.533 | 0.000 | tHld |  | 1 | R7C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.478%; route: 0.004, 0.500%; tC2Q: 0.400, 47.023%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path11

Path Summary:

Slack | 0.851
Data Arrival Time | 3.384
Data Required Time | 2.533
From | i_Z[2]
To | i_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C19[0][A] | i_Z[2]/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R4C19[0][A] | i_Z[2]/Q
2.938 | 0.004 | tNET | RR | 1 | R4C19[0][A] | i_ns_0[2]/I2
3.384 | 0.446 | tINS | RF | 1 | R4C19[0][A] | i_ns_0[2]/F
3.384 | 0.000 | tNET | FF | 1 | R4C19[0][A] | i_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C19[0][A] | i_Z[2]/CLK
2.533 | 0.000 | tUnc |  |  |  | i_Z[2]
2.533 | 0.000 | tHld |  | 1 | R4C19[0][A] | i_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.478%; route: 0.004, 0.500%; tC2Q: 0.400, 47.023%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path12

Path Summary:

Slack | 0.851
Data Arrival Time | 3.384
Data Required Time | 2.533
From | i_Z[9]
To | i_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[0][A] | i_Z[9]/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R3C19[0][A] | i_Z[9]/Q
2.938 | 0.004 | tNET | RR | 1 | R3C19[0][A] | i_ns_0[9]/I2
3.384 | 0.446 | tINS | RF | 1 | R3C19[0][A] | i_ns_0[9]/F
3.384 | 0.000 | tNET | FF | 1 | R3C19[0][A] | i_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[0][A] | i_Z[9]/CLK
2.533 | 0.000 | tUnc |  |  |  | i_Z[9]
2.533 | 0.000 | tHld |  | 1 | R3C19[0][A] | i_Z[9]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.478%; route: 0.004, 0.500%; tC2Q: 0.400, 47.023%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path13

Path Summary:

Slack | 0.852
Data Arrival Time | 3.385
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/CLK
2.933 | 0.400 | tC2Q | RR | 15 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/Q
2.939 | 0.006 | tNET | RR | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_i_m4_i_m2[1]/I3
3.385 | 0.446 | tINS | RF | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_i_m4_i_m2[1]/F
3.385 | 0.000 | tNET | FF | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]
2.533 | 0.000 | tHld |  | 1 | R7C5[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.390%; route: 0.006, 0.665%; tC2Q: 0.400, 46.945%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path14

Path Summary:

Slack | 0.852
Data Arrival Time | 3.385
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/CLK
2.933 | 0.400 | tC2Q | RR | 46 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/Q
2.939 | 0.006 | tNET | RR | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m4_i_0/I1
3.385 | 0.446 | tINS | RF | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m4_i_0/F
3.385 | 0.000 | tNET | FF | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]
2.533 | 0.000 | tHld |  | 1 | R2C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.390%; route: 0.006, 0.665%; tC2Q: 0.400, 46.945%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path15

Path Summary:

Slack | 0.852
Data Arrival Time | 3.385
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/CLK
2.933 | 0.400 | tC2Q | RR | 9 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/Q
2.939 | 0.006 | tNET | RR | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m110_i_0/I3
3.385 | 0.446 | tINS | RF | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m110_i_0/F
3.385 | 0.000 | tNET | FF | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]
2.533 | 0.000 | tHld |  | 1 | R5C14[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.390%; route: 0.006, 0.665%; tC2Q: 0.400, 46.945%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path16

Path Summary:

Slack | 0.853
Data Arrival Time | 3.387
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/CLK
2.933 | 0.400 | tC2Q | RR | 12 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/Q
2.940 | 0.007 | tNET | RR | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m82_i_0/I2
3.387 | 0.446 | tINS | RF | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m82_i_0/F
3.387 | 0.000 | tNET | FF | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]
2.533 | 0.000 | tHld |  | 1 | R5C15[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.303%; route: 0.007, 0.830%; tC2Q: 0.400, 46.867%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path17

Path Summary:

Slack | 0.855
Data Arrival Time | 3.388
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/CLK
2.933 | 0.400 | tC2Q | RR | 11 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/Q
2.942 | 0.009 | tNET | RR | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m16_i_0/I3
3.388 | 0.446 | tINS | RF | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_ns_8_0_.m16_i_0/F
3.388 | 0.000 | tNET | FF | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]
2.533 | 0.000 | tHld |  | 1 | R8C13[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.217%; route: 0.009, 0.994%; tC2Q: 0.400, 46.789%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path18

Path Summary:

Slack | 0.855
Data Arrival Time | 3.388
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/CLK
2.933 | 0.400 | tC2Q | RR | 18 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/Q
2.942 | 0.009 | tNET | RR | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_ns_cZ[4]/I2
3.388 | 0.446 | tINS | RF | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_ns_cZ[4]/F
3.388 | 0.000 | tNET | FF | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]
2.533 | 0.000 | tHld |  | 1 | R5C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/state_UFM_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 52.217%; route: 0.009, 0.994%; tC2Q: 0.400, 46.789%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path19

Path Summary:

Slack | 0.863
Data Arrival Time | 3.397
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/CLK
2.933 | 0.400 | tC2Q | RR | 56 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/Q
2.950 | 0.017 | tNET | RR | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m69_i_0/I2
3.397 | 0.446 | tINS | RF | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m69_i_0/F
3.397 | 0.000 | tNET | FF | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]
2.533 | 0.000 | tHld |  | 1 | R4C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.446, 51.703%; route: 0.017, 1.969%; tC2Q: 0.400, 46.328%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path20

Path Summary:

Slack | 1.009
Data Arrival Time | 3.542
Data Required Time | 2.533
From | i_Z[7]
To | i_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C19[2][B] | i_Z[7]/CLK
2.933 | 0.400 | tC2Q | RR | 4 | R2C19[2][B] | i_Z[7]/Q
3.542 | 0.609 | tNET | RR | 1 | R3C19[1][B] | i_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R3C19[1][B] | i_Z[8]/CLK
2.533 | 0.000 | tUnc |  |  |  | i_Z[8]
2.533 | 0.000 | tHld |  | 1 | R3C19[1][B] | i_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.609, 60.358%; tC2Q: 0.400, 39.642%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path21

Path Summary:

Slack | 1.015
Data Arrival Time | 3.548
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_busy_tmp
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C13[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_busy_tmp/CLK
2.933 | 0.400 | tC2Q | RR | 3 | R5C13[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/e_busy_tmp/Q
3.548 | 0.615 | tNET | RR | 1 | R5C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z
2.533 | 0.000 | tHld |  | 1 | R5C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/e_busy_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.615, 60.594%; tC2Q: 0.400, 39.406%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path22

Path Summary:

Slack | 1.057
Data Arrival Time | 3.591
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/comp_data[7]
To | rdata_reg[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R2C3[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/comp_data[7]/CLK
2.933 | 0.400 | tC2Q | RR | 1 | R2C3[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/comp_data[7]/Q
3.591 | 0.657 | tNET | RR | 1 | IOT11[B] | rdata_reg[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | IOT11[B] | rdata_reg[7]/CLK
2.533 | 0.000 | tUnc |  |  |  | rdata_reg[7]
2.533 | 0.000 | tHld |  | 1 | IOT11[B] | rdata_reg[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.657, 62.168%; tC2Q: 0.400, 37.832%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path23

Path Summary:

Slack | 1.070
Data Arrival Time | 3.603
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/CLK
2.933 | 0.400 | tC2Q | RR | 2 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/Q
2.936 | 0.003 | tNET | RR | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_0[0]/I2
3.603 | 0.667 | tINS | RR | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_ns_0[0]/F
3.603 | 0.000 | tNET | RR | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]
2.533 | 0.000 | tHld |  | 1 | R9C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_RD_UFM_64K/r_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.667, 62.353%; route: 0.003, 0.265%; tC2Q: 0.400, 37.382%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path24

Path Summary:

Slack | 1.070
Data Arrival Time | 3.603
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/CLK
2.933 | 0.400 | tC2Q | RR | 2 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/Q
2.936 | 0.003 | tNET | RR | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/N_231_i_cZ/I2
3.603 | 0.667 | tINS | RR | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/N_231_i_cZ/F
3.603 | 0.000 | tNET | RR | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]
2.533 | 0.000 | tHld |  | 1 | R5C14[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_ER_UFM_64K/end_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.667, 62.353%; route: 0.003, 0.265%; tC2Q: 0.400, 37.382%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Path25

Path Summary:

Slack | 1.079
Data Arrival Time | 3.612
Data Required Time | 2.533
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/CLK
2.933 | 0.400 | tC2Q | RR | 14 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/Q
2.945 | 0.011 | tNET | RR | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m49_0_0/I3
3.612 | 0.667 | tINS | RR | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_ns_9_0_.m49_0_0/F
3.612 | 0.000 | tNET | RR | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT10[A] | clk_ibuf/I
0.811 | 0.811 | tINS | RR | 360 | IOT10[A] | clk_ibuf/O
2.533 | 1.723 | tNET | RR | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]/CLK
2.533 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]
2.533 | 0.000 | tHld |  | 1 | R7C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/w_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%
Arrival Data Path Delay | cell: 0.667, 61.862%; route: 0.011, 1.051%; tC2Q: 0.400, 37.087%
Required Clock Path Delay | cell: 0.811, 31.998%; route: 1.723, 68.002%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | i_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | i_Z[0]/CLK

### MPW2

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | key1_temp2_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | key1_temp2_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | key1_temp2_Z/CLK

### MPW3

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | i_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | i_Z[9]/CLK

### MPW4

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | i_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | i_Z[1]/CLK

### MPW5

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wdata_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wdata_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wdata_Z[2]/CLK

### MPW6

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wyaddr_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wyaddr_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/wyaddr_Z[2]/CLK

### MPW7

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/ERASE_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/ERASE_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/ERASE_Z/CLK

### MPW8

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[4]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[4]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[4]/CLK

### MPW9

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/u_WR_UFM_64K/din_tmp[3]/CLK

### MPW10

MPW Summary:

Slack: | 2.738
Actual Width: | 4.238
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/w_command_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.945 | 0.945 | tINS | FF | clk_ibuf/O
8.295 | 2.350 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/w_command_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.811 | 0.811 | tINS | RR | clk_ibuf/O
12.533 | 1.723 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_64K/w_command_Z/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
360 | clk_c | 0.015 | 2.350
56 | w_state[8] | 5.634 | 1.840
48 | w_state[9] | 4.967 | 2.816
46 | erase_reg | 2.944 | 2.830
46 | w_state[0] | 5.831 | 1.782
43 | N_64_i | 4.408 | 1.624
38 | state_UFM[2] | 2.955 | 2.250
37 | state_UFM[3] | 3.514 | 2.208
37 | state_UFM[5] | 3.031 | 2.204
29 | e_state[4] | 5.113 | 2.419

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R4C10 | 0.514
R7C6 | 0.500
R5C6 | 0.500
R5C12 | 0.444
R4C15 | 0.444
R4C6 | 0.431
R7C10 | 0.417
R4C16 | 0.417
R5C15 | 0.403
R3C15 | 0.361

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---