Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_REG_IF\project\impl\synthesize\rev_1\FLASH256K_REG_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_REG_IF\project\src\FLASH256K_REG_IF.cst
Timing Constraint File | ---
GOWIN version | V1.9.2.01Beta
Part Number | GW1N-LV4LQ144C6/I5
Created Time | Tue Oct 22 17:09:15 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 1020
Numbers of Endpoints Analyzed | 949
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 124.786(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.986 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.414
2 | 2.198 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.202
3 | 2.454 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.946
4 | 2.481 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.919
5 | 2.489 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.911
6 | 2.511 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.889
7 | 2.577 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.823
8 | 2.722 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.678
9 | 2.775 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.625
10 | 2.775 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.625
11 | 2.778 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.622
12 | 2.835 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.565
13 | 2.854 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.546
14 | 2.861 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.539
15 | 3.019 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.381
16 | 3.049 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.351
17 | 3.073 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.327
18 | 3.104 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.296
19 | 3.118 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_Z[3]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.282
20 | 3.151 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.249
21 | 3.163 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.237
22 | 3.195 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.205
23 | 3.266 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.134
24 | 3.292 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.108
25 | 3.292 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.108

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.571 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_busy_tmp/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.571
2 | 0.572 | i_Z[7]/Q | i_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.572
3 | 0.577 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.577
4 | 0.598 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[30]/Q | rdata_reg[30]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.598
5 | 0.708 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
6 | 0.708 | erase_reg_Z/Q | erase_reg_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
7 | 0.708 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
8 | 0.708 | i_Z[5]/Q | i_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
9 | 0.708 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
10 | 0.709 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
11 | 0.709 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
12 | 0.710 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
13 | 0.710 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
14 | 0.711 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
15 | 0.714 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
16 | 0.714 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
17 | 0.714 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
18 | 0.833 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[9]/Q | rdata_reg[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.833
19 | 0.833 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[31]/Q | rdata_reg[31]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.833
20 | 0.837 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[1]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.837
21 | 0.841 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.841
22 | 0.842 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[2]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.842
23 | 0.846 | i_Z[6]/Q | i_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.846
24 | 0.859 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/Q | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.859
25 | 0.881 | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[18]/Q | rdata_reg[18]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.881

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[0]
2 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | key1_temp2_Z
3 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[9]
4 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[1]
5 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | rdata_reg[17]
6 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/wdata_Z[10]
7 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[29]
8 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[7]
9 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[6]
10 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[28]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.986
Data Arrival Time | 10.307
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
7.679 | 0.057 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
7.679 | 0.000 | tNET | FF | 2 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
7.736 | 0.057 | tINS | FF | 1 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
7.736 | 0.000 | tNET | FF | 2 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
7.793 | 0.057 | tINS | FF | 1 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
7.793 | 0.000 | tNET | FF | 2 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
7.850 | 0.057 | tINS | FF | 1 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/COUT
7.850 | 0.000 | tNET | FF | 2 | R16C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[17]/CIN
7.907 | 0.057 | tINS | FF | 1 | R16C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[17]/COUT
7.907 | 0.000 | tNET | FF | 2 | R16C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_s_0[18]/CIN
8.470 | 0.563 | tINS | FF | 1 | R16C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_s_0[18]/SUM
9.275 | 0.804 | tNET | FF | 1 | R16C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[18]/I3
10.307 | 1.032 | tINS | FF | 1 | R16C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[18]/F
10.307 | 0.000 | tNET | FF | 1 | R16C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]
12.293 | -0.400 | tSu |  | 1 | R16C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[18]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 4.032, 54.386%; route: 2.923, 39.432%; tC2Q: 0.458, 6.182%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path2

Path Summary:

Slack | 2.198
Data Arrival Time | 10.095
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
7.679 | 0.057 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
7.679 | 0.000 | tNET | FF | 2 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
8.242 | 0.563 | tINS | FF | 1 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/SUM
9.063 | 0.821 | tNET | FF | 1 | R16C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[14]/I3
10.095 | 1.032 | tINS | FF | 1 | R16C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[14]/F
10.095 | 0.000 | tNET | FF | 1 | R16C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]
12.293 | -0.400 | tSu |  | 1 | R16C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.804, 52.817%; route: 2.940, 40.819%; tC2Q: 0.458, 6.364%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path3

Path Summary:

Slack | 2.454
Data Arrival Time | 9.839
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
7.679 | 0.057 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
7.679 | 0.000 | tNET | FF | 2 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
7.736 | 0.057 | tINS | FF | 1 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
7.736 | 0.000 | tNET | FF | 2 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
7.793 | 0.057 | tINS | FF | 1 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
7.793 | 0.000 | tNET | FF | 2 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
8.321 | 0.528 | tINS | FR | 1 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/SUM
8.740 | 0.419 | tNET | RR | 1 | R16C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[16]/I3
9.839 | 1.099 | tINS | RF | 1 | R16C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[16]/F
9.839 | 0.000 | tNET | FF | 1 | R16C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]
12.293 | -0.400 | tSu |  | 1 | R16C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[16]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.950, 56.865%; route: 2.538, 36.537%; tC2Q: 0.458, 6.598%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path4

Path Summary:

Slack | 2.481
Data Arrival Time | 9.812
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
8.185 | 0.563 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/SUM
8.990 | 0.804 | tNET | FF | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[13]/I3
9.812 | 0.822 | tINS | FF | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[13]/F
9.812 | 0.000 | tNET | FF | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
12.293 | -0.400 | tSu |  | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.537, 51.122%; route: 2.923, 42.253%; tC2Q: 0.458, 6.625%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path5

Path Summary:

Slack | 2.489
Data Arrival Time | 9.804
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.900 | 0.563 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/SUM
8.705 | 0.804 | tNET | FF | 1 | R15C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[8]/I3
9.804 | 1.099 | tINS | FF | 1 | R15C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[8]/F
9.804 | 0.000 | tNET | FF | 1 | R15C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]
12.293 | -0.400 | tSu |  | 1 | R15C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.529, 51.066%; route: 2.923, 42.302%; tC2Q: 0.458, 6.632%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path6

Path Summary:

Slack | 2.511
Data Arrival Time | 9.782
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
7.679 | 0.057 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
7.679 | 0.000 | tNET | FF | 2 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
7.736 | 0.057 | tINS | FF | 1 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
7.736 | 0.000 | tNET | FF | 2 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
8.264 | 0.528 | tINS | FR | 1 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/SUM
8.683 | 0.419 | tNET | RR | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[15]/I3
9.782 | 1.099 | tINS | RF | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[15]/F
9.782 | 0.000 | tNET | FF | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]
12.293 | -0.400 | tSu |  | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.893, 56.508%; route: 2.538, 36.839%; tC2Q: 0.458, 6.653%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path7

Path Summary:

Slack | 2.577
Data Arrival Time | 9.716
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.617 | 1.524 | tNET | FF | 1 | R15C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m65_0_i/I2
9.716 | 1.099 | tINS | FF | 1 | R15C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m65_0_i/F
9.716 | 0.000 | tNET | FF | 1 | R15C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]
12.293 | -0.400 | tSu |  | 1 | R15C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.230, 47.337%; route: 3.135, 45.946%; tC2Q: 0.458, 6.717%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path8

Path Summary:

Slack | 2.722
Data Arrival Time | 9.571
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.472 | 1.378 | tNET | FF | 1 | R16C8[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[2]/I1
9.571 | 1.099 | tINS | FF | 1 | R16C8[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[2]/F
9.571 | 0.000 | tNET | FF | 1 | R16C8[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C8[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]
12.293 | -0.400 | tSu |  | 1 | R16C8[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.230, 48.370%; route: 2.989, 44.767%; tC2Q: 0.458, 6.864%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path9

Path Summary:

Slack | 2.775
Data Arrival Time | 9.518
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
8.071 | 0.563 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/SUM
8.892 | 0.821 | tNET | FF | 1 | R16C9[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[11]/I3
9.518 | 0.626 | tINS | FF | 1 | R16C9[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[11]/F
9.518 | 0.000 | tNET | FF | 1 | R16C9[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]
12.293 | -0.400 | tSu |  | 1 | R16C9[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[11]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.227, 48.708%; route: 2.940, 44.374%; tC2Q: 0.458, 6.918%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path10

Path Summary:

Slack | 2.775
Data Arrival Time | 9.518
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
7.622 | 0.057 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
7.622 | 0.000 | tNET | FF | 2 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
7.679 | 0.057 | tINS | FF | 1 | R16C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
7.679 | 0.000 | tNET | FF | 2 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
7.736 | 0.057 | tINS | FF | 1 | R16C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
7.736 | 0.000 | tNET | FF | 2 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
7.793 | 0.057 | tINS | FF | 1 | R16C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
7.793 | 0.000 | tNET | FF | 2 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
7.850 | 0.057 | tINS | FF | 1 | R16C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[16]/COUT
7.850 | 0.000 | tNET | FF | 2 | R16C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[17]/CIN
8.413 | 0.563 | tINS | FF | 1 | R16C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[17]/SUM
8.419 | 0.005 | tNET | FF | 1 | R16C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[17]/I3
9.518 | 1.099 | tINS | FF | 1 | R16C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[17]/F
9.518 | 0.000 | tNET | FF | 1 | R16C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]
12.293 | -0.400 | tSu |  | 1 | R16C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[17]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 4.042, 61.013%; route: 2.125, 32.069%; tC2Q: 0.458, 6.918%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path11

Path Summary:

Slack | 2.778
Data Arrival Time | 9.514
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[4]/F
6.138 | 1.135 | tNET | FF | 2 | R15C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/I0
7.183 | 1.045 | tINS | FF | 1 | R15C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
7.183 | 0.000 | tNET | FF | 2 | R15C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
7.240 | 0.057 | tINS | FF | 1 | R15C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
7.240 | 0.000 | tNET | FF | 2 | R15C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
7.297 | 0.057 | tINS | FF | 1 | R15C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
7.297 | 0.000 | tNET | FF | 2 | R15C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
7.354 | 0.057 | tINS | FF | 1 | R15C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
7.354 | 0.000 | tNET | FF | 2 | R15C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
7.411 | 0.057 | tINS | FF | 1 | R15C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[19]/COUT
7.411 | 0.000 | tNET | FF | 2 | R15C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[20]/CIN
7.468 | 0.057 | tINS | FF | 1 | R15C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[20]/COUT
7.468 | 0.000 | tNET | FF | 2 | R15C13[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[21]/CIN
7.996 | 0.528 | tINS | FR | 1 | R15C13[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[21]/SUM
8.415 | 0.419 | tNET | RR | 1 | R14C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[21]/I3
9.514 | 1.099 | tINS | RF | 1 | R14C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[21]/F
9.514 | 0.000 | tNET | FF | 1 | R14C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R14C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]
12.293 | -0.400 | tSu |  | 1 | R14C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.779, 57.071%; route: 2.384, 36.007%; tC2Q: 0.458, 6.922%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path12

Path Summary:

Slack | 2.835
Data Arrival Time | 9.457
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[4]/F
6.138 | 1.135 | tNET | FF | 2 | R15C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/I0
7.183 | 1.045 | tINS | FF | 1 | R15C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
7.183 | 0.000 | tNET | FF | 2 | R15C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
7.240 | 0.057 | tINS | FF | 1 | R15C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
7.240 | 0.000 | tNET | FF | 2 | R15C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
7.297 | 0.057 | tINS | FF | 1 | R15C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
7.297 | 0.000 | tNET | FF | 2 | R15C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
7.354 | 0.057 | tINS | FF | 1 | R15C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
7.354 | 0.000 | tNET | FF | 2 | R15C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
7.411 | 0.057 | tINS | FF | 1 | R15C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[19]/COUT
7.411 | 0.000 | tNET | FF | 2 | R15C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[20]/CIN
7.939 | 0.528 | tINS | FR | 1 | R15C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[20]/SUM
8.358 | 0.419 | tNET | RR | 1 | R16C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[20]/I3
9.457 | 1.099 | tINS | RF | 1 | R16C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[20]/F
9.457 | 0.000 | tNET | FF | 1 | R16C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]
12.293 | -0.400 | tSu |  | 1 | R16C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.722, 56.699%; route: 2.384, 36.319%; tC2Q: 0.458, 6.982%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path13

Path Summary:

Slack | 2.854
Data Arrival Time | 9.439
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.617 | 1.524 | tNET | FF | 1 | R15C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m56_i_0/I2
9.439 | 0.822 | tINS | FF | 1 | R15C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m56_i_0/F
9.439 | 0.000 | tNET | FF | 1 | R15C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]
12.293 | -0.400 | tSu |  | 1 | R15C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.953, 45.109%; route: 3.135, 47.890%; tC2Q: 0.458, 7.001%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path14

Path Summary:

Slack | 2.861
Data Arrival Time | 9.432
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/Q
4.651 | 1.300 | tNET | FF | 1 | R15C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_1_cZ/I0
5.712 | 1.061 | tINS | FR | 1 | R15C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_1_cZ/F
6.131 | 0.419 | tNET | RR | 1 | R16C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_cZ/I1
6.953 | 0.822 | tINS | RF | 24 | R16C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_cZ/F
8.333 | 1.380 | tNET | FF | 1 | R16C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[19]/I0
9.432 | 1.099 | tINS | FF | 1 | R16C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[19]/F
9.432 | 0.000 | tNET | FF | 1 | R16C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]
12.293 | -0.400 | tSu |  | 1 | R16C13[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[19]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.982, 45.602%; route: 3.099, 47.389%; tC2Q: 0.458, 7.009%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path15

Path Summary:

Slack | 3.019
Data Arrival Time | 9.274
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.452 | 1.358 | tNET | FF | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[5]/I1
9.274 | 0.822 | tINS | FF | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[5]/F
9.274 | 0.000 | tNET | FF | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
12.293 | -0.400 | tSu |  | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.953, 46.277%; route: 2.970, 46.540%; tC2Q: 0.458, 7.183%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path16

Path Summary:

Slack | 3.049
Data Arrival Time | 9.244
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
7.508 | 0.057 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
7.508 | 0.000 | tNET | FF | 2 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
7.565 | 0.057 | tINS | FF | 1 | R16C11[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
7.565 | 0.000 | tNET | FF | 2 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
8.128 | 0.563 | tINS | FF | 1 | R16C11[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[12]/SUM
8.618 | 0.490 | tNET | FF | 1 | R16C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[12]/I3
9.244 | 0.626 | tINS | FF | 1 | R16C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[12]/F
9.244 | 0.000 | tNET | FF | 1 | R16C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]
12.293 | -0.400 | tSu |  | 1 | R16C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.284, 51.705%; route: 2.609, 41.079%; tC2Q: 0.458, 7.216%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path17

Path Summary:

Slack | 3.073
Data Arrival Time | 9.220
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.121 | 1.028 | tNET | FF | 1 | R16C8[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[1]/I1
9.220 | 1.099 | tINS | FF | 1 | R16C8[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[1]/F
9.220 | 0.000 | tNET | FF | 1 | R16C8[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C8[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]
12.293 | -0.400 | tSu |  | 1 | R16C8[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.230, 51.048%; route: 2.639, 41.708%; tC2Q: 0.458, 7.244%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path18

Path Summary:

Slack | 3.104
Data Arrival Time | 9.189
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C12[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[15]/Q
4.651 | 1.300 | tNET | FF | 1 | R15C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_1_cZ/I0
5.712 | 1.061 | tINS | FR | 1 | R15C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_1_cZ/F
6.131 | 0.419 | tNET | RR | 1 | R16C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_cZ/I1
6.953 | 0.822 | tINS | RF | 24 | R16C9[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_18_cZ/F
8.157 | 1.204 | tNET | FF | 1 | R14C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[22]/I0
9.189 | 1.032 | tINS | FF | 1 | R14C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[22]/F
9.189 | 0.000 | tNET | FF | 1 | R14C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R14C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]
12.293 | -0.400 | tSu |  | 1 | R14C13[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.915, 46.299%; route: 2.923, 46.422%; tC2Q: 0.458, 7.280%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path19

Path Summary:

Slack | 3.118
Data Arrival Time | 9.175
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_Z[3]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_Z[3]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R17C10[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_Z[3]/Q
4.643 | 1.292 | tNET | FF | 1 | R14C11[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m100_i_o2_3/I1
5.704 | 1.061 | tINS | FR | 1 | R14C11[3][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m100_i_o2_3/F
6.123 | 0.419 | tNET | RR | 1 | R15C11[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m100_i_o2/I0
6.749 | 0.626 | tINS | RF | 11 | R15C11[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m100_i_o2/F
8.076 | 1.327 | tNET | FF | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i_0/I1
9.175 | 1.099 | tINS | FF | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i_0/F
9.175 | 0.000 | tNET | FF | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
12.293 | -0.400 | tSu |  | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.786, 44.348%; route: 3.038, 48.357%; tC2Q: 0.458, 7.296%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path20

Path Summary:

Slack | 3.151
Data Arrival Time | 9.142
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R9C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R9C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/Q
4.974 | 1.622 | tNET | FF | 2 | R12C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[1]/I0
6.019 | 1.045 | tINS | FF | 1 | R12C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[1]/COUT
6.019 | 0.000 | tNET | FF | 2 | R12C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[2]/CIN
6.076 | 0.057 | tINS | FF | 1 | R12C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[2]/COUT
6.076 | 0.000 | tNET | FF | 2 | R12C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[3]/CIN
6.133 | 0.057 | tINS | FF | 1 | R12C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[3]/COUT
6.133 | 0.000 | tNET | FF | 2 | R12C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[4]/CIN
6.190 | 0.057 | tINS | FF | 1 | R12C12[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[4]/COUT
6.190 | 0.000 | tNET | FF | 2 | R12C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[5]/CIN
6.247 | 0.057 | tINS | FF | 1 | R12C12[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[5]/COUT
6.247 | 0.000 | tNET | FF | 2 | R12C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[6]/CIN
6.304 | 0.057 | tINS | FF | 1 | R12C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[6]/COUT
6.304 | 0.000 | tNET | FF | 2 | R12C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[7]/CIN
6.867 | 0.563 | tINS | FF | 1 | R12C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[7]/SUM
8.320 | 1.453 | tNET | FF | 1 | R7C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_lm_0[7]/I1
9.142 | 0.822 | tINS | FF | 1 | R7C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_lm_0[7]/F
9.142 | 0.000 | tNET | FF | 1 | R7C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R7C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]
12.293 | -0.400 | tSu |  | 1 | R7C13[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.715, 43.445%; route: 3.076, 49.220%; tC2Q: 0.458, 7.334%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path21

Path Summary:

Slack | 3.163
Data Arrival Time | 9.130
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/CLK
3.351 | 0.458 | tC2Q | RF | 4 | R16C8[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[5]/Q
4.181 | 0.830 | tNET | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/I1
5.003 | 0.822 | tINS | FF | 1 | R15C9[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[4]/F
6.292 | 1.289 | tNET | FF | 2 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/I0
7.337 | 1.045 | tINS | FF | 1 | R16C10[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
7.337 | 0.000 | tNET | FF | 2 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
7.394 | 0.057 | tINS | FF | 1 | R16C10[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
7.394 | 0.000 | tNET | FF | 2 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
7.451 | 0.057 | tINS | FF | 1 | R16C10[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
7.451 | 0.000 | tNET | FF | 2 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
8.014 | 0.563 | tINS | FF | 1 | R16C11[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_cry_0[10]/SUM
8.504 | 0.490 | tNET | FF | 1 | R16C9[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[10]/I3
9.130 | 0.626 | tINS | FF | 1 | R16C9[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[10]/F
9.130 | 0.000 | tNET | FF | 1 | R16C9[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]
12.293 | -0.400 | tSu |  | 1 | R16C9[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.170, 50.822%; route: 2.609, 41.830%; tC2Q: 0.458, 7.348%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path22

Path Summary:

Slack | 3.195
Data Arrival Time | 9.098
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
8.472 | 1.378 | tNET | FF | 1 | R16C8[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[0]/I1
9.098 | 0.626 | tINS | FF | 1 | R16C8[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[0]/F
9.098 | 0.000 | tNET | FF | 1 | R16C8[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C8[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]
12.293 | -0.400 | tSu |  | 1 | R16C8[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.757, 44.434%; route: 2.989, 48.180%; tC2Q: 0.458, 7.387%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path23

Path Summary:

Slack | 3.266
Data Arrival Time | 9.026
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R9C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R9C12[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[1]/Q
4.974 | 1.622 | tNET | FF | 2 | R12C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[1]/I0
6.019 | 1.045 | tINS | FF | 1 | R12C11[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[1]/COUT
6.019 | 0.000 | tNET | FF | 2 | R12C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[2]/CIN
6.076 | 0.057 | tINS | FF | 1 | R12C11[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[2]/COUT
6.076 | 0.000 | tNET | FF | 2 | R12C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[3]/CIN
6.639 | 0.563 | tINS | FF | 1 | R12C11[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_cry_0[3]/SUM
7.927 | 1.289 | tNET | FF | 1 | R9C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_lm_0[3]/I1
9.026 | 1.099 | tINS | FF | 1 | R9C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_lm_0[3]/F
9.026 | 0.000 | tNET | FF | 1 | R9C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R9C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]
12.293 | -0.400 | tSu |  | 1 | R9C12[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/pgs_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.764, 45.063%; route: 2.911, 47.465%; tC2Q: 0.458, 7.472%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path24

Path Summary:

Slack | 3.292
Data Arrival Time | 9.001
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
7.969 | 0.875 | tNET | FF | 1 | R16C9[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[9]/I1
9.001 | 1.032 | tINS | FF | 1 | R16C9[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[9]/F
9.001 | 0.000 | tNET | FF | 1 | R16C9[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]
12.293 | -0.400 | tSu |  | 1 | R16C9[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.163, 51.783%; route: 2.487, 40.713%; tC2Q: 0.458, 7.504%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path25

Path Summary:

Slack | 3.292
Data Arrival Time | 9.001
Data Required Time | 12.293
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/CLK
3.351 | 0.458 | tC2Q | RF | 3 | R16C8[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[13]/Q
4.158 | 0.807 | tNET | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/I1
5.190 | 1.032 | tINS | FF | 1 | R15C9[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_10_cZ/F
5.995 | 0.804 | tNET | FF | 1 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/I0
7.094 | 1.099 | tINS | FF | 25 | R14C10[3][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state23_19_cZ/F
7.969 | 0.875 | tNET | FF | 1 | R16C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[4]/I1
9.001 | 1.032 | tINS | FF | 1 | R16C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_lm_0[4]/F
9.001 | 0.000 | tNET | FF | 1 | R16C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]/CLK
12.693 | -0.200 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]
12.293 | -0.400 | tSu |  | 1 | R16C9[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/erase_cnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.163, 51.783%; route: 2.487, 40.713%; tC2Q: 0.458, 7.504%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.571
Data Arrival Time | 2.851
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_busy_tmp
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_busy_tmp/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R13C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_busy_tmp/Q
2.851 | 0.238 | tNET | RR | 1 | R13C7[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C7[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z
2.280 | 0.000 | tHld |  | 1 | R13C7[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_busy_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path2

Path Summary:

Slack | 0.572
Data Arrival Time | 2.852
Data Required Time | 2.280
From | i_Z[7]
To | i_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C14[2][B] | i_Z[7]/CLK
2.613 | 0.333 | tC2Q | RR | 4 | R14C14[2][B] | i_Z[7]/Q
2.852 | 0.239 | tNET | RR | 1 | R14C14[2][A] | i_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C14[2][A] | i_Z[8]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[8]
2.280 | 0.000 | tHld |  | 1 | R14C14[2][A] | i_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path3

Path Summary:

Slack | 0.577
Data Arrival Time | 2.857
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 15 | R12C6[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[1]/Q
2.857 | 0.243 | tNET | RR | 1 | R12C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z
2.280 | 0.000 | tHld |  | 1 | R12C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/e_command_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.243, 42.211%; tC2Q: 0.333, 57.789%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path4

Path Summary:

Slack | 0.598
Data Arrival Time | 2.878
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[30]
To | rdata_reg[30]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R11C3[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[30]/CLK
2.613 | 0.333 | tC2Q | RR | 1 | R11C3[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[30]/Q
2.878 | 0.265 | tNET | RR | 1 | IOL11[B] | rdata_reg[30]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | IOL11[B] | rdata_reg[30]/CLK
2.280 | 0.000 | tUnc |  |  |  | rdata_reg[30]
2.280 | 0.000 | tHld |  | 1 | IOL11[B] | rdata_reg[30]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.265, 44.283%; tC2Q: 0.333, 55.717%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path5

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/Q
2.616 | 0.002 | tNET | RR | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/N_226_i_cZ/I2
2.988 | 0.372 | tINS | RF | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/N_226_i_cZ/F
2.988 | 0.000 | tNET | FF | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]
2.280 | 0.000 | tHld |  | 1 | R13C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path6

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | erase_reg_Z
To | erase_reg_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C14[0][A] | erase_reg_Z/CLK
2.613 | 0.333 | tC2Q | RR | 48 | R14C14[0][A] | erase_reg_Z/Q
2.616 | 0.002 | tNET | RR | 1 | R14C14[0][A] | erase_reg_3_f0_0_0/I0
2.988 | 0.372 | tINS | RF | 1 | R14C14[0][A] | erase_reg_3_f0_0_0/F
2.988 | 0.000 | tNET | FF | 1 | R14C14[0][A] | erase_reg_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C14[0][A] | erase_reg_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | erase_reg_Z
2.280 | 0.000 | tHld |  | 1 | R14C14[0][A] | erase_reg_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path7

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/Q
2.616 | 0.002 | tNET | RR | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_4_a4[0]/I0
2.988 | 0.372 | tINS | RF | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_4_a4[0]/F
2.988 | 0.000 | tNET | FF | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]
2.280 | 0.000 | tHld |  | 1 | R8C7[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path8

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | i_Z[5]
To | i_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C14[1][A] | i_Z[5]/CLK
2.613 | 0.333 | tC2Q | RR | 4 | R13C14[1][A] | i_Z[5]/Q
2.616 | 0.002 | tNET | RR | 1 | R13C14[1][A] | i_ns_0[5]/I2
2.988 | 0.372 | tINS | RF | 1 | R13C14[1][A] | i_ns_0[5]/F
2.988 | 0.000 | tNET | FF | 1 | R13C14[1][A] | i_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C14[1][A] | i_Z[5]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[5]
2.280 | 0.000 | tHld |  | 1 | R13C14[1][A] | i_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path9

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/Q
2.616 | 0.002 | tNET | RR | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[0]/I2
2.988 | 0.372 | tINS | RF | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[0]/F
2.988 | 0.000 | tNET | FF | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
2.280 | 0.000 | tHld |  | 1 | R7C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path10

Path Summary:

Slack | 0.709
Data Arrival Time | 2.989
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/Q
2.617 | 0.004 | tNET | RR | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt_4_0_a2_0_a2[0]/I0
2.989 | 0.372 | tINS | RF | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt_4_0_a2_0_a2[0]/F
2.989 | 0.000 | tNET | FF | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
2.280 | 0.000 | tHld |  | 1 | R12C9[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path11

Path Summary:

Slack | 0.709
Data Arrival Time | 2.989
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/CLK
2.613 | 0.333 | tC2Q | RR | 9 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/Q
2.617 | 0.004 | tNET | RR | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m4_i_0/I2
2.989 | 0.372 | tINS | RF | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m4_i_0/F
2.989 | 0.000 | tNET | FF | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]
2.280 | 0.000 | tHld |  | 1 | R13C4[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path12

Path Summary:

Slack | 0.710
Data Arrival Time | 2.990
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/CLK
2.613 | 0.333 | tC2Q | RR | 12 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/Q
2.618 | 0.005 | tNET | RR | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m25_0_i/I1
2.990 | 0.372 | tINS | RF | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m25_0_i/F
2.990 | 0.000 | tNET | FF | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]
2.280 | 0.000 | tHld |  | 1 | R15C6[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path13

Path Summary:

Slack | 0.710
Data Arrival Time | 2.990
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/CLK
2.613 | 0.333 | tC2Q | RR | 11 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/Q
2.618 | 0.005 | tNET | RR | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m16_i_0/I3
2.990 | 0.372 | tINS | RF | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m16_i_0/F
2.990 | 0.000 | tNET | FF | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
2.280 | 0.000 | tHld |  | 1 | R13C5[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path14

Path Summary:

Slack | 0.711
Data Arrival Time | 2.991
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/CLK
2.613 | 0.333 | tC2Q | RR | 12 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/Q
2.619 | 0.006 | tNET | RR | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m16_i_0/I2
2.991 | 0.372 | tINS | RF | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m16_i_0/F
2.991 | 0.000 | tNET | FF | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
2.280 | 0.000 | tHld |  | 1 | R5C12[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path15

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 17 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/Q
2.622 | 0.008 | tNET | RR | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_i_m4[1]/I3
2.994 | 0.372 | tINS | RF | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_i_m4[1]/F
2.994 | 0.000 | tNET | FF | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]
2.280 | 0.000 | tHld |  | 1 | R7C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path16

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/CLK
2.613 | 0.333 | tC2Q | RR | 11 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/Q
2.622 | 0.008 | tNET | RR | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i_0/I3
2.994 | 0.372 | tINS | RF | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i_0/F
2.994 | 0.000 | tNET | FF | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
2.280 | 0.000 | tHld |  | 1 | R15C7[0][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path17

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/CLK
2.613 | 0.333 | tC2Q | RR | 20 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/Q
2.622 | 0.008 | tNET | RR | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_ns_cZ[4]/I2
2.994 | 0.372 | tINS | RF | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_ns_cZ[4]/F
2.994 | 0.000 | tNET | FF | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]
2.280 | 0.000 | tHld |  | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path18

Path Summary:

Slack | 0.833
Data Arrival Time | 3.113
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[9]
To | rdata_reg[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[9]/CLK
2.613 | 0.333 | tC2Q | RR | 1 | R9C4[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[9]/Q
3.113 | 0.500 | tNET | RR | 1 | R9C2[0][A] | rdata_reg[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C2[0][A] | rdata_reg[9]/CLK
2.280 | 0.000 | tUnc |  |  |  | rdata_reg[9]
2.280 | 0.000 | tHld |  | 1 | R9C2[0][A] | rdata_reg[9]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path19

Path Summary:

Slack | 0.833
Data Arrival Time | 3.113
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[31]
To | rdata_reg[31]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R11C3[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[31]/CLK
2.613 | 0.333 | tC2Q | RR | 1 | R11C3[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[31]/Q
3.113 | 0.500 | tNET | RR | 1 | IOL11[A] | rdata_reg[31]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | IOL11[A] | rdata_reg[31]/CLK
2.280 | 0.000 | tUnc |  |  |  | rdata_reg[31]
2.280 | 0.000 | tHld |  | 1 | IOL11[A] | rdata_reg[31]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path20

Path Summary:

Slack | 0.837
Data Arrival Time | 3.117
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[1]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R7C13[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[1]/Q
3.117 | 0.504 | tNET | RR | 1 | R6C13[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R6C13[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]
2.280 | 0.000 | tHld |  | 1 | R6C13[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.504, 60.186%; tC2Q: 0.333, 39.814%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path21

Path Summary:

Slack | 0.841
Data Arrival Time | 3.121
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R6C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/CLK
2.613 | 0.333 | tC2Q | RR | 4 | R6C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/Q
3.121 | 0.508 | tNET | RR | 1 | R7C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z
2.280 | 0.000 | tHld |  | 1 | R7C6[2][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_busy_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 60.364%; tC2Q: 0.333, 39.636%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path22

Path Summary:

Slack | 0.842
Data Arrival Time | 3.122
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[2]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R6C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[2]/CLK
2.613 | 0.333 | tC2Q | RR | 17 | R6C6[1][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[2]/Q
3.122 | 0.508 | tNET | RR | 1 | R7C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp
2.280 | 0.000 | tHld |  | 1 | R7C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_RD_UFM/se_tmp

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 60.399%; tC2Q: 0.333, 39.601%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path23

Path Summary:

Slack | 0.846
Data Arrival Time | 3.126
Data Required Time | 2.280
From | i_Z[6]
To | i_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R15C14[2][B] | i_Z[6]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R15C14[2][B] | i_Z[6]/Q
3.126 | 0.513 | tNET | RR | 1 | R14C14[2][B] | i_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C14[2][B] | i_Z[7]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[7]
2.280 | 0.000 | tHld |  | 1 | R14C14[2][B] | i_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.513, 60.594%; tC2Q: 0.333, 39.406%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path24

Path Summary:

Slack | 0.859
Data Arrival Time | 3.139
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]
To | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/CLK
2.613 | 0.333 | tC2Q | RR | 20 | R8C6[1][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/state_UFM_Z[4]/Q
3.139 | 0.526 | tNET | RR | 1 | R9C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z
2.280 | 0.000 | tHld |  | 1 | R9C6[2][A] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/r_command_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.526, 61.204%; tC2Q: 0.333, 38.796%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path25

Path Summary:

Slack | 0.881
Data Arrival Time | 3.161
Data Required Time | 2.280
From | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[18]
To | rdata_reg[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R11C4[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[18]/CLK
2.613 | 0.333 | tC2Q | RR | 1 | R11C4[0][B] | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[18]/Q
3.161 | 0.548 | tNET | RR | 1 | IOT4[B] | rdata_reg[18]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 418 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | IOT4[B] | rdata_reg[18]/CLK
2.280 | 0.000 | tUnc |  |  |  | rdata_reg[18]
2.280 | 0.000 | tHld |  | 1 | IOT4[B] | rdata_reg[18]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[0]/CLK

### MPW2

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | key1_temp2_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | key1_temp2_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | key1_temp2_Z/CLK

### MPW3

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[9]/CLK

### MPW4

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[1]/CLK

### MPW5

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | rdata_reg[17]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | rdata_reg[17]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | rdata_reg[17]/CLK

### MPW6

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/wdata_Z[10]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/wdata_Z[10]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/wdata_Z[10]/CLK

### MPW7

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[29]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[29]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[29]/CLK

### MPW8

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[7]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[7]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[7]/CLK

### MPW9

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/u_ER_UFM/whd_cnt_Z[6]/CLK

### MPW10

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[28]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[28]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | u_gowin_flash_controller_top/u_Flash_Ctroller_256K/comp_data[28]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
418 | clk_c | 1.986 | 1.958
58 | w_state[8] | 5.661 | 2.185
50 | w_state[9] | 5.487 | 2.356
48 | erase_reg | 4.096 | 2.771
48 | w_state[0] | 5.909 | 2.000
45 | N_64_i | 4.661 | 1.705
38 | state_UFM[2] | 4.974 | 1.695
37 | state_UFM[5] | 4.087 | 1.515
37 | state_UFM[3] | 4.571 | 1.492
34 | state_UFM28 | 5.484 | 2.195

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R7C6 | 0.569
R8C6 | 0.569
R8C7 | 0.472
R5C12 | 0.431
R9C6 | 0.431
R16C9 | 0.417
R6C10 | 0.403
R11C6 | 0.389
R15C5 | 0.375
R7C13 | 0.361

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---