#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-059

# Tue Oct 22 17:14:24 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v" (library work)
@W: CG1337 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":38:7:38:15|Net key_write is not declared.
@W: CG1337 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":39:7:39:14|Net key_read is not declared.
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v" (library work)
Verilog syntax check successful!
Selecting top level module tb
@N: CG364 :"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v":1864:7:1864:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on DFF .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFS .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on ER_UFM_608K .......
Running optimization stage 1 on WR_UFM_608K .......
Running optimization stage 1 on RD_UFM_608K .......
Running optimization stage 1 on FLASH608K .......
Running optimization stage 1 on GW_USER_FLASH_608K .......
Running optimization stage 1 on Flash_Ctroller_608K .......
Running optimization stage 1 on Wishbone_Master_Top_608K .......
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":9929:7:9929:32|Synthesizing module Gowin_Flash_Controller_Top in library work.
Running optimization stage 1 on Gowin_Flash_Controller_Top .......
@W: CL168 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":9973:6:9973:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":3:7:3:8|Synthesizing module tb in library work.
Running optimization stage 1 on tb .......
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_adr_i[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_adr_i[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Optimizing register bit wb_reg_dat_i[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 31 to 29 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 27 to 25 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 23 to 22 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 20 to 18 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 16 to 15 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 13 to 11 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 9 to 8 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 6 to 4 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bit 2 of wb_reg_dat_i[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Pruning register bits 1 to 0 of wb_reg_adr_i[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on tb .......
@N: CL201 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\tb.v":46:0:46:5|Trying to extract state machine for register i.
Extracted state machine for register i
State machine has 29 reachable states with original encodings of:
   00000000
   00000001
   00000010
   00000011
   00000100
   00000101
   00000110
   00000111
   00001000
   00001001
   00001010
   00001011
   00001100
   00001101
   00001110
   00001111
   00010000
   00010001
   00010010
   00010011
   00010100
   00010101
   00010110
   00010111
   00011000
   00011001
   00011010
   00011011
   00011100
Running optimization stage 2 on Gowin_Flash_Controller_Top .......
Running optimization stage 2 on Wishbone_Master_Top_608K .......
Running optimization stage 2 on Flash_Ctroller_608K .......
Running optimization stage 2 on GW_USER_FLASH_608K .......
Running optimization stage 2 on FLASH608K .......
Running optimization stage 2 on RD_UFM_608K .......
Running optimization stage 2 on WR_UFM_608K .......
Running optimization stage 2 on ER_UFM_608K .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on DFFS .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on DFF .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 98MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:14:26 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:14:27 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\synwork\FLASH608K_WB_IF_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Tue Oct 22 17:14:27 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:14:28 2019

###########################################################]
Premap Report

# Tue Oct 22 17:14:29 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF_scck.rpt 
Printing clock  summary report in "C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[28] because it is equivalent to instance wb_reg_dat_i[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[24] because it is equivalent to instance wb_reg_dat_i[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[21] because it is equivalent to instance wb_reg_dat_i[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[17] because it is equivalent to instance wb_reg_dat_i[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[14] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[7] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[3] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine i[28:0] (in view: work.tb(verilog))
original code -> new code
   00000000 -> 00000000000000000000000000001
   00000001 -> 00000000000000000000000000010
   00000010 -> 00000000000000000000000000100
   00000011 -> 00000000000000000000000001000
   00000100 -> 00000000000000000000000010000
   00000101 -> 00000000000000000000000100000
   00000110 -> 00000000000000000000001000000
   00000111 -> 00000000000000000000010000000
   00001000 -> 00000000000000000000100000000
   00001001 -> 00000000000000000001000000000
   00001010 -> 00000000000000000010000000000
   00001011 -> 00000000000000000100000000000
   00001100 -> 00000000000000001000000000000
   00001101 -> 00000000000000010000000000000
   00001110 -> 00000000000000100000000000000
   00001111 -> 00000000000001000000000000000
   00010000 -> 00000000000010000000000000000
   00010001 -> 00000000000100000000000000000
   00010010 -> 00000000001000000000000000000
   00010011 -> 00000000010000000000000000000
   00010100 -> 00000000100000000000000000000
   00010101 -> 00000001000000000000000000000
   00010110 -> 00000010000000000000000000000
   00010111 -> 00000100000000000000000000000
   00011000 -> 00001000000000000000000000000
   00011001 -> 00010000000000000000000000000
   00011010 -> 00100000000000000000000000000
   00011011 -> 01000000000000000000000000000
   00011100 -> 10000000000000000000000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 228MB)



Clock Summary
******************

          Start      Requested     Requested     Clock        Clock                     Clock
Level     Clock      Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------
0 -       System     100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                             
0 -       tb|clk     100.0 MHz     10.000        inferred     Autoconstr_clkgroup_0     510  
=============================================================================================



Clock Load Summary
***********************

           Clock     Source        Clock Pin        Non-clock Pin     Non-clock Pin
Clock      Load      Pin           Seq Example      Seq Example       Comb Example 
-----------------------------------------------------------------------------------
System     0         -             -                -                 -            
                                                                                   
tb|clk     510       clk(port)     key1_temp1.C     -                 -            
===================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 510 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 port                   510        i[28]          
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 229MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 22 17:14:31 2019

###########################################################]
Map & Optimize Report

# Tue Oct 22 17:14:31 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 218MB peak: 218MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.73ns		 532 /        40
   2		0h:00m:01s		    -2.73ns		 540 /        40

   3		0h:00m:01s		    -2.37ns		 563 /        40

   4		0h:00m:01s		    -2.37ns		 551 /        40

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 227MB)

Writing Analyst data base C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\synwork\FLASH608K_WB_IF_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 229MB peak: 229MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 229MB peak: 229MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 229MB)

@W: MT246 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\gowin_flash_controller\gowin_flash_controller.v":5843:12:5843:21|Blackbox FLASH608K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock tb|clk with period 7.46ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing report written on Tue Oct 22 17:14:36 2019
#


Top view:               tb
Requested Frequency:    134.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.317

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
tb|clk             134.0 MHz     113.9 MHz     7.462         8.779         -1.317     inferred     Autoconstr_clkgroup_0
System             100.0 MHz     270.8 MHz     10.000        3.692         6.308      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
System    tb|clk  |  7.462       6.308   |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk    System  |  7.462       6.074   |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk    tb|clk  |  7.462       -1.317  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: tb|clk
====================================



Starting Points with Worst Slack
********************************

                                                                                                                  Starting                                         Arrival           
Instance                                                                                                          Reference     Type     Pin     Net               Time        Slack 
                                                                                                                  Clock                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
i[8]                                                                                                              tb|clk        DFFC     Q       i[8]              0.367       -1.317
i[7]                                                                                                              tb|clk        DFFC     Q       i[7]              0.367       -1.250
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[1\]      tb|clk        DFFC     Q       erase_cnt[1]      0.367       0.026 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[5\]      tb|clk        DFFC     Q       erase_cnt[5]      0.367       0.083 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[0\]      tb|clk        DFFC     Q       erase_cnt[0]      0.367       0.093 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[4\]      tb|clk        DFFC     Q       erase_cnt[4]      0.367       0.150 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[2\]      tb|clk        DFFC     Q       erase_cnt[2]      0.367       0.303 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[6\]      tb|clk        DFFC     Q       erase_cnt[6]      0.367       0.360 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[9\]      tb|clk        DFFC     Q       erase_cnt[9]      0.367       0.368 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[13\]     tb|clk        DFFC     Q       erase_cnt[13]     0.367       0.425 
=====================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                  Starting                                               Required           
Instance                                                                                                          Reference     Type      Pin     Net                    Time         Slack 
                                                                                                                  Clock                                                                     
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
wb_reg_adr_i[2]                                                                                                   tb|clk        DFFC      D       wb_reg_adr_ie_0[2]     7.329        -1.317
wb_reg_adr_i[3]                                                                                                   tb|clk        DFFC      D       wb_reg_adr_ie_0[3]     7.329        -1.317
wr_reg_enable_i                                                                                                   tb|clk        DFFC      D       wr_reg_enable_ie_0     7.329        -0.919
i[0]                                                                                                              tb|clk        DFFP      D       i_ns[0]                7.329        -0.656
wb_reg_adr_i[4]                                                                                                   tb|clk        DFFCE     CE      un1_i_8_0_a2           7.329        -0.285
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[18\]     tb|clk        DFFC      D       erase_cnt_lm[18]       7.329        0.026 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[17\]     tb|clk        DFFC      D       erase_cnt_lm[17]       7.329        0.083 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[16\]     tb|clk        DFFC      D       erase_cnt_lm[16]       7.329        0.140 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[15\]     tb|clk        DFFC      D       erase_cnt_lm[15]       7.329        0.197 
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_ER_UFM.\\erase_cnt_Z\[14\]     tb|clk        DFFC      D       erase_cnt_lm[14]       7.329        0.254 
============================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      8.646
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.317

    Number of logic level(s):                4
    Starting point:                          i[8] / Q
    Ending point:                            wb_reg_adr_i[2] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
i[8]                   DFFC     Q        Out     0.367     0.367       -         
i[8]                   Net      -        -       1.021     -           5         
i_ns_i_a2_0[8]         LUT2     I1       In      -         1.388       -         
i_ns_i_a2_0[8]         LUT2     F        Out     1.099     2.487       -         
N_370                  Net      -        -       1.021     -           2         
i_ns_a2_0[0]           LUT4     I0       In      -         3.508       -         
i_ns_a2_0[0]           LUT4     F        Out     1.032     4.540       -         
N_391                  Net      -        -       1.021     -           3         
un1_i_8_0_a2           LUT3     I0       In      -         5.561       -         
un1_i_8_0_a2           LUT3     F        Out     1.032     6.593       -         
un1_i_8_0_a2           Net      -        -       1.021     -           3         
wb_reg_adr_ie[2]       LUT3     I0       In      -         7.614       -         
wb_reg_adr_ie[2]       LUT3     F        Out     1.032     8.646       -         
wb_reg_adr_ie_0[2]     Net      -        -       0.000     -           1         
wb_reg_adr_i[2]        DFFC     D        In      -         8.646       -         
=================================================================================
Total path delay (propagation time + setup) of 8.779 is 4.695(53.5%) logic and 4.084(46.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      8.646
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.317

    Number of logic level(s):                4
    Starting point:                          i[8] / Q
    Ending point:                            wb_reg_adr_i[3] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
i[8]                   DFFC     Q        Out     0.367     0.367       -         
i[8]                   Net      -        -       1.021     -           5         
i_ns_i_a2_0[8]         LUT2     I1       In      -         1.388       -         
i_ns_i_a2_0[8]         LUT2     F        Out     1.099     2.487       -         
N_370                  Net      -        -       1.021     -           2         
i_ns_a2_0[0]           LUT4     I0       In      -         3.508       -         
i_ns_a2_0[0]           LUT4     F        Out     1.032     4.540       -         
N_391                  Net      -        -       1.021     -           3         
un1_i_8_0_a2           LUT3     I0       In      -         5.561       -         
un1_i_8_0_a2           LUT3     F        Out     1.032     6.593       -         
un1_i_8_0_a2           Net      -        -       1.021     -           3         
wb_reg_adr_ie[3]       LUT3     I0       In      -         7.614       -         
wb_reg_adr_ie[3]       LUT3     F        Out     1.032     8.646       -         
wb_reg_adr_ie_0[3]     Net      -        -       0.000     -           1         
wb_reg_adr_i[3]        DFFC     D        In      -         8.646       -         
=================================================================================
Total path delay (propagation time + setup) of 8.779 is 4.695(53.5%) logic and 4.084(46.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      8.579
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.250

    Number of logic level(s):                4
    Starting point:                          i[7] / Q
    Ending point:                            wb_reg_adr_i[2] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
i[7]                   DFFC     Q        Out     0.367     0.367       -         
i[7]                   Net      -        -       1.021     -           5         
i_ns_i_a2_0[8]         LUT2     I0       In      -         1.388       -         
i_ns_i_a2_0[8]         LUT2     F        Out     1.032     2.420       -         
N_370                  Net      -        -       1.021     -           2         
i_ns_a2_0[0]           LUT4     I0       In      -         3.441       -         
i_ns_a2_0[0]           LUT4     F        Out     1.032     4.473       -         
N_391                  Net      -        -       1.021     -           3         
un1_i_8_0_a2           LUT3     I0       In      -         5.494       -         
un1_i_8_0_a2           LUT3     F        Out     1.032     6.526       -         
un1_i_8_0_a2           Net      -        -       1.021     -           3         
wb_reg_adr_ie[2]       LUT3     I0       In      -         7.547       -         
wb_reg_adr_ie[2]       LUT3     F        Out     1.032     8.579       -         
wb_reg_adr_ie_0[2]     Net      -        -       0.000     -           1         
wb_reg_adr_i[2]        DFFC     D        In      -         8.579       -         
=================================================================================
Total path delay (propagation time + setup) of 8.712 is 4.628(53.1%) logic and 4.084(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      8.579
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.250

    Number of logic level(s):                4
    Starting point:                          i[7] / Q
    Ending point:                            wb_reg_adr_i[3] / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
i[7]                   DFFC     Q        Out     0.367     0.367       -         
i[7]                   Net      -        -       1.021     -           5         
i_ns_i_a2_0[8]         LUT2     I0       In      -         1.388       -         
i_ns_i_a2_0[8]         LUT2     F        Out     1.032     2.420       -         
N_370                  Net      -        -       1.021     -           2         
i_ns_a2_0[0]           LUT4     I0       In      -         3.441       -         
i_ns_a2_0[0]           LUT4     F        Out     1.032     4.473       -         
N_391                  Net      -        -       1.021     -           3         
un1_i_8_0_a2           LUT3     I0       In      -         5.494       -         
un1_i_8_0_a2           LUT3     F        Out     1.032     6.526       -         
un1_i_8_0_a2           Net      -        -       1.021     -           3         
wb_reg_adr_ie[3]       LUT3     I0       In      -         7.547       -         
wb_reg_adr_ie[3]       LUT3     F        Out     1.032     8.579       -         
wb_reg_adr_ie_0[3]     Net      -        -       0.000     -           1         
wb_reg_adr_i[3]        DFFC     D        In      -         8.579       -         
=================================================================================
Total path delay (propagation time + setup) of 8.712 is 4.628(53.1%) logic and 4.084(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      8.248
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.919

    Number of logic level(s):                4
    Starting point:                          i[8] / Q
    Ending point:                            wr_reg_enable_i / D
    The start point is clocked by            tb|clk [rising] on pin CLK
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
i[8]                   DFFC     Q        Out     0.367     0.367       -         
i[8]                   Net      -        -       1.021     -           5         
i_ns_i_a2_0[8]         LUT2     I1       In      -         1.388       -         
i_ns_i_a2_0[8]         LUT2     F        Out     1.099     2.487       -         
N_370                  Net      -        -       1.021     -           2         
i_ns_a2_0[0]           LUT4     I0       In      -         3.508       -         
i_ns_a2_0[0]           LUT4     F        Out     1.032     4.540       -         
N_391                  Net      -        -       1.021     -           3         
un1_i_7_0_a2           LUT4     I1       In      -         5.561       -         
un1_i_7_0_a2           LUT4     F        Out     1.099     6.660       -         
un1_i_7_0_a2           Net      -        -       0.766     -           1         
wr_reg_enable_ie       LUT4     I2       In      -         7.426       -         
wr_reg_enable_ie       LUT4     F        Out     0.822     8.248       -         
wr_reg_enable_ie_0     Net      -        -       0.000     -           1         
wr_reg_enable_i        DFFC     D        In      -         8.248       -         
=================================================================================
Total path delay (propagation time + setup) of 8.381 is 4.552(54.3%) logic and 3.829(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                                                                     Starting                                                   Arrival          
Instance                                                                                                             Reference     Type          Pin         Net                Time        Slack
                                                                                                                     Clock                                                                       
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\state_UFM_i_cZ\[0\]               System        INV           O           state_UFM_i[0]     0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[0]     DOUT[0]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[1]     DOUT[1]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[2]     DOUT[2]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[3]     DOUT[3]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[4]     DOUT[4]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[5]     DOUT[5]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[6]     DOUT[6]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[7]     DOUT[7]            0.000       6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.u_GW_USER_FLASH_608K.flash_inst     System        FLASH608K     DOUT[8]     DOUT[8]            0.000       6.308
=================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                      Starting                                    Required          
Instance                                                                                              Reference     Type      Pin     Net         Time         Slack
                                                                                                      Clock                                                         
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[0\]     System        DFFCE     D       DOUT[0]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[1\]     System        DFFCE     D       DOUT[1]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[2\]     System        DFFCE     D       DOUT[2]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[3\]     System        DFFCE     D       DOUT[3]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[4\]     System        DFFCE     D       DOUT[4]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[5\]     System        DFFCE     D       DOUT[5]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[6\]     System        DFFCE     D       DOUT[6]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[7\]     System        DFFCE     D       DOUT[7]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[8\]     System        DFFCE     D       DOUT[8]     7.329        6.308
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\comp_data\[9\]     System        DFFCE     D       DOUT[9]     7.329        6.308
====================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      7.462
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.329

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 6.308

    Number of logic level(s):                0
    Starting point:                          Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\state_UFM_i_cZ\[0\] / O
    Ending point:                            Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.Done_signal_reg / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            tb|clk [rising] on pin CLK

Instance / Net                                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                                       Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.\\state_UFM_i_cZ\[0\]     INV       O        Out     0.000     0.000       -         
state_UFM_i[0]                                                                                             Net       -        -       1.021     -           1         
Gowin_Flash_Controller_template.u_Wishbone_Master_Top_608K.u_Flash_Ctroller_608K.Done_signal_reg           DFFCE     D        In      -         1.021       -         
======================================================================================================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 229MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 229MB)

---------------------------------------
Resource Usage Report for tb 

Mapping to part: gw1n_9lqfp144-6
Cell usage:
ALU             123 uses
DFF             23 uses
DFFC            334 uses
DFFCE           138 uses
DFFP            5 uses
DFFS            9 uses
FLASH608K       1 use
GSR             1 use
INV             2 uses
LUT2            49 uses
LUT3            159 uses
LUT4            342 uses

I/O ports: 36
I/O primitives: 36
IBUF           4 uses
OBUF           32 uses

I/O Register bits:                  0
Register bits not including I/Os:   509 of 6480 (7%)
Total load per clock:
   tb|clk: 509

@S |Mapping Summary:
Total  LUTs: 550 (6%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 75MB peak: 229MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Oct 22 17:14:36 2019

###########################################################]
