PnR Analysis Report

- PnR Messages
- PnR Details
  - Placer
  - Resource Usage Summary
  - I/O Bank Usage Summary
  - Router
  - Global Clock Usage Summary
  - Global Clock Signals
  - Pinout by Port Name
  - All Package Pins
  - Memory Usage

# PnR Messages

Report Title | Gowin PnR Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH64KZ_REG_IF\project\impl\synthesize\rev_1\FLASH64KZ_REG_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH64KZ_REG_IF\project\src\FLASH64KZ_REG_IF.cst
Timing Constraints File | ---
GOWIN Version | V1.9.2.01Beta
Part Number | GW1NZ-ZV1FN32C5/I4
Created Time | Tue Oct 22 17:02:22 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# PnR Details

## Placer:

Starting Placer:

Placement Phase 0 ... REAL time: 0.043 secs

Placement Phase 1 ... REAL time: 0.057 secs

Placement Phase 2 ... REAL time: 0.168 secs

Placement Phase 3 ... REAL time: 1.009 secs

Total REAL time to Placement completion: 1.277 secs.

## Resource Usage Summary:

Resource | Usage | Utilization
Logics | 537/1152 | 46%
--LUTs,ALUs,ROM16s | 537(414 LUTs, 123 ALUs, 0 ROM16s) | -
--SSRAMs(RAM16s) | 0 | -
Registers | 360/942 | 38%
--logic Registers | 350/864 | 40%
--I/O Registers | 10/78 | 12%
CLSs | 341/576 | 59%
I/O Ports | 12 | -
I/O Bufs | 12 | -
--Input Bufs | 4 | -
--Output Bufs | 8 | -
--Inout Bufs | 0 | -
IOLOGICs | 0 | -
IODELAYs | 0/26 | 0%
BSRAMs | 0/4 | 0%
PLLs | 0/1 | 0%
DCSs | 0/4 | 0%
DQCEs | 0/12 | 0%
OSCs | 0/1 | 0%
User Flashes | 0/1 | 0%
CLKDIVs | 0/4 | 0%
DLLDLYs | 0/4 | 0%
DHCENs | 0/8 | 0%

## I/O Bank Usage Summary:

I/O Bank | Usage
bank 0 | 5/13(38%)
bank 1 | 7/13(53%)

## Router:

Starting Router:

Route Phase 0: 1166 unrouted; REAL time: 0 secs

Route Phase 1: 617 unrouted; REAL time: 0.02 secs

Route Phase 2: 0 unrouted; REAL time: 0.135 secs

Total REAL time to Router completion: 0.155 secs.

## Global Clock Usage Summary:

Global Clock | Usage
PRIMARY | 1/8(12%)
SECONDARY | 1/8(12%)
GCLK_PIN | 2/2(100%)
PLL | 0/1(0%)
CLKDIV | 0/4(0%)
DLLDLY | 0/4(0%)

## Global Clock Signals:

Signal | Global Clock | Location
clk_c | PRIMARY | LEFT
nreset_c | SECONDARY | -

## Pinout by Port Name:

Port Name | Loc./Bank | Dir. | Site | I/O Type | Drive | Pull Mode | Slew Rate | Clamp | OpenDrain | VREF | BankVccio
clk | 32/0 | in | IOT10[A] | LVCMOS18 | NA | UP | NA | NA | NA | UNKNOWN | 1.8
nreset | 31/0 | in | IOT10[B] | LVCMOS18 | NA | UP | NA | NA | NA | UNKNOWN | 1.8
key | 16/1 | in | IOR9[B] | LVCMOS18 | NA | UP | NA | NA | NA | UNKNOWN | 1.8
key2 | 12/1 | in | IOR10[A] | LVCMOS18 | NA | UP | NA | NA | NA | UNKNOWN | 1.8
rdata_wire[0] | 25/0 | out | IOT15[B] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[1] | 24/1 | out | IOR2[A] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[2] | 18/1 | out | IOR5[B] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[3] | 17/1 | out | IOR7[A] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[4] | 14/1 | out | IOR8[B] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[5] | 11/1 | out | IOR10[B] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[6] | 30/0 | out | IOT11[A] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8
rdata_wire[7] | 29/0 | out | IOT11[B] | LVCMOS18 | 8 | UP | FAST | NA | OFF | UNKNOWN | 1.8

## All Package Pins:

Loc./Bank | Signal | Dir. | Site | Io Type | Pull Mode | Hysteresis | DiffResistor | SingleResistor
7/0 | UNUSED | - | IOT7[A] | - | - | - | - | - | 6/0 | UNUSED | - | IOT7[B] | - | - | - | - | - | 3/0 | UNUSED | - | IOT8[A] | - | - | - | - | - | 1/0 | UNUSED | - | IOT8[B] | - | - | - | - | - | 2/0 | UNUSED | - | IOT9[B] | - | - | - | - | - | 32/0 | clk | in | IOT10[A] | LVCMOS18 | UP | NONE | UNKNOWN | UNKNOWN | 31/0 | nreset | in | IOT10[B] | LVCMOS18 | UP | NONE | UNKNOWN | UNKNOWN | 30/0 | rdata_wire[6] | out | IOT11[A] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 29/0 | rdata_wire[7] | out | IOT11[B] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 28/0 | UNUSED | - | IOT12[A] | - | - | - | - | - | 27/0 | UNUSED | - | IOT12[B] | - | - | - | - | - | 26/0 | UNUSED | - | IOT13[A] | - | - | - | - | - | 25/0 | rdata_wire[0] | out | IOT15[B] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 24/1 | rdata_wire[1] | out | IOR2[A] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 23/1 | UNUSED | - | IOR3[A] | - | - | - | - | - | 22/1 | UNUSED | - | IOR3[B] | - | - | - | - | - | 21/1 | UNUSED | - | IOR4[A] | - | - | - | - | - | 20/1 | UNUSED | - | IOR4[B] | - | - | - | - | - | 19/1 | UNUSED | - | IOR5[A] | - | - | - | - | - | 18/1 | rdata_wire[2] | out | IOR5[B] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 17/1 | rdata_wire[3] | out | IOR7[A] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 14/1 | rdata_wire[4] | out | IOR8[B] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN | 15/1 | UNUSED | - | IOR9[A] | - | - | - | - | - | 16/1 | key | in | IOR9[B] | LVCMOS18 | UP | NONE | UNKNOWN | UNKNOWN | 12/1 | key2 | in | IOR10[A] | LVCMOS18 | UP | NONE | UNKNOWN | UNKNOWN | 11/1 | rdata_wire[5] | out | IOR10[B] | LVCMOS18 | UP | NA | UNKNOWN | UNKNOWN

Placement and routing completed.

Memory usage: 83MB.