Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\src\FLASH608K_WB_IF.cst
Timing Constraint File | ---
GOWIN version | V1.9.2.01Beta
Part Number | GW1N-LV9LQ144C6/I5
Created Time | Tue Oct 22 17:14:42 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 1177
Numbers of Endpoints Analyzed | 1165
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 102.020(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.198 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.559
2 | 0.198 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.559
3 | 0.201 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.556
4 | 0.201 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.556
5 | 0.201 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.556
6 | 0.201 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.556
7 | 0.201 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.556
8 | 0.551 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q | i_Z[27]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.849
9 | 0.551 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q | i_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.849
10 | 0.568 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.188
11 | 0.573 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.184
12 | 0.573 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.184
13 | 0.629 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q | i_Z[26]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.771
14 | 0.735 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.022
15 | 0.735 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.022
16 | 0.735 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 9.022
17 | 0.754 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.646
18 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
19 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
20 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
21 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
22 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
23 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
24 | 0.933 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.824
25 | 0.941 | wb_reg_adr_i_Z[3]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.816

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.571 | i_Z[20]/Q | i_Z[21]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.571
2 | 0.576 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[1]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.576
3 | 0.576 | i_Z[16]/Q | i_Z[17]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.576
4 | 0.576 | i_Z[22]/Q | i_Z[23]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.576
5 | 0.582 | i_Z[23]/Q | i_Z[24]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582
6 | 0.582 | i_Z[1]/Q | i_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582
7 | 0.590 | i_Z[17]/Q | i_Z[18]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.590
8 | 0.708 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
9 | 0.708 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
10 | 0.708 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
11 | 0.709 | wb_reg_adr_i_Z[2]/Q | wb_reg_adr_i_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
12 | 0.709 | i_Z[19]/Q | i_Z[19]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
13 | 0.710 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
14 | 0.711 | wb_reg_dat_i[10]/Q | wb_reg_dat_i[10]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
15 | 0.711 | wr_reg_enable_i_Z/Q | wr_reg_enable_i_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
16 | 0.711 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
17 | 0.712 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.712
18 | 0.720 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.719
19 | 0.836 | i_Z[24]/Q | i_Z[25]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.836
20 | 0.894 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.894
21 | 0.895 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.895
22 | 0.896 | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/Q | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.896
23 | 0.906 | i_Z[5]/Q | i_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.906
24 | 0.908 | i_Z[10]/Q | i_Z[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.908
25 | 0.910 | i_Z[4]/Q | i_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.910

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[1]
2 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | key2_temp2_Z
3 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[16]
4 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[8]
5 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[19]
6 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]
7 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[11]
8 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/XADR_Z[0]
9 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/DIN_Z[1]
10 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.198
Data Arrival Time | 13.881
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.881 | 2.790 | tNET | RR | 1 | R14C4[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C4[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]
14.079 | -0.043 | tSu |  | 1 | R14C4[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.597%; route: 6.940, 72.608%; tC2Q: 0.458, 4.795%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path2

Path Summary:

Slack | 0.198
Data Arrival Time | 13.881
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.881 | 2.790 | tNET | RR | 1 | R14C4[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C4[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]
14.079 | -0.043 | tSu |  | 1 | R14C4[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.597%; route: 6.940, 72.608%; tC2Q: 0.458, 4.795%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path3

Path Summary:

Slack | 0.201
Data Arrival Time | 13.878
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.878 | 2.787 | tNET | RR | 1 | R17C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R17C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]
14.079 | -0.043 | tSu |  | 1 | R17C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[19]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.604%; route: 6.938, 72.600%; tC2Q: 0.458, 4.796%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path4

Path Summary:

Slack | 0.201
Data Arrival Time | 13.878
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.878 | 2.787 | tNET | RR | 1 | R13C4[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R13C4[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]
14.079 | -0.043 | tSu |  | 1 | R13C4[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[25]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.604%; route: 6.938, 72.600%; tC2Q: 0.458, 4.796%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path5

Path Summary:

Slack | 0.201
Data Arrival Time | 13.878
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.878 | 2.787 | tNET | RR | 1 | R16C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R16C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]
14.079 | -0.043 | tSu |  | 1 | R16C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.604%; route: 6.938, 72.600%; tC2Q: 0.458, 4.796%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path6

Path Summary:

Slack | 0.201
Data Arrival Time | 13.878
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.878 | 2.787 | tNET | RR | 1 | R17C10[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R17C10[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]
14.079 | -0.043 | tSu |  | 1 | R17C10[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.604%; route: 6.938, 72.600%; tC2Q: 0.458, 4.796%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path7

Path Summary:

Slack | 0.201
Data Arrival Time | 13.878
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.878 | 2.787 | tNET | RR | 1 | R13C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R13C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]
14.079 | -0.043 | tSu |  | 1 | R13C4[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 22.604%; route: 6.938, 72.600%; tC2Q: 0.458, 4.796%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path8

Path Summary:

Slack | 0.551
Data Arrival Time | 13.171
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]
To | i_Z[27]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q
5.918 | 1.138 | tNET | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/I3
7.017 | 1.099 | tINS | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/F
8.791 | 1.773 | tNET | FF | 1 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/I1
9.613 | 0.822 | tINS | FF | 6 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/F
12.072 | 2.459 | tNET | FF | 1 | R24C14[1][A] | i_ns_a2[27]/I2
13.171 | 1.099 | tINS | FF | 1 | R24C14[1][A] | i_ns_a2[27]/F
13.171 | 0.000 | tNET | FF | 1 | R24C14[1][A] | i_Z[27]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R24C14[1][A] | i_Z[27]/CLK
14.122 | -0.200 | tUnc |  |  |  | i_Z[27]
13.722 | -0.400 | tSu |  | 1 | R24C14[1][A] | i_Z[27]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.020, 34.129%; route: 5.370, 60.691%; tC2Q: 0.458, 5.180%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path9

Path Summary:

Slack | 0.551
Data Arrival Time | 13.171
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]
To | i_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q
5.918 | 1.138 | tNET | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/I3
7.017 | 1.099 | tINS | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/F
8.791 | 1.773 | tNET | FF | 1 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/I1
9.613 | 0.822 | tINS | FF | 6 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/F
12.072 | 2.459 | tNET | FF | 1 | R24C14[0][B] | i_ns_a2[9]/I2
13.171 | 1.099 | tINS | FF | 1 | R24C14[0][B] | i_ns_a2[9]/F
13.171 | 0.000 | tNET | FF | 1 | R24C14[0][B] | i_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R24C14[0][B] | i_Z[9]/CLK
14.122 | -0.200 | tUnc |  |  |  | i_Z[9]
13.722 | -0.400 | tSu |  | 1 | R24C14[0][B] | i_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.020, 34.129%; route: 5.370, 60.691%; tC2Q: 0.458, 5.180%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path10

Path Summary:

Slack | 0.568
Data Arrival Time | 13.510
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.510 | 2.419 | tNET | RR | 1 | R16C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R16C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]
14.079 | -0.043 | tSu |  | 1 | R16C10[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[16]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.508%; route: 6.570, 71.504%; tC2Q: 0.458, 4.988%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path11

Path Summary:

Slack | 0.573
Data Arrival Time | 13.506
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.506 | 2.415 | tNET | RR | 1 | R14C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]
14.079 | -0.043 | tSu |  | 1 | R14C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[24]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.520%; route: 6.565, 71.489%; tC2Q: 0.458, 4.991%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path12

Path Summary:

Slack | 0.573
Data Arrival Time | 13.506
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.506 | 2.415 | tNET | RR | 1 | R14C5[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C5[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]
14.079 | -0.043 | tSu |  | 1 | R14C5[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.520%; route: 6.565, 71.489%; tC2Q: 0.458, 4.991%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path13

Path Summary:

Slack | 0.629
Data Arrival Time | 13.093
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]
To | i_Z[26]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R11C6[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[23]/Q
5.918 | 1.138 | tNET | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/I3
7.017 | 1.099 | tINS | FF | 1 | R9C5[1][B] | i_ns_i_a2_1_21_cZ[8]/F
8.791 | 1.773 | tNET | FF | 1 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/I1
9.613 | 0.822 | tINS | FF | 6 | R12C8[0][B] | i_ns_i_a2_1_29_cZ[8]/F
12.061 | 2.448 | tNET | FF | 1 | R24C14[1][B] | N_272_i_cZ/I3
13.093 | 1.032 | tINS | FF | 1 | R24C14[1][B] | N_272_i_cZ/F
13.093 | 0.000 | tNET | FF | 1 | R24C14[1][B] | i_Z[26]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R24C14[1][B] | i_Z[26]/CLK
14.122 | -0.200 | tUnc |  |  |  | i_Z[26]
13.722 | -0.400 | tSu |  | 1 | R24C14[1][B] | i_Z[26]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.953, 33.668%; route: 5.360, 61.107%; tC2Q: 0.458, 5.226%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path14

Path Summary:

Slack | 0.735
Data Arrival Time | 13.344
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.344 | 2.253 | tNET | RR | 1 | R18C5[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C5[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]
14.079 | -0.043 | tSu |  | 1 | R18C5[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[26]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.942%; route: 6.403, 70.977%; tC2Q: 0.458, 5.080%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path15

Path Summary:

Slack | 0.735
Data Arrival Time | 13.344
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.344 | 2.253 | tNET | RR | 1 | R18C5[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C5[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]
14.079 | -0.043 | tSu |  | 1 | R18C5[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.942%; route: 6.403, 70.977%; tC2Q: 0.458, 5.080%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path16

Path Summary:

Slack | 0.735
Data Arrival Time | 13.344
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.344 | 2.253 | tNET | RR | 1 | R18C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]
14.079 | -0.043 | tSu |  | 1 | R18C5[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 23.942%; route: 6.403, 70.977%; tC2Q: 0.458, 5.080%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path17

Path Summary:

Slack | 0.754
Data Arrival Time | 12.967
Data Required Time | 13.722
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
9.825 | 1.822 | tNET | FF | 1 | R13C5[3][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o_9_0_iv_0_cZ[4]/I0
10.647 | 0.822 | tINS | FF | 1 | R13C5[3][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o_9_0_iv_0_cZ[4]/F
11.935 | 1.289 | tNET | FF | 1 | R11C6[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o_9_0_iv_2[4]/I0
12.967 | 1.032 | tINS | FF | 1 | R11C6[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o_9_0_iv_2[4]/F
12.967 | 0.000 | tNET | FF | 1 | R11C6[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R11C6[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]
13.722 | -0.400 | tSu |  | 1 | R11C6[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.953, 34.156%; route: 5.234, 60.542%; tC2Q: 0.458, 5.301%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path18

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R13C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R13C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]
14.079 | -0.043 | tSu |  | 1 | R13C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[31]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path19

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R13C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R13C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]
14.079 | -0.043 | tSu |  | 1 | R13C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[30]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path20

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R14C8[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C8[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]
14.079 | -0.043 | tSu |  | 1 | R14C8[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[23]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path21

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R14C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]
14.079 | -0.043 | tSu |  | 1 | R14C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path22

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R14C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]
14.079 | -0.043 | tSu |  | 1 | R14C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path23

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R13C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R13C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]
14.079 | -0.043 | tSu |  | 1 | R13C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[27]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path24

Path Summary:

Slack | 0.933
Data Arrival Time | 13.145
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.145 | 2.055 | tNET | RR | 1 | R14C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R14C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]
14.079 | -0.043 | tSu |  | 1 | R14C8[0][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.480%; route: 6.205, 70.325%; tC2Q: 0.458, 5.194%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path25

Path Summary:

Slack | 0.941
Data Arrival Time | 13.138
Data Required Time | 14.079
From | wb_reg_adr_i_Z[3]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][B] | wb_reg_adr_i_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 8 | R24C7[0][B] | wb_reg_adr_i_Z[3]/Q
6.903 | 2.123 | tNET | FF | 1 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/I1
8.002 | 1.099 | tINS | FF | 33 | R12C5[3][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/wb_dat_o23_i_o3/F
10.030 | 2.027 | tNET | FF | 1 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/I0
11.091 | 1.061 | tINS | FR | 32 | R22C8[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_1_sqmuxa_cZ/F
13.138 | 2.047 | tNET | RR | 1 | R17C7[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R17C7[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]
14.079 | -0.043 | tSu |  | 1 | R17C7[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[29]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.160, 24.500%; route: 6.198, 70.301%; tC2Q: 0.458, 5.199%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.571
Data Arrival Time | 3.911
Data Required Time | 3.340
From | i_Z[20]
To | i_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C10[0][B] | i_Z[20]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R24C10[0][B] | i_Z[20]/Q
3.911 | 0.238 | tNET | RR | 1 | R24C10[0][A] | i_Z[21]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C10[0][A] | i_Z[21]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[21]
3.340 | 0.000 | tHld |  | 1 | R24C10[0][A] | i_Z[21]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path2

Path Summary:

Slack | 0.576
Data Arrival Time | 3.916
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[1]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R18C9[1][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[1]/Q
3.916 | 0.243 | tNET | RR | 1 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]
3.340 | 0.000 | tHld |  | 1 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path3

Path Summary:

Slack | 0.576
Data Arrival Time | 3.916
Data Required Time | 3.340
From | i_Z[16]
To | i_Z[17]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[1][A] | i_Z[16]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R24C13[1][A] | i_Z[16]/Q
3.916 | 0.243 | tNET | RR | 1 | R24C13[0][A] | i_Z[17]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[0][A] | i_Z[17]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[17]
3.340 | 0.000 | tHld |  | 1 | R24C13[0][A] | i_Z[17]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path4

Path Summary:

Slack | 0.576
Data Arrival Time | 3.916
Data Required Time | 3.340
From | i_Z[22]
To | i_Z[23]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[0][A] | i_Z[22]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R23C11[0][A] | i_Z[22]/Q
3.916 | 0.243 | tNET | RR | 1 | R23C11[1][A] | i_Z[23]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[1][A] | i_Z[23]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[23]
3.340 | 0.000 | tHld |  | 1 | R23C11[1][A] | i_Z[23]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path5

Path Summary:

Slack | 0.582
Data Arrival Time | 3.922
Data Required Time | 3.340
From | i_Z[23]
To | i_Z[24]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[1][A] | i_Z[23]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R23C11[1][A] | i_Z[23]/Q
3.922 | 0.249 | tNET | RR | 1 | R23C11[2][B] | i_Z[24]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[2][B] | i_Z[24]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[24]
3.340 | 0.000 | tHld |  | 1 | R23C11[2][B] | i_Z[24]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 42.741%; tC2Q: 0.333, 57.259%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path6

Path Summary:

Slack | 0.582
Data Arrival Time | 3.922
Data Required Time | 3.340
From | i_Z[1]
To | i_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[0][B] | i_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R23C11[0][B] | i_Z[1]/Q
3.922 | 0.249 | tNET | RR | 1 | R23C11[2][A] | i_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[2][A] | i_Z[2]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[2]
3.340 | 0.000 | tHld |  | 1 | R23C11[2][A] | i_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 42.741%; tC2Q: 0.333, 57.259%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path7

Path Summary:

Slack | 0.590
Data Arrival Time | 3.930
Data Required Time | 3.340
From | i_Z[17]
To | i_Z[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[0][A] | i_Z[17]/CLK
3.674 | 0.333 | tC2Q | RR | 5 | R24C13[0][A] | i_Z[17]/Q
3.930 | 0.256 | tNET | RR | 1 | R24C13[1][B] | i_Z[18]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[1][B] | i_Z[18]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[18]
3.340 | 0.000 | tHld |  | 1 | R24C13[1][B] | i_Z[18]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.256, 43.459%; tC2Q: 0.333, 56.541%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path8

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/Q
3.676 | 0.002 | tNET | RR | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[0]/I2
4.048 | 0.372 | tINS | RF | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[0]/F
4.048 | 0.000 | tNET | FF | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]
3.340 | 0.000 | tHld |  | 1 | R16C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path9

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/Q
3.676 | 0.002 | tNET | RR | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m111/I2
4.048 | 0.372 | tINS | RF | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m111/F
4.048 | 0.000 | tNET | FF | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
3.340 | 0.000 | tHld |  | 1 | R18C11[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path10

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/Q
3.676 | 0.002 | tNET | RR | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m45/I2
4.048 | 0.372 | tINS | RF | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m45/F
4.048 | 0.000 | tNET | FF | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]
3.340 | 0.000 | tHld |  | 1 | R9C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path11

Path Summary:

Slack | 0.709
Data Arrival Time | 4.049
Data Required Time | 3.340
From | wb_reg_adr_i_Z[2]
To | wb_reg_adr_i_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C7[0][A] | wb_reg_adr_i_Z[2]/CLK
3.674 | 0.333 | tC2Q | RR | 8 | R24C7[0][A] | wb_reg_adr_i_Z[2]/Q
3.677 | 0.004 | tNET | RR | 1 | R24C7[0][A] | wb_reg_adr_ie[2]/I2
4.049 | 0.372 | tINS | RF | 1 | R24C7[0][A] | wb_reg_adr_ie[2]/F
4.049 | 0.000 | tNET | FF | 1 | R24C7[0][A] | wb_reg_adr_i_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C7[0][A] | wb_reg_adr_i_Z[2]/CLK
3.340 | 0.000 | tUnc |  |  |  | wb_reg_adr_i_Z[2]
3.340 | 0.000 | tHld |  | 1 | R24C7[0][A] | wb_reg_adr_i_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path12

Path Summary:

Slack | 0.709
Data Arrival Time | 4.049
Data Required Time | 3.340
From | i_Z[19]
To | i_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C11[0][A] | i_Z[19]/CLK
3.674 | 0.333 | tC2Q | RR | 6 | R24C11[0][A] | i_Z[19]/Q
3.677 | 0.004 | tNET | RR | 1 | R24C11[0][A] | N_260_i_cZ/I1
4.049 | 0.372 | tINS | RF | 1 | R24C11[0][A] | N_260_i_cZ/F
4.049 | 0.000 | tNET | FF | 1 | R24C11[0][A] | i_Z[19]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C11[0][A] | i_Z[19]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[19]
3.340 | 0.000 | tHld |  | 1 | R24C11[0][A] | i_Z[19]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path13

Path Summary:

Slack | 0.710
Data Arrival Time | 4.050
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/CLK
3.674 | 0.333 | tC2Q | RR | 12 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/Q
3.678 | 0.005 | tNET | RR | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m124/I3
4.050 | 0.372 | tINS | RF | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m124/F
4.050 | 0.000 | tNET | FF | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
3.340 | 0.000 | tHld |  | 1 | R18C8[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path14

Path Summary:

Slack | 0.711
Data Arrival Time | 4.052
Data Required Time | 3.340
From | wb_reg_dat_i[10]
To | wb_reg_dat_i[10]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C8[0][A] | wb_reg_dat_i[10]/CLK
3.674 | 0.333 | tC2Q | RR | 14 | R24C8[0][A] | wb_reg_dat_i[10]/Q
3.680 | 0.006 | tNET | RR | 1 | R24C8[0][A] | g0/I3
4.052 | 0.372 | tINS | RF | 1 | R24C8[0][A] | g0/F
4.052 | 0.000 | tNET | FF | 1 | R24C8[0][A] | wb_reg_dat_i[10]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C8[0][A] | wb_reg_dat_i[10]/CLK
3.340 | 0.000 | tUnc |  |  |  | wb_reg_dat_i[10]
3.340 | 0.000 | tHld |  | 1 | R24C8[0][A] | wb_reg_dat_i[10]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path15

Path Summary:

Slack | 0.711
Data Arrival Time | 4.052
Data Required Time | 3.340
From | wr_reg_enable_i_Z
To | wr_reg_enable_i_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C8[1][A] | wr_reg_enable_i_Z/CLK
3.674 | 0.333 | tC2Q | RR | 7 | R24C8[1][A] | wr_reg_enable_i_Z/Q
3.680 | 0.006 | tNET | RR | 1 | R24C8[1][A] | wr_reg_enable_ie/I3
4.052 | 0.372 | tINS | RF | 1 | R24C8[1][A] | wr_reg_enable_ie/F
4.052 | 0.000 | tNET | FF | 1 | R24C8[1][A] | wr_reg_enable_i_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C8[1][A] | wr_reg_enable_i_Z/CLK
3.340 | 0.000 | tUnc |  |  |  | wr_reg_enable_i_Z
3.340 | 0.000 | tHld |  | 1 | R24C8[1][A] | wr_reg_enable_i_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path16

Path Summary:

Slack | 0.711
Data Arrival Time | 4.052
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/CLK
3.674 | 0.333 | tC2Q | RR | 21 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/Q
3.680 | 0.006 | tNET | RR | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_161_mux_i/I1
4.052 | 0.372 | tINS | RF | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_161_mux_i/F
4.052 | 0.000 | tNET | FF | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
3.340 | 0.000 | tHld |  | 1 | R12C9[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path17

Path Summary:

Slack | 0.712
Data Arrival Time | 4.053
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 17 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/Q
3.681 | 0.007 | tNET | RR | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_ns_cZ[1]/I3
4.053 | 0.372 | tINS | RF | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_ns_cZ[1]/F
4.053 | 0.000 | tNET | FF | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]
3.340 | 0.000 | tHld |  | 1 | R8C5[1][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/state_UFM_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path18

Path Summary:

Slack | 0.720
Data Arrival Time | 4.060
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/CLK
3.674 | 0.333 | tC2Q | RR | 60 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/Q
3.688 | 0.014 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_162_mux_i_cZ/I2
4.060 | 0.372 | tINS | RF | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_162_mux_i_cZ/F
4.060 | 0.000 | tNET | FF | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]
3.340 | 0.000 | tHld |  | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 51.703%; route: 0.014, 1.969%; tC2Q: 0.333, 46.328%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path19

Path Summary:

Slack | 0.836
Data Arrival Time | 4.176
Data Required Time | 3.340
From | i_Z[24]
To | i_Z[25]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C11[2][B] | i_Z[24]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R23C11[2][B] | i_Z[24]/Q
4.176 | 0.503 | tNET | RR | 1 | R24C11[2][A] | i_Z[25]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C11[2][A] | i_Z[25]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[25]
3.340 | 0.000 | tHld |  | 1 | R24C11[2][A] | i_Z[25]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.503, 60.120%; tC2Q: 0.333, 39.880%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path20

Path Summary:

Slack | 0.894
Data Arrival Time | 4.234
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/CLK
3.674 | 0.333 | tC2Q | RR | 4 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/Q
3.678 | 0.005 | tNET | RR | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[4]/I3
4.234 | 0.556 | tINS | RR | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[4]/F
4.234 | 0.000 | tNET | RR | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]
3.340 | 0.000 | tHld |  | 1 | R16C13[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path21

Path Summary:

Slack | 0.895
Data Arrival Time | 4.236
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/CLK
3.674 | 0.333 | tC2Q | RR | 12 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/Q
3.680 | 0.006 | tNET | RR | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_180_mux_i/I1
4.236 | 0.556 | tINS | RR | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/N_180_mux_i/F
4.236 | 0.000 | tNET | RR | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
3.340 | 0.000 | tHld |  | 1 | R12C9[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path22

Path Summary:

Slack | 0.896
Data Arrival Time | 4.237
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]
To | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/CLK
3.674 | 0.333 | tC2Q | RR | 14 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/Q
3.681 | 0.007 | tNET | RR | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m120/I3
4.237 | 0.556 | tINS | RR | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/m120/F
4.237 | 0.000 | tNET | RR | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]
3.340 | 0.000 | tHld |  | 1 | R18C8[2][A] | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.025%; route: 0.007, 0.790%; tC2Q: 0.333, 37.185%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path23

Path Summary:

Slack | 0.906
Data Arrival Time | 4.246
Data Required Time | 3.340
From | i_Z[5]
To | i_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[2][A] | i_Z[5]/CLK
3.674 | 0.333 | tC2Q | RR | 5 | R24C13[2][A] | i_Z[5]/Q
4.246 | 0.573 | tNET | RR | 1 | R24C12[1][A] | i_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C12[1][A] | i_Z[6]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[6]
3.340 | 0.000 | tHld |  | 1 | R24C12[1][A] | i_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.573, 63.212%; tC2Q: 0.333, 36.788%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path24

Path Summary:

Slack | 0.908
Data Arrival Time | 4.248
Data Required Time | 3.340
From | i_Z[10]
To | i_Z[11]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[2][B] | i_Z[10]/CLK
3.674 | 0.333 | tC2Q | RR | 5 | R24C13[2][B] | i_Z[10]/Q
4.248 | 0.574 | tNET | RR | 1 | R23C12[0][A] | i_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R23C12[0][A] | i_Z[11]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[11]
3.340 | 0.000 | tHld |  | 1 | R23C12[0][A] | i_Z[11]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 63.282%; tC2Q: 0.333, 36.718%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path25

Path Summary:

Slack | 0.910
Data Arrival Time | 4.250
Data Required Time | 3.340
From | i_Z[4]
To | i_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C12[0][B] | i_Z[4]/CLK
3.674 | 0.333 | tC2Q | RR | 5 | R24C12[0][B] | i_Z[4]/Q
4.250 | 0.576 | tNET | RR | 1 | R24C13[2][A] | i_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 509 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R24C13[2][A] | i_Z[5]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[5]
3.340 | 0.000 | tHld |  | 1 | R24C13[2][A] | i_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.576, 63.363%; tC2Q: 0.333, 36.637%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[1]/CLK

### MPW2

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | key2_temp2_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | key2_temp2_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | key2_temp2_Z/CLK

### MPW3

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[16]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[16]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[16]/CLK

### MPW4

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[8]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[8]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[8]/CLK

### MPW5

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[19]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[19]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[19]/CLK

### MPW6

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wdata_Z[3]/CLK

### MPW7

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[11]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[11]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/wb_dat_o_Z[11]/CLK

### MPW8

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/XADR_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/XADR_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/XADR_Z[0]/CLK

### MPW9

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/DIN_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/DIN_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/DIN_Z[1]/CLK

### MPW10

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_RD_UFM/r_state[4]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
509 | clk_c | 0.198 | 3.631
60 | w_state[8] | 6.003 | 1.840
52 | w_state[9] | 6.347 | 1.525
51 | cr[0] | 4.423 | 2.164
51 | cr[1] | 4.603 | 2.024
50 | state_UFM[2] | 2.788 | 3.465
50 | w_state[0] | 6.334 | 1.508
47 | N_64_i | 5.809 | 2.349
35 | state_UFM[5] | 4.718 | 2.806
33 | N_27 | 0.198 | 2.518

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R12C5 | 0.639
R18C9 | 0.583
R12C6 | 0.542
R16C8 | 0.514
R15C6 | 0.500
R16C5 | 0.500
R8C13 | 0.486
R18C8 | 0.486
R14C5 | 0.472
R16C6 | 0.458

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---