
`timescale 1ns / 10ps

module tb
(
    input       wire        clk,
    input       wire        rstn,
    input       wire        key1,
    input       wire        key2,
    output      wire  [31:0] wb_data_o
);

wire[31:0] wb_wire_dat_o;
assign wb_data_o = wb_wire_dat_o;

reg key1_temp1,key1_temp2;
reg key2_temp1,key2_temp2;
always @(posedge clk or negedge rstn)
begin
    if(~rstn)
    begin
        key1_temp1 <= 1'b0;
        key1_temp2 <= 1'b0;

        key2_temp1 <= 1'b0;
        key2_temp2 <= 1'b0;
    end
    else
    begin
        key1_temp1 <= key1;
        key1_temp2 <= key1_temp1; 

        key2_temp1 <= key2;
        key2_temp2 <= key2_temp1;  
    end 
end

assign key_write = ~key1_temp1 &key1_temp2;
assign key_read  = ~key2_temp1 &key2_temp2;

reg [7:0]  i;
reg [4:0]  wb_reg_adr_i;
reg [31:0] wb_reg_dat_i;
reg        wr_reg_enable_i;

always @(posedge clk or negedge rstn)
begin
    if(~rstn)
    begin
        //i <= 8'd22;
        i <= 8'd0;
        wb_reg_adr_i <= 5'b0;
        wb_reg_dat_i <= 32'h0;
        wr_reg_enable_i <= 1'b0;
    end
    else
    begin
        case (i)
            8'd0://Erase the 0 page step
            begin
                if(key_write)
                begin
                    wb_reg_adr_i <= 5'b0;//Select the xaddress
                    wr_reg_enable_i <= 1'b1;//write to wishbone bus
                    wb_reg_dat_i <= 32'b0;//write data to bus
                    i <= i + 1'b1;
                end
                else if(key_read)
                begin
                    i <= 8'd22;
                end
            end
            8'd1:
            begin
                wb_reg_adr_i <= 5'h04;//Select the yaddress
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;
                i <= i + 1'b1;
            end
            8'd2:
            begin
                wb_reg_adr_i <= 5'h10;//Select the cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h2; //Erase cmd to wishbone bus
                i <= i + 1'b1;
            end
            8'd3:
            begin
                wb_reg_adr_i <= 5'h14;//Select the start cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h1; //Erase cmd to wishbone bus
                i <= i + 1'b1;
            end
            8'd4:
            begin
                wr_reg_enable_i <= 1'b0;
                i <= i + 1'b1;
            end
            8'd5://Read status
            begin
                wb_reg_adr_i <= 5'h18;
                i <= i + 1'b1;
            end
            8'd6://Read status
            begin
                i <= i + 1'b1;
            end
            8'd7://Read status
            begin
                i <= i + 1'b1;
            end
            8'd8:
            begin
                if(wb_wire_dat_o == 32'h01) //Done signal
                i <= i + 1'b1;
            end
			8'd9://Clear the Status
			begin
                wb_reg_adr_i <= 5'h18;//Select the sr register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;//write data to sr register
                i <= i + 1'b1;
			end
			8'd10:
			begin
				wr_reg_enable_i <= 1'b0;
				i <= i + 1'b1;
			end
			
			
			
			8'd11://Write data to Flash step
			begin
                wb_reg_adr_i <= 5'b0;//Select the xaddress
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;//write data to bus
                i <= i + 1'b1;
			end
			8'd12:
			begin
                wb_reg_adr_i <= 5'h04;//Select the yaddress
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;
                i <= i + 1'b1;
			end
			8'd13:
			begin
				wb_reg_adr_i <= 5'h0C;//Select the wdata register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'hFEFFFFF;
                i <= i + 1'b1;
			end
			8'd14:
			begin
                wb_reg_adr_i <= 5'h10;//Select the cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h1; //Write cmd to wishbone bus
                i <= i + 1'b1;
			end
			8'd15:
			begin
                wb_reg_adr_i <= 5'h14;//Select the start cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h1; //Erase cmd to wishbone bus
                i <= i + 1'b1;
			end
			8'd16:
			begin
                wr_reg_enable_i <= 1'b0;
				 wb_reg_dat_i <= 32'h0;
                i <= i + 1'b1;
			end
			8'd17:
			begin
                wb_reg_adr_i <= 5'h18;
                i <= i + 1'b1;
			end
			8'd18:
			begin
                i <= i + 1'b1;
			end
			8'd19:
			begin
                if(wb_wire_dat_o == 32'h01) //Done signal
                i <= i + 1'b1;
			end
			8'd20://Clear the Status
			begin
                wb_reg_adr_i <= 5'h18;//Select the sr register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;//write data to sr register
                i <= i + 1'b1;
			end
			8'd21:
			begin
				wr_reg_enable_i <= 1'b0;
				//i <= i + 1'b1;
                i <= 8'd0;
			end
			
			
			8'd22://Read data from Flash step
			begin
                wb_reg_adr_i <= 5'b0;//Select the xaddress
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;//write data to bus
                i <= i + 1'b1;
			end
			8'd23:
			begin
                wb_reg_adr_i <= 5'h04;//Select the yaddress
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;
                i <= i + 1'b1;
			end
			8'd24:
			begin
                wb_reg_adr_i <= 5'h10;//Select the cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h0; //Read cmd to wishbone bus
                i <= i + 1'b1;
			end
			8'd25:
			begin
                wb_reg_adr_i <= 5'h14;//Select the start cmd register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'h1; //Start cmd to wishbone bus
                i <= i + 1'b1;
			end
			8'd26:
			begin
                wb_reg_adr_i <= 5'h18;
                if(wb_wire_dat_o == 32'h01) //Done signal
                i <= i + 1'b1;
			end
			8'd27://Clear the Status
			begin
                wb_reg_adr_i <= 5'h18;//Select the sr register
                wr_reg_enable_i <= 1'b1;//write to wishbone bus
                wb_reg_dat_i <= 32'b0;//write data to sr register
                i <= i + 1'b1;
			end
			8'd28:
			begin
				wr_reg_enable_i <= 1'b0;
				wb_reg_adr_i <= 5'h08;
				i <= 8'd0;
			end
				
        endcase
    end
end

Gowin_Flash_Controller_Top flash_controller_inst
(
                .wb_clk_i(clk),// master clock input
                .wb_rst_i(~rstn),// synchronous active high reset
                .wb_addr_i(wb_reg_adr_i),// lower address bits
                .wb_data_i(wb_reg_dat_i),// databus input
                .wb_data_o(wb_wire_dat_o),// databus output
                .wb_we_i(wr_reg_enable_i), // write enable input
                .wb_stb_i(1'b1),// stobe/core select signal
                .wb_cyc_i(1'b1),// valid bus cycle input
                .wb_ack_o()// bus cycle acknowledge output
);

endmodule