#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-059

# Tue Oct 22 17:05:20 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\Gowin_PLL.v" (library work)
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v" (library work)
@I::"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\gowin_flash_controller\gowin_flash_controller.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module tb
@N: CG364 :"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v":1800:7:1800:9|Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\Gowin_PLL.v":9:7:9:15|Synthesizing module Gowin_PLL in library work.
Running optimization stage 1 on Gowin_PLL .......
@N: CG364 :"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v":1864:7:1864:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
@N: CG364 :"D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro\lib\generic\gw1n.v":375:7:375:10|Synthesizing module TBUF in library work.
Running optimization stage 1 on TBUF .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on Flash_ctroller_96K .......
Running optimization stage 1 on FLASH96K .......
Running optimization stage 1 on GW_USER_FLASH_96K .......
Running optimization stage 1 on User_Flash_Ctroller_Top_96K .......
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":4374:7:4374:32|Synthesizing module Gowin_Flash_Controller_Top in library work.
Running optimization stage 1 on Gowin_Flash_Controller_Top .......
@N: CG364 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":2:7:2:8|Synthesizing module tb in library work.
@N: CG179 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":154:38:154:44|Removing redundant assignment.
Running optimization stage 1 on tb .......
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Optimizing register bit reg_page_address[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Optimizing register bit reg_page_address[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Optimizing register bit reg_page_address[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Optimizing register bit reg_page_address[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Optimizing register bit reg_page_address[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Pruning register bits 5 to 1 of reg_page_address[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on tb .......
@N: CL201 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":63:0:63:5|Trying to extract state machine for register i.
Extracted state machine for register i
State machine has 6 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000110
@W: CL156 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":162:14:162:20|*Input clk_10m to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\tb.v":163:17:163:27|*Input clk_10m_p90 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on Gowin_Flash_Controller_Top .......
@N: CL159 :"C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\src\gowin_flash_controller\gowin_flash_controller.v":4389:6:4389:12|Input clk_sys is unused.
Running optimization stage 2 on User_Flash_Ctroller_Top_96K .......
Running optimization stage 2 on GW_USER_FLASH_96K .......
Running optimization stage 2 on FLASH96K .......
Running optimization stage 2 on Flash_ctroller_96K .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on TBUF .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on Gowin_PLL .......
Running optimization stage 2 on PLL .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 94MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:05:22 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:05:22 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\synwork\FLASH96K_REG_IF_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 19MB peak: 19MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:05:22 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
File C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\synwork\FLASH96K_REG_IF_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct 22 17:05:24 2019

###########################################################]
# Tue Oct 22 17:05:24 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\FLASH96K_REG_IF_scck.rpt 
Printing clock  summary report in "C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\FLASH96K_REG_IF_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)

@N: BN362 :"c:\users\qinfei\desktop\gowin_flash_controller\flash96k_reg_if\project\src\tb.v":63:0:63:5|Removing sequential instance i[5:0] (in view: work.tb(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 221MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)



Clock Summary
******************

          Start          Requested     Requested     Clock        Clock                     Clock
Level     Clock          Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------
0 -       System         100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                                 
0 -       tb|clk_sys     283.2 MHz     3.532         inferred     Autoconstr_clkgroup_0     8    
=================================================================================================



Clock Load Summary
***********************

               Clock     Source            Clock Pin          Non-clock Pin     Non-clock Pin
Clock          Load      Pin               Seq Example        Seq Example       Comb Example 
---------------------------------------------------------------------------------------------
System         0         -                 -                  -                 -            
                                                                                             
tb|clk_sys     8         clk_sys(port)     rst_cnt[7:0].C     -                 -            
=============================================================================================

@W: MT529 :"c:\users\qinfei\desktop\gowin_flash_controller\flash96k_reg_if\project\src\tb.v":147:0:147:5|Found inferred clock tb|clk_sys which controls 8 sequential elements including rst_cnt[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk_sys             port                   8          rst_cnt[7:0]   
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\FLASH96K_REG_IF.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 223MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 22 17:05:26 2019

###########################################################]
# Tue Oct 22 17:05:26 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 217MB peak: 217MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

@N: MO231 :"c:\users\qinfei\desktop\gowin_flash_controller\flash96k_reg_if\project\src\tb.v":147:0:147:5|Found counter in view:work.tb(verilog) instance rst_cnt[7:0] 

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.58ns		 230 /         8
   2		0h:00m:01s		    -1.58ns		 230 /         8

   3		0h:00m:01s		    -1.58ns		 230 /         8


   4		0h:00m:01s		    -1.58ns		 232 /         8

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 224MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 225MB)

Writing Analyst data base C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH96K_REG_IF\project\impl\synthesize\rev_1\synwork\FLASH96K_REG_IF_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 226MB peak: 226MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 226MB peak: 226MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 224MB peak: 226MB)

@W: MT246 :"c:\users\qinfei\desktop\gowin_flash_controller\flash96k_reg_if\project\src\gowin_flash_controller\gowin_flash_controller.v":4248:11:4248:20|Blackbox FLASH96K is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\users\qinfei\desktop\gowin_flash_controller\flash96k_reg_if\project\src\gowin_pll.v":24:4:24:11|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock tb|clk_sys with period 4.68ns. Please declare a user-defined clock on port clk_sys.


##### START OF TIMING REPORT #####[
# Timing report written on Tue Oct 22 17:05:30 2019
#


Top view:               tb
Requested Frequency:    213.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.826

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
tb|clk_sys         213.7 MHz     181.7 MHz     4.678         5.504         -0.826     inferred     Autoconstr_clkgroup_0
System             100.0 MHz     133.2 MHz     10.000        7.508         2.493      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------
Starting    Ending      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------
System      tb|clk_sys  |  4.678       2.493   |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk_sys  System      |  4.678       -0.694  |  No paths    -      |  No paths    -      |  No paths    -    
tb|clk_sys  tb|clk_sys  |  4.678       -0.826  |  No paths    -      |  No paths    -      |  No paths    -    
===============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: tb|clk_sys
====================================



Starting Points with Worst Slack
********************************

               Starting                                       Arrival           
Instance       Reference      Type     Pin     Net            Time        Slack 
               Clock                                                            
--------------------------------------------------------------------------------
rst_cnt[0]     tb|clk_sys     DFFC     Q       rst_cnt[0]     0.367       -0.826
rst_cnt[1]     tb|clk_sys     DFFC     Q       rst_cnt[1]     0.367       -0.769
rst_cnt[2]     tb|clk_sys     DFFC     Q       rst_cnt[2]     0.367       -0.712
rst_cnt[6]     tb|clk_sys     DFFC     Q       rst_cnt[6]     0.367       -0.694
rst_cnt[3]     tb|clk_sys     DFFC     Q       rst_cnt[3]     0.367       -0.655
rst_cnt[5]     tb|clk_sys     DFFC     Q       rst_cnt[5]     0.367       -0.627
rst_cnt[4]     tb|clk_sys     DFFC     Q       rst_cnt[4]     0.367       -0.598
rst_cnt[7]     tb|clk_sys     DFFC     Q       rst_cnt[7]     0.367       -0.417
================================================================================


Ending Points with Worst Slack
******************************

                                                                                                   Starting                                          Required           
Instance                                                                                           Reference      Type     Pin     Net               Time         Slack 
                                                                                                   Clock                                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
rst_cnt[7]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[7]     4.545        -0.826
rst_cnt[6]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[6]     4.545        -0.769
rst_cnt[5]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[5]     4.545        -0.712
u_gowin_flash_controller_top.u_User_Flash_Ctroller_Top_96K.u_Flash_ctroller_96K.rst_n_dly_i_cZ     tb|clk_sys     INV      I       rst_n_dly         4.678        -0.694
rst_cnt[4]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[4]     4.545        -0.655
rst_cnt[3]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[3]     4.545        -0.598
rst_cnt[2]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[2]     4.545        -0.541
rst_cnt[1]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[1]     4.545        -0.484
rst_cnt[0]                                                                                         tb|clk_sys     DFFC     D       rst_cnt_lm[0]     4.545        0.043 
========================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      5.371
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.826

    Number of logic level(s):                9
    Starting point:                          rst_cnt[0] / Q
    Ending point:                            rst_cnt[7] / D
    The start point is clocked by            tb|clk_sys [rising] on pin CLK
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_cnt[0]           DFFC     Q        Out     0.367     0.367       -         
rst_cnt[0]           Net      -        -       1.021     -           3         
rst_cnt_cry_0[0]     ALU      I0       In      -         1.388       -         
rst_cnt_cry_0[0]     ALU      COUT     Out     0.958     2.346       -         
rst_cnt_cry[0]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[1]     ALU      CIN      In      -         2.346       -         
rst_cnt_cry_0[1]     ALU      COUT     Out     0.057     2.403       -         
rst_cnt_cry[1]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[2]     ALU      CIN      In      -         2.403       -         
rst_cnt_cry_0[2]     ALU      COUT     Out     0.057     2.460       -         
rst_cnt_cry[2]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[3]     ALU      CIN      In      -         2.460       -         
rst_cnt_cry_0[3]     ALU      COUT     Out     0.057     2.517       -         
rst_cnt_cry[3]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[4]     ALU      CIN      In      -         2.517       -         
rst_cnt_cry_0[4]     ALU      COUT     Out     0.057     2.574       -         
rst_cnt_cry[4]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[5]     ALU      CIN      In      -         2.574       -         
rst_cnt_cry_0[5]     ALU      COUT     Out     0.057     2.631       -         
rst_cnt_cry[5]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[6]     ALU      CIN      In      -         2.631       -         
rst_cnt_cry_0[6]     ALU      COUT     Out     0.057     2.688       -         
rst_cnt_cry[6]       Net      -        -       0.000     -           1         
rst_cnt_s_0[7]       ALU      CIN      In      -         2.688       -         
rst_cnt_s_0[7]       ALU      SUM      Out     0.563     3.251       -         
rst_cnt_s[7]         Net      -        -       1.021     -           1         
rst_cnt_lm_0[7]      LUT4     I1       In      -         4.272       -         
rst_cnt_lm_0[7]      LUT4     F        Out     1.099     5.371       -         
rst_cnt_lm[7]        Net      -        -       0.000     -           1         
rst_cnt[7]           DFFC     D        In      -         5.371       -         
===============================================================================
Total path delay (propagation time + setup) of 5.504 is 3.462(62.9%) logic and 2.042(37.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      5.314
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.769

    Number of logic level(s):                8
    Starting point:                          rst_cnt[1] / Q
    Ending point:                            rst_cnt[7] / D
    The start point is clocked by            tb|clk_sys [rising] on pin CLK
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_cnt[1]           DFFC     Q        Out     0.367     0.367       -         
rst_cnt[1]           Net      -        -       1.021     -           3         
rst_cnt_cry_0[1]     ALU      I0       In      -         1.388       -         
rst_cnt_cry_0[1]     ALU      COUT     Out     0.958     2.346       -         
rst_cnt_cry[1]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[2]     ALU      CIN      In      -         2.346       -         
rst_cnt_cry_0[2]     ALU      COUT     Out     0.057     2.403       -         
rst_cnt_cry[2]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[3]     ALU      CIN      In      -         2.403       -         
rst_cnt_cry_0[3]     ALU      COUT     Out     0.057     2.460       -         
rst_cnt_cry[3]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[4]     ALU      CIN      In      -         2.460       -         
rst_cnt_cry_0[4]     ALU      COUT     Out     0.057     2.517       -         
rst_cnt_cry[4]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[5]     ALU      CIN      In      -         2.517       -         
rst_cnt_cry_0[5]     ALU      COUT     Out     0.057     2.574       -         
rst_cnt_cry[5]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[6]     ALU      CIN      In      -         2.574       -         
rst_cnt_cry_0[6]     ALU      COUT     Out     0.057     2.631       -         
rst_cnt_cry[6]       Net      -        -       0.000     -           1         
rst_cnt_s_0[7]       ALU      CIN      In      -         2.631       -         
rst_cnt_s_0[7]       ALU      SUM      Out     0.563     3.194       -         
rst_cnt_s[7]         Net      -        -       1.021     -           1         
rst_cnt_lm_0[7]      LUT4     I1       In      -         4.215       -         
rst_cnt_lm_0[7]      LUT4     F        Out     1.099     5.314       -         
rst_cnt_lm[7]        Net      -        -       0.000     -           1         
rst_cnt[7]           DFFC     D        In      -         5.314       -         
===============================================================================
Total path delay (propagation time + setup) of 5.447 is 3.405(62.5%) logic and 2.042(37.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      5.314
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.769

    Number of logic level(s):                8
    Starting point:                          rst_cnt[0] / Q
    Ending point:                            rst_cnt[6] / D
    The start point is clocked by            tb|clk_sys [rising] on pin CLK
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_cnt[0]           DFFC     Q        Out     0.367     0.367       -         
rst_cnt[0]           Net      -        -       1.021     -           3         
rst_cnt_cry_0[0]     ALU      I0       In      -         1.388       -         
rst_cnt_cry_0[0]     ALU      COUT     Out     0.958     2.346       -         
rst_cnt_cry[0]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[1]     ALU      CIN      In      -         2.346       -         
rst_cnt_cry_0[1]     ALU      COUT     Out     0.057     2.403       -         
rst_cnt_cry[1]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[2]     ALU      CIN      In      -         2.403       -         
rst_cnt_cry_0[2]     ALU      COUT     Out     0.057     2.460       -         
rst_cnt_cry[2]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[3]     ALU      CIN      In      -         2.460       -         
rst_cnt_cry_0[3]     ALU      COUT     Out     0.057     2.517       -         
rst_cnt_cry[3]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[4]     ALU      CIN      In      -         2.517       -         
rst_cnt_cry_0[4]     ALU      COUT     Out     0.057     2.574       -         
rst_cnt_cry[4]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[5]     ALU      CIN      In      -         2.574       -         
rst_cnt_cry_0[5]     ALU      COUT     Out     0.057     2.631       -         
rst_cnt_cry[5]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[6]     ALU      CIN      In      -         2.631       -         
rst_cnt_cry_0[6]     ALU      SUM      Out     0.563     3.194       -         
rst_cnt_s[6]         Net      -        -       1.021     -           1         
rst_cnt_lm_0[6]      LUT4     I1       In      -         4.215       -         
rst_cnt_lm_0[6]      LUT4     F        Out     1.099     5.314       -         
rst_cnt_lm[6]        Net      -        -       0.000     -           1         
rst_cnt[6]           DFFC     D        In      -         5.314       -         
===============================================================================
Total path delay (propagation time + setup) of 5.447 is 3.405(62.5%) logic and 2.042(37.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      5.257
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.712

    Number of logic level(s):                7
    Starting point:                          rst_cnt[2] / Q
    Ending point:                            rst_cnt[7] / D
    The start point is clocked by            tb|clk_sys [rising] on pin CLK
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_cnt[2]           DFFC     Q        Out     0.367     0.367       -         
rst_cnt[2]           Net      -        -       1.021     -           3         
rst_cnt_cry_0[2]     ALU      I0       In      -         1.388       -         
rst_cnt_cry_0[2]     ALU      COUT     Out     0.958     2.346       -         
rst_cnt_cry[2]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[3]     ALU      CIN      In      -         2.346       -         
rst_cnt_cry_0[3]     ALU      COUT     Out     0.057     2.403       -         
rst_cnt_cry[3]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[4]     ALU      CIN      In      -         2.403       -         
rst_cnt_cry_0[4]     ALU      COUT     Out     0.057     2.460       -         
rst_cnt_cry[4]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[5]     ALU      CIN      In      -         2.460       -         
rst_cnt_cry_0[5]     ALU      COUT     Out     0.057     2.517       -         
rst_cnt_cry[5]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[6]     ALU      CIN      In      -         2.517       -         
rst_cnt_cry_0[6]     ALU      COUT     Out     0.057     2.574       -         
rst_cnt_cry[6]       Net      -        -       0.000     -           1         
rst_cnt_s_0[7]       ALU      CIN      In      -         2.574       -         
rst_cnt_s_0[7]       ALU      SUM      Out     0.563     3.137       -         
rst_cnt_s[7]         Net      -        -       1.021     -           1         
rst_cnt_lm_0[7]      LUT4     I1       In      -         4.158       -         
rst_cnt_lm_0[7]      LUT4     F        Out     1.099     5.257       -         
rst_cnt_lm[7]        Net      -        -       0.000     -           1         
rst_cnt[7]           DFFC     D        In      -         5.257       -         
===============================================================================
Total path delay (propagation time + setup) of 5.390 is 3.348(62.1%) logic and 2.042(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      5.257
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.712

    Number of logic level(s):                7
    Starting point:                          rst_cnt[0] / Q
    Ending point:                            rst_cnt[5] / D
    The start point is clocked by            tb|clk_sys [rising] on pin CLK
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
rst_cnt[0]           DFFC     Q        Out     0.367     0.367       -         
rst_cnt[0]           Net      -        -       1.021     -           3         
rst_cnt_cry_0[0]     ALU      I0       In      -         1.388       -         
rst_cnt_cry_0[0]     ALU      COUT     Out     0.958     2.346       -         
rst_cnt_cry[0]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[1]     ALU      CIN      In      -         2.346       -         
rst_cnt_cry_0[1]     ALU      COUT     Out     0.057     2.403       -         
rst_cnt_cry[1]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[2]     ALU      CIN      In      -         2.403       -         
rst_cnt_cry_0[2]     ALU      COUT     Out     0.057     2.460       -         
rst_cnt_cry[2]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[3]     ALU      CIN      In      -         2.460       -         
rst_cnt_cry_0[3]     ALU      COUT     Out     0.057     2.517       -         
rst_cnt_cry[3]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[4]     ALU      CIN      In      -         2.517       -         
rst_cnt_cry_0[4]     ALU      COUT     Out     0.057     2.574       -         
rst_cnt_cry[4]       Net      -        -       0.000     -           1         
rst_cnt_cry_0[5]     ALU      CIN      In      -         2.574       -         
rst_cnt_cry_0[5]     ALU      SUM      Out     0.563     3.137       -         
rst_cnt_s[5]         Net      -        -       1.021     -           1         
rst_cnt_lm_0[5]      LUT4     I1       In      -         4.158       -         
rst_cnt_lm_0[5]      LUT4     F        Out     1.099     5.257       -         
rst_cnt_lm[5]        Net      -        -       0.000     -           1         
rst_cnt[5]           DFFC     D        In      -         5.257       -         
===============================================================================
Total path delay (propagation time + setup) of 5.390 is 3.348(62.1%) logic and 2.042(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                       Starting                                         Arrival          
Instance               Reference     Type     Pin      Net              Time        Slack
                       Clock                                                             
-----------------------------------------------------------------------------------------
u_pll_10M.pll_inst     System        PLL      LOCK     clk_10M_lock     0.000       2.493
=========================================================================================


Ending Points with Worst Slack
******************************

               Starting                                         Required          
Instance       Reference     Type     Pin     Net               Time         Slack
               Clock                                                              
----------------------------------------------------------------------------------
rst_cnt[0]     System        DFFC     D       rst_cnt_lm[0]     4.545        2.493
rst_cnt[1]     System        DFFC     D       rst_cnt_lm[1]     4.545        2.493
rst_cnt[2]     System        DFFC     D       rst_cnt_lm[2]     4.545        2.493
rst_cnt[3]     System        DFFC     D       rst_cnt_lm[3]     4.545        2.493
rst_cnt[4]     System        DFFC     D       rst_cnt_lm[4]     4.545        2.493
rst_cnt[5]     System        DFFC     D       rst_cnt_lm[5]     4.545        2.493
rst_cnt[6]     System        DFFC     D       rst_cnt_lm[6]     4.545        2.493
rst_cnt[7]     System        DFFC     D       rst_cnt_lm[7]     4.545        2.493
==================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.678
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.545

    - Propagation time:                      2.053
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.492

    Number of logic level(s):                1
    Starting point:                          u_pll_10M.pll_inst / LOCK
    Ending point:                            rst_cnt[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            tb|clk_sys [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
u_pll_10M.pll_inst     PLL      LOCK     Out     0.000     0.000       -         
clk_10M_lock           Net      -        -       1.021     -           8         
rst_cnt_lm_0[0]        LUT4     I0       In      -         1.021       -         
rst_cnt_lm_0[0]        LUT4     F        Out     1.032     2.053       -         
rst_cnt_lm[0]          Net      -        -       0.000     -           1         
rst_cnt[0]             DFFC     D        In      -         2.053       -         
=================================================================================
Total path delay (propagation time + setup) of 2.186 is 1.165(53.3%) logic and 1.021(46.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 225MB peak: 226MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 225MB peak: 226MB)

---------------------------------------
Resource Usage Report for tb 

Mapping to part: gw1n_1lqfp144-6
Cell usage:
ALU             77 uses
DFFC            50 uses
DFFCE           140 uses
DFFPE           1 use
FLASH96K        1 use
GSR             1 use
INV             2 uses
MUX2_LUT5       4 uses
MUX2_LUT6       1 use
PLL             1 use
LUT2            54 uses
LUT3            43 uses
LUT4            127 uses

I/O ports: 79
I/O primitives: 77
IBUF           2 uses
OBUF           74 uses
TBUF           1 use

I/O Register bits:                  0
Register bits not including I/Os:   191 of 864 (22%)
Total load per clock:
   tb|clk_sys: 9

@S |Mapping Summary:
Total  LUTs: 224 (19%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 73MB peak: 226MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Oct 22 17:05:31 2019

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