# Tue Oct 22 17:14:29 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF_scck.rpt 
Printing clock  summary report in "C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[28] because it is equivalent to instance wb_reg_dat_i[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[24] because it is equivalent to instance wb_reg_dat_i[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[21] because it is equivalent to instance wb_reg_dat_i[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[17] because it is equivalent to instance wb_reg_dat_i[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[14] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[7] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\qinfei\desktop\gowin_flash_controller\flash608k_wb_if\project\src\tb.v":46:0:46:5|Removing sequential instance wb_reg_dat_i[3] because it is equivalent to instance wb_reg_dat_i[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine i[28:0] (in view: work.tb(verilog))
original code -> new code
   00000000 -> 00000000000000000000000000001
   00000001 -> 00000000000000000000000000010
   00000010 -> 00000000000000000000000000100
   00000011 -> 00000000000000000000000001000
   00000100 -> 00000000000000000000000010000
   00000101 -> 00000000000000000000000100000
   00000110 -> 00000000000000000000001000000
   00000111 -> 00000000000000000000010000000
   00001000 -> 00000000000000000000100000000
   00001001 -> 00000000000000000001000000000
   00001010 -> 00000000000000000010000000000
   00001011 -> 00000000000000000100000000000
   00001100 -> 00000000000000001000000000000
   00001101 -> 00000000000000010000000000000
   00001110 -> 00000000000000100000000000000
   00001111 -> 00000000000001000000000000000
   00010000 -> 00000000000010000000000000000
   00010001 -> 00000000000100000000000000000
   00010010 -> 00000000001000000000000000000
   00010011 -> 00000000010000000000000000000
   00010100 -> 00000000100000000000000000000
   00010101 -> 00000001000000000000000000000
   00010110 -> 00000010000000000000000000000
   00010111 -> 00000100000000000000000000000
   00011000 -> 00001000000000000000000000000
   00011001 -> 00010000000000000000000000000
   00011010 -> 00100000000000000000000000000
   00011011 -> 01000000000000000000000000000
   00011100 -> 10000000000000000000000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 228MB)



Clock Summary
******************

          Start      Requested     Requested     Clock        Clock                     Clock
Level     Clock      Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------
0 -       System     100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                             
0 -       tb|clk     100.0 MHz     10.000        inferred     Autoconstr_clkgroup_0     510  
=============================================================================================



Clock Load Summary
***********************

           Clock     Source        Clock Pin        Non-clock Pin     Non-clock Pin
Clock      Load      Pin           Seq Example      Seq Example       Comb Example 
-----------------------------------------------------------------------------------
System     0         -             -                -                 -            
                                                                                   
tb|clk     510       clk(port)     key1_temp1.C     -                 -            
===================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 510 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 port                   510        i[28]          
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_WB_IF\project\impl\synthesize\rev_1\FLASH608K_WB_IF.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 229MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 22 17:14:31 2019

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