=====
SETUP
0.960
11.333
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
N_272_i_cZ
10.511
11.333
i_Z[26]
11.333
=====
SETUP
1.301
10.992
12.293
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[3]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o22
5.465
6.287
flash_controller_inst/u_Wishbone_Master_Top_256K/rdata_m_cZ[0]
7.643
8.269
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_iv_3[0]
9.893
10.992
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]
10.992
=====
SETUP
1.320
10.973
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
N_260_i_cZ
9.874
10.973
i_Z[19]
10.973
=====
SETUP
1.388
10.904
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
i_ns_a2[27]
9.872
10.904
i_Z[27]
10.904
=====
SETUP
1.388
10.904
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
N_239_i_cZ
9.872
10.904
i_Z[8]
10.904
=====
SETUP
1.563
10.730
12.293
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_0_cZ[4]
7.795
8.827
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_2[4]
9.631
10.730
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]
10.730
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]
10.956
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]
10.956
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]
10.956
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]
10.956
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]
10.956
=====
SETUP
1.693
10.956
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]
10.956
=====
SETUP
1.747
10.902
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]
10.902
=====
SETUP
1.747
10.902
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]
10.902
=====
SETUP
1.747
10.902
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]
10.902
=====
SETUP
1.755
10.538
12.293
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[3]
7.959
9.020
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[3]
9.439
10.538
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]
10.538
=====
SETUP
1.788
10.505
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
i_ns_a2[20]
9.879
10.505
i_Z[20]
10.505
=====
SETUP
1.788
10.505
12.293
clk_ibuf
0.000
0.982
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
2.893
3.351
i_ns_i_a2_1_20_cZ[8]
4.489
5.521
i_ns_i_a2_1_29_cZ[8]
6.974
8.073
i_ns_a2[9]
9.879
10.505
i_Z[9]
10.505
=====
SETUP
1.907
10.386
12.293
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[1]
7.975
8.797
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[1]
9.287
10.386
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]
10.386
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]
10.535
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]
10.535
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]
10.535
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]
10.535
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]
10.535
=====
SETUP
2.114
10.535
12.649
clk_ibuf
0.000
0.982
wb_reg_adr_i_Z[2]
2.893
3.351
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23
5.809
6.435
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ
8.136
8.938
flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]
10.535
=====
HOLD
0.577
2.857
2.280
clk_ibuf
0.000
0.844
i_Z[23]
2.280
2.613
i_Z[24]
2.857
=====
HOLD
0.577
2.857
2.280
clk_ibuf
0.000
0.844
i_Z[15]
2.280
2.613
i_Z[16]
2.857
=====
HOLD
0.578
2.858
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[2]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z
2.858
=====
HOLD
0.581
2.861
2.280
clk_ibuf
0.000
0.844
wb_reg_dat_i_Z[0]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]
2.861
=====
HOLD
0.582
2.862
2.280
clk_ibuf
0.000
0.844
i_Z[3]
2.280
2.613
i_Z[4]
2.862
=====
HOLD
0.582
2.862
2.280
clk_ibuf
0.000
0.844
i_Z[12]
2.280
2.613
i_Z[13]
2.862
=====
HOLD
0.708
2.988
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_46_i_cZ
2.616
2.988
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z
2.988
=====
HOLD
0.708
2.988
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[0]
2.616
2.988
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
2.988
=====
HOLD
0.708
2.988
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_44_i_cZ
2.616
2.988
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]
2.988
=====
HOLD
0.709
2.989
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[4]
2.617
2.989
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]
2.989
=====
HOLD
0.710
2.990
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m69_i
2.618
2.990
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]
2.990
=====
HOLD
0.710
2.990
2.280
clk_ibuf
0.000
0.844
i_Z[26]
2.280
2.613
N_272_i_cZ
2.618
2.990
i_Z[26]
2.990
=====
HOLD
0.710
2.990
2.280
clk_ibuf
0.000
0.844
wb_reg_adr_i_Z[3]
2.280
2.613
wb_reg_adr_ie[3]
2.618
2.990
wb_reg_adr_i_Z[3]
2.990
=====
HOLD
0.712
2.992
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m38_0
2.620
2.992
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]
2.992
=====
HOLD
0.712
2.992
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.N_28_i
2.620
2.992
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]
2.992
=====
HOLD
0.714
2.994
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m16_i
2.622
2.994
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
2.994
=====
HOLD
0.714
2.994
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i
2.622
2.994
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
2.994
=====
HOLD
0.714
2.994
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m16_i
2.622
2.994
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
2.994
=====
HOLD
0.714
2.994
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_ns_cZ[1]
2.622
2.994
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]
2.994
=====
HOLD
0.892
3.172
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_1_sqmuxa_0_a4
2.616
3.172
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z
3.172
=====
HOLD
0.892
3.172
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt_4_0_a2[0]
2.616
3.172
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
3.172
=====
HOLD
0.893
3.173
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_4_0_a2[0]
2.617
3.173
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]
3.173
=====
HOLD
0.896
3.176
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m59_0
2.620
3.176
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]
3.176
=====
HOLD
0.905
3.185
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z
3.185
=====
HOLD
0.937
3.217
2.280
clk_ibuf
0.000
0.844
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/comp_data[23]
2.280
2.613
flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv[23]
2.845
3.217
flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]
3.217
