Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\impl\synthesize\rev_1\FLASH256K_WB_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH256K_WB_IF\project\src\FLASH256K_WB_IF.cst
Timing Constraint File | ---
GOWIN version | V1.9.2.01Beta
Part Number | GW1N-LV4LQ144C6/I5
Created Time | Tue Oct 22 17:11:30 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 1173
Numbers of Endpoints Analyzed | 1138
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 110.619(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.960 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[26]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.440
2 | 1.301 | wb_reg_adr_i_Z[3]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.099
3 | 1.320 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[19]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.080
4 | 1.388 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[27]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.012
5 | 1.388 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.012
6 | 1.563 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.837
7 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
8 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
9 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
10 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
11 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
12 | 1.693 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.064
13 | 1.747 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.010
14 | 1.747 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.010
15 | 1.747 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.010
16 | 1.755 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.645
17 | 1.788 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.612
18 | 1.788 | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q | i_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.612
19 | 1.907 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.493
20 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643
21 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643
22 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643
23 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643
24 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643
25 | 2.114 | wb_reg_adr_i_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.643

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.577 | i_Z[23]/Q | i_Z[24]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.577
2 | 0.577 | i_Z[15]/Q | i_Z[16]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.577
3 | 0.578 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.578
4 | 0.581 | wb_reg_dat_i_Z[0]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.581
5 | 0.582 | i_Z[3]/Q | i_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582
6 | 0.582 | i_Z[12]/Q | i_Z[13]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582
7 | 0.708 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
8 | 0.708 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
9 | 0.708 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
10 | 0.709 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
11 | 0.710 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
12 | 0.710 | i_Z[26]/Q | i_Z[26]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
13 | 0.710 | wb_reg_adr_i_Z[3]/Q | wb_reg_adr_i_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.710
14 | 0.712 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.712
15 | 0.712 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.712
16 | 0.714 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
17 | 0.714 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
18 | 0.714 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
19 | 0.714 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.714
20 | 0.892 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.892
21 | 0.892 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.892
22 | 0.893 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.893
23 | 0.896 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.896
24 | 0.905 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.905
25 | 0.937 | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/comp_data[23]/Q | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.937

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[1]
2 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | key2_temp2_Z
3 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[16]
4 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[8]
5 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[19]
6 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[4]
7 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[15]
8 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/ERASE_Z
9 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z
10 | 3.087 | 4.337 | 1.250 | Low Pulse Width | DEFAULT_CLK | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[14]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.960
Data Arrival Time | 11.333
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[26]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
10.511 | 2.437 | tNET | FF | 1 | R17C9[0][A] | N_272_i_cZ/I3
11.333 | 0.822 | tINS | FF | 1 | R17C9[0][A] | N_272_i_cZ/F
11.333 | 0.000 | tNET | FF | 1 | R17C9[0][A] | i_Z[26]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C9[0][A] | i_Z[26]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[26]
12.293 | -0.400 | tSu |  | 1 | R17C9[0][A] | i_Z[26]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.953, 34.988%; route: 5.029, 59.582%; tC2Q: 0.458, 5.430%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path2

Path Summary:

Slack | 1.301
Data Arrival Time | 10.992
Data Required Time | 12.293
From | wb_reg_adr_i_Z[3]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C5[1][A] | wb_reg_adr_i_Z[3]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C5[1][A] | wb_reg_adr_i_Z[3]/Q
5.465 | 2.113 | tNET | FF | 1 | R5C8[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o22/I1
6.287 | 0.822 | tINS | FF | 32 | R5C8[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o22/F
7.643 | 1.356 | tNET | FF | 1 | R4C5[3][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/rdata_m_cZ[0]/I1
8.269 | 0.626 | tINS | FF | 1 | R4C5[3][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/rdata_m_cZ[0]/F
9.893 | 1.624 | tNET | FF | 1 | R16C5[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_iv_3[0]/I0
10.992 | 1.099 | tINS | FF | 1 | R16C5[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_iv_3[0]/F
10.992 | 0.000 | tNET | FF | 1 | R16C5[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R16C5[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]
12.293 | -0.400 | tSu |  | 1 | R16C5[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.547, 31.448%; route: 5.094, 62.893%; tC2Q: 0.458, 5.659%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path3

Path Summary:

Slack | 1.320
Data Arrival Time | 10.973
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
9.874 | 1.800 | tNET | FF | 1 | R17C4[1][A] | N_260_i_cZ/I3
10.973 | 1.099 | tINS | FF | 1 | R17C4[1][A] | N_260_i_cZ/F
10.973 | 0.000 | tNET | FF | 1 | R17C4[1][A] | i_Z[19]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C4[1][A] | i_Z[19]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[19]
12.293 | -0.400 | tSu |  | 1 | R17C4[1][A] | i_Z[19]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.230, 39.974%; route: 4.392, 54.353%; tC2Q: 0.458, 5.672%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path4

Path Summary:

Slack | 1.388
Data Arrival Time | 10.904
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[27]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
9.872 | 1.799 | tNET | FF | 1 | R17C8[1][A] | i_ns_a2[27]/I2
10.904 | 1.032 | tINS | FF | 1 | R17C8[1][A] | i_ns_a2[27]/F
10.904 | 0.000 | tNET | FF | 1 | R17C8[1][A] | i_Z[27]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C8[1][A] | i_Z[27]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[27]
12.293 | -0.400 | tSu |  | 1 | R17C8[1][A] | i_Z[27]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.163, 39.480%; route: 4.390, 54.799%; tC2Q: 0.458, 5.721%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path5

Path Summary:

Slack | 1.388
Data Arrival Time | 10.904
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
9.872 | 1.799 | tNET | FF | 1 | R17C8[0][B] | N_239_i_cZ/I3
10.904 | 1.032 | tINS | FF | 1 | R17C8[0][B] | N_239_i_cZ/F
10.904 | 0.000 | tNET | FF | 1 | R17C8[0][B] | i_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C8[0][B] | i_Z[8]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[8]
12.293 | -0.400 | tSu |  | 1 | R17C8[0][B] | i_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 3.163, 39.480%; route: 4.390, 54.799%; tC2Q: 0.458, 5.721%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path6

Path Summary:

Slack | 1.563
Data Arrival Time | 10.730
Data Required Time | 12.293
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
7.795 | 1.360 | tNET | FF | 1 | R8C5[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_0_cZ[4]/I1
8.827 | 1.032 | tINS | FF | 1 | R8C5[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_0_cZ[4]/F
9.631 | 0.804 | tNET | FF | 1 | R5C5[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_2[4]/I0
10.730 | 1.099 | tINS | FF | 1 | R5C5[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv_2[4]/F
10.730 | 0.000 | tNET | FF | 1 | R5C5[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R5C5[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]
12.293 | -0.400 | tSu |  | 1 | R5C5[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.757, 35.178%; route: 4.622, 58.974%; tC2Q: 0.458, 5.848%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path7

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]
12.649 | -0.043 | tSu |  | 1 | R8C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[30]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path8

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]
12.649 | -0.043 | tSu |  | 1 | R8C8[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[25]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path9

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]
12.649 | -0.043 | tSu |  | 1 | R8C8[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[26]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path10

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]
12.649 | -0.043 | tSu |  | 1 | R8C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[24]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path11

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]
12.649 | -0.043 | tSu |  | 1 | R8C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[28]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path12

Path Summary:

Slack | 1.693
Data Arrival Time | 10.956
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.956 | 2.019 | tNET | RR | 1 | R8C8[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C8[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]
12.649 | -0.043 | tSu |  | 1 | R8C8[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.709%; route: 6.177, 76.607%; tC2Q: 0.458, 5.684%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path13

Path Summary:

Slack | 1.747
Data Arrival Time | 10.902
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.902 | 1.965 | tNET | RR | 1 | R9C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R9C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]
12.649 | -0.043 | tSu |  | 1 | R9C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[31]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.829%; route: 6.123, 76.449%; tC2Q: 0.458, 5.722%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path14

Path Summary:

Slack | 1.747
Data Arrival Time | 10.902
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.902 | 1.965 | tNET | RR | 1 | R9C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R9C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]
12.649 | -0.043 | tSu |  | 1 | R9C8[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.829%; route: 6.123, 76.449%; tC2Q: 0.458, 5.722%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path15

Path Summary:

Slack | 1.747
Data Arrival Time | 10.902
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.902 | 1.965 | tNET | RR | 1 | R9C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R9C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]
12.649 | -0.043 | tSu |  | 1 | R9C8[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 17.829%; route: 6.123, 76.449%; tC2Q: 0.458, 5.722%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path16

Path Summary:

Slack | 1.755
Data Arrival Time | 10.538
Data Required Time | 12.293
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
7.959 | 1.525 | tNET | FF | 1 | R15C6[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[3]/I1
9.020 | 1.061 | tINS | FR | 1 | R15C6[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[3]/F
9.439 | 0.419 | tNET | RR | 1 | R15C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[3]/I1
10.538 | 1.099 | tINS | RF | 1 | R15C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[3]/F
10.538 | 0.000 | tNET | FF | 1 | R15C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]
12.293 | -0.400 | tSu |  | 1 | R15C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.786, 36.440%; route: 4.401, 57.565%; tC2Q: 0.458, 5.995%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path17

Path Summary:

Slack | 1.788
Data Arrival Time | 10.505
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
9.879 | 1.805 | tNET | FF | 1 | R17C7[0][B] | i_ns_a2[20]/I2
10.505 | 0.626 | tINS | FF | 1 | R17C7[0][B] | i_ns_a2[20]/F
10.505 | 0.000 | tNET | FF | 1 | R17C7[0][B] | i_Z[20]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C7[0][B] | i_Z[20]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[20]
12.293 | -0.400 | tSu |  | 1 | R17C7[0][B] | i_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.757, 36.221%; route: 4.396, 57.758%; tC2Q: 0.458, 6.021%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path18

Path Summary:

Slack | 1.788
Data Arrival Time | 10.505
Data Required Time | 12.293
From | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]
To | i_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/CLK
3.351 | 0.458 | tC2Q | RF | 2 | R4C6[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[19]/Q
4.489 | 1.138 | tNET | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/I3
5.521 | 1.032 | tINS | FF | 1 | R4C9[0][A] | i_ns_i_a2_1_20_cZ[8]/F
6.974 | 1.453 | tNET | FF | 1 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/I0
8.073 | 1.099 | tINS | FF | 6 | R5C6[3][A] | i_ns_i_a2_1_29_cZ[8]/F
9.879 | 1.805 | tNET | FF | 1 | R17C7[0][A] | i_ns_a2[9]/I2
10.505 | 0.626 | tINS | FF | 1 | R17C7[0][A] | i_ns_a2[9]/F
10.505 | 0.000 | tNET | FF | 1 | R17C7[0][A] | i_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R17C7[0][A] | i_Z[9]/CLK
12.693 | -0.200 | tUnc |  |  |  | i_Z[9]
12.293 | -0.400 | tSu |  | 1 | R17C7[0][A] | i_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.757, 36.221%; route: 4.396, 57.758%; tC2Q: 0.458, 6.021%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path19

Path Summary:

Slack | 1.907
Data Arrival Time | 10.386
Data Required Time | 12.293
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
7.975 | 1.541 | tNET | FF | 1 | R15C6[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[1]/I1
8.797 | 0.822 | tINS | FF | 1 | R15C6[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_0_cZ[1]/F
9.287 | 0.490 | tNET | FF | 1 | R15C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[1]/I1
10.386 | 1.099 | tINS | FF | 1 | R15C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_9_0_iv_2[1]/F
10.386 | 0.000 | tNET | FF | 1 | R15C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R15C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]
12.293 | -0.400 | tSu |  | 1 | R15C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 2.547, 33.990%; route: 4.488, 59.894%; tC2Q: 0.458, 6.117%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path20

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]
12.649 | -0.043 | tSu |  | 1 | R8C4[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path21

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]
12.649 | -0.043 | tSu |  | 1 | R8C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path22

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]
12.649 | -0.043 | tSu |  | 1 | R8C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[13]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path23

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]
12.649 | -0.043 | tSu |  | 1 | R8C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[18]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path24

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]
12.649 | -0.043 | tSu |  | 1 | R8C4[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Path25

Path Summary:

Slack | 2.114
Data Arrival Time | 10.535
Data Required Time | 12.649
From | wb_reg_adr_i_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.893 | 1.911 | tNET | RR | 1 | R17C10[1][B] | wb_reg_adr_i_Z[2]/CLK
3.351 | 0.458 | tC2Q | RF | 8 | R17C10[1][B] | wb_reg_adr_i_Z[2]/Q
5.809 | 2.457 | tNET | FF | 1 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/I0
6.435 | 0.626 | tINS | FF | 33 | R5C7[3][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o23/F
8.136 | 1.701 | tNET | FF | 1 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/I0
8.938 | 0.802 | tINS | FR | 32 | R15C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_1_sqmuxa_cZ/F
10.535 | 1.598 | tNET | RR | 1 | R8C4[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
12.893 | 1.911 | tNET | RR | 1 | R8C4[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]/CLK
12.693 | -0.200 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]
12.649 | -0.043 | tSu |  | 1 | R8C4[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%
Arrival Data Path Delay | cell: 1.428, 18.685%; route: 5.756, 75.318%; tC2Q: 0.458, 5.997%
Required Clock Path Delay | cell: 0.982, 33.942%; route: 1.911, 66.058%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.577
Data Arrival Time | 2.857
Data Required Time | 2.280
From | i_Z[23]
To | i_Z[24]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C11[0][B] | i_Z[23]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R17C11[0][B] | i_Z[23]/Q
2.857 | 0.244 | tNET | RR | 1 | R17C11[2][B] | i_Z[24]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C11[2][B] | i_Z[24]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[24]
2.280 | 0.000 | tHld |  | 1 | R17C11[2][B] | i_Z[24]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.244, 42.242%; tC2Q: 0.333, 57.758%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path2

Path Summary:

Slack | 0.577
Data Arrival Time | 2.857
Data Required Time | 2.280
From | i_Z[15]
To | i_Z[16]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[2][A] | i_Z[15]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R17C9[2][A] | i_Z[15]/Q
2.857 | 0.244 | tNET | RR | 1 | R17C9[1][A] | i_Z[16]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[1][A] | i_Z[16]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[16]
2.280 | 0.000 | tHld |  | 1 | R17C9[1][A] | i_Z[16]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.244, 42.242%; tC2Q: 0.333, 57.758%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path3

Path Summary:

Slack | 0.578
Data Arrival Time | 2.858
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C7[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[2]/CLK
2.613 | 0.333 | tC2Q | RR | 47 | R9C7[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[2]/Q
2.858 | 0.245 | tNET | RR | 1 | R9C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z
2.280 | 0.000 | tHld |  | 1 | R9C7[2][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 42.329%; tC2Q: 0.333, 57.671%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path4

Path Summary:

Slack | 0.581
Data Arrival Time | 2.861
Data Required Time | 2.280
From | wb_reg_dat_i_Z[0]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C5[2][B] | wb_reg_dat_i_Z[0]/CLK
2.613 | 0.333 | tC2Q | RF | 5 | R17C5[2][B] | wb_reg_dat_i_Z[0]/Q
2.861 | 0.248 | tNET | FF | 1 | R16C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R16C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]
2.280 | 0.000 | tHld |  | 1 | R16C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/xaddr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.248, 42.657%; tC2Q: 0.333, 57.343%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path5

Path Summary:

Slack | 0.582
Data Arrival Time | 2.862
Data Required Time | 2.280
From | i_Z[3]
To | i_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[1][B] | i_Z[3]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R17C9[1][B] | i_Z[3]/Q
2.862 | 0.249 | tNET | RR | 1 | R17C9[0][B] | i_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[0][B] | i_Z[4]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[4]
2.280 | 0.000 | tHld |  | 1 | R17C9[0][B] | i_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 42.741%; tC2Q: 0.333, 57.259%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path6

Path Summary:

Slack | 0.582
Data Arrival Time | 2.862
Data Required Time | 2.280
From | i_Z[12]
To | i_Z[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C11[2][A] | i_Z[12]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R17C11[2][A] | i_Z[12]/Q
2.862 | 0.249 | tNET | RR | 1 | R17C11[0][A] | i_Z[13]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C11[0][A] | i_Z[13]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[13]
2.280 | 0.000 | tHld |  | 1 | R17C11[0][A] | i_Z[13]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 42.741%; tC2Q: 0.333, 57.259%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path7

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/Q
2.616 | 0.002 | tNET | RR | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_46_i_cZ/I0
2.988 | 0.372 | tINS | RF | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_46_i_cZ/F
2.988 | 0.000 | tNET | FF | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z
2.280 | 0.000 | tHld |  | 1 | R9C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/as_cnt_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path8

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/Q
2.616 | 0.002 | tNET | RR | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[0]/I2
2.988 | 0.372 | tINS | RF | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[0]/F
2.988 | 0.000 | tNET | FF | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]
2.280 | 0.000 | tHld |  | 1 | R7C4[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path9

Path Summary:

Slack | 0.708
Data Arrival Time | 2.988
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/Q
2.616 | 0.002 | tNET | RR | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_44_i_cZ/I1
2.988 | 0.372 | tINS | RF | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/N_44_i_cZ/F
2.988 | 0.000 | tNET | FF | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]
2.280 | 0.000 | tHld |  | 1 | R7C5[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/end_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path10

Path Summary:

Slack | 0.709
Data Arrival Time | 2.989
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/CLK
2.613 | 0.333 | tC2Q | RR | 4 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/Q
2.617 | 0.004 | tNET | RR | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[4]/I3
2.989 | 0.372 | tINS | RF | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_ns_cZ[4]/F
2.989 | 0.000 | tNET | FF | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]
2.280 | 0.000 | tHld |  | 1 | R7C4[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/r_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path11

Path Summary:

Slack | 0.710
Data Arrival Time | 2.990
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/CLK
2.613 | 0.333 | tC2Q | RR | 58 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/Q
2.618 | 0.005 | tNET | RR | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m69_i/I2
2.990 | 0.372 | tINS | RF | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m69_i/F
2.990 | 0.000 | tNET | FF | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]
2.280 | 0.000 | tHld |  | 1 | R12C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path12

Path Summary:

Slack | 0.710
Data Arrival Time | 2.990
Data Required Time | 2.280
From | i_Z[26]
To | i_Z[26]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[0][A] | i_Z[26]/CLK
2.613 | 0.333 | tC2Q | RR | 6 | R17C9[0][A] | i_Z[26]/Q
2.618 | 0.005 | tNET | RR | 1 | R17C9[0][A] | N_272_i_cZ/I1
2.990 | 0.372 | tINS | RF | 1 | R17C9[0][A] | N_272_i_cZ/F
2.990 | 0.000 | tNET | FF | 1 | R17C9[0][A] | i_Z[26]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C9[0][A] | i_Z[26]/CLK
2.280 | 0.000 | tUnc |  |  |  | i_Z[26]
2.280 | 0.000 | tHld |  | 1 | R17C9[0][A] | i_Z[26]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path13

Path Summary:

Slack | 0.710
Data Arrival Time | 2.990
Data Required Time | 2.280
From | wb_reg_adr_i_Z[3]
To | wb_reg_adr_i_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C5[1][A] | wb_reg_adr_i_Z[3]/CLK
2.613 | 0.333 | tC2Q | RR | 8 | R17C5[1][A] | wb_reg_adr_i_Z[3]/Q
2.618 | 0.005 | tNET | RR | 1 | R17C5[1][A] | wb_reg_adr_ie[3]/I2
2.990 | 0.372 | tINS | RF | 1 | R17C5[1][A] | wb_reg_adr_ie[3]/F
2.990 | 0.000 | tNET | FF | 1 | R17C5[1][A] | wb_reg_adr_i_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R17C5[1][A] | wb_reg_adr_i_Z[3]/CLK
2.280 | 0.000 | tUnc |  |  |  | wb_reg_adr_i_Z[3]
2.280 | 0.000 | tHld |  | 1 | R17C5[1][A] | wb_reg_adr_i_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path14

Path Summary:

Slack | 0.712
Data Arrival Time | 2.992
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/CLK
2.613 | 0.333 | tC2Q | RR | 14 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/Q
2.620 | 0.007 | tNET | RR | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m38_0/I3
2.992 | 0.372 | tINS | RF | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m38_0/F
2.992 | 0.000 | tNET | FF | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]
2.280 | 0.000 | tHld |  | 1 | R14C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path15

Path Summary:

Slack | 0.712
Data Arrival Time | 2.992
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/CLK
2.613 | 0.333 | tC2Q | RR | 14 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/Q
2.620 | 0.007 | tNET | RR | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.N_28_i/I3
2.992 | 0.372 | tINS | RF | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.N_28_i/F
2.992 | 0.000 | tNET | FF | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]
2.280 | 0.000 | tHld |  | 1 | R14C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path16

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/CLK
2.613 | 0.333 | tC2Q | RR | 12 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/Q
2.622 | 0.008 | tNET | RR | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m16_i/I2
2.994 | 0.372 | tINS | RF | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m16_i/F
2.994 | 0.000 | tNET | FF | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]
2.280 | 0.000 | tHld |  | 1 | R13C9[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path17

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/CLK
2.613 | 0.333 | tC2Q | RR | 11 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/Q
2.622 | 0.008 | tNET | RR | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i/I3
2.994 | 0.372 | tINS | RF | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m110_i/F
2.994 | 0.000 | tNET | FF | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]
2.280 | 0.000 | tHld |  | 1 | R7C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path18

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/CLK
2.613 | 0.333 | tC2Q | RR | 11 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/Q
2.622 | 0.008 | tNET | RR | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m16_i/I3
2.994 | 0.372 | tINS | RF | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_ns_8_0_.m16_i/F
2.994 | 0.000 | tNET | FF | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]
2.280 | 0.000 | tHld |  | 1 | R5C12[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/e_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path19

Path Summary:

Slack | 0.714
Data Arrival Time | 2.994
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/CLK
2.613 | 0.333 | tC2Q | RR | 15 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/Q
2.622 | 0.008 | tNET | RR | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_ns_cZ[1]/I3
2.994 | 0.372 | tINS | RF | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_ns_cZ[1]/F
2.994 | 0.000 | tNET | FF | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]
2.280 | 0.000 | tHld |  | 1 | R9C12[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/state_UFM_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path20

Path Summary:

Slack | 0.892
Data Arrival Time | 3.172
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/CLK
2.613 | 0.333 | tC2Q | RR | 2 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/Q
2.616 | 0.002 | tNET | RR | 1 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_1_sqmuxa_0_a4/I0
3.172 | 0.556 | tINS | RR | 2 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_1_sqmuxa_0_a4/F
3.172 | 0.000 | tNET | RR | 1 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z
2.280 | 0.000 | tHld |  | 1 | R7C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/pws_cnt_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path21

Path Summary:

Slack | 0.892
Data Arrival Time | 3.172
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/Q
2.616 | 0.002 | tNET | RR | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt_4_0_a2[0]/I0
3.172 | 0.556 | tINS | RR | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt_4_0_a2[0]/F
3.172 | 0.000 | tNET | RR | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]
2.280 | 0.000 | tHld |  | 1 | R11C4[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/wait_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path22

Path Summary:

Slack | 0.893
Data Arrival Time | 3.173
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/CLK
2.613 | 0.333 | tC2Q | RR | 3 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/Q
2.617 | 0.004 | tNET | RR | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_4_0_a2[0]/I0
3.173 | 0.556 | tINS | RR | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt_4_0_a2[0]/F
3.173 | 0.000 | tNET | RR | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]
2.280 | 0.000 | tHld |  | 1 | R7C12[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_ER_UFM/end_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path23

Path Summary:

Slack | 0.896
Data Arrival Time | 3.176
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/CLK
2.613 | 0.333 | tC2Q | RR | 12 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/Q
2.620 | 0.007 | tNET | RR | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m59_0/I3
3.176 | 0.556 | tINS | RR | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_ns_9_0_.m59_0/F
3.176 | 0.000 | tNET | RR | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]
2.280 | 0.000 | tHld |  | 1 | R12C9[2][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.556, 62.025%; route: 0.007, 0.790%; tC2Q: 0.333, 37.185%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path24

Path Summary:

Slack | 0.905
Data Arrival Time | 3.185
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp
To | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/CLK
2.613 | 0.333 | tC2Q | RR | 5 | R7C8[1][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_RD_UFM/xe_tmp/Q
3.185 | 0.572 | tNET | RR | 1 | R7C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R7C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z
2.280 | 0.000 | tHld |  | 1 | R7C5[0][A] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/r_busy_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.572, 63.164%; tC2Q: 0.333, 36.836%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Path25

Path Summary:

Slack | 0.937
Data Arrival Time | 3.217
Data Required Time | 2.280
From | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/comp_data[23]
To | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R4C5[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/comp_data[23]/CLK
2.613 | 0.333 | tC2Q | RF | 1 | R4C5[1][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/comp_data[23]/Q
2.845 | 0.231 | tNET | FF | 1 | R5C5[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv[23]/I0
3.217 | 0.372 | tINS | FF | 1 | R5C5[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/wb_dat_o_9_0_iv[23]/F
3.217 | 0.000 | tNET | FF | 1 | R5C5[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL9[A] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 498 | IOL9[A] | clk_ibuf/O
2.280 | 1.436 | tNET | RR | 1 | R5C5[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]/CLK
2.280 | 0.000 | tUnc |  |  |  | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]
2.280 | 0.000 | tHld |  | 1 | R5C5[0][B] | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[23]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%
Arrival Data Path Delay | cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590%
Required Clock Path Delay | cell: 0.844, 37.035%; route: 1.436, 62.965%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[1]/CLK

### MPW2

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | key2_temp2_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | key2_temp2_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | key2_temp2_Z/CLK

### MPW3

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[16]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[16]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[16]/CLK

### MPW4

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[8]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[8]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[8]/CLK

### MPW5

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[19]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | i_Z[19]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | i_Z[19]/CLK

### MPW6

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[4]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[4]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | flash_controller_inst/u_Wishbone_Master_Top_256K/wdata_Z[4]/CLK

### MPW7

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[15]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[15]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[15]/CLK

### MPW8

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/ERASE_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/ERASE_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/ERASE_Z/CLK

### MPW9

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | flash_controller_inst/u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/w_command_Z/CLK

### MPW10

MPW Summary:

Slack: | 3.087
Actual Width: | 4.337
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[14]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
7.943 | 1.958 | tNET | FF | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[14]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
12.280 | 1.436 | tNET | RR | flash_controller_inst/u_Wishbone_Master_Top_256K/wb_dat_o_Z[14]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
498 | clk_c | 0.960 | 1.958
58 | w_state[8] | 4.616 | 3.294
50 | w_state[9] | 6.378 | 1.532
49 | cr[0] | 4.424 | 2.023
49 | cr[1] | 3.832 | 2.839
48 | w_state[0] | 6.297 | 1.545
47 | state_UFM[2] | 3.712 | 1.849
45 | N_64_i | 5.751 | 1.860
41 | wb_reg_dat_i[2] | 5.747 | 3.194
35 | state_UFM28 | 4.582 | 1.880

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R7C8 | 0.583
R5C7 | 0.500
R17C9 | 0.500
R7C4 | 0.472
R9C7 | 0.472
R8C7 | 0.458
R8C8 | 0.444
R17C7 | 0.444
R17C5 | 0.431
R7C5 | 0.431

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---