
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1

# Written on Tue Oct 22 17:05:24 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start          Requested     Requested     Clock        Clock                     Clock
Level     Clock          Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------
0 -       System         100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                                 
0 -       tb|clk_sys     283.2 MHz     3.532         inferred     Autoconstr_clkgroup_0     8    
=================================================================================================


Clock Load Summary
******************

               Clock     Source            Clock Pin          Non-clock Pin     Non-clock Pin
Clock          Load      Pin               Seq Example        Seq Example       Comb Example 
---------------------------------------------------------------------------------------------
System         0         -                 -                  -                 -            
                                                                                             
tb|clk_sys     8         clk_sys(port)     rst_cnt[7:0].C     -                 -            
=============================================================================================
