//
// Written by Synplify Pro 
// Product Version "P-2019.03G"
// Program "Synplify Pro", Mapper "mapgw, Build 1450R"
// Tue Oct 22 17:02:15 2019
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\generic\gw1nz.v "
// file 1 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\vlog\hypermods.v "
// file 2 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\c:\users\qinfei\desktop\gowin_flash_controller\flash64kz_reg_if\project\src\gowin_flash_controller\gowin_flash_controller.v "
// file 6 "\c:\users\qinfei\desktop\gowin_flash_controller\flash64kz_reg_if\project\src\tb.v "
// file 7 "\d:\swgowin\gowin_v1.9.2.01beta_35214_20191015\synplifypro\lib\nlconst.dat "

`timescale 100 ps/100 ps
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
`pragma protect key_block
OgoPleCFjju75sGdWYBohdWy2c0InEZZUXMx69cM5Chqj9LN1ovxPCurUOp+TOZ+9fgeCEkk4I5m
XiVR6VIeiYFCRGYx8i+XvEWl12JC4OAQQ6s11exReRB0Rn9mEVMf4t5s1Eveb4uO5FEs+xKIOkxZ
eOvkqqTs8Me/1W0CCDJ4uJSl/oZSayFHEyBgsivAeuya3nCM8k81mdQt/XHDjZ6ynj2khIjOcLlV
VLU6KPJQcUbkOX3oHaRbNh04VouNAq6CaQ+jvePpN+ggA5Y02F/VBIgVnZK++Zw3rS/phrVFKVCC
O/Fpjtbk1N+B92eW8gY/e5820djqosdAfaQrfA==

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GoWin"
`pragma protect key_keyname="GoWin2016"
`pragma protect key_method="rsa"
`pragma protect key_block
sDB623tqHB0CEb6UFM2TGwbyzTDYdlgvHJ/HN9qrm+AOLE03QsudSbIskXSDjOnL12z9IMNlDbAW
jc6g4VxFRXL3OzM/NQfl2Igrjm9wZZ8DjA5D//GU1K49Bn1Bd0cYJ8xQTApi1hi1Q2DNIGQ8zcus
3ohhIPPMNM53SfRleaWdsBp4dQ6SNT4eWtpcRhFme1qj4mlWUDJzE+0y9DcVtkTWLvIWyaGwj6q6
Ehs/lceFYssYh9nA0v3XEXF1U7sVdVGxV8HTpp4nBlqDiywpTqAIRsqiIsWTZwl7++ZD/iqPLzDm
xFon2ieP/WblCJdLbX48+7+TXroXmY1b+IN4/Q==

`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=133520)
`pragma protect data_block
[encoded data, 177992 characters]
GEWI+G7Rz7fWPTh4fi7vEulydSG43JWTE+8=
`pragma protect end_protected
module Gowin_Flash_Controller_Top (
  rdata,
  wdata_0,
  erase_reg,
  Start_signal_i,
  Done_signal_o,
  w_r_signal_i,
  nreset_c,
  clk_c
)
;
output [7:0] rdata ;
input wdata_0 ;
input erase_reg ;
input Start_signal_i ;
output Done_signal_o ;
input w_r_signal_i ;
input nreset_c ;
input clk_c ;
wire wdata_0 ;
wire erase_reg ;
wire Start_signal_i ;
wire Done_signal_o ;
wire w_r_signal_i ;
wire nreset_c ;
wire clk_c ;
wire [31:8] rdata_Z;
wire GND ;
wire VCC ;
// @5:7724
  Flash_Ctroller_64K u_Flash_Ctroller_64K (
	.clk(clk_c),
	.nreset(nreset_c),
	.wdata_i({wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, GND, wdata_0, GND, GND, GND, wdata_0, GND, GND, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, wdata_0, GND, wdata_0, GND, wdata_0, GND, GND, GND}),
	.w_r_signal(w_r_signal_i),
	.wxaddr_i({GND, GND, GND, GND, GND}),
	.wyaddr_i({GND, GND, GND, GND, GND, GND}),
	.Done_signal(Done_signal_o),
	.Start_signal(Start_signal_i),
	.rdata_o({rdata_Z[31:8], rdata[7:0]}),
	.erase_i(erase_reg)
);
// @5:7720
  GSR GSR_INST (
	.GSRI(VCC)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* Gowin_Flash_Controller_Top */

module tb (
  clk,
  nreset,
  key,
  key2,
  rdata_wire
)
;
input clk ;
input nreset ;
input key ;
input key2 ;
output [7:0] rdata_wire ;
wire clk ;
wire nreset ;
wire key ;
wire key2 ;
wire [3:3] wdata;
wire [7:0] rdata;
wire [10:0] i;
wire [9:0] i_ns;
wire [7:0] rdata_wire_c;
wire [0:0] i_ns_0_a2_0_4;
wire [0:0] i_ns_0_a2_0_5;
wire [0:0] i_ns_0_a2_0_6;
wire [0:0] i_ns_0_0;
wire GND ;
wire erase_reg ;
wire Done_signal_o ;
wire Start_signal_i ;
wire w_r_signal_i ;
wire key1_temp1 ;
wire key2_temp1 ;
wire VCC ;
wire rdata_reg_1_sqmuxa ;
wire key1_temp2 ;
wire key2_temp2 ;
wire key_write ;
wire erase_reg_3 ;
wire N_1 ;
wire N_2 ;
wire N_3 ;
wire N_4 ;
wire N_5 ;
wire N_6 ;
wire N_7 ;
wire N_8 ;
wire N_9 ;
wire N_10 ;
wire N_11 ;
wire un1_i_2_0_a3_0_a2 ;
wire un1_i_2_0_a3_0_o2 ;
wire clk_c ;
wire nreset_c ;
wire key_c ;
wire key2_c ;
wire nreset_c_i ;
wire N_57_i ;
wire N_48_i ;
wire N_35_i ;
wire N_34_i ;
wire N_37_i ;
wire un1_i_2_0_a3_0_a2_2 ;
// @6:55
  INV nreset_c_i_cZ (
	.I(nreset_c),
	.O(nreset_c_i)
);
// @6:55
  LUT4 \i_ns_0[0]  (
	.I0(i_ns_0_0[0]),
	.I1(i_ns_0_a2_0_4[0]),
	.I2(i_ns_0_a2_0_5[0]),
	.I3(i_ns_0_a2_0_6[0]),
	.F(i_ns[0])
);
defparam \i_ns_0[0] .INIT=16'hEAAA;
// @6:68
  LUT4 un1_i_2_0_a3_0_a2_cZ (
	.I0(un1_i_2_0_a3_0_o2),
	.I1(i[9]),
	.I2(i[10]),
	.I3(un1_i_2_0_a3_0_a2_2),
	.F(un1_i_2_0_a3_0_a2)
);
defparam un1_i_2_0_a3_0_a2_cZ.INIT=16'h0200;
// @6:55
  LUT4 N_37_i_cZ (
	.I0(i[3]),
	.I1(i[4]),
	.I2(i[7]),
	.I3(i[8]),
	.F(N_37_i)
);
defparam N_37_i_cZ.INIT=16'hFFFE;
// @6:55
  LUT3 N_34_i_cZ (
	.I0(i[0]),
	.I1(i[3]),
	.I2(i[7]),
	.F(N_34_i)
);
defparam N_34_i_cZ.INIT=8'hFE;
// @6:55
  LUT2 N_35_i_cZ (
	.I0(i[0]),
	.I1(key_write),
	.F(N_35_i)
);
defparam N_35_i_cZ.INIT=4'h8;
// @6:55
  LUT3 \i_ns_a3_0_a2[6]  (
	.I0(un1_i_2_0_a3_0_o2),
	.I1(key2_temp1),
	.I2(key2_temp2),
	.F(i_ns[6])
);
defparam \i_ns_a3_0_a2[6] .INIT=8'h10;
// @6:68
  LUT4 erase_reg_3_f0_0_0 (
	.I0(erase_reg),
	.I1(i[0]),
	.I2(i[1]),
	.I3(key_write),
	.F(erase_reg_3)
);
defparam erase_reg_3_f0_0_0.INIT=16'h0E0A;
// @6:55
  LUT4 \i_ns_0_a2_0_6_cZ[0]  (
	.I0(i[1]),
	.I1(i[2]),
	.I2(i[6]),
	.I3(key_write),
	.F(i_ns_0_a2_0_6[0])
);
defparam \i_ns_0_a2_0_6_cZ[0] .INIT=16'h0001;
// @6:55
  LUT2 N_48_i_cZ (
	.I0(Done_signal_o),
	.I1(i[2]),
	.F(N_48_i)
);
defparam N_48_i_cZ.INIT=4'h8;
// @6:55
  LUT2 N_57_i_cZ (
	.I0(Done_signal_o),
	.I1(i[9]),
	.F(N_57_i)
);
defparam N_57_i_cZ.INIT=4'h8;
// @6:55
  LUT3 \i_ns_0[9]  (
	.I0(Done_signal_o),
	.I1(i[8]),
	.I2(i[9]),
	.F(i_ns[9])
);
defparam \i_ns_0[9] .INIT=8'hDC;
// @6:55
  LUT3 \i_ns_0[5]  (
	.I0(Done_signal_o),
	.I1(i[4]),
	.I2(i[5]),
	.F(i_ns[5])
);
defparam \i_ns_0[5] .INIT=8'hDC;
// @6:55
  LUT3 \i_ns_0[2]  (
	.I0(Done_signal_o),
	.I1(i[1]),
	.I2(i[2]),
	.F(i_ns[2])
);
defparam \i_ns_0[2] .INIT=8'hDC;
// @6:55
  LUT4 \i_ns_0_a2_0_4_cZ[0]  (
	.I0(i[4]),
	.I1(i[5]),
	.I2(i[8]),
	.I3(i[9]),
	.F(i_ns_0_a2_0_4[0])
);
defparam \i_ns_0_a2_0_4_cZ[0] .INIT=16'h0001;
// @6:55
  LUT4 \i_ns_0_a2_0_5_cZ[0]  (
	.I0(i[3]),
	.I1(i[7]),
	.I2(key2_temp1),
	.I3(key2_temp2),
	.F(i_ns_0_a2_0_5[0])
);
defparam \i_ns_0_a2_0_5_cZ[0] .INIT=16'h1011;
// @6:68
  LUT3 un1_i_2_0_a3_0_a2_2_cZ (
	.I0(i[2]),
	.I1(i[5]),
	.I2(i[6]),
	.F(un1_i_2_0_a3_0_a2_2)
);
defparam un1_i_2_0_a3_0_a2_2_cZ.INIT=8'h01;
// @6:55
  LUT3 \i_ns_0_0_cZ[0]  (
	.I0(Done_signal_o),
	.I1(i[5]),
	.I2(i[10]),
	.F(i_ns_0_0[0])
);
defparam \i_ns_0_0_cZ[0] .INIT=8'hF8;
// @6:156
  LUT2 rdata_reg_1_sqmuxa_cZ (
	.I0(i[10]),
	.I1(nreset_c),
	.F(rdata_reg_1_sqmuxa)
);
defparam rdata_reg_1_sqmuxa_cZ.INIT=4'h8;
// @6:38
  LUT2 key_write_cZ (
	.I0(key1_temp1),
	.I1(key1_temp2),
	.F(key_write)
);
defparam key_write_cZ.INIT=4'h4;
// @6:68
  LUT3 un1_i_2_0_a3_0_o2_cZ (
	.I0(i[0]),
	.I1(key1_temp1),
	.I2(key1_temp2),
	.F(un1_i_2_0_a3_0_o2)
);
defparam un1_i_2_0_a3_0_o2_cZ.INIT=8'h75;
// @6:55
  DFFP \i_Z[0]  (
	.Q(i[0]),
	.D(i_ns[0]),
	.CLK(clk_c),
	.PRESET(nreset_c_i)
);
// @6:18
  DFFC key2_temp2_Z (
	.Q(key2_temp2),
	.D(key2_temp1),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:18
  DFFC key1_temp2_Z (
	.Q(key1_temp2),
	.D(key1_temp1),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:18
  DFFC key2_temp1_Z (
	.Q(key2_temp1),
	.D(key2_c),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:18
  DFFC key1_temp1_Z (
	.Q(key1_temp1),
	.D(key_c),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[10]  (
	.Q(i[10]),
	.D(N_57_i),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[9]  (
	.Q(i[9]),
	.D(i_ns[9]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[8]  (
	.Q(i[8]),
	.D(i[7]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[7]  (
	.Q(i[7]),
	.D(i[6]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[6]  (
	.Q(i[6]),
	.D(i_ns[6]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[5]  (
	.Q(i[5]),
	.D(i_ns[5]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[4]  (
	.Q(i[4]),
	.D(i[3]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[3]  (
	.Q(i[3]),
	.D(N_48_i),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[2]  (
	.Q(i[2]),
	.D(i_ns[2]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFC \i_Z[1]  (
	.Q(i[1]),
	.D(N_35_i),
	.CLK(clk_c),
	.CLEAR(nreset_c_i)
);
// @6:55
  DFFCE \wdata[18]  (
	.Q(wdata[3]),
	.D(VCC),
	.CLK(clk_c),
	.CLEAR(nreset_c_i),
	.CE(i[3])
);
// @6:55
  DFFE \rdata_reg[7]  (
	.Q(rdata_wire_c[7]),
	.D(rdata[7]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[6]  (
	.Q(rdata_wire_c[6]),
	.D(rdata[6]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[5]  (
	.Q(rdata_wire_c[5]),
	.D(rdata[5]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[4]  (
	.Q(rdata_wire_c[4]),
	.D(rdata[4]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[3]  (
	.Q(rdata_wire_c[3]),
	.D(rdata[3]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[2]  (
	.Q(rdata_wire_c[2]),
	.D(rdata[2]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[1]  (
	.Q(rdata_wire_c[1]),
	.D(rdata[1]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFE \rdata_reg[0]  (
	.Q(rdata_wire_c[0]),
	.D(rdata[0]),
	.CLK(clk_c),
	.CE(rdata_reg_1_sqmuxa)
);
// @6:55
  DFFCE Start_signal_i_Z (
	.Q(Start_signal_i),
	.D(N_34_i),
	.CLK(clk_c),
	.CLEAR(nreset_c_i),
	.CE(un1_i_2_0_a3_0_a2)
);
// @6:55
  DFFCE w_r_signal_i_Z (
	.Q(w_r_signal_i),
	.D(i[3]),
	.CLK(clk_c),
	.CLEAR(nreset_c_i),
	.CE(N_37_i)
);
// @6:55
  DFFE erase_reg_Z (
	.Q(erase_reg),
	.D(erase_reg_3),
	.CLK(clk_c),
	.CE(nreset_c)
);
// @6:5
  IBUF clk_ibuf (
	.O(clk_c),
	.I(clk)
);
// @6:6
  IBUF nreset_ibuf (
	.O(nreset_c),
	.I(nreset)
);
// @6:7
  IBUF key_ibuf (
	.O(key_c),
	.I(key)
);
// @6:8
  IBUF key2_ibuf (
	.O(key2_c),
	.I(key2)
);
// @6:9
  OBUF \rdata_wire_obuf[0]  (
	.O(rdata_wire[0]),
	.I(rdata_wire_c[0])
);
// @6:9
  OBUF \rdata_wire_obuf[1]  (
	.O(rdata_wire[1]),
	.I(rdata_wire_c[1])
);
// @6:9
  OBUF \rdata_wire_obuf[2]  (
	.O(rdata_wire[2]),
	.I(rdata_wire_c[2])
);
// @6:9
  OBUF \rdata_wire_obuf[3]  (
	.O(rdata_wire[3]),
	.I(rdata_wire_c[3])
);
// @6:9
  OBUF \rdata_wire_obuf[4]  (
	.O(rdata_wire[4]),
	.I(rdata_wire_c[4])
);
// @6:9
  OBUF \rdata_wire_obuf[5]  (
	.O(rdata_wire[5]),
	.I(rdata_wire_c[5])
);
// @6:9
  OBUF \rdata_wire_obuf[6]  (
	.O(rdata_wire[6]),
	.I(rdata_wire_c[6])
);
// @6:9
  OBUF \rdata_wire_obuf[7]  (
	.O(rdata_wire[7]),
	.I(rdata_wire_c[7])
);
// @6:156
  Gowin_Flash_Controller_Top Gowin_Flash_Controller_template (
	.rdata(rdata[7:0]),
	.wdata_0(wdata[3]),
	.erase_reg(erase_reg),
	.Start_signal_i(Start_signal_i),
	.Done_signal_o(Done_signal_o),
	.w_r_signal_i(w_r_signal_i),
	.nreset_c(nreset_c),
	.clk_c(clk_c)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* tb */

