Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_REG_IF\project\impl\synthesize\rev_1\FLASH608K_REG_IF.vm
Physical Constraints File | C:\Users\qinfei\Desktop\Gowin_Flash_Controller\FLASH608K_REG_IF\project\src\FLASH608K_REG_IF.cst
Timing Constraint File | ---
GOWIN version | V1.9.2.01Beta
Part Number | GW1N-LV9LQ144C6/I5
Created Time | Tue Oct 22 17:13:08 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 1052
Numbers of Endpoints Analyzed | 979
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 113.220(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.168 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.232
2 | 1.236 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.164
3 | 1.329 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.071
4 | 1.339 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.061
5 | 1.346 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.054
6 | 1.596 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.804
7 | 1.631 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.769
8 | 1.693 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.707
9 | 1.802 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.598
10 | 1.812 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/nvs_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.588
11 | 2.030 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.370
12 | 2.071 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.329
13 | 2.083 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.317
14 | 2.173 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.227
15 | 2.177 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.223
16 | 2.336 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.064
17 | 2.692 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[3]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.708
18 | 2.952 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.448
19 | 3.030 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.370
20 | 3.054 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.346
21 | 3.086 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.314
22 | 3.169 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.231
23 | 3.184 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.216
24 | 3.253 | key1_temp1_Z/Q | i_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.147
25 | 3.255 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.145

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.571 | i_Z[6]/Q | i_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.571
2 | 0.708 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
3 | 0.708 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
4 | 0.708 | i_Z[9]/Q | i_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.708
5 | 0.709 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
6 | 0.709 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
7 | 0.709 | i_Z[5]/Q | i_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709
8 | 0.711 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
9 | 0.711 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.711
10 | 0.837 | i_Z[7]/Q | i_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.837
11 | 0.842 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.842
12 | 0.881 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[13]/Q | rdata_reg[13]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.881
13 | 0.892 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.892
14 | 0.892 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.892
15 | 0.893 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.893
16 | 0.893 | erase_reg_Z/Q | erase_reg_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.893
17 | 0.894 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.894
18 | 0.894 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.894
19 | 0.895 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.895
20 | 0.895 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.895
21 | 0.896 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.896
22 | 0.898 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.898
23 | 0.908 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[1]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.908
24 | 0.942 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[5]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.942
25 | 0.942 | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[3]/Q | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.942

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[0]
2 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | key1_temp2_Z
3 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[9]
4 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | i_Z[1]
5 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | rdata_reg[17]
6 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/wdata_Z[10]
7 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[27]
8 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[6]
9 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[5]
10 | 2.475 | 3.725 | 1.250 | Low Pulse Width | DEFAULT_CLK | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[26]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.168
Data Arrival Time | 12.554
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
9.984 | 0.057 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
9.984 | 0.000 | tNET | FF | 2 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
10.041 | 0.057 | tINS | FF | 1 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
10.041 | 0.000 | tNET | FF | 2 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
10.098 | 0.057 | tINS | FF | 1 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
10.098 | 0.000 | tNET | FF | 2 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
10.155 | 0.057 | tINS | FF | 1 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/COUT
10.155 | 0.000 | tNET | FF | 2 | R21C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[17]/CIN
10.718 | 0.563 | tINS | FF | 1 | R21C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[17]/SUM
11.522 | 0.804 | tNET | FF | 1 | R21C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[17]/I3
12.554 | 1.032 | tINS | FF | 1 | R21C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[17]/F
12.554 | 0.000 | tNET | FF | 1 | R21C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]
13.722 | -0.400 | tSu |  | 1 | R21C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[17]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 4.032, 48.978%; route: 3.742, 45.455%; tC2Q: 0.458, 5.567%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path2

Path Summary:

Slack | 1.236
Data Arrival Time | 12.486
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
10.205 | 0.563 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/SUM
11.664 | 1.459 | tNET | FF | 1 | R21C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[8]/I3
12.486 | 0.822 | tINS | FF | 1 | R21C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[8]/F
12.486 | 0.000 | tNET | FF | 1 | R21C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]
13.722 | -0.400 | tSu |  | 1 | R21C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.309, 40.531%; route: 4.397, 53.855%; tC2Q: 0.458, 5.614%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path3

Path Summary:

Slack | 1.329
Data Arrival Time | 12.393
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
10.490 | 0.563 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/SUM
11.294 | 0.804 | tNET | FF | 1 | R21C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[13]/I3
12.393 | 1.099 | tINS | FF | 1 | R21C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[13]/F
12.393 | 0.000 | tNET | FF | 1 | R21C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]
13.722 | -0.400 | tSu |  | 1 | R21C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[13]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.871, 47.960%; route: 3.742, 46.362%; tC2Q: 0.458, 5.679%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path4

Path Summary:

Slack | 1.339
Data Arrival Time | 12.383
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
9.984 | 0.057 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
9.984 | 0.000 | tNET | FF | 2 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
10.547 | 0.563 | tINS | FF | 1 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/SUM
11.351 | 0.804 | tNET | FF | 1 | R20C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[14]/I3
12.383 | 1.032 | tINS | FF | 1 | R20C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[14]/F
12.383 | 0.000 | tNET | FF | 1 | R20C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]
13.722 | -0.400 | tSu |  | 1 | R20C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.861, 47.895%; route: 3.742, 46.419%; tC2Q: 0.458, 5.686%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path5

Path Summary:

Slack | 1.346
Data Arrival Time | 12.376
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
9.984 | 0.057 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
9.984 | 0.000 | tNET | FF | 2 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
10.041 | 0.057 | tINS | FF | 1 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
10.041 | 0.000 | tNET | FF | 2 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
10.098 | 0.057 | tINS | FF | 1 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
10.098 | 0.000 | tNET | FF | 2 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
10.155 | 0.057 | tINS | FF | 1 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/COUT
10.155 | 0.000 | tNET | FF | 2 | R21C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[17]/CIN
10.212 | 0.057 | tINS | FF | 1 | R21C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[17]/COUT
10.212 | 0.000 | tNET | FF | 2 | R21C9[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_s_0[18]/CIN
10.775 | 0.563 | tINS | FF | 1 | R21C9[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_s_0[18]/SUM
11.750 | 0.975 | tNET | FF | 1 | R21C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[18]/I3
12.376 | 0.626 | tINS | FF | 1 | R21C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[18]/F
12.376 | 0.000 | tNET | FF | 1 | R21C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]
13.722 | -0.400 | tSu |  | 1 | R21C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[18]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.683, 45.731%; route: 3.912, 48.578%; tC2Q: 0.458, 5.691%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path6

Path Summary:

Slack | 1.596
Data Arrival Time | 12.126
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
9.984 | 0.057 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
9.984 | 0.000 | tNET | FF | 2 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
10.041 | 0.057 | tINS | FF | 1 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
10.041 | 0.000 | tNET | FF | 2 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
10.604 | 0.563 | tINS | FF | 1 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/SUM
11.094 | 0.490 | tNET | FF | 1 | R21C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[15]/I3
12.126 | 1.032 | tINS | FF | 1 | R21C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[15]/F
12.126 | 0.000 | tNET | FF | 1 | R21C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]
13.722 | -0.400 | tSu |  | 1 | R21C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.918, 50.205%; route: 3.428, 43.922%; tC2Q: 0.458, 5.873%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path7

Path Summary:

Slack | 1.631
Data Arrival Time | 12.091
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
9.927 | 0.057 | tINS | FF | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/COUT
9.927 | 0.000 | tNET | FF | 2 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/CIN
9.984 | 0.057 | tINS | FF | 1 | R21C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[13]/COUT
9.984 | 0.000 | tNET | FF | 2 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/CIN
10.041 | 0.057 | tINS | FF | 1 | R21C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[14]/COUT
10.041 | 0.000 | tNET | FF | 2 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/CIN
10.098 | 0.057 | tINS | FF | 1 | R21C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[15]/COUT
10.098 | 0.000 | tNET | FF | 2 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/CIN
10.661 | 0.563 | tINS | FF | 1 | R21C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[16]/SUM
11.465 | 0.804 | tNET | FF | 1 | R21C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[16]/I3
12.091 | 0.626 | tINS | FF | 1 | R21C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[16]/F
12.091 | 0.000 | tNET | FF | 1 | R21C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]
13.722 | -0.400 | tSu |  | 1 | R21C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[16]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.569, 45.937%; route: 3.742, 48.164%; tC2Q: 0.458, 5.899%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path8

Path Summary:

Slack | 1.693
Data Arrival Time | 12.028
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/F
8.226 | 0.821 | tNET | FF | 2 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/I0
9.271 | 1.045 | tINS | FF | 1 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/COUT
9.271 | 0.000 | tNET | FF | 2 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/CIN
9.328 | 0.057 | tINS | FF | 1 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
9.328 | 0.000 | tNET | FF | 2 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
9.385 | 0.057 | tINS | FF | 1 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
9.385 | 0.000 | tNET | FF | 2 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
9.442 | 0.057 | tINS | FF | 1 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
9.442 | 0.000 | tNET | FF | 2 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
9.499 | 0.057 | tINS | FF | 1 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
9.499 | 0.000 | tNET | FF | 2 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
9.556 | 0.057 | tINS | FF | 1 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/COUT
9.556 | 0.000 | tNET | FF | 2 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/CIN
9.613 | 0.057 | tINS | FF | 1 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/COUT
9.613 | 0.000 | tNET | FF | 2 | R20C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[21]/CIN
10.176 | 0.563 | tINS | FF | 1 | R20C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[21]/SUM
10.996 | 0.821 | tNET | FF | 1 | R20C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[21]/I3
12.028 | 1.032 | tINS | FF | 1 | R20C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[21]/F
12.028 | 0.000 | tNET | FF | 1 | R20C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]
13.722 | -0.400 | tSu |  | 1 | R20C6[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.804, 49.361%; route: 3.444, 44.692%; tC2Q: 0.458, 5.947%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path9

Path Summary:

Slack | 1.802
Data Arrival Time | 11.920
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
10.319 | 0.563 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/SUM
11.294 | 0.975 | tNET | FF | 1 | R21C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[10]/I3
11.920 | 0.626 | tINS | FF | 1 | R21C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[10]/F
11.920 | 0.000 | tNET | FF | 1 | R21C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]
13.722 | -0.400 | tSu |  | 1 | R21C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.227, 42.474%; route: 3.912, 51.493%; tC2Q: 0.458, 6.033%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path10

Path Summary:

Slack | 1.812
Data Arrival Time | 11.909
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/nvs_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R23C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/nvs_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R23C8[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/nvs_cnt_Z[1]/Q
6.556 | 1.776 | tNET | FF | 1 | R23C8[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_i_0_a2_4_cZ/I0
7.378 | 0.822 | tINS | FF | 10 | R23C8[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_i_0_a2_4_cZ/F
8.710 | 1.332 | tNET | FF | 1 | R20C6[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m56_i_0_a3_0/I2
9.742 | 1.032 | tINS | FF | 1 | R20C6[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m56_i_0_a3_0/F
10.877 | 1.135 | tNET | FF | 1 | R18C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m56_i_0/I0
11.909 | 1.032 | tINS | FF | 1 | R18C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m56_i_0/F
11.909 | 0.000 | tNET | FF | 1 | R18C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]
13.722 | -0.400 | tSu |  | 1 | R18C6[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.886, 38.036%; route: 4.243, 55.923%; tC2Q: 0.458, 6.041%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path11

Path Summary:

Slack | 2.030
Data Arrival Time | 11.692
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
10.262 | 0.563 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/SUM
11.066 | 0.804 | tNET | FF | 1 | R21C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[9]/I3
11.692 | 0.626 | tINS | FF | 1 | R21C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[9]/F
11.692 | 0.000 | tNET | FF | 1 | R21C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]
13.722 | -0.400 | tSu |  | 1 | R21C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.170, 43.010%; route: 3.742, 50.771%; tC2Q: 0.458, 6.219%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path12

Path Summary:

Slack | 2.071
Data Arrival Time | 11.651
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/F
8.226 | 0.821 | tNET | FF | 2 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/I0
9.271 | 1.045 | tINS | FF | 1 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/COUT
9.271 | 0.000 | tNET | FF | 2 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/CIN
9.328 | 0.057 | tINS | FF | 1 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
9.328 | 0.000 | tNET | FF | 2 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
9.385 | 0.057 | tINS | FF | 1 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
9.385 | 0.000 | tNET | FF | 2 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
9.442 | 0.057 | tINS | FF | 1 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
9.442 | 0.000 | tNET | FF | 2 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
9.499 | 0.057 | tINS | FF | 1 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
9.499 | 0.000 | tNET | FF | 2 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
10.062 | 0.563 | tINS | FF | 1 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/SUM
10.552 | 0.490 | tNET | FF | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[19]/I3
11.651 | 1.099 | tINS | FF | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[19]/F
11.651 | 0.000 | tNET | FF | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]
13.722 | -0.400 | tSu |  | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.757, 51.264%; route: 3.113, 42.482%; tC2Q: 0.458, 6.254%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path13

Path Summary:

Slack | 2.083
Data Arrival Time | 11.639
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
9.870 | 0.057 | tINS | FF | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/COUT
9.870 | 0.000 | tNET | FF | 2 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/CIN
10.398 | 0.528 | tINS | FR | 1 | R21C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[12]/SUM
10.817 | 0.419 | tNET | RR | 1 | R21C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[12]/I3
11.639 | 0.822 | tINS | RF | 1 | R21C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[12]/F
11.639 | 0.000 | tNET | FF | 1 | R21C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]
13.722 | -0.400 | tSu |  | 1 | R21C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.502, 47.862%; route: 3.357, 45.874%; tC2Q: 0.458, 6.264%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path14

Path Summary:

Slack | 2.173
Data Arrival Time | 11.549
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/F
8.226 | 0.821 | tNET | FF | 2 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/I0
9.271 | 1.045 | tINS | FF | 1 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/COUT
9.271 | 0.000 | tNET | FF | 2 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/CIN
9.328 | 0.057 | tINS | FF | 1 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
9.328 | 0.000 | tNET | FF | 2 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
9.385 | 0.057 | tINS | FF | 1 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
9.385 | 0.000 | tNET | FF | 2 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
9.442 | 0.057 | tINS | FF | 1 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
9.442 | 0.000 | tNET | FF | 2 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
9.499 | 0.057 | tINS | FF | 1 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
9.499 | 0.000 | tNET | FF | 2 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
9.556 | 0.057 | tINS | FF | 1 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/COUT
9.556 | 0.000 | tNET | FF | 2 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/CIN
10.119 | 0.563 | tINS | FF | 1 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/SUM
10.923 | 0.804 | tNET | FF | 1 | R20C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[20]/I3
11.549 | 0.626 | tINS | FF | 1 | R20C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[20]/F
11.549 | 0.000 | tNET | FF | 1 | R20C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]
13.722 | -0.400 | tSu |  | 1 | R20C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.341, 46.229%; route: 3.428, 47.429%; tC2Q: 0.458, 6.342%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path15

Path Summary:

Slack | 2.177
Data Arrival Time | 11.545
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cp_cZ[0]/F
8.226 | 0.821 | tNET | FF | 2 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/I0
9.271 | 1.045 | tINS | FF | 1 | R20C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[0]/COUT
9.271 | 0.000 | tNET | FF | 2 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/CIN
9.328 | 0.057 | tINS | FF | 1 | R20C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_cp_0[4]/COUT
9.328 | 0.000 | tNET | FF | 2 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/CIN
9.385 | 0.057 | tINS | FF | 1 | R20C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[8]/COUT
9.385 | 0.000 | tNET | FF | 2 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/CIN
9.442 | 0.057 | tINS | FF | 1 | R20C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[12]/COUT
9.442 | 0.000 | tNET | FF | 2 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/CIN
9.499 | 0.057 | tINS | FF | 1 | R20C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[16]/COUT
9.499 | 0.000 | tNET | FF | 2 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/CIN
9.556 | 0.057 | tINS | FF | 1 | R20C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[19]/COUT
9.556 | 0.000 | tNET | FF | 2 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/CIN
9.613 | 0.057 | tINS | FF | 1 | R20C8[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[20]/COUT
9.613 | 0.000 | tNET | FF | 2 | R20C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[21]/CIN
9.670 | 0.057 | tINS | FF | 1 | R20C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[21]/COUT
9.670 | 0.000 | tNET | FF | 2 | R20C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_s_0[22]/CIN
10.233 | 0.563 | tINS | FF | 1 | R20C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_s_0[22]/SUM
10.723 | 0.490 | tNET | FF | 1 | R20C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[22]/I3
11.545 | 0.822 | tINS | FF | 1 | R20C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[22]/F
11.545 | 0.000 | tNET | FF | 1 | R20C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]
13.722 | -0.400 | tSu |  | 1 | R20C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.651, 50.549%; route: 3.113, 43.105%; tC2Q: 0.458, 6.346%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path16

Path Summary:

Slack | 2.336
Data Arrival Time | 11.386
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 4 | R20C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[1]/Q
6.583 | 1.802 | tNET | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/I1
7.405 | 0.822 | tINS | FF | 1 | R20C9[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_0_cZ[0]/F
8.540 | 1.135 | tNET | FF | 2 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/I0
9.585 | 1.045 | tINS | FF | 1 | R21C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[0]/COUT
9.585 | 0.000 | tNET | FF | 2 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/CIN
9.642 | 0.057 | tINS | FF | 1 | R21C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_qxu_par_1[4]/COUT
9.642 | 0.000 | tNET | FF | 2 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/CIN
9.699 | 0.057 | tINS | FF | 1 | R21C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[8]/COUT
9.699 | 0.000 | tNET | FF | 2 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/CIN
9.756 | 0.057 | tINS | FF | 1 | R21C7[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[9]/COUT
9.756 | 0.000 | tNET | FF | 2 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/CIN
9.813 | 0.057 | tINS | FF | 1 | R21C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[10]/COUT
9.813 | 0.000 | tNET | FF | 2 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/CIN
10.341 | 0.528 | tINS | FR | 1 | R21C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_cry_0[11]/SUM
10.760 | 0.419 | tNET | RR | 1 | R21C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[11]/I3
11.386 | 0.626 | tINS | RF | 1 | R21C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_lm_0[11]/F
11.386 | 0.000 | tNET | FF | 1 | R21C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R21C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]
13.722 | -0.400 | tSu |  | 1 | R21C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[11]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.249, 45.995%; route: 3.357, 47.517%; tC2Q: 0.458, 6.488%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path17

Path Summary:

Slack | 2.692
Data Arrival Time | 11.030
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[3]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[3]/CLK
4.780 | 0.458 | tC2Q | RF | 3 | R9C12[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[3]/Q
6.084 | 1.303 | tNET | FF | 1 | R12C11[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_1_sqmuxa_2_i_a2_4_x_cZ/I0
7.116 | 1.032 | tINS | FF | 2 | R12C11[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_1_sqmuxa_2_i_a2_4_x_cZ/F
7.925 | 0.809 | tNET | FF | 1 | R13C10[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_1_sqmuxa_2_i_a2/I0
8.957 | 1.032 | tINS | FF | 1 | R13C10[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_1_sqmuxa_2_i_a2/F
9.931 | 0.975 | tNET | FF | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m27_i_i/I3
11.030 | 1.099 | tINS | FF | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m27_i_i/F
11.030 | 0.000 | tNET | FF | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]
13.722 | -0.400 | tSu |  | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.163, 47.151%; route: 3.087, 46.017%; tC2Q: 0.458, 6.832%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path18

Path Summary:

Slack | 2.952
Data Arrival Time | 10.770
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R20C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_Z[19]/Q
5.610 | 0.829 | tNET | FF | 1 | R20C8[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state23_13_cZ/I2
6.709 | 1.099 | tINS | FF | 1 | R20C8[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state23_13_cZ/F
7.199 | 0.490 | tNET | FF | 1 | R20C10[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state23_19_cZ/I3
8.231 | 1.032 | tINS | FF | 25 | R20C10[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state23_19_cZ/F
9.738 | 1.508 | tNET | FF | 1 | R18C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m65_0_i/I2
10.770 | 1.032 | tINS | FF | 1 | R18C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m65_0_i/F
10.770 | 0.000 | tNET | FF | 1 | R18C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]
13.722 | -0.400 | tSu |  | 1 | R18C6[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.163, 49.052%; route: 2.827, 43.840%; tC2Q: 0.458, 7.108%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path19

Path Summary:

Slack | 3.030
Data Arrival Time | 10.692
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R24C7[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/Q
5.595 | 0.814 | tNET | FF | 1 | R23C6[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_4_cZ/I1
6.656 | 1.061 | tINS | FR | 1 | R23C6[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_4_cZ/F
7.074 | 0.419 | tNET | RR | 1 | R23C7[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_cZ/I1
8.106 | 1.032 | tINS | RF | 10 | R23C7[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_cZ/F
9.593 | 1.486 | tNET | FF | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m82_i_0/I1
10.692 | 1.099 | tINS | FF | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m82_i_0/F
10.692 | 0.000 | tNET | FF | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
13.722 | -0.400 | tSu |  | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.192, 50.111%; route: 2.720, 42.694%; tC2Q: 0.458, 7.195%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path20

Path Summary:

Slack | 3.054
Data Arrival Time | 10.668
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[0]/CLK
4.780 | 0.458 | tC2Q | RF | 1 | R9C12[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[0]/Q
6.238 | 1.458 | tNET | FF | 2 | R12C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[0]/I0
7.283 | 1.045 | tINS | FF | 1 | R12C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[0]/COUT
7.283 | 0.000 | tNET | FF | 2 | R12C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[1]/CIN
7.846 | 0.563 | tINS | FF | 1 | R12C10[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[1]/SUM
9.636 | 1.790 | tNET | FF | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_lm_0[1]/I0
10.668 | 1.032 | tINS | FF | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_lm_0[1]/F
10.668 | 0.000 | tNET | FF | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]
13.722 | -0.400 | tSu |  | 1 | R9C12[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.640, 41.601%; route: 3.248, 51.177%; tC2Q: 0.458, 7.222%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path21

Path Summary:

Slack | 3.086
Data Arrival Time | 10.636
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R24C7[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R24C7[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/whd_cnt_Z[1]/Q
5.595 | 0.814 | tNET | FF | 1 | R23C6[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_4_cZ/I1
6.656 | 1.061 | tINS | FR | 1 | R23C6[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_4_cZ/F
7.074 | 0.419 | tNET | RR | 1 | R23C7[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_cZ/I1
8.106 | 1.032 | tINS | RF | 10 | R23C7[3][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_1_sqmuxa_3_i_i_o2_cZ/F
9.604 | 1.498 | tNET | FF | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m100_i_0/I0
10.636 | 1.032 | tINS | FF | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m100_i_0/F
10.636 | 0.000 | tNET | FF | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
13.722 | -0.400 | tSu |  | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 3.125, 49.492%; route: 2.731, 43.249%; tC2Q: 0.458, 7.259%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path22

Path Summary:

Slack | 3.169
Data Arrival Time | 10.553
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/Q
6.567 | 1.787 | tNET | FF | 2 | R22C12[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_cry_0[5]/I0
7.612 | 1.045 | tINS | FF | 1 | R22C12[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_cry_0[5]/COUT
7.612 | 0.000 | tNET | FF | 2 | R22C13[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_cry_0[6]/CIN
7.669 | 0.057 | tINS | FF | 1 | R22C13[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_cry_0[6]/COUT
7.669 | 0.000 | tNET | FF | 2 | R22C13[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_s_0[7]/CIN
8.232 | 0.563 | tINS | FF | 1 | R22C13[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_s_0[7]/SUM
9.521 | 1.289 | tNET | FF | 1 | R23C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_lm_0[7]/I0
10.553 | 1.032 | tINS | FF | 1 | R23C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_lm_0[7]/F
10.553 | 0.000 | tNET | FF | 1 | R23C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R23C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]
13.722 | -0.400 | tSu |  | 1 | R23C10[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.697, 43.282%; route: 3.076, 49.363%; tC2Q: 0.458, 7.355%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path23

Path Summary:

Slack | 3.184
Data Arrival Time | 10.538
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/CLK
4.780 | 0.458 | tC2Q | RF | 2 | R18C9[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/cps_cnt_Z[5]/Q
5.922 | 1.142 | tNET | FF | 1 | R22C10[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state11_5_cZ/I1
6.954 | 1.032 | tINS | FF | 10 | R22C10[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state11_5_cZ/F
8.271 | 1.317 | tNET | FF | 1 | R20C7[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m25_0_i_a3_0/I1
9.297 | 1.026 | tINS | FR | 1 | R20C7[3][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m25_0_i_a3_0/F
9.716 | 0.419 | tNET | RR | 1 | R20C6[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m25_0_i/I0
10.538 | 0.822 | tINS | RF | 1 | R20C6[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m25_0_i/F
10.538 | 0.000 | tNET | FF | 1 | R20C6[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C6[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]
13.722 | -0.400 | tSu |  | 1 | R20C6[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.880, 46.334%; route: 2.877, 46.292%; tC2Q: 0.458, 7.374%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path24

Path Summary:

Slack | 3.253
Data Arrival Time | 10.469
Data Required Time | 13.722
From | key1_temp1_Z
To | i_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | IOB11[B] | key1_temp1_Z/CLK
4.780 | 0.458 | tC2Q | RF | 3 | IOB11[B] | key1_temp1_Z/Q
6.726 | 1.946 | tNET | FF | 1 | R18C13[0][B] | key_write_cZ/I0
7.548 | 0.822 | tINS | FF | 3 | R18C13[0][B] | key_write_cZ/F
8.363 | 0.815 | tNET | FF | 1 | R21C13[2][A] | i_ns_0_a2_0_6_cZ[0]/I3
9.424 | 1.061 | tINS | FR | 1 | R21C13[2][A] | i_ns_0_a2_0_6_cZ[0]/F
9.843 | 0.419 | tNET | RR | 1 | R20C13[1][A] | i_ns_0[0]/I3
10.469 | 0.626 | tINS | RF | 1 | R20C13[1][A] | i_ns_0[0]/F
10.469 | 0.000 | tNET | FF | 1 | R20C13[1][A] | i_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R20C13[1][A] | i_Z[0]/CLK
14.122 | -0.200 | tUnc |  |  |  | i_Z[0]
13.722 | -0.400 | tSu |  | 1 | R20C13[1][A] | i_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.509, 40.815%; route: 3.180, 51.729%; tC2Q: 0.458, 7.456%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Path25

Path Summary:

Slack | 3.255
Data Arrival Time | 10.467
Data Required Time | 13.722
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
4.322 | 3.340 | tNET | RR | 1 | R9C12[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[2]/CLK
4.780 | 0.458 | tC2Q | RF | 3 | R9C12[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[2]/Q
6.414 | 1.634 | tNET | FF | 2 | R12C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[2]/I0
7.459 | 1.045 | tINS | FF | 1 | R12C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[2]/COUT
7.459 | 0.000 | tNET | FF | 2 | R12C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[3]/CIN
7.516 | 0.057 | tINS | FF | 1 | R12C10[2][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[3]/COUT
7.516 | 0.000 | tNET | FF | 2 | R12C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[4]/CIN
8.079 | 0.563 | tINS | FF | 1 | R12C11[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_cry_0[4]/SUM
9.368 | 1.289 | tNET | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_lm_0[4]/I0
10.467 | 1.099 | tINS | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_lm_0[4]/F
10.467 | 0.000 | tNET | FF | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
10.982 | 0.982 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
14.322 | 3.340 | tNET | RR | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]/CLK
14.122 | -0.200 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]
13.722 | -0.400 | tSu |  | 1 | R9C12[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/pgs_cnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%
Arrival Data Path Delay | cell: 2.764, 44.980%; route: 2.923, 47.562%; tC2Q: 0.458, 7.459%
Required Clock Path Delay | cell: 0.982, 22.718%; route: 3.340, 77.282%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.571
Data Arrival Time | 3.911
Data Required Time | 3.340
From | i_Z[6]
To | i_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R20C13[0][B] | i_Z[6]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R20C13[0][B] | i_Z[6]/Q
3.911 | 0.238 | tNET | RR | 1 | R20C13[2][B] | i_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R20C13[2][B] | i_Z[7]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[7]
3.340 | 0.000 | tHld |  | 1 | R20C13[2][B] | i_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path2

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/Q
3.676 | 0.002 | tNET | RR | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/N_46_i_cZ/I0
4.048 | 0.372 | tINS | RF | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/N_46_i_cZ/F
4.048 | 0.000 | tNET | FF | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z
3.340 | 0.000 | tHld |  | 1 | R11C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/as_cnt_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path3

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/Q
3.676 | 0.002 | tNET | RR | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/N_31_i_cZ/I2
4.048 | 0.372 | tINS | RF | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/N_31_i_cZ/F
4.048 | 0.000 | tNET | FF | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]
3.340 | 0.000 | tHld |  | 1 | R11C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/wait_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path4

Path Summary:

Slack | 0.708
Data Arrival Time | 4.048
Data Required Time | 3.340
From | i_Z[9]
To | i_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R20C13[0][A] | i_Z[9]/CLK
3.674 | 0.333 | tC2Q | RR | 4 | R20C13[0][A] | i_Z[9]/Q
3.676 | 0.002 | tNET | RR | 1 | R20C13[0][A] | i_ns_0[9]/I2
4.048 | 0.372 | tINS | RF | 1 | R20C13[0][A] | i_ns_0[9]/F
4.048 | 0.000 | tNET | FF | 1 | R20C13[0][A] | i_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R20C13[0][A] | i_Z[9]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[9]
3.340 | 0.000 | tHld |  | 1 | R20C13[0][A] | i_Z[9]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path5

Path Summary:

Slack | 0.709
Data Arrival Time | 4.049
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/CLK
3.674 | 0.333 | tC2Q | RR | 52 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/Q
3.677 | 0.004 | tNET | RR | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m79_i_0/I2
4.049 | 0.372 | tINS | RF | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m79_i_0/F
4.049 | 0.000 | tNET | FF | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]
3.340 | 0.000 | tHld |  | 1 | R17C10[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[9]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path6

Path Summary:

Slack | 0.709
Data Arrival Time | 4.049
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/CLK
3.674 | 0.333 | tC2Q | RR | 3 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/Q
3.677 | 0.004 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt_4_0_a2_0_a3[0]/I0
4.049 | 0.372 | tINS | RF | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt_4_0_a2_0_a3[0]/F
4.049 | 0.000 | tNET | FF | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]
3.340 | 0.000 | tHld |  | 1 | R18C9[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/end_cnt[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path7

Path Summary:

Slack | 0.709
Data Arrival Time | 4.049
Data Required Time | 3.340
From | i_Z[5]
To | i_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R21C13[1][A] | i_Z[5]/CLK
3.674 | 0.333 | tC2Q | RR | 4 | R21C13[1][A] | i_Z[5]/Q
3.677 | 0.004 | tNET | RR | 1 | R21C13[1][A] | i_ns_0[5]/I2
4.049 | 0.372 | tINS | RF | 1 | R21C13[1][A] | i_ns_0[5]/F
4.049 | 0.000 | tNET | FF | 1 | R21C13[1][A] | i_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R21C13[1][A] | i_Z[5]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[5]
3.340 | 0.000 | tHld |  | 1 | R21C13[1][A] | i_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path8

Path Summary:

Slack | 0.711
Data Arrival Time | 4.052
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/CLK
3.674 | 0.333 | tC2Q | RR | 12 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/Q
3.680 | 0.006 | tNET | RR | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m82_i_0/I3
4.052 | 0.372 | tINS | RF | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m82_i_0/F
4.052 | 0.000 | tNET | FF | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]
3.340 | 0.000 | tHld |  | 1 | R18C6[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path9

Path Summary:

Slack | 0.711
Data Arrival Time | 4.052
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/CLK
3.674 | 0.333 | tC2Q | RR | 11 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/Q
3.680 | 0.006 | tNET | RR | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m16_i_0/I3
4.052 | 0.372 | tINS | RF | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m16_i_0/F
4.052 | 0.000 | tNET | FF | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]
3.340 | 0.000 | tHld |  | 1 | R18C7[1][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path10

Path Summary:

Slack | 0.837
Data Arrival Time | 4.177
Data Required Time | 3.340
From | i_Z[7]
To | i_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R20C13[2][B] | i_Z[7]/CLK
3.674 | 0.333 | tC2Q | RR | 4 | R20C13[2][B] | i_Z[7]/Q
4.177 | 0.504 | tNET | RR | 1 | R21C13[2][A] | i_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R21C13[2][A] | i_Z[8]/CLK
3.340 | 0.000 | tUnc |  |  |  | i_Z[8]
3.340 | 0.000 | tHld |  | 1 | R21C13[2][A] | i_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.504, 60.176%; tC2Q: 0.333, 39.824%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path11

Path Summary:

Slack | 0.842
Data Arrival Time | 4.182
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R9C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[2]/CLK
3.674 | 0.333 | tC2Q | RR | 19 | R9C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[2]/Q
4.182 | 0.509 | tNET | RR | 1 | R11C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp
3.340 | 0.000 | tHld |  | 1 | R11C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/se_tmp

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.509, 60.409%; tC2Q: 0.333, 39.591%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path12

Path Summary:

Slack | 0.881
Data Arrival Time | 4.221
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[13]
To | rdata_reg[13]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C5[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[13]/CLK
3.674 | 0.333 | tC2Q | RR | 1 | R16C5[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[13]/Q
4.221 | 0.548 | tNET | RR | 1 | IOL15[A] | rdata_reg[13]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | IOL15[A] | rdata_reg[13]/CLK
3.340 | 0.000 | tUnc |  |  |  | rdata_reg[13]
3.340 | 0.000 | tHld |  | 1 | IOL15[A] | rdata_reg[13]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path13

Path Summary:

Slack | 0.892
Data Arrival Time | 4.232
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/CLK
3.674 | 0.333 | tC2Q | RR | 2 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/Q
3.676 | 0.002 | tNET | RR | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[0]/I2
4.232 | 0.556 | tINS | RR | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[0]/F
4.232 | 0.000 | tNET | RR | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]
3.340 | 0.000 | tHld |  | 1 | R8C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path14

Path Summary:

Slack | 0.892
Data Arrival Time | 4.232
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/CLK
3.674 | 0.333 | tC2Q | RR | 50 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/Q
3.676 | 0.002 | tNET | RR | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m4_i_0/I1
4.232 | 0.556 | tINS | RR | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m4_i_0/F
4.232 | 0.000 | tNET | RR | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]
3.340 | 0.000 | tHld |  | 1 | R11C9[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path15

Path Summary:

Slack | 0.893
Data Arrival Time | 4.233
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/CLK
3.674 | 0.333 | tC2Q | RR | 4 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/Q
3.677 | 0.004 | tNET | RR | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[4]/I3
4.233 | 0.556 | tINS | RR | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_ns_cZ[4]/F
4.233 | 0.000 | tNET | RR | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]
3.340 | 0.000 | tHld |  | 1 | R7C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/r_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path16

Path Summary:

Slack | 0.893
Data Arrival Time | 4.233
Data Required Time | 3.340
From | erase_reg_Z
To | erase_reg_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C13[2][A] | erase_reg_Z/CLK
3.674 | 0.333 | tC2Q | RR | 36 | R18C13[2][A] | erase_reg_Z/Q
3.677 | 0.004 | tNET | RR | 1 | R18C13[2][A] | erase_reg_3_f0_0_0/I0
4.233 | 0.556 | tINS | RR | 1 | R18C13[2][A] | erase_reg_3_f0_0_0/F
4.233 | 0.000 | tNET | RR | 1 | R18C13[2][A] | erase_reg_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C13[2][A] | erase_reg_Z/CLK
3.340 | 0.000 | tUnc |  |  |  | erase_reg_Z
3.340 | 0.000 | tHld |  | 1 | R18C13[2][A] | erase_reg_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path17

Path Summary:

Slack | 0.894
Data Arrival Time | 4.234
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/CLK
3.674 | 0.333 | tC2Q | RR | 14 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/Q
3.678 | 0.005 | tNET | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m27_i_i/I2
4.234 | 0.556 | tINS | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m27_i_i/F
4.234 | 0.000 | tNET | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]
3.340 | 0.000 | tHld |  | 1 | R17C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path18

Path Summary:

Slack | 0.894
Data Arrival Time | 4.234
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/CLK
3.674 | 0.333 | tC2Q | RR | 50 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/Q
3.678 | 0.005 | tNET | RR | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_ns_cZ[2]/I2
4.234 | 0.556 | tINS | RR | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_ns_cZ[2]/F
4.234 | 0.000 | tNET | RR | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]
3.340 | 0.000 | tHld |  | 1 | R15C7[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path19

Path Summary:

Slack | 0.895
Data Arrival Time | 4.236
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/CLK
3.674 | 0.333 | tC2Q | RR | 12 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/Q
3.680 | 0.006 | tNET | RR | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.N_370_i/I3
4.236 | 0.556 | tINS | RR | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.N_370_i/F
4.236 | 0.000 | tNET | RR | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]
3.340 | 0.000 | tHld |  | 1 | R13C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path20

Path Summary:

Slack | 0.895
Data Arrival Time | 4.236
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/CLK
3.674 | 0.333 | tC2Q | RR | 24 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/Q
3.680 | 0.006 | tNET | RR | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_ns_cZ[4]/I2
4.236 | 0.556 | tINS | RR | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_ns_cZ[4]/F
4.236 | 0.000 | tNET | RR | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]
3.340 | 0.000 | tHld |  | 1 | R15C8[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path21

Path Summary:

Slack | 0.896
Data Arrival Time | 4.237
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/CLK
3.674 | 0.333 | tC2Q | RR | 12 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/Q
3.681 | 0.007 | tNET | RR | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m16_i_0/I2
4.237 | 0.556 | tINS | RR | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_ns_9_0_.m16_i_0/F
4.237 | 0.000 | tNET | RR | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]
3.340 | 0.000 | tHld |  | 1 | R16C10[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_WR_UFM/w_state_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 62.025%; route: 0.007, 0.790%; tC2Q: 0.333, 37.185%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path22

Path Summary:

Slack | 0.898
Data Arrival Time | 4.238
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/CLK
3.674 | 0.333 | tC2Q | RR | 21 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/Q
3.682 | 0.008 | tNET | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m100_i_0/I3
4.238 | 0.556 | tINS | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_ns_8_0_.m100_i_0/F
4.238 | 0.000 | tNET | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]
3.340 | 0.000 | tHld |  | 1 | R18C6[2][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/e_state_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.556, 61.943%; route: 0.008, 0.921%; tC2Q: 0.333, 37.136%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path23

Path Summary:

Slack | 0.908
Data Arrival Time | 4.249
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[1]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R15C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[1]/CLK
3.674 | 0.333 | tC2Q | RR | 17 | R15C7[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/state_UFM_Z[1]/Q
4.249 | 0.575 | tNET | RR | 1 | R16C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R16C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z
3.340 | 0.000 | tHld |  | 1 | R16C8[0][A] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/e_command_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.575, 63.307%; tC2Q: 0.333, 36.693%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path24

Path Summary:

Slack | 0.942
Data Arrival Time | 4.282
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[5]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[5]/CLK
3.674 | 0.333 | tC2Q | RR | 1 | R11C8[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[5]/Q
3.910 | 0.236 | tNET | RR | 1 | R11C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/YADR_6_cZ[5]/I1
4.282 | 0.372 | tINS | RF | 1 | R11C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/YADR_6_cZ[5]/F
4.282 | 0.000 | tNET | FF | 1 | R11C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R11C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]
3.340 | 0.000 | tHld |  | 1 | R11C8[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Path25

Path Summary:

Slack | 0.942
Data Arrival Time | 4.282
Data Required Time | 3.340
From | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[3]
To | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[3]/CLK
3.674 | 0.333 | tC2Q | RR | 1 | R12C9[1][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/yadr_tmp[3]/Q
3.910 | 0.236 | tNET | RR | 1 | R12C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/YADR_6_cZ[3]/I1
4.282 | 0.372 | tINS | RF | 1 | R12C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_RD_UFM/YADR_6_cZ[3]/F
4.282 | 0.000 | tNET | FF | 1 | R12C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOL6[B] | clk_ibuf/I
0.844 | 0.844 | tINS | RR | 432 | IOL6[B] | clk_ibuf/O
3.340 | 2.496 | tNET | RR | 1 | R12C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]/CLK
3.340 | 0.000 | tUnc |  |  |  | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]
3.340 | 0.000 | tHld |  | 1 | R12C9[0][B] | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/YADR_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%
Arrival Data Path Delay | cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay | cell: 0.844, 25.279%; route: 2.496, 74.721%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[0]/CLK

### MPW2

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | key1_temp2_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | key1_temp2_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | key1_temp2_Z/CLK

### MPW3

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[9]/CLK

### MPW4

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | i_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | i_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | i_Z[1]/CLK

### MPW5

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | rdata_reg[17]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | rdata_reg[17]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | rdata_reg[17]/CLK

### MPW6

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/wdata_Z[10]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/wdata_Z[10]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/wdata_Z[10]/CLK

### MPW7

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[27]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[27]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[27]/CLK

### MPW8

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[6]/CLK

### MPW9

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[5]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[5]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/u_ER_UFM/rcv_cnt_Z[5]/CLK

### MPW10

MPW Summary:

Slack: | 2.475
Actual Width: | 3.725
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[26]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.984 | 0.984 | tINS | FF | clk_ibuf/O
9.615 | 3.631 | tNET | FF | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[26]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.844 | 0.844 | tINS | RR | clk_ibuf/O
13.340 | 2.496 | tNET | RR | Gowin_Flash_Controller_template/u_Flash_Ctroller_608K/comp_data[26]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
432 | clk_c | 1.168 | 3.631
60 | w_state[8] | 5.951 | 1.891
52 | w_state[9] | 6.490 | 1.352
50 | state_UFM[2] | 4.187 | 2.042
50 | w_state[0] | 5.767 | 2.143
47 | N_64_i | 3.568 | 3.982
36 | erase_reg | 3.672 | 2.021
36 | state_UFM28 | 4.609 | 2.200
32 | rdata_reg_1_sqmuxa | 5.225 | 3.643
29 | e_state[4] | 5.916 | 1.994

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R15C8 | 0.472
R13C10 | 0.444
R10C47 | 0.403
R14C8 | 0.403
R18C6 | 0.403
R20C6 | 0.403
R12C8 | 0.389
R8C8 | 0.389
R15C7 | 0.375
R15C12 | 0.347

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---