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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\SWGowin\Gowin_V1.9.2.01Beta_35214_20191015\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-059

Implementation : rev_1

# Written on Tue Oct 22 17:05:26 2019

##### DESIGN INFO #######################################################

Top View:                "tb"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting       Ending         |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------------
System         tb|clk_sys     |     3.532            |     No paths         |     No paths         |     No paths                         
tb|clk_sys     System         |     3.532            |     No paths         |     No paths         |     No paths                         
tb|clk_sys     tb|clk_sys     |     3.532            |     No paths         |     No paths         |     No paths                         
=========================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:data_in[0]
p:data_in[1]
p:data_in[2]
p:data_in[3]
p:data_in[4]
p:data_in[5]
p:data_in[6]
p:data_in[7]
p:data_in[8]
p:data_in[9]
p:data_in[10]
p:data_in[11]
p:data_in[12]
p:data_in[13]
p:data_in[14]
p:data_in[15]
p:data_in[16]
p:data_in[17]
p:data_in[18]
p:data_in[19]
p:data_in[20]
p:data_in[21]
p:data_in[22]
p:data_in[23]
p:data_in[24]
p:data_in[25]
p:data_in[26]
p:data_in[27]
p:data_in[28]
p:data_in[29]
p:data_in[30]
p:data_in[31]
p:data_in_flag
p:data_out[0]
p:data_out[1]
p:data_out[2]
p:data_out[3]
p:data_out[4]
p:data_out[5]
p:data_out[6]
p:data_out[7]
p:data_out[8]
p:data_out[9]
p:data_out[10]
p:data_out[11]
p:data_out[12]
p:data_out[13]
p:data_out[14]
p:data_out[15]
p:data_out[16]
p:data_out[17]
p:data_out[18]
p:data_out[19]
p:data_out[20]
p:data_out[21]
p:data_out[22]
p:data_out[23]
p:data_out[24]
p:data_out[25]
p:data_out[26]
p:data_out[27]
p:data_out[28]
p:data_out[29]
p:data_out[30]
p:data_out[31]
p:data_out_flag
p:key
p:key2
p:page_address[0]
p:page_address[1]
p:page_address[2]
p:page_address[3]
p:page_address[4]
p:page_address[5]
p:read_en
p:rstn
p:wr_cycle
p:write_en


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
