Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1N-LV2MG132XC7/I6
Device GW1N-2
Created Time Wed Oct 26 11:15:19 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.328s, Peak memory usage = 47.074MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 47.074MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 47.074MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 47.074MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 47.074MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 47.074MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 47.074MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 47.074MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.074MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 47.074MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 47.074MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 47.074MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.488MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 58.488MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 58.488MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.488MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 83
I/O Buf 83
    IBUF 50
    OBUF 33
Register 346
    DFFC 266
    DFFCE 80
LUT 463
    LUT2 88
    LUT3 108
    LUT4 267
INV 1
    INV 1
User Flash 1
    FLASH96KA 1

Resource Utilization Summary

Resource Usage Utilization
Logic 464(464 LUTs, 0 ALUs) / 2304 20%
Register 346 / 2616 13%
  --Register as Latch 0 / 2616 0%
  --Register as FF 346 / 2328 15%
BSRAM 0 / 4 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 20.000 50.0 0.000 10.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 50.0(MHz) 176.3(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 14.328
Data Arrival Time 6.372
Data Required Time 20.700
From u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0
To u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 346 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/CLK
1.336 0.340 tC2Q RF 3 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/Q
1.692 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n257_s21/I1
2.506 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n257_s21/F
2.862 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s20/I1
3.676 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s20/F
4.032 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s19/I1
4.846 0.814 tINS FF 11 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s19/F
5.202 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n263_s19/I1
6.016 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n263_s19/F
6.372 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 346 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0/CLK
20.700 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.257, 60.598%; route: 1.778, 33.084%; tC2Q: 0.340, 6.318%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 14.328
Data Arrival Time 6.372
Data Required Time 20.700
From u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_5_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/e_state_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 346 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_5_s0/CLK
1.336 0.340 tC2Q RF 3 u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_5_s0/Q
1.692 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n264_s20/I1
2.506 0.814 tINS FF 3 u_Flash_Ctroller_96KA/u_ER_UFM/n264_s20/F
2.862 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n276_s21/I1
3.676 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n276_s21/F
4.032 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n277_s21/I1
4.846 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n277_s21/F
5.202 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n277_s20/I1
6.016 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n277_s20/F
6.372 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/e_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 346 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/e_state_2_s0/CLK
20.700 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/e_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.257, 60.598%; route: 1.778, 33.084%; tC2Q: 0.340, 6.318%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 14.378
Data Arrival Time 6.322
Data Required Time 20.700
From u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_1_s0
To u_Flash_Ctroller_96KA/u_WR_UFM/w_state_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 346 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_1_s0/CLK
1.336 0.340 tC2Q RF 5 u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_1_s0/Q
1.692 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n272_s21/I1
2.506 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n272_s21/F
2.862 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n272_s20/I1
3.676 0.814 tINS FF 11 u_Flash_Ctroller_96KA/u_WR_UFM/n272_s20/F
4.032 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n237_s19/I1
4.846 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n237_s19/F
5.202 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n237_s18/I0
5.967 0.765 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n237_s18/F
6.322 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 346 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_0_s0/CLK
20.700 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 14.378
Data Arrival Time 6.322
Data Required Time 20.700
From u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0
To u_Flash_Ctroller_96KA/u_WR_UFM/w_state_1_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 346 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/CLK
1.336 0.340 tC2Q RF 3 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/Q
1.692 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n257_s21/I1
2.506 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n257_s21/F
2.862 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s20/I1
3.676 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s20/F
4.032 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s19/I1
4.846 0.814 tINS FF 11 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s19/F
5.202 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n236_s19/I0
5.967 0.765 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n236_s19/F
6.322 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 346 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_1_s0/CLK
20.700 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_WR_UFM/w_state_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 14.378
Data Arrival Time 6.322
Data Required Time 20.700
From u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_19_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 346 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/CLK
1.336 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/Q
1.692 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n231_s20/I1
2.506 0.814 tINS FF 3 u_Flash_Ctroller_96KA/u_ER_UFM/n231_s20/F
2.862 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n229_s22/I0
3.627 0.765 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n229_s22/F
3.982 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n228_s20/I1
4.797 0.814 tINS FF 4 u_Flash_Ctroller_96KA/u_ER_UFM/n228_s20/F
5.152 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n228_s19/I1
5.967 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n228_s19/F
6.322 0.356 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_19_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 346 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_19_s0/CLK
20.700 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_19_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%