Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1N-LV9LQ144C6/I5
Device GW1N-9
Created Time Mon Oct 24 17:06:50 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.275s, Peak memory usage = 46.594MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 46.594MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 46.594MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 46.594MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 46.594MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 46.594MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.594MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.594MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.594MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 46.594MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 46.594MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 46.594MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 59.633MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 59.633MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 59.633MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 59.633MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 75
I/O Buf 75
    IBUF 42
    OBUF 33
Register 450
    DFF 9
    DFFS 23
    DFFR 1
    DFFC 278
    DFFCE 139
LUT 587
    LUT2 172
    LUT3 136
    LUT4 279
User Flash 1
    FLASH608K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 587(587 LUTs, 0 ALUs) / 8640 7%
Register 450 / 6843 7%
  --Register as Latch 0 / 6843 0%
  --Register as FF 450 / 6843 7%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
wb_clk_i Base 20.000 50.0 0.000 10.000 wb_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 wb_clk_i 50.0(MHz) 130.6(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_5_s0
To u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_0_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 3 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n267_s20/I1
3.382 1.099 tINS FF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n267_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n235_s21/I1
4.961 1.099 tINS FF 3 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n235_s21/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n275_s21/I1
6.540 1.099 tINS FF 9 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n275_s21/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n275_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n275_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_0_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/pgh_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_7_s0
To u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_0_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_7_s0/CLK
1.803 0.458 tC2Q RF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_7_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n258_s20/I1
3.382 1.099 tINS FF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n258_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n234_s20/I1
4.961 1.099 tINS FF 3 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n234_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n234_s19/I1
6.540 1.099 tINS FF 10 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n234_s19/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n266_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/n266_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_0_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_WR_UFM/prog_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0
To u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_14_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/CLK
1.803 0.458 tC2Q RF 5 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/I1
3.382 1.099 tINS FF 7 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/I1
4.961 1.099 tINS FF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/I1
6.540 1.099 tINS FF 4 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_14_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0
To u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_15_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/CLK
1.803 0.458 tC2Q RF 5 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/I1
3.382 1.099 tINS FF 7 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/I1
4.961 1.099 tINS FF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/I1
6.540 1.099 tINS FF 4 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n235_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n235_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_15_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0
To u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_16_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/CLK
1.803 0.458 tC2Q RF 5 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_1_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/I1
3.382 1.099 tINS FF 7 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n246_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/I1
4.961 1.099 tINS FF 2 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n241_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/I1
6.540 1.099 tINS FF 4 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n236_s20/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n234_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/n234_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_16_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 450 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_16_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_608K/u_Flash_Ctroller_608K/u_ER_UFM/erase_cnt_16_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%