Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Mon Oct 24 17:00:15 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.266s, Peak memory usage = 45.957MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.957MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 45.957MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 45.957MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 45.957MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 45.957MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.957MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.957MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.957MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 45.957MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 45.957MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 45.957MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.113MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 58.113MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 58.113MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.113MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 83
I/O Buf 83
    IBUF 50
    OBUF 33
Register 350
    DFFC 270
    DFFCE 80
LUT 467
    LUT2 91
    LUT3 142
    LUT4 234
INV 1
    INV 1
User Flash 1
    FLASH256K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 468(468 LUTs, 0 ALUs) / 4608 10%
Register 350 / 3756 9%
  --Register as Latch 0 / 3756 0%
  --Register as FF 350 / 3756 9%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 20.000 50.0 0.000 10.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 50.0(MHz) 130.6(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_5_s0
To u_Flash_Ctroller_256K/u_ER_UFM/e_state_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.982 0.982 tINS RR 350 clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 3 u_Flash_Ctroller_256K/u_ER_UFM/rcv_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n265_s20/I1
3.382 1.099 tINS FF 3 u_Flash_Ctroller_256K/u_ER_UFM/n265_s20/F
3.862 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n277_s22/I1
4.961 1.099 tINS FF 2 u_Flash_Ctroller_256K/u_ER_UFM/n277_s22/F
5.441 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n278_s21/I1
6.540 1.099 tINS FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n278_s21/F
7.020 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n278_s20/I1
8.119 1.099 tINS FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n278_s20/F
8.599 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.982 0.982 tINS RR 350 clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_2_s0/CLK
20.945 -0.400 tSu 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 12.480
Data Arrival Time 8.465
Data Required Time 20.945
From u_Flash_Ctroller_256K/u_ER_UFM/nhv_cnt_1_s0
To u_Flash_Ctroller_256K/u_ER_UFM/e_state_1_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.982 0.982 tINS RR 350 clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_ER_UFM/nhv_cnt_1_s0/CLK
1.803 0.458 tC2Q RF 5 u_Flash_Ctroller_256K/u_ER_UFM/nhv_cnt_1_s0/Q
2.283 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n256_s21/I1
3.382 1.099 tINS FF 2 u_Flash_Ctroller_256K/u_ER_UFM/n256_s21/F
3.862 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s29/I1
4.961 1.099 tINS FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s29/F
5.441 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s28/I0
6.473 1.032 tINS FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s28/F
6.953 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s27/I0
7.985 1.032 tINS FF 1 u_Flash_Ctroller_256K/u_ER_UFM/n279_s27/F
8.465 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.982 0.982 tINS RR 350 clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_1_s1/CLK
20.945 -0.400 tSu 1 u_Flash_Ctroller_256K/u_ER_UFM/e_state_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.262, 59.857%; route: 2.400, 33.706%; tC2Q: 0.458, 6.437%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.982 0.982 tINS RR 350 clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n289_s19/I2
7.842 0.822 tINS FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n289_s19/F
8.322 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.982 0.982 tINS RR 350 clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0/CLK
20.945 -0.400 tSu 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.982 0.982 tINS RR 350 clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n287_s19/I2
7.842 0.822 tINS FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n287_s19/F
8.322 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.982 0.982 tINS RR 350 clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0/CLK
20.945 -0.400 tSu 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.982 0.982 tINS RR 350 clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n286_s19/I2
7.842 0.822 tINS FF 1 u_Flash_Ctroller_256K/u_WR_UFM/n286_s19/F
8.322 0.480 tNET FF 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.982 0.982 tINS RR 350 clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0/CLK
20.945 -0.400 tSu 1 u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%