Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1NZ-ZV1FN32I2
Device GW1NZ-1
Created Time Mon Oct 24 16:49:27 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.271s, Peak memory usage = 46.527MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 46.527MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 46.527MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 46.527MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 46.527MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.527MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 46.527MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.527MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.527MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 46.527MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 46.527MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 46.527MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.230MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 58.230MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 58.230MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.230MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 82
I/O Buf 82
    IBUF 49
    OBUF 33
Register 341
    DFFC 262
    DFFCE 79
LUT 462
    LUT2 94
    LUT3 99
    LUT4 269
INV 1
    INV 1
User Flash 1
    FLASH64K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 463(463 LUTs, 0 ALUs) / 1152 40%
Register 341 / 939 36%
  --Register as Latch 0 / 939 0%
  --Register as FF 341 / 939 36%
BSRAM 0 / 4 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 20.000 50.0 0.000 10.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 50.0(MHz) 18.7(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -33.580
Data Arrival Time 60.194
Data Required Time 26.614
From u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0
To u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_21_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
6.873 6.873 tINS RR 341 clk_i_ibuf/O
9.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0/CLK
12.622 3.208 tC2Q RF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0/Q
15.982 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n229_s20/I1
23.675 7.693 tINS FF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n229_s20/F
27.035 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n228_s20/I1
34.728 7.693 tINS FF 5 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n228_s20/F
38.088 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n225_s21/I1
45.781 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n225_s21/F
49.141 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n225_s19/I1
56.834 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n225_s19/F
60.194 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
26.873 6.873 tINS RR 341 clk_i_ibuf/O
29.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_21_s0/CLK
26.614 -2.800 tSu 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%
Arrival Data Path Delay: cell: 30.772, 60.598%; route: 16.800, 33.084%; tC2Q: 3.208, 6.318%
Required Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%

Path 2

Path Summary:
Slack -33.580
Data Arrival Time 60.194
Data Required Time 26.614
From u_Flash_Ctroller_64KZ/u_ER_UFM_64K/rcv_cnt_5_s0
To u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
6.873 6.873 tINS RR 341 clk_i_ibuf/O
9.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/rcv_cnt_5_s0/CLK
12.622 3.208 tC2Q RF 3 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/rcv_cnt_5_s0/Q
15.982 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n263_s20/I1
23.675 7.693 tINS FF 3 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n263_s20/F
27.035 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n275_s22/I1
34.728 7.693 tINS FF 3 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n275_s22/F
38.088 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n276_s21/I1
45.781 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n276_s21/F
49.141 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n276_s20/I1
56.834 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n276_s20/F
60.194 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
26.873 6.873 tINS RR 341 clk_i_ibuf/O
29.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_2_s0/CLK
26.614 -2.800 tSu 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%
Arrival Data Path Delay: cell: 30.772, 60.598%; route: 16.800, 33.084%; tC2Q: 3.208, 6.318%
Required Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%

Path 3

Path Summary:
Slack -33.111
Data Arrival Time 59.725
Data Required Time 26.614
From u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0
To u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
6.873 6.873 tINS RR 341 clk_i_ibuf/O
9.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0/CLK
12.622 3.208 tC2Q RF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_14_s0/Q
15.982 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n229_s20/I1
23.675 7.693 tINS FF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n229_s20/F
27.035 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n228_s20/I1
34.728 7.693 tINS FF 5 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n228_s20/F
38.088 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n246_s20/I0
45.312 7.224 tINS FF 23 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n246_s20/F
48.672 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n246_s19/I1
56.365 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n246_s19/F
59.725 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
26.873 6.873 tINS RR 341 clk_i_ibuf/O
29.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_0_s0/CLK
26.614 -2.800 tSu 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/erase_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%
Arrival Data Path Delay: cell: 30.303, 60.231%; route: 16.800, 33.392%; tC2Q: 3.208, 6.377%
Required Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%

Path 4

Path Summary:
Slack -33.111
Data Arrival Time 59.725
Data Required Time 26.614
From u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0
To u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
6.873 6.873 tINS RR 341 clk_i_ibuf/O
9.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0/CLK
12.622 3.208 tC2Q RF 3 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0/Q
15.982 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n216_s20/I1
23.675 7.693 tINS FF 2 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n216_s20/F
27.035 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_1_s4/I1
34.728 7.693 tINS FF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_1_s4/F
38.088 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n223_s21/I0
45.312 7.224 tINS FF 8 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n223_s21/F
48.672 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n223_s19/I1
56.365 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n223_s19/F
59.725 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
26.873 6.873 tINS RR 341 clk_i_ibuf/O
29.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_0_s0/CLK
26.614 -2.800 tSu 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%
Arrival Data Path Delay: cell: 30.303, 60.231%; route: 16.800, 33.392%; tC2Q: 3.208, 6.377%
Required Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%

Path 5

Path Summary:
Slack -33.111
Data Arrival Time 59.725
Data Required Time 26.614
From u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0
To u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
6.873 6.873 tINS RR 341 clk_i_ibuf/O
9.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0/CLK
12.622 3.208 tC2Q RF 3 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/nvs_cnt_5_s0/Q
15.982 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n216_s20/I1
23.675 7.693 tINS FF 2 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n216_s20/F
27.035 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_1_s4/I1
34.728 7.693 tINS FF 4 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_1_s4/F
38.088 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n278_s19/I0
45.312 7.224 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n278_s19/F
48.672 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n278_s17/I1
56.365 7.693 tINS FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/n278_s17/F
59.725 3.360 tNET FF 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
26.873 6.873 tINS RR 341 clk_i_ibuf/O
29.414 2.541 tNET RR 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_0_s0/CLK
26.614 -2.800 tSu 1 u_Flash_Ctroller_64KZ/u_ER_UFM_64K/e_state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%
Arrival Data Path Delay: cell: 30.303, 60.231%; route: 16.800, 33.392%; tC2Q: 3.208, 6.377%
Required Clock Path Delay: cell: 6.873, 73.009%; route: 2.541, 26.991%