Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.09 |
Part Number | GW1N-LV1LQ144C6/I5 |
Device | GW1N-1 |
Created Time | Wed Oct 26 17:10:12 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_Flash_Controller_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.258s, Peak memory usage = 46.754MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.754MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 46.754MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 46.754MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 46.754MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 46.754MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 46.754MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.754MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 46.754MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 46.754MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 46.754MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 46.754MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.383MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 60.383MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 60.383MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.383MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 94 |
I/O Buf | 91 |
    IBUF | 58 |
    OBUF | 33 |
Register | 107 |
    DFFC | 13 |
    DFFCE | 94 |
LUT | 321 |
    LUT2 | 84 |
    LUT3 | 45 |
    LUT4 | 192 |
INV | 2 |
    INV | 2 |
User Flash | 1 |
    FLASH96K | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 323(323 LUTs, 0 ALUs) / 1152 | 28% |
Register | 107 / 1155 | 9% |
  --Register as Latch | 0 / 1155 | 0% |
  --Register as FF | 107 / 1155 | 9% |
BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_i | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_i | 50.0(MHz) | 93.1(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 9.255 |
Data Arrival Time | 11.690 |
Data Required Time | 20.945 |
From | u_GW_USER_FLASH_96K/rcnt_10_s1 |
To | u_GW_USER_FLASH_96K/rcnt_0_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_10_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 6 | u_GW_USER_FLASH_96K/rcnt_10_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/oe_s12/I1 |
3.382 | 1.099 | tINS | FF | 4 | u_GW_USER_FLASH_96K/oe_s12/F |
3.862 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s115/I1 |
4.961 | 1.099 | tINS | FF | 2 | u_GW_USER_FLASH_96K/n1301_s115/F |
5.441 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s107/I1 |
6.540 | 1.099 | tINS | FF | 5 | u_GW_USER_FLASH_96K/n1301_s107/F |
7.020 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/I0 |
8.052 | 1.032 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/F |
8.532 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s103/I1 |
9.631 | 1.099 | tINS | FF | 20 | u_GW_USER_FLASH_96K/n1252_s103/F |
10.111 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1271_s101/I1 |
11.210 | 1.099 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1271_s101/F |
11.690 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/rcnt_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_i | |||
20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
20.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_0_s1/CLK |
20.945 | -0.400 | tSu | 1 | u_GW_USER_FLASH_96K/rcnt_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 6.527, 63.092%; route: 3.360, 32.478%; tC2Q: 0.458, 4.430% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:Slack | 9.255 |
Data Arrival Time | 11.690 |
Data Required Time | 20.945 |
From | u_GW_USER_FLASH_96K/rcnt_10_s1 |
To | u_GW_USER_FLASH_96K/rcnt_1_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_10_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 6 | u_GW_USER_FLASH_96K/rcnt_10_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/oe_s12/I1 |
3.382 | 1.099 | tINS | FF | 4 | u_GW_USER_FLASH_96K/oe_s12/F |
3.862 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s115/I1 |
4.961 | 1.099 | tINS | FF | 2 | u_GW_USER_FLASH_96K/n1301_s115/F |
5.441 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s107/I1 |
6.540 | 1.099 | tINS | FF | 5 | u_GW_USER_FLASH_96K/n1301_s107/F |
7.020 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/I0 |
8.052 | 1.032 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/F |
8.532 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s103/I1 |
9.631 | 1.099 | tINS | FF | 20 | u_GW_USER_FLASH_96K/n1252_s103/F |
10.111 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1270_s101/I1 |
11.210 | 1.099 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1270_s101/F |
11.690 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/rcnt_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_i | |||
20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
20.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_1_s1/CLK |
20.945 | -0.400 | tSu | 1 | u_GW_USER_FLASH_96K/rcnt_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 6.527, 63.092%; route: 3.360, 32.478%; tC2Q: 0.458, 4.430% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:Slack | 9.255 |
Data Arrival Time | 11.690 |
Data Required Time | 20.945 |
From | u_GW_USER_FLASH_96K/rcnt_10_s1 |
To | u_GW_USER_FLASH_96K/rcnt_2_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_10_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 6 | u_GW_USER_FLASH_96K/rcnt_10_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/oe_s12/I1 |
3.382 | 1.099 | tINS | FF | 4 | u_GW_USER_FLASH_96K/oe_s12/F |
3.862 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s115/I1 |
4.961 | 1.099 | tINS | FF | 2 | u_GW_USER_FLASH_96K/n1301_s115/F |
5.441 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s107/I1 |
6.540 | 1.099 | tINS | FF | 5 | u_GW_USER_FLASH_96K/n1301_s107/F |
7.020 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/I0 |
8.052 | 1.032 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/F |
8.532 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s103/I1 |
9.631 | 1.099 | tINS | FF | 20 | u_GW_USER_FLASH_96K/n1252_s103/F |
10.111 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1269_s101/I1 |
11.210 | 1.099 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1269_s101/F |
11.690 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/rcnt_2_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_i | |||
20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
20.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_2_s1/CLK |
20.945 | -0.400 | tSu | 1 | u_GW_USER_FLASH_96K/rcnt_2_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 6.527, 63.092%; route: 3.360, 32.478%; tC2Q: 0.458, 4.430% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:Slack | 9.255 |
Data Arrival Time | 11.690 |
Data Required Time | 20.945 |
From | u_GW_USER_FLASH_96K/rcnt_10_s1 |
To | u_GW_USER_FLASH_96K/rcnt_3_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_10_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 6 | u_GW_USER_FLASH_96K/rcnt_10_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/oe_s12/I1 |
3.382 | 1.099 | tINS | FF | 4 | u_GW_USER_FLASH_96K/oe_s12/F |
3.862 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s115/I1 |
4.961 | 1.099 | tINS | FF | 2 | u_GW_USER_FLASH_96K/n1301_s115/F |
5.441 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s107/I1 |
6.540 | 1.099 | tINS | FF | 5 | u_GW_USER_FLASH_96K/n1301_s107/F |
7.020 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/I0 |
8.052 | 1.032 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/F |
8.532 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s103/I1 |
9.631 | 1.099 | tINS | FF | 20 | u_GW_USER_FLASH_96K/n1252_s103/F |
10.111 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1268_s101/I1 |
11.210 | 1.099 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1268_s101/F |
11.690 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/rcnt_3_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_i | |||
20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
20.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_3_s1/CLK |
20.945 | -0.400 | tSu | 1 | u_GW_USER_FLASH_96K/rcnt_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 6.527, 63.092%; route: 3.360, 32.478%; tC2Q: 0.458, 4.430% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:Slack | 9.255 |
Data Arrival Time | 11.690 |
Data Required Time | 20.945 |
From | u_GW_USER_FLASH_96K/rcnt_10_s1 |
To | u_GW_USER_FLASH_96K/rcnt_4_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_10_s1/CLK |
1.803 | 0.458 | tC2Q | RF | 6 | u_GW_USER_FLASH_96K/rcnt_10_s1/Q |
2.283 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/oe_s12/I1 |
3.382 | 1.099 | tINS | FF | 4 | u_GW_USER_FLASH_96K/oe_s12/F |
3.862 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s115/I1 |
4.961 | 1.099 | tINS | FF | 2 | u_GW_USER_FLASH_96K/n1301_s115/F |
5.441 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1301_s107/I1 |
6.540 | 1.099 | tINS | FF | 5 | u_GW_USER_FLASH_96K/n1301_s107/F |
7.020 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/I0 |
8.052 | 1.032 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1252_s105/F |
8.532 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1252_s103/I1 |
9.631 | 1.099 | tINS | FF | 20 | u_GW_USER_FLASH_96K/n1252_s103/F |
10.111 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/n1267_s101/I1 |
11.210 | 1.099 | tINS | FF | 1 | u_GW_USER_FLASH_96K/n1267_s101/F |
11.690 | 0.480 | tNET | FF | 1 | u_GW_USER_FLASH_96K/rcnt_4_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_i | |||
20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
20.982 | 0.982 | tINS | RR | 107 | clk_i_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | u_GW_USER_FLASH_96K/rcnt_4_s1/CLK |
20.945 | -0.400 | tSu | 1 | u_GW_USER_FLASH_96K/rcnt_4_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 6.527, 63.092%; route: 3.360, 32.478%; tC2Q: 0.458, 4.430% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |