Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Mon Oct 24 17:00:55 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.271s, Peak memory usage = 46.602MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 46.602MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 46.602MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 46.602MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 46.602MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 46.602MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.602MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.602MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 46.602MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 46.602MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 46.602MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 46.602MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.844MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 58.844MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 58.844MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 58.844MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 75
I/O Buf 75
    IBUF 42
    OBUF 33
Register 438
    DFF 8
    DFFS 24
    DFFR 1
    DFFC 270
    DFFCE 135
LUT 567
    LUT2 136
    LUT3 161
    LUT4 270
User Flash 1
    FLASH256K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 567(567 LUTs, 0 ALUs) / 4608 12%
Register 438 / 3756 12%
  --Register as Latch 0 / 3756 0%
  --Register as FF 438 / 3756 12%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
wb_clk_i Base 20.000 50.0 0.000 10.000 wb_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 wb_clk_i 50.0(MHz) 130.6(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.346
Data Arrival Time 8.599
Data Required Time 20.945
From u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0
To u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_0_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0/CLK
1.803 0.458 tC2Q RF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s21/I1
3.382 1.099 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s21/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s20/I1
4.961 1.099 tINS FF 2 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s19/I1
6.540 1.099 tINS FF 11 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s19/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n264_s19/I1
8.119 1.099 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n264_s19/F
8.599 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_0_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 12.413
Data Arrival Time 8.532
Data Required Time 20.945
From u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0
To u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_1_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0/CLK
1.803 0.458 tC2Q RF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/prog_cnt_2_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s21/I1
3.382 1.099 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s21/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s20/I1
4.961 1.099 tINS FF 2 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s20/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s19/I1
6.540 1.099 tINS FF 11 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n232_s19/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n237_s19/I0
8.052 1.032 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n237_s19/F
8.532 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_1_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/w_state_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n289_s19/I2
7.842 0.822 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n289_s19/F
8.322 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n287_s19/I2
7.842 0.822 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n287_s19/F
8.322 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0
To u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0
Launch Clk wb_clk_i[R]
Latch Clk wb_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 wb_clk_i
0.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
0.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
1.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/CLK
1.803 0.458 tC2Q RF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_5_s0/Q
2.283 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/I1
3.382 1.099 tINS FF 2 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n282_s20/F
3.862 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/I1
4.961 1.099 tINS FF 4 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s24/F
5.441 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/I1
6.540 1.099 tINS FF 8 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n231_s22/F
7.020 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n286_s19/I2
7.842 0.822 tINS FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/n286_s19/F
8.322 0.480 tNET FF 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 wb_clk_i
20.000 0.000 tCL RR 1 wb_clk_i_ibuf/I
20.982 0.982 tINS RR 438 wb_clk_i_ibuf/O
21.345 0.363 tNET RR 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0/CLK
20.945 -0.400 tSu 1 u_Wishbone_Master_Top_256K/u_Flash_Ctroller_256K/u_WR_UFM/whd_cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%