Synthesis Messages

Report Title GowinSynthesis Report
Design File /iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/rev_1/gamma_correction.vm
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Created Time Fri Jan 29 09:16:24 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: Gamma_Correction_Top
Part Number: GW2A-LV18PG256C8/I7
Device: GW2A-18

Resource

Resource Usage Summary

I/O Port 105
I/O Buf 77
    IBUF 50
    OBUF 27
Register 80
    DFFC 20
    DFFCE 60
LUT 24
    LUT2 5
    LUT3 18
    LUT4 1
INV 1
    INV 1
BSRAM 1
    SDPB 1

Resource Utilization Summary

Logic 25(25 LUTs, 0 ALUs) / 20736 1%
Register 80 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 80 / 16173 1%
BSRAM 1 / 46 2%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 493.8(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.975
Data Arrival Time 2.766
Data Required Time 10.741
From gamma_top/correction/gamma_controller/waddr_d1_Z[2]
To gamma_top/correction/gamma_rom/mem_mem_0_0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 82 clk_ibuf/O
0.862 0.18 tNET RR 1 gamma_top/correction/gamma_controller/waddr_d1_Z[2]/CLK
1.094 0.232 tC2Q RF 1 gamma_top/correction/gamma_controller/waddr_d1_Z[2]/Q
1.331 0.237 tNET FF 1 gamma_top/correction/gamma_controller/wreR_1/I1
1.886 0.555 tINS FF 1 gamma_top/correction/gamma_controller/wreR_1/F
2.123 0.237 tNET FF 1 gamma_top/correction/gamma_rom/mem_mem_0_0_wenp_cZ/I2
2.585 0.462 tINS FR 1 gamma_top/correction/gamma_rom/mem_mem_0_0_wenp_cZ/F
2.765 0.18 tNET RR 1 gamma_top/correction/gamma_rom/mem_mem_0_0/CEA

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 82 clk_ibuf/O
0.862 0.18 tNET RR 1 gamma_top/correction/gamma_rom/mem_mem_0_0/CLKA

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.017, 53.442%; route: 0.654, 34.367%; tC2Q: 0.232, 12.191%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Synthesis completed successfully!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
Memory peak: 59.1MB