#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
#install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
#OS: Linux 
#Hostname: jinan9110.sdgowin.com

# Fri Jan 29 09:16:14 2021

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/generic/gw2a.v" (library work)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top.v" (library work)
@I:"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top.v":"/iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/define.v" (library work)
@I:"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top.v":"/iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/parameter.v" (library work)
@I:"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top.v":"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/static_macro_define.v" (library work)
@I::"/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top_wrap.v" (library work)
Verilog syntax check successful!
Selecting top level module Gamma_Correction_Top
Running optimization stage 1 on delay_6s_1s .......
Running optimization stage 1 on delay_5s_1s .......
Running optimization stage 1 on delay_1s_1s .......
Running optimization stage 1 on gamma_controller .......
Opening data file ./gamma_curve.dat from directory /iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/.
Running optimization stage 1 on gamma_rom .......
Running optimization stage 1 on gamma_correction .......
Running optimization stage 1 on \~gamma_top.Gamma_Correction_Top  .......
@N:CG364 : gamma_top_wrap.v(16) | Synthesizing module Gamma_Correction_Top in library work.
Running optimization stage 1 on Gamma_Correction_Top .......
Running optimization stage 2 on Gamma_Correction_Top .......
Running optimization stage 2 on \~gamma_top.Gamma_Correction_Top  .......
Running optimization stage 2 on gamma_correction .......
Running optimization stage 2 on gamma_rom .......
Running optimization stage 2 on gamma_controller .......
Running optimization stage 2 on delay_1s_1s .......
Running optimization stage 2 on delay_5s_1s .......
Running optimization stage 2 on delay_6s_1s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jan 29 09:16:14 2021

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475

@N: :  | Running in 64-bit mode 
@N:NF107 : gamma_top_wrap.v(16) | Selected library: work cell: Gamma_Correction_Top view verilog as top level
@N:NF107 : gamma_top_wrap.v(16) | Selected library: work cell: Gamma_Correction_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jan 29 09:16:14 2021

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  gamma_correction_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jan 29 09:16:14 2021

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475

@N: :  | Running in 64-bit mode 
@N:NF107 : gamma_top_wrap.v(16) | Selected library: work cell: Gamma_Correction_Top view verilog as top level
@N:NF107 : gamma_top_wrap.v(16) | Selected library: work cell: Gamma_Correction_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Jan 29 09:16:16 2021

###########################################################]


Premap Report



# Fri Jan 29 09:16:16 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 09:32:57, @1003843


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  gamma_correction_scck.rpt
See clock summary report "/iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/rev_1/gamma_correction_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 238MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 249MB peak: 249MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 332MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 333MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 333MB)

@W:BN117 : gamma_top_wrap.v(67) | Instance gamma_top of partition view:work.\\\~gamma_top\.Gamma_Correction_Top\ (verilog) has no references to its outputs; instance not removed. 
@W:BN117 : gamma_top_wrap.v(67) | Instance gamma_top of partition view:work.\\\~gamma_top\.Gamma_Correction_Top\ (verilog) has no references to its outputs; instance not removed. 

Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 334MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 334MB)



Clock Summary
******************

          Start                        Requested     Requested     Clock        Clock                     Clock
Level     Clock                        Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------------------------
0 -       Gamma_Correction_Top|clk     449.0 MHz     2.227         inferred     Autoconstr_clkgroup_0     96   
===============================================================================================================



Clock Load Summary
***********************

                             Clock     Source        Clock Pin                                       Non-clock Pin     Non-clock Pin
Clock                        Load      Pin           Seq Example                                     Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------------------
Gamma_Correction_Top|clk     96        clk(port)     gamma_top.correction.gamma_rom.mem[7:0].CLK     -                 -            
====================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 port                   89         ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/rev_1/gamma_correction.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 333MB peak: 335MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 333MB peak: 335MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 333MB peak: 335MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 333MB peak: 335MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Fri Jan 29 09:16:18 2021

###########################################################]


Map & Optimize Report



# Fri Jan 29 09:16:18 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 09:32:57, @1003843


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 234MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 249MB peak: 249MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 329MB peak: 330MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 329MB peak: 330MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 329MB peak: 330MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.29ns		  25 /        80
   2		0h:00m:01s		    -1.29ns		  25 /        80

   3		0h:00m:01s		    -1.29ns		  25 /        80

   4		0h:00m:01s		    -1.29ns		  25 /        80

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 329MB peak: 330MB)

Writing Analyst data base /iscsi/share/farm/wenxuan/ISP/GAMMA/On_Board/Ref_Design_0129/fpga_project/src/gamma_correction/temp/GammaCorrection/rev_1/synwork/gamma_correction_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 330MB peak: 330MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 330MB peak: 331MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 330MB peak: 332MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 330MB peak: 332MB)

@W:MT420 :  | Found inferred clock Gamma_Correction_Top|clk with period 2.48ns. Please declare a user-defined clock on port clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Fri Jan 29 09:16:23 2021
#


Top view:               Gamma_Correction_Top
Requested Frequency:    403.2 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.438

                             Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock               Frequency     Frequency     Period        Period        Slack      Type         Group                
----------------------------------------------------------------------------------------------------------------------------------
Gamma_Correction_Top|clk     403.2 MHz     342.7 MHz     2.480         2.918         -0.438     inferred     Autoconstr_clkgroup_0
==================================================================================================================================





Clock Relationships
*******************

Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------
Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------
Gamma_Correction_Top|clk  Gamma_Correction_Top|clk  |  2.480       -0.438  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Gamma_Correction_Top|clk
====================================



Starting Points with Worst Slack
********************************

                                                                    Starting                                                         Arrival           
Instance                                                            Reference                    Type      Pin       Net             Time        Slack 
                                                                    Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.waddr_d1[2]                   Gamma_Correction_Top|clk     DFFCE     Q         waddr_d1[2]     0.243       -0.438
gamma_top.correction.gamma_controller.waddr_d1[1]                   Gamma_Correction_Top|clk     DFFCE     Q         waddr_d1[1]     0.243       -0.417
gamma_top.correction.gamma_controller.rd_cnt[0]                     Gamma_Correction_Top|clk     DFFC      Q         CO0             0.243       0.147 
gamma_top.correction.gamma_controller.rd_cnt[1]                     Gamma_Correction_Top|clk     DFFC      Q         rd_cnt[1]       0.243       0.475 
gamma_top.correction.gamma_controller.waddr_d1[3]                   Gamma_Correction_Top|clk     DFFCE     Q         waddr_d1[3]     0.243       0.559 
gamma_top.correction.gamma_controller.waddr_d1[0]                   Gamma_Correction_Top|clk     DFFCE     Q         waddr_d1[0]     0.243       0.580 
gamma_top.correction.gamma_controller.delay_inpvalid.dReg_4_[0]     Gamma_Correction_Top|clk     DFFC      Q         outvalid_r      0.243       1.519 
gamma_top.correction.gamma_rom.mem_mem_0_0                          Gamma_Correction_Top|clk     SDPB      DO[0]     dout_r[0]       0.317       1.567 
gamma_top.correction.gamma_rom.mem_mem_0_0                          Gamma_Correction_Top|clk     SDPB      DO[1]     dout_r[1]       0.317       1.567 
gamma_top.correction.gamma_rom.mem_mem_0_0                          Gamma_Correction_Top|clk     SDPB      DO[2]     dout_r[2]       0.317       1.567 
=======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                               Starting                                                            Required           
Instance                                       Reference                    Type      Pin     Net                  Time         Slack 
                                               Clock                                                                                  
--------------------------------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_rom.mem_mem_0_0     Gamma_Correction_Top|clk     SDPB      CEA     mem_mem_0_0_wenp     2.442        -0.438
gamma_top.correction.gamma_rom.rd_addr[0]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[0]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[1]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[1]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[2]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[2]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[3]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[3]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[4]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[4]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[5]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[5]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[6]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[6]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[7]      Gamma_Correction_Top|clk     DFFCE     D       rd_addr_5[7]         2.419        0.147 
gamma_top.correction.gamma_rom.rd_addr[0]      Gamma_Correction_Top|clk     DFFCE     CE      un1_rd_addr9_1_i     2.419        0.475 
======================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      2.480
    - Setup time:                            0.038
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.442

    - Propagation time:                      2.880
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.438

    Number of logic level(s):                2
    Starting point:                          gamma_top.correction.gamma_controller.waddr_d1[2] / Q
    Ending point:                            gamma_top.correction.gamma_rom.mem_mem_0_0 / CEA
    The start point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK
    The end   point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLKA

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.waddr_d1[2]     DFFCE     Q        Out     0.243     0.243 r     -         
waddr_d1[2]                                           Net       -        -       0.535     -           1         
gamma_top.correction.gamma_controller.wreR_1          LUT2      I1       In      -         0.778 r     -         
gamma_top.correction.gamma_controller.wreR_1          LUT2      F        Out     0.570     1.348 r     -         
wreR_1                                                Net       -        -       0.535     -           1         
gamma_top.correction.gamma_rom.mem_mem_0_0_wenp       LUT4      I2       In      -         1.883 r     -         
gamma_top.correction.gamma_rom.mem_mem_0_0_wenp       LUT4      F        Out     0.462     2.345 r     -         
mem_mem_0_0_wenp                                      Net       -        -       0.535     -           1         
gamma_top.correction.gamma_rom.mem_mem_0_0            SDPB      CEA      In      -         2.880 r     -         
=================================================================================================================
Total path delay (propagation time + setup) of 2.918 is 1.313(45.0%) logic and 1.605(55.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.480
    - Setup time:                            0.038
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.442

    - Propagation time:                      2.859
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.417

    Number of logic level(s):                2
    Starting point:                          gamma_top.correction.gamma_controller.waddr_d1[1] / Q
    Ending point:                            gamma_top.correction.gamma_rom.mem_mem_0_0 / CEA
    The start point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK
    The end   point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLKA

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.waddr_d1[1]     DFFCE     Q        Out     0.243     0.243 r     -         
waddr_d1[1]                                           Net       -        -       0.535     -           1         
gamma_top.correction.gamma_controller.wreR_1          LUT2      I0       In      -         0.778 r     -         
gamma_top.correction.gamma_controller.wreR_1          LUT2      F        Out     0.549     1.327 r     -         
wreR_1                                                Net       -        -       0.535     -           1         
gamma_top.correction.gamma_rom.mem_mem_0_0_wenp       LUT4      I2       In      -         1.862 r     -         
gamma_top.correction.gamma_rom.mem_mem_0_0_wenp       LUT4      F        Out     0.462     2.324 r     -         
mem_mem_0_0_wenp                                      Net       -        -       0.535     -           1         
gamma_top.correction.gamma_rom.mem_mem_0_0            SDPB      CEA      In      -         2.859 r     -         
=================================================================================================================
Total path delay (propagation time + setup) of 2.897 is 1.292(44.6%) logic and 1.605(55.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.480
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.419

    - Propagation time:                      2.272
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.147

    Number of logic level(s):                2
    Starting point:                          gamma_top.correction.gamma_controller.rd_cnt[0] / Q
    Ending point:                            gamma_top.correction.gamma_rom.rd_addr[0] / D
    The start point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK
    The end   point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.rd_cnt[0]     DFFC      Q        Out     0.243     0.243 r     -         
CO0                                                 Net       -        -       0.596     -           14        
gamma_top.correction.gamma_rom.rd_addr_5_0[0]       LUT3      I2       In      -         0.839 r     -         
gamma_top.correction.gamma_rom.rd_addr_5_0[0]       LUT3      F        Out     0.462     1.301 r     -         
N_143                                               Net       -        -       0.401     -           1         
gamma_top.correction.gamma_rom.rd_addr_5[0]         LUT3      I1       In      -         1.702 r     -         
gamma_top.correction.gamma_rom.rd_addr_5[0]         LUT3      F        Out     0.570     2.272 r     -         
rd_addr_5[0]                                        Net       -        -       0.000     -           1         
gamma_top.correction.gamma_rom.rd_addr[0]           DFFCE     D        In      -         2.272 r     -         
===============================================================================================================
Total path delay (propagation time + setup) of 2.333 is 1.336(57.3%) logic and 0.997(42.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.480
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.419

    - Propagation time:                      2.272
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.147

    Number of logic level(s):                2
    Starting point:                          gamma_top.correction.gamma_controller.rd_cnt[0] / Q
    Ending point:                            gamma_top.correction.gamma_rom.rd_addr[1] / D
    The start point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK
    The end   point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.rd_cnt[0]     DFFC      Q        Out     0.243     0.243 r     -         
CO0                                                 Net       -        -       0.596     -           14        
gamma_top.correction.gamma_rom.rd_addr_5_0[1]       LUT3      I2       In      -         0.839 r     -         
gamma_top.correction.gamma_rom.rd_addr_5_0[1]       LUT3      F        Out     0.462     1.301 r     -         
N_144                                               Net       -        -       0.401     -           1         
gamma_top.correction.gamma_rom.rd_addr_5[1]         LUT3      I1       In      -         1.702 r     -         
gamma_top.correction.gamma_rom.rd_addr_5[1]         LUT3      F        Out     0.570     2.272 r     -         
rd_addr_5[1]                                        Net       -        -       0.000     -           1         
gamma_top.correction.gamma_rom.rd_addr[1]           DFFCE     D        In      -         2.272 r     -         
===============================================================================================================
Total path delay (propagation time + setup) of 2.333 is 1.336(57.3%) logic and 0.997(42.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.480
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.419

    - Propagation time:                      2.272
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.147

    Number of logic level(s):                2
    Starting point:                          gamma_top.correction.gamma_controller.rd_cnt[0] / Q
    Ending point:                            gamma_top.correction.gamma_rom.rd_addr[2] / D
    The start point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK
    The end   point is clocked by            Gamma_Correction_Top|clk [rising] (rise=0.000 fall=1.240 period=2.480) on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
gamma_top.correction.gamma_controller.rd_cnt[0]     DFFC      Q        Out     0.243     0.243 r     -         
CO0                                                 Net       -        -       0.596     -           14        
gamma_top.correction.gamma_rom.rd_addr_5_0[2]       LUT3      I2       In      -         0.839 r     -         
gamma_top.correction.gamma_rom.rd_addr_5_0[2]       LUT3      F        Out     0.462     1.301 r     -         
N_145                                               Net       -        -       0.401     -           1         
gamma_top.correction.gamma_rom.rd_addr_5[2]         LUT3      I1       In      -         1.702 r     -         
gamma_top.correction.gamma_rom.rd_addr_5[2]         LUT3      F        Out     0.570     2.272 r     -         
rd_addr_5[2]                                        Net       -        -       0.000     -           1         
gamma_top.correction.gamma_rom.rd_addr[2]           DFFCE     D        In      -         2.272 r     -         
===============================================================================================================
Total path delay (propagation time + setup) of 2.333 is 1.336(57.3%) logic and 0.997(42.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 333MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 333MB)

---------------------------------------
Resource Usage Report for Gamma_Correction_Top 

Mapping to part: gw2a_18pbga256-8
Cell usage:
DFFC            20 uses
DFFCE           60 uses
GSR             1 use
INV             1 use
SDPB            1 use
LUT2            5 uses
LUT3            18 uses
LUT4            1 use

I/O Register bits:                  0
Register bits not including I/Os:   80 of 15552 (0%)

RAM/ROM usage summary
Block Rams : 1 of 46 (2%)

Total load per clock:
   Gamma_Correction_Top|clk: 82

@S |Mapping Summary:
Total  LUTs: 24 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 332MB peak: 334MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Fri Jan 29 09:16:23 2021

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