Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\Gamma_Correction\data\gamma_top.v
C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\Gamma_Correction\data\gamma_top_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.01
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Nov 01 14:36:42 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gamma_Correction_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 42.813MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.813MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.813MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.813MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.813MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.813MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.813MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.813MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.813MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.813MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.813MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.813MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 50.641MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 50.641MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 50.641MB
Total Time and Memory Usage CPU time = 0h 0m 0.217s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 50.641MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 105
I/O Buf 77
    IBUF 50
    OBUF 27
Register 30
    DFFC 6
    DFFCE 24
LUT 4
    LUT2 1
    LUT4 3
INV 1
    INV 1
BSRAM 3
    SDPB 3

Resource Utilization Summary

Resource Usage Utilization
Logic 5(5 LUTs, 0 ALUs) / 20736 1%
Register 30 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 30 / 16173 1%
BSRAM 3 / 46 7%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 9.496
Data Arrival Time 1.332
Data Required Time 10.828
From gamma_top/valid_r_0_s0
To gamma_top/valid_r_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 36 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/valid_r_0_s0/CLK
1.095 0.232 tC2Q RF 25 gamma_top/valid_r_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/valid_r_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 36 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/valid_r_1_s0/CLK
10.828 -0.035 tSu 1 gamma_top/valid_r_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 9.496
Data Arrival Time 1.332
Data Required Time 10.828
From gamma_top/frame_r_0_s0
To gamma_top/frame_r_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 36 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/frame_r_0_s0/CLK
1.095 0.232 tC2Q RF 1 gamma_top/frame_r_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/frame_r_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 36 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/frame_r_1_s0/CLK
10.828 -0.035 tSu 1 gamma_top/frame_r_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 9.496
Data Arrival Time 1.332
Data Required Time 10.828
From gamma_top/line_r_0_s0
To gamma_top/line_r_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 36 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/line_r_0_s0/CLK
1.095 0.232 tC2Q RF 1 gamma_top/line_r_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/line_r_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 36 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/line_r_1_s0/CLK
10.828 -0.035 tSu 1 gamma_top/line_r_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 9.554
Data Arrival Time 1.273
Data Required Time 10.828
From gamma_top/valid_r_0_s0
To gamma_top/B_dout_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 36 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/valid_r_0_s0/CLK
1.094 0.231 tC2Q RR 25 gamma_top/valid_r_0_s0/Q
1.273 0.180 tNET RR 1 gamma_top/B_dout_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 36 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/B_dout_0_s0/CLK
10.828 -0.035 tSu 1 gamma_top/B_dout_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 9.554
Data Arrival Time 1.273
Data Required Time 10.828
From gamma_top/valid_r_0_s0
To gamma_top/B_dout_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 36 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/valid_r_0_s0/CLK
1.094 0.231 tC2Q RR 25 gamma_top/valid_r_0_s0/Q
1.273 0.180 tNET RR 1 gamma_top/B_dout_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 36 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/B_dout_1_s0/CLK
10.828 -0.035 tSu 1 gamma_top/B_dout_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%