Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\GOWIN SW\V198_01_test\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v D:\GOWIN SW\V198_01_test\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW1N-LV4LQ144C6/I5 |
| Device | GW1N-4B |
| Created Time | Sat Sep 18 11:10:15 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | I2C_MASTER_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.269s, Peak memory usage = 52.848MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 52.848MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 52.848MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 52.848MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 52.848MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 52.848MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 52.848MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 52.848MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 52.848MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 52.848MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 52.848MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 52.848MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.951s, Elapsed time = 0h 0m 0.976s, Peak memory usage = 64.402MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 64.402MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 64.402MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 64.402MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 29 |
| I/O Buf | 29 |
| IBUF | 18 |
| OBUF | 9 |
| IOBUF | 2 |
| Register | 124 |
| DFF | 1 |
| DFFP | 5 |
| DFFPE | 2 |
| DFFC | 23 |
| DFFCE | 93 |
| LUT | 216 |
| LUT2 | 27 |
| LUT3 | 75 |
| LUT4 | 114 |
| INV | 1 |
| INV | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 217(217 LUTs, 0 ALUs) / 4608 | 5% |
| Register | 124 / 3756 | 3% |
| --Register as Latch | 0 / 3756 | 0% |
| --Register as FF | 124 / 3756 | 3% |
| BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_CLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_CLK | 100.0(MHz) | 130.6(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.346 |
| Data Arrival Time | 8.599 |
| Data Required Time | 10.945 |
| From | u_i2c_master/bit_controller/cnt_10_s1 |
| To | u_i2c_master/bit_controller/cnt_14_s1 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_10_s1/CLK |
| 1.803 | 0.458 | tC2Q | RF | 4 | u_i2c_master/bit_controller/cnt_10_s1/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s3/I1 |
| 3.382 | 1.099 | tINS | FF | 1 | u_i2c_master/bit_controller/n13_s3/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
| 4.961 | 1.099 | tINS | FF | 4 | u_i2c_master/bit_controller/n13_s1/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s1/I1 |
| 6.540 | 1.099 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s1/F |
| 7.020 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s0/I1 |
| 8.119 | 1.099 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s0/F |
| 8.599 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/cnt_14_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CLK |
| 10.945 | -0.400 | tSu | 1 | u_i2c_master/bit_controller/cnt_14_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | 2.413 |
| Data Arrival Time | 8.532 |
| Data Required Time | 10.945 |
| From | u_i2c_master/byte_controller/c_state_2_s0 |
| To | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s3/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s3/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s4/I0 |
| 4.894 | 1.032 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s4/F |
| 5.374 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s2/I1 |
| 6.473 | 1.099 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s2/F |
| 6.953 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s1/I1 |
| 8.052 | 1.099 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s1/F |
| 8.532 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
| 10.945 | -0.400 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | 2.413 |
| Data Arrival Time | 8.532 |
| Data Required Time | 10.945 |
| From | u_i2c_master/byte_controller/c_state_2_s0 |
| To | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s3/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s3/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s4/I0 |
| 4.894 | 1.032 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s4/F |
| 5.374 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s2/I1 |
| 6.473 | 1.099 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s2/F |
| 6.953 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/n199_s1/I1 |
| 8.052 | 1.099 | tINS | FF | 1 | u_i2c_master/byte_controller/n199_s1/F |
| 8.532 | 0.480 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK |
| 10.945 | -0.400 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | 2.480 |
| Data Arrival Time | 8.465 |
| Data Required Time | 10.945 |
| From | u_i2c_master/bit_controller/c_state_3_s1 |
| To | u_i2c_master/bit_controller/SDA_OEN_s1 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
| 1.803 | 0.458 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s5/I1 |
| 3.382 | 1.099 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s5/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n226_s3/I1 |
| 4.961 | 1.099 | tINS | FF | 4 | u_i2c_master/bit_controller/n226_s3/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s8/I0 |
| 6.473 | 1.032 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s8/F |
| 6.953 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s1/I0 |
| 7.985 | 1.032 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s1/F |
| 8.465 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
| 10.945 | -0.400 | tSu | 1 | u_i2c_master/bit_controller/SDA_OEN_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.262, 59.857%; route: 2.400, 33.706%; tC2Q: 0.458, 6.437% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | 2.480 |
| Data Arrival Time | 8.465 |
| Data Required Time | 10.945 |
| From | u_i2c_master/bit_controller/c_state_14_s1 |
| To | u_i2c_master/bit_controller/CMD_ACK_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_14_s1/CLK |
| 1.803 | 0.458 | tC2Q | RF | 5 | u_i2c_master/bit_controller/c_state_14_s1/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n123_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 11 | u_i2c_master/bit_controller/n123_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s4/I1 |
| 4.961 | 1.099 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s4/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s2/I0 |
| 6.473 | 1.032 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s2/F |
| 6.953 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s1/I0 |
| 7.985 | 1.032 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s1/F |
| 8.465 | 0.480 | tNET | FF | 1 | u_i2c_master/bit_controller/CMD_ACK_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_i2c_master/bit_controller/CMD_ACK_s0/CLK |
| 10.945 | -0.400 | tSu | 1 | u_i2c_master/bit_controller/CMD_ACK_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.262, 59.857%; route: 2.400, 33.706%; tC2Q: 0.458, 6.437% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |