#Build: Synplify Pro (R) M-2017.03G-SP1, Build 128R, Sep  1 2017
#install: /gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro
#OS: Linux 
#Hostname: jinan9110.sdgowin.com

# Tue Sep 26 09:03:26 2017

#Implementation: rev_1

Synopsys HDL Compiler, version comp2017q2p1, Build 237R, built Sep  5 2017
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys Verilog Compiler, version comp2017q2p1, Build 237R, built Sep  5 2017
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Running on host :jinan9110.sdgowin.com
@N: :  | : Running Verilog Compiler in System Verilog mode 
@N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"/gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro/lib/generic/gw2a.v" (library work)
@I::"/gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/gwsw/gui_proj/sw_test/Gowin/1.7/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/liulie/ref_design/i2c_slave/project/src/i2c_slave_top/i2c_slave_top.v" (library work)
Verilog syntax check successful!
Selecting top level module i2c_slave_top
@N:CG364 : gw2a.v(1597) | Synthesizing module GSR in library work.
@N:CG364 : gw2a.v(360) | Synthesizing module INV in library work.
@N:CG364 : gw2a.v(380) | Synthesizing module IOBUF in library work.



















@N:CG364 : i2c_slave_top.v(3244) | Synthesizing module i2c_slave_top in library work.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 26 09:03:27 2017

###########################################################]
Synopsys Netlist Linker, version comp2017q2p1, Build 237R, built Sep  5 2017
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 26 09:03:27 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 26 09:03:27 2017

###########################################################]


Synopsys Netlist Linker, version comp2017q2p1, Build 237R, built Sep  5 2017
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 26 09:03:28 2017

###########################################################]


Pre-mapping Report



# Tue Sep 26 09:03:28 2017

Synopsys Generic Technology Pre-mapping, Version maprc, Build 910R, Built Sep  1 2017 09:38:49
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03G-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: i2c_slave_scck.rpt
Printing clock  summary report in "/home/liulie/ref_design/i2c_slave/project/impl/synthesize/rev_1/i2c_slave_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=140  set on top level netlist i2c_slave_top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)



Clock Summary
******************

          Start                                                           Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                          150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                                                                  
0 -       i2c_slave_top|clk                                               313.2 MHz     3.193         inferred     Autoconstr_clkgroup_0     93   
                                                                                                                                                  
0 -       _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_1_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_2     2    
                                                                                                                                                  
0 -       _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_2_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_3     2    
                                                                                                                                                  
0 -       _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_3_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_4     2    
                                                                                                                                                  
0 -       _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_1     2    
==================================================================================================================================================


Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file /home/liulie/ref_design/i2c_slave/project/impl/synthesize/rev_1/i2c_slave.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 190MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 26 09:03:30 2017

###########################################################]


Map & Optimize Report



# Tue Sep 26 09:03:30 2017

Synopsys Generic Technology Mapper, Version maprc, Build 910R, Built Sep  1 2017 09:38:49
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03G-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.52ns		 218 /         0
   2		0h:00m:01s		    -2.52ns		 218 /         0

   3		0h:00m:01s		    -2.52ns		 218 /         0

   4		0h:00m:01s		    -2.52ns		 218 /         0

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 93 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 4 clock pin(s) of sequential element(s)
0 instances converted, 4 sequential instances remain driven by gated/generated clocks

============================================= Non-Gated/Non-Generated Clocks ==============================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                    
---------------------------------------------------------------------------------------------------------------------------
ClockId0005        clk                 port                   93         u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_Z
===========================================================================================================================
======================================================================================================== Gated/Generated Clocks ========================================================================================================
Clock Tree ID     Driving Element                                        Drive Element Type     Fanout     Sample Instance                                  Explanation                                                                 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_cZ       LUT2                   1          u_i2c_slave_top_inst.u_i2c_slave.nstate_2_Z      Multiple clocks on instance from nets nstate_1, nstate_2, nstate_0[0]       
ClockId0002        u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_1_cZ     LUT2                   1          u_i2c_slave_top_inst.u_i2c_slave.nstate_6_Z      Multiple clocks on instance from nets nstate_5, nstate_6_scalar, nstate_0[1]
ClockId0003        u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_2_cZ     LUT2                   1          u_i2c_slave_top_inst.u_i2c_slave.nstate_10_Z     Multiple clocks on instance from nets nstate_9, nstate_10, nstate_0[2]      
ClockId0004        u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_3_cZ     LUT2                   1          u_i2c_slave_top_inst.u_i2c_slave.nstate_14_Z     Multiple clocks on instance from nets nstate_13, nstate_14, nstate_0[3]     
========================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 190MB)

Writing Analyst data base /home/liulie/ref_design/i2c_slave/project/impl/synthesize/rev_1/synwork/i2c_slave_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 190MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 186MB peak: 190MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 187MB peak: 190MB)

@W:MT420 :  | Found inferred clock i2c_slave_top|clk with period 6.67ns. Please declare a user-defined clock on object "p:clk" 
@W:MT420 :  | Found inferred clock _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_3_inferred_clock with period 6.67ns. Please declare a user-defined clock on object "n:u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_3" 
@W:MT420 :  | Found inferred clock _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_2_inferred_clock with period 6.67ns. Please declare a user-defined clock on object "n:u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_2" 
@W:MT420 :  | Found inferred clock _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_1_inferred_clock with period 6.67ns. Please declare a user-defined clock on object "n:u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11_1" 
@W:MT420 :  | Found inferred clock _\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_inferred_clock with period 6.67ns. Please declare a user-defined clock on object "n:u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg11" 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 26 09:03:35 2017
#


Top view:               i2c_slave_top
Requested Frequency:    150.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.209

                                                                Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                                                  Frequency     Frequency     Period        Period        Slack      Type         Group                
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_1_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_2
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_2_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_3
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_3_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_4
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_inferred_clock       150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_1
i2c_slave_top|clk                                               150.0 MHz     127.0 MHz     6.667         7.875         -1.209     inferred     Autoconstr_clkgroup_0
System                                                          150.0 MHz     656.4 MHz     6.667         1.524         5.143      system       system_clkgroup      
=====================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                     Ending             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                       i2c_slave_top|clk  |  6.667       5.143   |  No paths    -      |  No paths    -      |  No paths    -    
i2c_slave_top|clk                                            System             |  6.667       2.444   |  No paths    -      |  No paths    -      |  No paths    -    
i2c_slave_top|clk                                            i2c_slave_top|clk  |  6.667       -1.209  |  No paths    -      |  No paths    -      |  No paths    -    
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_inferred_clock    i2c_slave_top|clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_1_inferred_clock  i2c_slave_top|clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_2_inferred_clock  i2c_slave_top|clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
_\~i2c_slave_i2c_slave_top_\ |un1_in_reg11_3_inferred_clock  i2c_slave_top|clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: i2c_slave_top|clk
====================================



Starting Points with Worst Slack
********************************

                                                               Starting                                                        Arrival           
Instance                                                       Reference             Type      Pin     Net                     Time        Slack 
                                                               Clock                                                                             
-------------------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[1\]     i2c_slave_top|clk     DFFRE     Q       bit_counter_fast[1]     0.292       -1.209
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_Z\[3\]          i2c_slave_top|clk     DFFRE     Q       bit_counter[3]          0.292       -1.183
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[2\]     i2c_slave_top|clk     DFFRE     Q       bit_counter_fast[2]     0.292       -1.079
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_Z               i2c_slave_top|clk     DFFCE     Q       w_r_flag_fast           0.292       -0.970
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_Z            i2c_slave_top|clk     DFFC      Q       scl_negedge_fast        0.292       -0.607
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[3\]     i2c_slave_top|clk     DFFRE     Q       bit_counter_fast[3]     0.292       -0.582
u_i2c_slave_top_inst.u_i2c_slave.in_reg_enable_fast_Z          i2c_slave_top|clk     DFFE      Q       in_reg_enable_fast      0.292       -0.536
u_i2c_slave_top_inst.u_i2c_slave.scl_posedge_fast_Z            i2c_slave_top|clk     DFFC      Q       scl_posedge_fast        0.292       -0.456
u_i2c_slave_top_inst.u_i2c_slave.\\cstate_Z\[1\]               i2c_slave_top|clk     DFFC      Q       cstate_17[1]            0.292       -0.278
u_i2c_slave_top_inst.u_i2c_slave.\\cstate_Z\[0\]               i2c_slave_top|clk     DFFC      Q       cstate_17[0]            0.292       -0.253
=================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                               Starting                                                       Required           
Instance                                                       Reference             Type      Pin     Net                    Time         Slack 
                                                               Clock                                                                             
-------------------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                       i2c_slave_top|clk     DFFE      D       clken_4                6.593        -1.209
u_i2c_slave_top_inst.u_i2c_slave.\\cstate_Z\[2\]               i2c_slave_top|clk     DFFC      D       cstate_15[2]           6.593        -0.536
u_i2c_slave_top_inst.u_i2c_slave.wre_reg_Z                     i2c_slave_top|clk     DFFE      CE      wre_reg_0_sqmuxa       6.593        -0.362
u_i2c_slave_top_inst.u_i2c_slave.\\addr_len_reg_Z\[8\]         i2c_slave_top|clk     DFFC      D       addr_len_reg_11[8]     6.593        -0.278
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_Z\[3\]          i2c_slave_top|clk     DFFRE     D       N_17_0                 6.593        -0.253
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[3\]     i2c_slave_top|clk     DFFRE     D       N_17_fast_0            6.593        -0.253
u_i2c_slave_top_inst.u_i2c_slave.\\addr_len_reg_Z\[7\]         i2c_slave_top|clk     DFFC      D       addr_len_reg_11[7]     6.593        -0.236
u_i2c_slave_top_inst.u_i2c_slave.\\addr_len_reg_Z\[6\]         i2c_slave_top|clk     DFFC      D       addr_len_reg_11[6]     6.593        -0.194
u_i2c_slave_top_inst.u_i2c_slave.\\addr_len_reg_Z\[5\]         i2c_slave_top|clk     DFFC      D       addr_len_reg_11[5]     6.593        -0.152
u_i2c_slave_top_inst.u_i2c_slave.\\addr_len_reg_Z\[4\]         i2c_slave_top|clk     DFFC      D       addr_len_reg_11[4]     6.593        -0.110
=================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      7.802
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.209

    Number of logic level(s):                7
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[1\] / Q
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.clken_Z / D
    The start point is clocked by            i2c_slave_top|clk [rising] on pin CLK
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                  Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[1\]            DFFRE         Q        Out     0.292     0.292       -         
bit_counter_fast[1]                                                   Net           -        -       0.535     -           8         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          I1       In      -         0.827       -         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          F        Out     0.684     1.511       -         
g0_2_sx                                                               Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          I1       In      -         1.912       -         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          F        Out     0.684     2.596       -         
in_reg_enable27                                                       Net           -        -       0.535     -           6         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     S0       In      -         3.131       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     O        Out     0.323     3.454       -         
N_180                                                                 Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          I0       In      -         3.989       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          F        Out     0.659     4.647       -         
un1_in_reg_enable24_4_1_cZ                                            Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          I1       In      -         5.182       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          F        Out     0.684     5.866       -         
un1_in_reg_enable24_4_cZ                                              Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          I3       In      -         6.401       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          F        Out     0.445     6.847       -         
clken_0_sqmuxa_d                                                      Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          I2       In      -         7.248       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          F        Out     0.554     7.802       -         
clken_4                                                               Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                              DFFE          D        In      -         7.802       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 7.875 is 4.398(55.8%) logic and 3.477(44.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      7.777
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.184

    Number of logic level(s):                7
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_Z\[3\] / Q
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.clken_Z / D
    The start point is clocked by            i2c_slave_top|clk [rising] on pin CLK
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                  Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_Z\[3\]                 DFFRE         Q        Out     0.292     0.292       -         
bit_counter[3]                                                        Net           -        -       0.535     -           10        
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          I0       In      -         0.827       -         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          F        Out     0.659     1.485       -         
g0_2_sx                                                               Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          I1       In      -         1.887       -         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          F        Out     0.684     2.571       -         
in_reg_enable27                                                       Net           -        -       0.535     -           6         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     S0       In      -         3.106       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     O        Out     0.323     3.428       -         
N_180                                                                 Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          I0       In      -         3.963       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          F        Out     0.659     4.622       -         
un1_in_reg_enable24_4_1_cZ                                            Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          I1       In      -         5.157       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          F        Out     0.684     5.841       -         
un1_in_reg_enable24_4_cZ                                              Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          I3       In      -         6.376       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          F        Out     0.445     6.821       -         
clken_0_sqmuxa_d                                                      Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          I2       In      -         7.223       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          F        Out     0.554     7.777       -         
clken_4                                                               Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                              DFFE          D        In      -         7.777       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 7.850 is 4.373(55.7%) logic and 3.477(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      7.673
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.079

    Number of logic level(s):                7
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[2\] / Q
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.clken_Z / D
    The start point is clocked by            i2c_slave_top|clk [rising] on pin CLK
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                  Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_Z\[2\]            DFFRE         Q        Out     0.292     0.292       -         
bit_counter_fast[2]                                                   Net           -        -       0.535     -           9         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          I2       In      -         0.827       -         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          F        Out     0.554     1.381       -         
g0_2_sx                                                               Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          I1       In      -         1.782       -         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          F        Out     0.684     2.466       -         
in_reg_enable27                                                       Net           -        -       0.535     -           6         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     S0       In      -         3.001       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     O        Out     0.323     3.324       -         
N_180                                                                 Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          I0       In      -         3.859       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          F        Out     0.659     4.518       -         
un1_in_reg_enable24_4_1_cZ                                            Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          I1       In      -         5.053       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          F        Out     0.684     5.737       -         
un1_in_reg_enable24_4_cZ                                              Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          I3       In      -         6.272       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          F        Out     0.445     6.717       -         
clken_0_sqmuxa_d                                                      Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          I2       In      -         7.118       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          F        Out     0.554     7.673       -         
clken_4                                                               Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                              DFFE          D        In      -         7.673       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 7.746 is 4.268(55.1%) logic and 3.477(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      7.563
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.970

    Number of logic level(s):                7
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_Z / Q
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.clken_Z / D
    The start point is clocked by            i2c_slave_top|clk [rising] on pin CLK
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                  Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_Z                      DFFCE         Q        Out     0.292     0.292       -         
w_r_flag_fast                                                         Net           -        -       0.535     -           7         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          I3       In      -         0.827       -         
u_i2c_slave_top_inst.u_i2c_slave.w_r_flag_fast_RNI8LAP                LUT4          F        Out     0.445     1.272       -         
g0_2_sx                                                               Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          I1       In      -         1.673       -         
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_RNICDK51            LUT3          F        Out     0.684     2.357       -         
in_reg_enable27                                                       Net           -        -       0.535     -           6         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     S0       In      -         2.892       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     O        Out     0.323     3.215       -         
N_180                                                                 Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          I0       In      -         3.750       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          F        Out     0.659     4.409       -         
un1_in_reg_enable24_4_1_cZ                                            Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          I1       In      -         4.944       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          F        Out     0.684     5.628       -         
un1_in_reg_enable24_4_cZ                                              Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          I3       In      -         6.163       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          F        Out     0.445     6.608       -         
clken_0_sqmuxa_d                                                      Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          I2       In      -         7.009       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          F        Out     0.554     7.563       -         
clken_4                                                               Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                              DFFE          D        In      -         7.563       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 7.637 is 4.159(54.5%) logic and 3.477(45.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      7.201
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.607

    Number of logic level(s):                8
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_Z / Q
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.clken_Z / D
    The start point is clocked by            i2c_slave_top|clk [rising] on pin CLK
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                  Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.scl_negedge_fast_Z                   DFFC          Q        Out     0.292     0.292       -         
scl_negedge_fast                                                      Net           -        -       0.535     -           3         
u_i2c_slave_top_inst.u_i2c_slave.in_reg_enable28_0_cZ                 LUT2          I1       In      -         0.827       -         
u_i2c_slave_top_inst.u_i2c_slave.in_reg_enable28_0_cZ                 LUT2          F        Out     0.684     1.511       -         
in_reg_enable28_0                                                     Net           -        -       0.535     -           3         
u_i2c_slave_top_inst.u_i2c_slave.in_reg_enable28_0_RNII15U            LUT4          I2       In      -         2.046       -         
u_i2c_slave_top_inst.u_i2c_slave.in_reg_enable28_0_RNII15U            LUT4          F        Out     0.554     2.600       -         
in_reg_enable28_0_RNII15U                                             Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIV5601\[0\]     MUX2_LUT5     I1       In      -         2.600       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIV5601\[0\]     MUX2_LUT5     O        Out     0.126     2.726       -         
Z\\bit_counter_fast_RNIV5601\[0\]                                     Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     I0       In      -         2.726       -         
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNIONR72\[0\]     MUX2_LUT6     O        Out     0.126     2.852       -         
N_180                                                                 Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          I0       In      -         3.387       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_1_cZ           LUT4          F        Out     0.659     4.046       -         
un1_in_reg_enable24_4_1_cZ                                            Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          I1       In      -         4.581       -         
u_i2c_slave_top_inst.u_i2c_slave.un1_in_reg_enable24_4_cZ             LUT4          F        Out     0.684     5.265       -         
un1_in_reg_enable24_4_cZ                                              Net           -        -       0.535     -           2         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          I3       In      -         5.800       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_0_sqmuxa_d_cZ                  LUT4          F        Out     0.445     6.245       -         
clken_0_sqmuxa_d                                                      Net           -        -       0.401     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          I2       In      -         6.646       -         
u_i2c_slave_top_inst.u_i2c_slave.clken_4_iv                           LUT4          F        Out     0.554     7.201       -         
clken_4                                                               Net           -        -       0.000     -           1         
u_i2c_slave_top_inst.u_i2c_slave.clken_Z                              DFFE          D        In      -         7.201       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 7.274 is 4.198(57.7%) logic and 3.076(42.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                       Arrival          
Instance                                                         Reference     Type     Pin     Net             Time        Slack
                                                                 Clock                                                           
---------------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.rst_i_cZ                        System        INV      O       rst_i           0.000       5.143
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_RNO\[0\]          System        INV      O       N_23_0          0.000       6.059
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_fast_RNO\[0\]     System        INV      O       N_23_fast_0     0.000       6.059
u_i2c_slave_top_inst.u_i2c_slave.wre_reg_RNI5VR8                 System        INV      O       mem_wre_i       0.000       6.059
u_i2c_slave_top_inst.u_i2c_slave.wre_reg_RNO                     System        INV      O       w_r_flag_i      0.000       6.059
=================================================================================================================================


Ending Points with Worst Slack
******************************

                                                          Starting                                        Required          
Instance                                                  Reference     Type      Pin       Net           Time         Slack
                                                          Clock                                                             
----------------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[0\]      System        DFFE      D         mem_do[0]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[1\]      System        DFFE      D         mem_do[1]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[2\]      System        DFFE      D         mem_do[2]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[3\]      System        DFFE      D         mem_do[3]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[4\]      System        DFFE      D         mem_do[4]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[5\]      System        DFFE      D         mem_do[5]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[6\]      System        DFFE      D         mem_do[6]     6.593        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[7\]      System        DFFE      D         mem_do[7]     6.593        5.143
u_i2c_slave_top_inst.gw_sp                                System        SP        RESET     rst_i         5.678        5.143
u_i2c_slave_top_inst.u_i2c_slave.\\bit_counter_Z\[0\]     System        DFFRE     D         N_23_0        6.593        6.059
============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.667
    - Setup time:                            0.073
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.593

    - Propagation time:                      1.450
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.143

    Number of logic level(s):                1
    Starting point:                          u_i2c_slave_top_inst.u_i2c_slave.rst_i_cZ / O
    Ending point:                            u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[7\] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            i2c_slave_top|clk [rising] on pin CLK

Instance / Net                                                    Pin       Pin               Arrival     No. of    
Name                                                     Type     Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
u_i2c_slave_top_inst.u_i2c_slave.rst_i_cZ                INV      O         Out     0.000     0.000       -         
rst_i                                                    Net      -         -       0.535     -           47        
u_i2c_slave_top_inst.gw_sp                               SP       RESET     In      -         0.535       -         
u_i2c_slave_top_inst.gw_sp                               SP       DO[7]     Out     0.380     0.915       -         
mem_do[7]                                                Net      -         -       0.535     -           1         
u_i2c_slave_top_inst.u_i2c_slave.\\sp_out_reg_Z\[7\]     DFFE     D         In      -         1.450       -         
====================================================================================================================
Total path delay (propagation time + setup) of 1.524 is 0.454(29.8%) logic and 1.070(70.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 188MB peak: 190MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 188MB peak: 190MB)

---------------------------------------
Resource Usage Report for i2c_slave_top 

Mapping to part: gw2a_55pbga484-6
Cell usage:
ALU             9 uses
DFF             1 use
DFFC            35 uses
DFFCE           15 uses
DFFE            29 uses
DFFP            4 uses
DFFRE           8 uses
DLC             4 uses
GSR             1 use
INV             6 uses
MUX2_LUT5       24 uses
MUX2_LUT6       9 uses
SP              1 use
LUT2            43 uses
LUT3            58 uses
LUT4            109 uses

I/O ports: 5
I/O primitives: 5
IBUF           3 uses
IOBUF          1 use
OBUF           1 use

I/O Register bits:                  0
Register bits not including I/Os:   92 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 1 of 140 (0%)

Total load per clock:
   i2c_slave_top|clk: 93

@S |Mapping Summary:
Total  LUTs: 210 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 38MB peak: 190MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Sep 26 09:03:35 2017

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