Timing Messages
Report Title | Gowin Timing Analysis Report |
Tool Version | v1.7.9Beta |
Series, Device, Package, Speed, Operating Conditions | GW2A, GW2A-55, PBGA484, 6, INDUSTRIAL |
Design Name | i2c_slave_top |
Design File | /home/liulie/ref_design/i2c_slave/project/impl/synthesize/rev_1/i2c_slave.vm |
Timing Constraint File | --- |
Timing Report File | /home/liulie/ref_design/i2c_slave/project/impl/pnr/i2c_slave.tr.html |
Created Time | Tue Sep 26 09:03:41 2017 |
Command Line | /home/liulie/IP_Review/1.7/Pnr/bin/gowin -do /home/liulie/ref_design/i2c_slave/project/impl/pnr/cmd.do |
Legal Announcement | Copyright (C)2014-2017 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C |
Hold Delay Model | Fast 1.05V 0C |
Numbers of Paths Analyzed | 358 |
Numbers of Endpoints Analyzed | 268 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 116.998(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 25
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.453 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.305 |
2 | 1.505 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.253 |
3 | 1.513 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.245 |
4 | 1.540 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.218 |
5 | 1.682 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.076 |
6 | 1.864 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.894 |
7 | 1.904 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.854 |
8 | 1.958 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.800 |
9 | 1.985 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.773 |
10 | 1.989 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.769 |
11 | 2.072 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.686 |
12 | 2.225 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.533 |
13 | 2.272 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.486 |
14 | 2.292 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.466 |
15 | 2.602 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.156 |
16 | 2.603 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.155 |
17 | 2.603 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.155 |
18 | 2.811 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.947 |
19 | 2.864 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.894 |
20 | 2.871 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.887 |
21 | 2.885 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.873 |
22 | 2.910 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.848 |
23 | 2.931 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.827 |
24 | 2.931 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.827 |
25 | 2.967 | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z/CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 6.791 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 25
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.402 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.415 |
2 | 0.402 | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[4]/Q | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.415 |
3 | 0.410 | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.423 |
4 | 0.413 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.426 |
5 | 0.551 | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[6]/Q | u_i2c_slave_top_inst/gw_sp/DI6 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.808 |
6 | 0.566 | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.579 |
7 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/Q | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
8 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
9 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
10 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
11 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
12 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
13 | 0.569 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.582 |
14 | 0.571 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.584 |
15 | 0.572 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.585 |
16 | 0.573 | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/Q | u_i2c_slave_top_inst/gw_sp/DI3 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.830 |
17 | 0.573 | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/Q | u_i2c_slave_top_inst/gw_sp/DI2 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.830 |
18 | 0.573 | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1]/Q | u_i2c_slave_top_inst/gw_sp/DI1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.830 |
19 | 0.573 | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/Q | u_i2c_slave_top_inst/gw_sp/DI0 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.830 |
20 | 0.575 | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.588 |
21 | 0.589 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.602 |
22 | 0.590 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[4]/Q | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.603 |
23 | 0.592 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.606 |
24 | 0.593 | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.606 |
25 | 0.594 | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[6]/Q | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.607 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 25
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 7.202 | u_i2c_slave_top_inst/u_i2c_slave/nstate_9_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.556 |
2 | 7.206 | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.552 |
3 | 7.229 | u_i2c_slave_top_inst/u_i2c_slave/nstate_1_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.529 |
4 | 7.257 | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 2.501 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 25
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.678 | u_i2c_slave_top_inst/u_i2c_slave/nstate_13_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.691 |
2 | 1.688 | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.701 |
3 | 1.838 | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.851 |
4 | 1.851 | u_i2c_slave_top_inst/u_i2c_slave/nstate_5_Z_Z/Q | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLEAR | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.864 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/gw_sp |
2 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] |
3 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] |
4 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/scl_reg_dly_Z_Z |
5 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] |
6 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
7 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
8 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1] |
9 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/stop_condition_Z_Z |
10 | 3.372 | 4.572 | 1.200 | Low Pulse Width | DEFAULT_CLK | u_i2c_slave_top_inst/u_i2c_slave/scl_posedge_Z_Z |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 25
Path1
Path Summary:
Slack | 1.453 |
Data Arrival Time | 10.657 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
2.630 | 0.278 | tC2Q | RF | 9 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q |
3.934 | 1.304 | tNET | FF | 1 | R42C47[3][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_RNO/I1 |
4.733 | 0.799 | tINS | FF | 1 | R42C47[3][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_RNO/F |
4.733 | 0.000 | tNET | FF | 1 | R42C47[3][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_cZ/I1 |
4.881 | 0.148 | tINS | FF | 8 | R42C47[3][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_cZ/O |
6.198 | 1.317 | tNET | FF | 1 | R42C50[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable29_0_cZ_cZ/I2 |
7.019 | 0.821 | tINS | FR | 1 | R42C50[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable29_0_cZ_cZ/F |
7.266 | 0.247 | tNET | RR | 1 | R43C50[3][A] | u_i2c_slave_top_inst/u_i2c_slave/int_reg_1_sqmuxa_cZ/I3 |
8.087 | 0.821 | tINS | RR | 1 | R43C50[3][A] | u_i2c_slave_top_inst/u_i2c_slave/int_reg_1_sqmuxa_cZ/F |
10.657 | 2.570 | tNET | RR | 1 | IOB40[B] | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | IOB40[B] | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z | |||
12.109 | -0.042 | tSu | 1 | IOB40[B] | u_i2c_slave_top_inst/u_i2c_slave/int_reg_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 2.589, 31.175%; route: 5.438, 65.473%; tC2Q: 0.278, 3.352% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path2
Path Summary:
Slack | 1.505 |
Data Arrival Time | 10.604 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
8.516 | 0.051 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/COUT |
8.516 | 0.000 | tNET | FF | 2 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/CIN |
9.193 | 0.677 | tINS | FF | 1 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/SUM |
9.783 | 0.590 | tNET | FF | 1 | R44C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[4]/I0 |
10.604 | 0.821 | tINS | FR | 1 | R44C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[4]/F |
10.604 | 0.000 | tNET | RR | 1 | R44C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R44C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4] | |||
12.109 | -0.042 | tSu | 1 | R44C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.089, 49.552%; route: 3.885, 47.075%; tC2Q: 0.278, 3.373% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path3
Path Summary:
Slack | 1.513 |
Data Arrival Time | 10.597 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.356 | 1.113 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/I0 |
6.101 | 0.744 | tINS | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/F |
6.101 | 0.000 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/I0 |
6.249 | 0.148 | tINS | FF | 4 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/O |
6.628 | 0.379 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/I2 |
7.281 | 0.652 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/F |
7.281 | 0.000 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/I0 |
7.429 | 0.148 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/O |
7.429 | 0.000 | tNET | FF | 1 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/I0 |
7.577 | 0.148 | tINS | FF | 7 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/O |
8.188 | 0.611 | tNET | FF | 1 | R41C48[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_6_ac0_1_cZ/I1 |
8.987 | 0.799 | tINS | FF | 2 | R41C48[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_6_ac0_1_cZ/F |
9.931 | 0.944 | tNET | FF | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[3]/I1 |
10.597 | 0.665 | tINS | FR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[3]/F |
10.597 | 0.000 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] | |||
12.109 | -0.042 | tSu | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.959, 48.011%; route: 4.008, 48.613%; tC2Q: 0.278, 3.377% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path4
Path Summary:
Slack | 1.540 |
Data Arrival Time | 10.570 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
8.516 | 0.051 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/COUT |
8.516 | 0.000 | tNET | FF | 2 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/CIN |
8.567 | 0.051 | tINS | FF | 1 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/COUT |
8.567 | 0.000 | tNET | FF | 2 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/CIN |
8.617 | 0.051 | tINS | FF | 1 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/COUT |
8.617 | 0.000 | tNET | FF | 2 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/CIN |
8.668 | 0.051 | tINS | FF | 1 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/COUT |
8.668 | 0.000 | tNET | FF | 2 | R43C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_7_0/CIN |
8.719 | 0.051 | tINS | FF | 1 | R43C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_7_0/COUT |
8.719 | 0.000 | tNET | FF | 2 | R43C51[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_s_8_0/CIN |
9.396 | 0.677 | tINS | FF | 1 | R43C51[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_s_8_0/SUM |
9.749 | 0.353 | tNET | FF | 1 | R43C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_RNO[8]/I0 |
10.570 | 0.821 | tINS | FR | 1 | R43C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_RNO[8]/F |
10.570 | 0.000 | tNET | RR | 1 | R43C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8] | |||
12.109 | -0.042 | tSu | 1 | R43C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.292, 52.225%; route: 3.648, 44.387%; tC2Q: 0.278, 3.388% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path5
Path Summary:
Slack | 1.682 |
Data Arrival Time | 10.427 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
2.630 | 0.278 | tC2Q | RF | 9 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q |
3.934 | 1.304 | tNET | FF | 1 | R42C47[3][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_RNO/I1 |
4.733 | 0.799 | tINS | FF | 1 | R42C47[3][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_RNO/F |
4.733 | 0.000 | tNET | FF | 1 | R42C47[3][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_cZ/I1 |
4.881 | 0.148 | tINS | FF | 8 | R42C47[3][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable29_cZ/O |
5.891 | 1.009 | tNET | FF | 1 | R43C40[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_clken18_5_cZ_cZ/I2 |
6.543 | 0.652 | tINS | FF | 2 | R43C40[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_clken18_5_cZ_cZ/F |
7.291 | 0.748 | tNET | FF | 1 | R42C44[0][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_RNO_7[2]/I2 |
7.943 | 0.652 | tINS | FF | 1 | R42C44[0][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_RNO_7[2]/F |
8.162 | 0.219 | tNET | FF | 1 | R42C44[1][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_RNO_1[2]/S0 |
8.524 | 0.361 | tINS | FF | 1 | R42C44[1][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_RNO_1[2]/O |
10.031 | 1.508 | tNET | FF | 1 | R42C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_cZ[2]/S0 |
10.418 | 0.387 | tINS | FR | 1 | R42C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_cZ[2]/O |
10.427 | 0.009 | tNET | RR | 1 | R42C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2] | |||
12.109 | -0.042 | tSu | 1 | R42C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.001, 37.161%; route: 4.796, 59.391%; tC2Q: 0.278, 3.447% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path6
Path Summary:
Slack | 1.864 |
Data Arrival Time | 10.246 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.990 | 0.677 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/SUM |
9.580 | 0.590 | tNET | FF | 1 | R42C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[0]/I0 |
10.246 | 0.665 | tINS | FR | 1 | R42C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[0]/F |
10.246 | 0.000 | tNET | RR | 1 | R42C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0] | |||
12.109 | -0.042 | tSu | 1 | R42C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.731, 47.262%; route: 3.885, 49.211%; tC2Q: 0.278, 3.527% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path7
Path Summary:
Slack | 1.904 |
Data Arrival Time | 10.205 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
9.142 | 0.677 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/SUM |
9.384 | 0.242 | tNET | FF | 1 | R43C49[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[3]/I0 |
10.205 | 0.821 | tINS | FR | 1 | R43C49[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[3]/F |
10.205 | 0.000 | tNET | RR | 1 | R43C49[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C49[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3] | |||
12.109 | -0.042 | tSu | 1 | R43C49[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.039, 51.423%; route: 3.537, 45.032%; tC2Q: 0.278, 3.545% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path8
Path Summary:
Slack | 1.958 |
Data Arrival Time | 10.151 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
8.516 | 0.051 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/COUT |
8.516 | 0.000 | tNET | FF | 2 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/CIN |
8.567 | 0.051 | tINS | FF | 1 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/COUT |
8.567 | 0.000 | tNET | FF | 2 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/CIN |
9.244 | 0.677 | tINS | FF | 1 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/SUM |
9.486 | 0.242 | tNET | FF | 1 | R44C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[5]/I0 |
10.151 | 0.665 | tINS | FR | 1 | R44C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[5]/F |
10.151 | 0.000 | tNET | RR | 1 | R44C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R44C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5] | |||
12.109 | -0.042 | tSu | 1 | R44C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.984, 51.086%; route: 3.537, 45.345%; tC2Q: 0.278, 3.569% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path9
Path Summary:
Slack | 1.985 |
Data Arrival Time | 10.124 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
9.091 | 0.677 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/SUM |
9.334 | 0.242 | tNET | FF | 1 | R43C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[2]/I0 |
10.124 | 0.791 | tINS | FR | 1 | R43C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[2]/F |
10.124 | 0.000 | tNET | RR | 1 | R43C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2] | |||
12.109 | -0.042 | tSu | 1 | R43C49[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.958, 50.917%; route: 3.537, 45.501%; tC2Q: 0.278, 3.582% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path10
Path Summary:
Slack | 1.989 |
Data Arrival Time | 10.120 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
8.516 | 0.051 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/COUT |
8.516 | 0.000 | tNET | FF | 2 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/CIN |
8.567 | 0.051 | tINS | FF | 1 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/COUT |
8.567 | 0.000 | tNET | FF | 2 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/CIN |
8.617 | 0.051 | tINS | FF | 1 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/COUT |
8.617 | 0.000 | tNET | FF | 2 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/CIN |
9.294 | 0.677 | tINS | FF | 1 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/SUM |
9.299 | 0.005 | tNET | FF | 1 | R43C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[6]/I0 |
10.120 | 0.821 | tINS | FR | 1 | R43C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[6]/F |
10.120 | 0.000 | tNET | RR | 1 | R43C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6] | |||
12.109 | -0.042 | tSu | 1 | R43C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.191, 53.942%; route: 3.300, 42.474%; tC2Q: 0.278, 3.584% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path11
Path Summary:
Slack | 2.072 |
Data Arrival Time | 10.037 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.356 | 1.113 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/I0 |
6.101 | 0.744 | tINS | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/F |
6.101 | 0.000 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/I0 |
6.249 | 0.148 | tINS | FF | 4 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/O |
6.628 | 0.379 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/I2 |
7.281 | 0.652 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/F |
7.281 | 0.000 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/I0 |
7.429 | 0.148 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/O |
7.429 | 0.000 | tNET | FF | 1 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/I0 |
7.577 | 0.148 | tINS | FF | 7 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/O |
8.188 | 0.611 | tNET | FF | 1 | R41C48[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_6_ac0_1_cZ/I1 |
9.009 | 0.821 | tINS | FR | 2 | R41C48[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_6_ac0_1_cZ/F |
9.217 | 0.208 | tNET | RR | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[3]/I1 |
10.037 | 0.821 | tINS | RR | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[3]/F |
10.037 | 0.000 | tNET | RR | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3] | |||
12.109 | -0.042 | tSu | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.136, 53.808%; route: 3.272, 42.570%; tC2Q: 0.278, 3.622% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path12
Path Summary:
Slack | 2.225 |
Data Arrival Time | 9.884 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
8.415 | 0.051 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/COUT |
8.415 | 0.000 | tNET | FF | 2 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/CIN |
8.465 | 0.051 | tINS | FF | 1 | R43C50[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_2_0/COUT |
8.465 | 0.000 | tNET | FF | 2 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/CIN |
8.516 | 0.051 | tINS | FF | 1 | R43C50[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_3_0/COUT |
8.516 | 0.000 | tNET | FF | 2 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/CIN |
8.567 | 0.051 | tINS | FF | 1 | R43C50[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_4_0/COUT |
8.567 | 0.000 | tNET | FF | 2 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/CIN |
8.617 | 0.051 | tINS | FF | 1 | R43C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_5_0/COUT |
8.617 | 0.000 | tNET | FF | 2 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/CIN |
8.668 | 0.051 | tINS | FF | 1 | R43C51[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_6_0/COUT |
8.668 | 0.000 | tNET | FF | 2 | R43C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_7_0/CIN |
9.345 | 0.677 | tINS | FF | 1 | R43C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_7_0/SUM |
9.350 | 0.005 | tNET | FF | 1 | R43C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[7]/I0 |
9.884 | 0.534 | tINS | FF | 1 | R43C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[7]/F |
9.884 | 0.000 | tNET | FF | 1 | R43C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7] | |||
12.109 | -0.042 | tSu | 1 | R43C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.955, 52.500%; route: 3.300, 43.804%; tC2Q: 0.278, 3.696% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path13
Path Summary:
Slack | 2.272 |
Data Arrival Time | 9.838 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 10 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q |
3.587 | 0.957 | tNET | FF | 1 | R41C45[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un16_ac0_5_cZ_cZ/I3 |
4.239 | 0.652 | tINS | FF | 9 | R41C45[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un16_ac0_5_cZ_cZ/F |
5.231 | 0.992 | tNET | FF | 1 | R43C43[0][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate25_cZ/I2 |
6.052 | 0.821 | tINS | FR | 1 | R43C43[0][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate25_cZ/F |
6.054 | 0.002 | tNET | RR | 1 | R43C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_cstate25_cZ_cZ/I0 |
6.853 | 0.799 | tINS | RF | 2 | R43C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_cstate25_cZ_cZ/F |
8.147 | 1.294 | tNET | FF | 1 | R43C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_cnst_i_a2_RNO[1]/S0 |
8.508 | 0.361 | tINS | FF | 1 | R43C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_cnst_i_a2_RNO[1]/O |
8.508 | 0.000 | tNET | FF | 1 | R43C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_cnst_i_a2[1]/I0 |
8.656 | 0.148 | tINS | FF | 1 | R43C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/cstate_cnst_i_a2[1]/O |
9.017 | 0.360 | tNET | FF | 1 | R43C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_cZ[1]/I0 |
9.838 | 0.821 | tINS | FR | 1 | R43C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_15_cZ[1]/F |
9.838 | 0.000 | tNET | RR | 1 | R43C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1] | |||
12.109 | -0.042 | tSu | 1 | R43C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.603, 48.127%; route: 3.605, 48.154%; tC2Q: 0.278, 3.719% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path14
Path Summary:
Slack | 2.292 |
Data Arrival Time | 9.817 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/CLK |
2.630 | 0.278 | tC2Q | RF | 7 | R43C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[0]/Q |
3.582 | 0.952 | tNET | FF | 1 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/I0 |
4.381 | 0.799 | tINS | FF | 13 | R42C43[1][B] | u_i2c_slave_top_inst/u_i2c_slave/clken18_cZ/F |
5.403 | 1.022 | tNET | FF | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/I0 |
6.194 | 0.791 | tINS | FR | 1 | R43C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_1/F |
6.195 | 0.002 | tNET | RR | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/I1 |
6.995 | 0.799 | tINS | RF | 1 | R43C48[0][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0_RNO_cZ/F |
8.313 | 1.319 | tNET | FF | 2 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/CIN |
8.364 | 0.051 | tINS | FF | 1 | R43C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_0_0/COUT |
8.364 | 0.000 | tNET | FF | 2 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/CIN |
9.041 | 0.677 | tINS | FF | 1 | R43C50[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_addr_len_reg_1_cry_1_0/SUM |
9.283 | 0.242 | tNET | FF | 1 | R43C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[1]/I0 |
9.817 | 0.534 | tINS | FF | 1 | R43C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_11_iv[1]/F |
9.817 | 0.000 | tNET | FF | 1 | R43C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1] | |||
12.109 | -0.042 | tSu | 1 | R43C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/addr_len_reg_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.651, 48.899%; route: 3.537, 47.372%; tC2Q: 0.278, 3.729% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path15
Path Summary:
Slack | 2.602 |
Data Arrival Time | 9.508 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 10 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q |
2.901 | 0.271 | tNET | FF | 1 | R42C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/w_r_flag_fast_RNI8LAP/I0 |
3.722 | 0.821 | tINS | FR | 1 | R42C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/w_r_flag_fast_RNI8LAP/F |
3.969 | 0.247 | tNET | RR | 1 | R42C49[0][B] | u_i2c_slave_top_inst/u_i2c_slave/scl_negedge_fast_RNICDK51/I1 |
4.769 | 0.799 | tINS | RF | 6 | R42C49[0][B] | u_i2c_slave_top_inst/u_i2c_slave/scl_negedge_fast_RNICDK51/F |
5.352 | 0.583 | tNET | FF | 1 | R42C48[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNIONR72[0]/S0 |
5.713 | 0.361 | tINS | FF | 2 | R42C48[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNIONR72[0]/O |
6.712 | 0.998 | tNET | FF | 1 | R41C41[3][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_1_cZ_cZ/I0 |
7.246 | 0.534 | tINS | FF | 2 | R41C41[3][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_1_cZ_cZ/F |
7.256 | 0.011 | tNET | FF | 1 | R41C41[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_cZ_cZ/I1 |
8.047 | 0.791 | tINS | FR | 2 | R41C41[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_cZ_cZ/F |
8.050 | 0.003 | tNET | RR | 1 | R41C41[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_0_sqmuxa_d_cZ/I3 |
8.841 | 0.791 | tINS | RR | 1 | R41C41[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_0_sqmuxa_d_cZ/F |
8.842 | 0.002 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_4_iv/I2 |
9.508 | 0.665 | tINS | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_4_iv/F |
9.508 | 0.000 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z | |||
12.109 | -0.042 | tSu | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.762, 66.546%; route: 2.116, 29.564%; tC2Q: 0.278, 3.890% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path16
Path Summary:
Slack | 2.603 |
Data Arrival Time | 9.507 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.181 | 0.938 | tNET | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/I1 |
5.980 | 0.799 | tINS | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/F |
6.571 | 0.590 | tNET | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/I0 |
7.105 | 0.534 | tINS | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/F |
7.110 | 0.005 | tNET | FF | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/I0 |
7.931 | 0.821 | tINS | FR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/F |
7.931 | 0.000 | tNET | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/I0 |
8.082 | 0.151 | tINS | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/O |
8.082 | 0.000 | tNET | RR | 1 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/I0 |
8.233 | 0.151 | tINS | RR | 8 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/O |
9.507 | 1.274 | tNET | RR | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] | |||
12.109 | -0.042 | tSu | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.109, 43.449%; route: 3.768, 52.660%; tC2Q: 0.278, 3.891% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path17
Path Summary:
Slack | 2.603 |
Data Arrival Time | 9.507 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.181 | 0.938 | tNET | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/I1 |
5.980 | 0.799 | tINS | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/F |
6.571 | 0.590 | tNET | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/I0 |
7.105 | 0.534 | tINS | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/F |
7.110 | 0.005 | tNET | FF | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/I0 |
7.931 | 0.821 | tINS | FR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/F |
7.931 | 0.000 | tNET | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/I0 |
8.082 | 0.151 | tINS | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/O |
8.082 | 0.000 | tNET | RR | 1 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/I0 |
8.233 | 0.151 | tINS | RR | 8 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/O |
9.507 | 1.274 | tNET | RR | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] | |||
12.109 | -0.042 | tSu | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.109, 43.449%; route: 3.768, 52.660%; tC2Q: 0.278, 3.891% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path18
Path Summary:
Slack | 2.811 |
Data Arrival Time | 9.299 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 4 | R41C48[2][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[3]/Q |
2.990 | 0.360 | tNET | FF | 1 | R41C46[0][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable26_a0_0_cZ/I0 |
3.642 | 0.652 | tINS | FF | 4 | R41C46[0][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable26_a0_0_cZ/F |
4.400 | 0.758 | tNET | FF | 1 | R42C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable26_a0/I3 |
5.145 | 0.744 | tINS | FF | 10 | R42C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_enable26_a0/F |
6.156 | 1.011 | tNET | FF | 1 | R41C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_cstate_2_sqmuxa_cZ_cZ/I0 |
6.955 | 0.799 | tINS | FF | 5 | R41C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_cstate_2_sqmuxa_cZ_cZ/F |
7.550 | 0.594 | tNET | FF | 1 | R41C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_word_address_ac0_7_cZ/S0 |
7.911 | 0.361 | tINS | FF | 1 | R41C50[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_word_address_ac0_7_cZ/O |
8.508 | 0.597 | tNET | FF | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[5]/I2 |
9.299 | 0.791 | tINS | FR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[5]/F |
9.299 | 0.000 | tNET | RR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] | |||
12.109 | -0.042 | tSu | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.348, 48.191%; route: 3.321, 47.802%; tC2Q: 0.278, 4.007% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path19
Path Summary:
Slack | 2.864 |
Data Arrival Time | 9.245 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 10 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q |
2.901 | 0.271 | tNET | FF | 1 | R42C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/w_r_flag_fast_RNI8LAP/I0 |
3.722 | 0.821 | tINS | FR | 1 | R42C48[1][B] | u_i2c_slave_top_inst/u_i2c_slave/w_r_flag_fast_RNI8LAP/F |
3.969 | 0.247 | tNET | RR | 1 | R42C49[0][B] | u_i2c_slave_top_inst/u_i2c_slave/scl_negedge_fast_RNICDK51/I1 |
4.769 | 0.799 | tINS | RF | 6 | R42C49[0][B] | u_i2c_slave_top_inst/u_i2c_slave/scl_negedge_fast_RNICDK51/F |
5.352 | 0.583 | tNET | FF | 1 | R42C48[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNIONR72[0]/S0 |
5.713 | 0.361 | tINS | FF | 2 | R42C48[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNIONR72[0]/O |
6.712 | 0.998 | tNET | FF | 1 | R41C41[3][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_1_cZ_cZ/I0 |
7.246 | 0.534 | tINS | FF | 2 | R41C41[3][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_1_cZ_cZ/F |
7.256 | 0.011 | tNET | FF | 1 | R41C41[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_cZ_cZ/I1 |
8.047 | 0.791 | tINS | FR | 2 | R41C41[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg_enable24_4_cZ_cZ/F |
8.050 | 0.003 | tNET | RR | 1 | R41C41[2][A] | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_0_sqmuxa_cZ/I2 |
8.841 | 0.791 | tINS | RR | 1 | R41C41[2][A] | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_0_sqmuxa_cZ/F |
9.245 | 0.405 | tNET | RR | 1 | R41C41[0][A] | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R41C41[0][A] | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z | |||
12.109 | -0.042 | tSu | 1 | R41C41[0][A] | u_i2c_slave_top_inst/u_i2c_slave/wre_reg_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 4.097, 59.427%; route: 2.519, 36.535%; tC2Q: 0.278, 4.038% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path20
Path Summary:
Slack | 2.871 |
Data Arrival Time | 9.239 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.181 | 0.938 | tNET | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/I1 |
5.980 | 0.799 | tINS | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/F |
6.571 | 0.590 | tNET | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/I0 |
7.105 | 0.534 | tINS | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/F |
7.110 | 0.005 | tNET | FF | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/I0 |
7.931 | 0.821 | tINS | FR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/F |
7.931 | 0.000 | tNET | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/I0 |
8.082 | 0.151 | tINS | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/O |
8.082 | 0.000 | tNET | RR | 1 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/I0 |
8.233 | 0.151 | tINS | RR | 8 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/O |
9.239 | 1.006 | tNET | RR | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] | |||
12.109 | -0.042 | tSu | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.109, 45.139%; route: 3.500, 50.818%; tC2Q: 0.278, 4.042% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path21
Path Summary:
Slack | 2.885 |
Data Arrival Time | 9.225 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.356 | 1.113 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/I0 |
6.101 | 0.744 | tINS | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_RNO/F |
6.101 | 0.000 | tNET | FF | 1 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/I0 |
6.249 | 0.148 | tINS | FF | 4 | R41C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_2_sqmuxa_1_cZ/O |
6.628 | 0.379 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/I2 |
7.281 | 0.652 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_2_cZ/F |
7.281 | 0.000 | tNET | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/I0 |
7.429 | 0.148 | tINS | FF | 1 | R41C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_RNO_cZ/O |
7.429 | 0.000 | tNET | FF | 1 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/I0 |
7.577 | 0.148 | tINS | FF | 7 | R41C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_2_sqmuxa_cZ_cZ/O |
8.559 | 0.982 | tNET | FF | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[2]/I1 |
9.225 | 0.665 | tINS | FR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[2]/F |
9.225 | 0.000 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] | |||
12.109 | -0.042 | tSu | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.159, 45.965%; route: 3.436, 49.984%; tC2Q: 0.278, 4.050% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path22
Path Summary:
Slack | 2.910 |
Data Arrival Time | 9.199 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.242 | 0.613 | tNET | FF | 1 | R43C44[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken17_cZ/I3 |
3.895 | 0.652 | tINS | FF | 6 | R43C44[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken17_cZ/F |
5.424 | 1.529 | tNET | FF | 1 | R42C44[0][A] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_1_sqmuxa_0_cZ/I1 |
6.168 | 0.744 | tINS | FF | 2 | R42C44[0][A] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_1_sqmuxa_0_cZ/F |
6.764 | 0.596 | tNET | FF | 1 | R41C45[0][B] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f1_0_cZ/I0 |
7.554 | 0.791 | tINS | FR | 1 | R41C45[0][B] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f1_0_cZ/F |
7.556 | 0.002 | tNET | RR | 1 | R41C45[1][B] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f1_cZ/I3 |
8.377 | 0.821 | tINS | RR | 1 | R41C45[1][B] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f1_cZ/F |
8.378 | 0.002 | tNET | RR | 1 | R41C45[1][A] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f0/I2 |
9.199 | 0.821 | tINS | RR | 1 | R41C45[1][A] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_6_f0/F |
9.199 | 0.000 | tNET | RR | 1 | R41C45[1][A] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R41C45[1][A] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z | |||
12.109 | -0.042 | tSu | 1 | R41C45[1][A] | u_i2c_slave_top_inst/u_i2c_slave/sda_out_en_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.829, 55.917%; route: 2.740, 40.018%; tC2Q: 0.278, 4.066% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path23
Path Summary:
Slack | 2.931 |
Data Arrival Time | 9.178 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.181 | 0.938 | tNET | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/I1 |
5.980 | 0.799 | tINS | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/F |
6.571 | 0.590 | tNET | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/I0 |
7.105 | 0.534 | tINS | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/F |
7.110 | 0.005 | tNET | FF | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/I0 |
7.931 | 0.821 | tINS | FR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/F |
7.931 | 0.000 | tNET | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/I0 |
8.082 | 0.151 | tINS | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/O |
8.082 | 0.000 | tNET | RR | 1 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/I0 |
8.233 | 0.151 | tINS | RR | 8 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/O |
9.178 | 0.945 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] | |||
12.109 | -0.042 | tSu | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.109, 45.539%; route: 3.440, 50.383%; tC2Q: 0.278, 4.078% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path24
Path Summary:
Slack | 2.931 |
Data Arrival Time | 9.178 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.591 | 0.961 | tNET | FF | 1 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/I3 |
4.243 | 0.652 | tINS | FF | 7 | R43C40[2][B] | u_i2c_slave_top_inst/u_i2c_slave/clken15_cZ/F |
5.181 | 0.938 | tNET | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/I1 |
5.980 | 0.799 | tINS | FF | 1 | R43C44[2][B] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_1_sqmuxa_2_cZ/F |
6.571 | 0.590 | tNET | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/I0 |
7.105 | 0.534 | tINS | FF | 1 | R42C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_0_cZ_cZ/F |
7.110 | 0.005 | tNET | FF | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/I0 |
7.931 | 0.821 | tINS | FR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_1_cZ/F |
7.931 | 0.000 | tNET | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/I0 |
8.082 | 0.151 | tINS | RR | 1 | R42C46[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_RNO_cZ/O |
8.082 | 0.000 | tNET | RR | 1 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/I0 |
8.233 | 0.151 | tINS | RR | 8 | R42C46[2][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_bit_counter_1_sqmuxa_cZ_cZ/O |
9.178 | 0.945 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] | |||
12.109 | -0.042 | tSu | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.109, 45.539%; route: 3.440, 50.383%; tC2Q: 0.278, 4.078% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path25
Path Summary:
Slack | 2.967 |
Data Arrival Time | 9.143 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 8 | R42C43[0][A] | u_i2c_slave_top_inst/u_i2c_slave/cstate_Z_Z[3]/Q |
3.242 | 0.613 | tNET | FF | 1 | R43C44[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken17_cZ/I3 |
3.895 | 0.652 | tINS | FF | 6 | R43C44[3][A] | u_i2c_slave_top_inst/u_i2c_slave/clken17_cZ/F |
5.424 | 1.529 | tNET | FF | 1 | R42C44[0][A] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_1_sqmuxa_0_cZ/I1 |
6.214 | 0.791 | tINS | FR | 2 | R42C44[0][A] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_1_sqmuxa_0_cZ/F |
6.463 | 0.249 | tNET | RR | 1 | R41C44[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_ack_flag_1_sqmuxa_1_cZ_cZ/I0 |
7.262 | 0.799 | tINS | RF | 2 | R41C44[1][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_ack_flag_1_sqmuxa_1_cZ_cZ/F |
7.858 | 0.596 | tNET | FF | 1 | R42C46[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_ack_flag_1_sqmuxa_4_cZ_cZ/I0 |
8.679 | 0.821 | tINS | FR | 1 | R42C46[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_ack_flag_1_sqmuxa_4_cZ_cZ/F |
9.143 | 0.464 | tNET | RR | 1 | R41C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R41C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z | |||
12.109 | -0.042 | tSu | 1 | R41C46[1][B] | u_i2c_slave_top_inst/u_i2c_slave/ack_flag_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 3.063, 45.101%; route: 3.450, 50.800%; tC2Q: 0.278, 4.099% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 25
Path1
Path Summary:
Slack | 0.402 |
Data Arrival Time | 2.380 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/CLK |
2.206 | 0.241 | tC2Q | RF | 5 | R41C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/Q |
2.380 | 0.174 | tNET | FF | 1 | R41C47[1][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[1][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3] | |||
1.978 | 0.013 | tHld | 1 | R41C47[1][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.174, 41.896%; tC2Q: 0.241, 58.104% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path2
Path Summary:
Slack | 0.402 |
Data Arrival Time | 2.380 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[4] |
To | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[4]/CLK |
2.206 | 0.241 | tC2Q | RF | 7 | R41C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[4]/Q |
2.380 | 0.174 | tNET | FF | 1 | R41C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4] | |||
1.978 | 0.013 | tHld | 1 | R41C51[2][A] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.174, 41.896%; tC2Q: 0.241, 58.104% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path3
Path Summary:
Slack | 0.410 |
Data Arrival Time | 2.388 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[3]/CLK |
2.206 | 0.241 | tC2Q | RF | 7 | R41C51[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[3]/Q |
2.388 | 0.182 | tNET | FF | 1 | R41C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3] | |||
1.978 | 0.013 | tHld | 1 | R41C51[2][B] | u_i2c_slave_top_inst/u_i2c_slave/ad_reg_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.182, 42.976%; tC2Q: 0.241, 57.024% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path4
Path Summary:
Slack | 0.413 |
Data Arrival Time | 2.392 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[0]/CLK |
2.206 | 0.241 | tC2Q | RF | 6 | R43C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[0]/Q |
2.392 | 0.185 | tNET | FF | 1 | R43C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] | |||
1.978 | 0.013 | tHld | 1 | R43C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 43.433%; tC2Q: 0.241, 56.567% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path5
Path Summary:
Slack | 0.551 |
Data Arrival Time | 2.773 |
Data Required Time | 2.222 |
From | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[6] |
To | u_i2c_slave_top_inst/gw_sp |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[6]/CLK |
2.208 | 0.242 | tC2Q | RR | 1 | R42C48[0][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[6]/Q |
2.773 | 0.566 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/DI6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/gw_sp | |||
2.222 | 0.257 | tHld | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.566, 70.006%; tC2Q: 0.242, 29.994% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path6
Path Summary:
Slack | 0.566 |
Data Arrival Time | 2.545 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/CLK |
2.208 | 0.242 | tC2Q | RR | 3 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/Q |
2.211 | 0.003 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_4_iv/I0 |
2.545 | 0.334 | tINS | RF | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_4_iv/F |
2.545 | 0.000 | tNET | FF | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z | |||
1.978 | 0.013 | tHld | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.658%; route: 0.003, 0.506%; tC2Q: 0.242, 41.835% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path7
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] |
To | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/CLK |
2.208 | 0.242 | tC2Q | RR | 4 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/Q |
2.213 | 0.006 | tNET | RR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[5]/I3 |
2.548 | 0.334 | tINS | RF | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[5]/F |
2.548 | 0.000 | tNET | FF | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] | |||
1.978 | 0.013 | tHld | 1 | R40C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path8
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/CLK |
2.208 | 0.242 | tC2Q | RR | 5 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/Q |
2.213 | 0.006 | tNET | RR | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[0]/I3 |
2.548 | 0.334 | tINS | RF | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[0]/F |
2.548 | 0.000 | tNET | FF | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0] | |||
1.978 | 0.013 | tHld | 1 | R42C51[0][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path9
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/CLK |
2.208 | 0.242 | tC2Q | RR | 8 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/Q |
2.213 | 0.006 | tNET | RR | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[2]/I3 |
2.548 | 0.334 | tINS | RF | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_9_cZ[2]/F |
2.548 | 0.000 | tNET | FF | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2] | |||
1.978 | 0.013 | tHld | 1 | R41C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/word_address_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path10
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/CLK |
2.208 | 0.242 | tC2Q | RR | 7 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/Q |
2.213 | 0.006 | tNET | RR | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[1]/I0 |
2.548 | 0.334 | tINS | RF | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[1]/F |
2.548 | 0.000 | tNET | FF | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] | |||
1.978 | 0.013 | tHld | 1 | R42C46[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path11
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/CLK |
2.208 | 0.242 | tC2Q | RR | 9 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/Q |
2.213 | 0.006 | tNET | RR | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[0]/I0 |
2.548 | 0.334 | tINS | RF | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[0]/F |
2.548 | 0.000 | tNET | FF | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] | |||
1.978 | 0.013 | tHld | 1 | R42C45[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path12
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/CLK |
2.208 | 0.242 | tC2Q | RR | 8 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/Q |
2.213 | 0.006 | tNET | RR | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[1]/I0 |
2.548 | 0.334 | tINS | RF | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[1]/F |
2.548 | 0.000 | tNET | FF | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] | |||
1.978 | 0.013 | tHld | 1 | R43C48[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path13
Path Summary:
Slack | 0.569 |
Data Arrival Time | 2.548 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
2.208 | 0.242 | tC2Q | RR | 9 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/Q |
2.213 | 0.006 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[2]/I0 |
2.548 | 0.334 | tINS | RF | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_RNO[2]/F |
2.548 | 0.000 | tNET | FF | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] | |||
1.978 | 0.013 | tHld | 1 | R42C49[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.368%; route: 0.006, 1.007%; tC2Q: 0.242, 41.625% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path14
Path Summary:
Slack | 0.571 |
Data Arrival Time | 2.549 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/CLK |
2.208 | 0.242 | tC2Q | RR | 9 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/Q |
2.215 | 0.007 | tNET | RR | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[2]/I0 |
2.549 | 0.334 | tINS | RF | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[2]/F |
2.549 | 0.000 | tNET | FF | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] | |||
1.978 | 0.013 | tHld | 1 | R41C47[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.224%; route: 0.007, 1.256%; tC2Q: 0.242, 41.520% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path15
Path Summary:
Slack | 0.572 |
Data Arrival Time | 2.550 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
2.208 | 0.242 | tC2Q | RR | 10 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/Q |
2.216 | 0.009 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[3]/I0 |
2.550 | 0.334 | tINS | RF | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[3]/F |
2.550 | 0.000 | tNET | FF | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] | |||
1.978 | 0.013 | tHld | 1 | R42C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 57.080%; route: 0.009, 1.504%; tC2Q: 0.242, 41.416% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path16
Path Summary:
Slack | 0.573 |
Data Arrival Time | 2.796 |
Data Required Time | 2.222 |
From | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3] |
To | u_i2c_slave_top_inst/gw_sp |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/CLK |
2.208 | 0.242 | tC2Q | RR | 1 | R42C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/Q |
2.796 | 0.588 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/DI3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/gw_sp | |||
2.222 | 0.257 | tHld | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.588, 70.811%; tC2Q: 0.242, 29.189% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path17
Path Summary:
Slack | 0.573 |
Data Arrival Time | 2.796 |
Data Required Time | 2.222 |
From | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2] |
To | u_i2c_slave_top_inst/gw_sp |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/CLK |
2.208 | 0.242 | tC2Q | RR | 1 | R41C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/Q |
2.796 | 0.588 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/DI2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/gw_sp | |||
2.222 | 0.257 | tHld | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.588, 70.811%; tC2Q: 0.242, 29.189% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path18
Path Summary:
Slack | 0.573 |
Data Arrival Time | 2.796 |
Data Required Time | 2.222 |
From | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1] |
To | u_i2c_slave_top_inst/gw_sp |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1]/CLK |
2.208 | 0.242 | tC2Q | RR | 1 | R41C49[1][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1]/Q |
2.796 | 0.588 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/DI1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/gw_sp | |||
2.222 | 0.257 | tHld | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.588, 70.811%; tC2Q: 0.242, 29.189% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path19
Path Summary:
Slack | 0.573 |
Data Arrival Time | 2.796 |
Data Required Time | 2.222 |
From | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] |
To | u_i2c_slave_top_inst/gw_sp |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/CLK |
2.208 | 0.242 | tC2Q | RR | 1 | R43C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/Q |
2.796 | 0.588 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/DI0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/gw_sp | |||
2.222 | 0.257 | tHld | 1 | BSRAM_R36C47 | u_i2c_slave_top_inst/gw_sp |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.588, 70.811%; tC2Q: 0.242, 29.189% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path20
Path Summary:
Slack | 0.575 |
Data Arrival Time | 2.553 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/CLK |
2.208 | 0.242 | tC2Q | RR | 11 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/Q |
2.219 | 0.012 | tNET | RR | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[0]/I0 |
2.553 | 0.334 | tINS | RF | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_RNO[0]/F |
2.553 | 0.000 | tNET | FF | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] | |||
1.978 | 0.013 | tHld | 1 | R42C46[0][A] | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.334, 56.796%; route: 0.012, 1.995%; tC2Q: 0.242, 41.210% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path21
Path Summary:
Slack | 0.589 |
Data Arrival Time | 2.567 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[1][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/CLK |
2.208 | 0.242 | tC2Q | RR | 5 | R41C47[1][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[3]/Q |
2.567 | 0.360 | tNET | RR | 1 | R42C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3] | |||
1.978 | 0.013 | tHld | 1 | R42C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.360, 59.732%; tC2Q: 0.242, 40.268% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path22
Path Summary:
Slack | 0.590 |
Data Arrival Time | 2.569 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[4] |
To | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[4]/CLK |
2.208 | 0.242 | tC2Q | RR | 5 | R43C47[2][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[4]/Q |
2.569 | 0.361 | tNET | RR | 1 | R42C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4] | |||
1.978 | 0.013 | tHld | 1 | R42C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.361, 59.830%; tC2Q: 0.242, 40.170% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path23
Path Summary:
Slack | 0.592 |
Data Arrival Time | 2.571 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/CLK |
2.208 | 0.242 | tC2Q | RR | 5 | R41C47[2][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[2]/Q |
2.571 | 0.363 | tNET | RR | 1 | R41C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2] | |||
1.978 | 0.013 | tHld | 1 | R41C49[1][B] | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.363, 59.971%; tC2Q: 0.242, 40.029% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path24
Path Summary:
Slack | 0.593 |
Data Arrival Time | 2.572 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/CLK |
2.208 | 0.242 | tC2Q | RR | 3 | R41C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_Z_Z/Q |
2.572 | 0.364 | tNET | RR | 1 | R41C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z | |||
1.978 | 0.013 | tHld | 1 | R41C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/clken_reg_Z_Z |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.364, 60.030%; tC2Q: 0.242, 39.970% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path25
Path Summary:
Slack | 0.594 |
Data Arrival Time | 2.572 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[6] |
To | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C47[0][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[6]/CLK |
2.208 | 0.242 | tC2Q | RR | 5 | R43C47[0][B] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[6]/Q |
2.572 | 0.365 | tNET | RR | 1 | R41C47[1][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7]/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R41C47[1][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7] | |||
1.978 | 0.013 | tHld | 1 | R41C47[1][A] | u_i2c_slave_top_inst/u_i2c_slave/in_reg_Z_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 0 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.365, 60.068%; tC2Q: 0.242, 39.932% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 25
Path1
Path Summary:
Slack | 7.202 |
Data Arrival Time | 4.907 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_9_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R44C40[2][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_9_Z_Z/CLK |
2.630 | 0.278 | tC2Q | RF | 1 | R44C40[2][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_9_Z_Z/Q |
2.848 | 0.218 | tNET | FF | 1 | R44C40[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[2]/I0 |
3.668 | 0.821 | tINS | FR | 7 | R44C40[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[2]/F |
3.675 | 0.006 | tNET | RR | 1 | R44C40[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_7_cZ_cZ/I1 |
4.474 | 0.799 | tINS | RF | 2 | R44C40[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_7_cZ_cZ/F |
4.907 | 0.433 | tNET | FF | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] | |||
12.109 | -0.042 | tSu | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 1.620, 63.388%; route: 0.657, 25.719%; tC2Q: 0.278, 10.893% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path2
Path Summary:
Slack | 7.206 |
Data Arrival Time | 4.903 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLK |
2.630 | 0.278 | tC2Q | RF | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/Q |
2.848 | 0.218 | tNET | FF | 1 | R43C42[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[1]/I2 |
3.668 | 0.821 | tINS | FR | 4 | R43C42[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[1]/F |
3.675 | 0.006 | tNET | RR | 1 | R43C42[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_6_cZ_cZ/I1 |
4.474 | 0.799 | tINS | RF | 2 | R43C42[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_6_cZ_cZ/F |
4.903 | 0.429 | tNET | FF | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] | |||
12.109 | -0.042 | tSu | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 1.620, 63.491%; route: 0.653, 25.598%; tC2Q: 0.278, 10.911% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path3
Path Summary:
Slack | 7.229 |
Data Arrival Time | 4.881 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_1_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R43C41[2][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_1_Z_Z/CLK |
2.629 | 0.277 | tC2Q | RR | 1 | R43C41[2][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_1_Z_Z/Q |
2.876 | 0.247 | tNET | RR | 1 | R43C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[0]/I0 |
3.697 | 0.821 | tINS | RR | 4 | R43C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[0]/F |
3.703 | 0.006 | tNET | RR | 1 | R43C42[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_5_cZ_cZ/I1 |
4.448 | 0.744 | tINS | RF | 2 | R43C42[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_5_cZ_cZ/F |
4.881 | 0.433 | tNET | FF | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] | |||
12.109 | -0.042 | tSu | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 1.565, 61.889%; route: 0.687, 27.151%; tC2Q: 0.277, 10.960% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Path4
Path Summary:
Slack | 7.257 |
Data Arrival Time | 4.852 |
Data Required Time | 12.109 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
2.351 | 1.532 | tNET | RR | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLK |
2.630 | 0.278 | tC2Q | RF | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/Q |
2.848 | 0.218 | tNET | FF | 1 | R42C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[3]/I2 |
3.668 | 0.821 | tINS | FR | 4 | R42C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[3]/F |
3.675 | 0.006 | tNET | RR | 1 | R42C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_4_cZ_cZ/I1 |
4.419 | 0.744 | tINS | RF | 2 | R42C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_4_cZ_cZ/F |
4.852 | 0.433 | tNET | FF | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
10.819 | 0.819 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
12.351 | 1.532 | tNET | RR | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLK |
12.151 | -0.200 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] | |||
12.109 | -0.042 | tSu | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Arrival Data Path Delay | cell: 1.565, 62.587%; route: 0.657, 26.281%; tC2Q: 0.278, 11.132% |
Required Clock Path Delay | cell: 0.819, 34.830%; route: 1.532, 65.170% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 25
Path1
Path Summary:
Slack | 1.678 |
Data Arrival Time | 3.656 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_13_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_13_Z_Z/CLK |
2.206 | 0.241 | tC2Q | RF | 1 | R42C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_13_Z_Z/Q |
2.380 | 0.173 | tNET | FF | 1 | R42C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[3]/I0 |
2.718 | 0.338 | tINS | FR | 4 | R42C43[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[3]/F |
2.724 | 0.006 | tNET | RR | 1 | R42C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_4_cZ_cZ/I1 |
3.277 | 0.553 | tINS | RR | 2 | R42C43[3][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_4_cZ_cZ/F |
3.656 | 0.379 | tNET | RR | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] | |||
1.978 | 0.013 | tHld | 1 | R42C43[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.891, 52.719%; route: 0.558, 33.015%; tC2Q: 0.241, 14.266% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path2
Path Summary:
Slack | 1.688 |
Data Arrival Time | 3.666 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLK |
2.206 | 0.241 | tC2Q | RF | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/Q |
2.380 | 0.173 | tNET | FF | 1 | R44C40[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[2]/I2 |
2.718 | 0.338 | tINS | FR | 7 | R44C40[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[2]/F |
2.724 | 0.006 | tNET | RR | 1 | R44C40[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_7_cZ_cZ/I1 |
3.287 | 0.563 | tINS | RR | 2 | R44C40[1][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_7_cZ_cZ/F |
3.666 | 0.379 | tNET | RR | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] | |||
1.978 | 0.013 | tHld | 1 | R44C40[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 0.901, 52.999%; route: 0.558, 32.820%; tC2Q: 0.241, 14.181% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path3
Path Summary:
Slack | 1.838 |
Data Arrival Time | 3.816 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLK |
2.206 | 0.241 | tC2Q | RF | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/Q |
2.372 | 0.166 | tNET | FF | 1 | R43C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[0]/I2 |
2.868 | 0.495 | tINS | FF | 4 | R43C42[2][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[0]/F |
2.885 | 0.017 | tNET | FF | 1 | R43C42[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_5_cZ_cZ/I1 |
3.438 | 0.553 | tINS | FR | 2 | R43C42[0][B] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_5_cZ_cZ/F |
3.816 | 0.379 | tNET | RR | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] | |||
1.978 | 0.013 | tHld | 1 | R43C42[0][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 1.048, 56.632%; route: 0.562, 30.339%; tC2Q: 0.241, 13.030% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Path4
Path Summary:
Slack | 1.851 |
Data Arrival Time | 3.829 |
Data Required Time | 1.978 |
From | u_i2c_slave_top_inst/u_i2c_slave/nstate_5_Z_Z |
To | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_5_Z_Z/CLK |
2.206 | 0.241 | tC2Q | RF | 1 | R43C41[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_5_Z_Z/Q |
2.380 | 0.173 | tNET | FF | 1 | R43C42[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[1]/I0 |
2.875 | 0.495 | tINS | FF | 4 | R43C42[1][B] | u_i2c_slave_top_inst/u_i2c_slave/nstate_6_RNO[1]/F |
2.892 | 0.017 | tNET | FF | 1 | R43C42[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_6_cZ_cZ/I1 |
3.455 | 0.563 | tINS | FR | 2 | R43C42[2][A] | u_i2c_slave_top_inst/u_i2c_slave/un1_in_reg11_6_cZ_cZ/F |
3.829 | 0.374 | tNET | RR | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I |
0.811 | 0.811 | tINS | RR | 93 | IOT48[A] | clk_ibuf/O |
1.965 | 1.155 | tNET | RR | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1]/CLK |
1.965 | 0.000 | tUnc | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] | |||
1.978 | 0.013 | tHld | 1 | R43C42[1][A] | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Arrival Data Path Delay | cell: 1.058, 56.778%; route: 0.565, 30.283%; tC2Q: 0.241, 12.939% |
Required Clock Path Delay | cell: 0.811, 41.248%; route: 1.155, 58.752% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/gw_sp |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/gw_sp/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/gw_sp/CLK |
MPW2
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_fast_Z_Z[1]/CLK |
MPW3
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/bit_counter_Z_Z[2]/CLK |
MPW4
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/scl_reg_dly_Z_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/scl_reg_dly_Z_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/scl_reg_dly_Z_Z/CLK |
MPW5
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[0]/CLK |
MPW6
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[2]/CLK |
MPW7
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/nstate_Z_Z[3]/CLK |
MPW8
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/di_reg_Z_Z[1]/CLK |
MPW9
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/stop_condition_Z_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/stop_condition_Z_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/stop_condition_Z_Z/CLK |
MPW10
MPW Summary:
Slack: | 3.372 |
Actual Width: | 4.572 |
Required Width: | 1.200 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | u_i2c_slave_top_inst/u_i2c_slave/scl_posedge_Z_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.825 | 0.825 | tINS | FF | clk_ibuf/O |
7.393 | 1.568 | tNET | FF | u_i2c_slave_top_inst/u_i2c_slave/scl_posedge_Z_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.811 | 0.811 | tINS | RR | clk_ibuf/O |
11.965 | 1.155 | tNET | RR | u_i2c_slave_top_inst/u_i2c_slave/scl_posedge_Z_Z/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
93 | clk_c | 1.453 | 1.568 |
32 | un1_cstate5_cZ | 2.452 | 1.329 |
17 | in_reg_enable | 2.876 | 1.215 |
17 | addr_len_reg_1_sqmuxa_1 | 2.263 | 1.095 |
16 | scl_posedge | 3.377 | 1.316 |
15 | clken_1_sqmuxa_1 | 2.179 | 1.190 |
13 | w_r_flag | 1.893 | 0.982 |
13 | clken18 | 1.505 | 1.022 |
11 | clken19 | 2.642 | 0.970 |
11 | bit_counter[0] | 2.730 | 1.517 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R42C45 | 0.583 |
R42C47 | 0.569 |
R41C47 | 0.556 |
R42C43 | 0.542 |
R42C42 | 0.500 |
R43C44 | 0.500 |
R41C48 | 0.486 |
R42C48 | 0.472 |
R42C49 | 0.472 |
R42C44 | 0.458 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 5
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 5
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 5
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 5
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|