#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: C:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-032 # Thu Sep 27 09:28:04 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Gowin\1.8\IDE\ipcore\I3C_HDR\data\i3c_wrap.sv" (library work) @I:"C:\Gowin\1.8\IDE\ipcore\I3C_HDR\data\i3c_wrap.sv":"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\temp\I3C_HDR\define.v" (library work) @I::"C:\Gowin\1.8\IDE\ipcore\I3C_HDR\data\i3c_hdr.sv" (library work) @I:"C:\Gowin\1.8\IDE\ipcore\I3C_HDR\data\i3c_hdr.sv":"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\temp\I3C_HDR\parameter.v" (library work) Verilog syntax check successful! File E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\temp\I3C_HDR\define.v changed - recompiling File E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\temp\I3C_HDR\parameter.v changed - recompiling Selecting top level module I3C_HDR Running optimization stage 1 on DP ....... Running optimization stage 1 on Cache ....... Running optimization stage 1 on SclkGen ....... Running optimization stage 1 on Core ....... Running optimization stage 1 on encoder83 ....... Running optimization stage 1 on encoder164 ....... Running optimization stage 1 on encoder325 ....... Running optimization stage 1 on I3cPhy ....... @N:CG364 : i3c_wrap.sv(3) | Synthesizing module I3C_HDR in library work. Running optimization stage 1 on I3C_HDR ....... Running optimization stage 2 on I3C_HDR ....... Running optimization stage 2 on I3cPhy ....... Running optimization stage 2 on encoder325 ....... Running optimization stage 2 on encoder164 ....... Running optimization stage 2 on encoder83 ....... Running optimization stage 2 on Core ....... Running optimization stage 2 on SclkGen ....... Running optimization stage 2 on Cache ....... Running optimization stage 2 on DP ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 85MB peak: 96MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Thu Sep 27 09:28:07 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode File E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\temp\I3C_HDR\rev_1\synwork\layer0.srs changed - recompiling @N:NF107 : i3c_wrap.sv(3) | Selected library: work cell: I3C_HDR view verilog as top level @N:NF107 : i3c_wrap.sv(3) | Selected library: work cell: I3C_HDR view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:28:08 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:03s realtime, 0h:00m:02s cputime Process completed successfully. # Thu Sep 27 09:28:08 2018 ###########################################################]