#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: C:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-032 # Thu Sep 27 09:29:20 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\gw_pll\gw_pll.v" (library work) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv" (library work) @W:CG921 : slave.sv(215) | pcInc is already declared in this scope. @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\dejitter.sv" (library work) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\i3c_hdr\i3c_hdr.v" (library work) Verilog syntax check successful! Selecting top level module topS @N:CG364 : dejitter.sv(1) | Synthesizing module deJitter in library work. alwaysState=32'b00000000000000000000000000000001 keyInINI=32'b00000000000000000000000000001111 keyValueINI=32'b00000000000000000000000000000011 Generated name = deJitter_1s_15_3 Running optimization stage 1 on deJitter_1s_15_3 ....... @N:CG364 : gw1n.v(1547) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on LUT2 ....... Running optimization stage 1 on DFFNCE ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFPE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on DP ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on Cache ....... Running optimization stage 1 on Cache_0 ....... Running optimization stage 1 on MUX2_LUT5 ....... Running optimization stage 1 on MUX2_LUT6 ....... Running optimization stage 1 on MUX2_LUT7 ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on SclkGen ....... Running optimization stage 1 on DFFNPE ....... Running optimization stage 1 on DFFNP ....... Running optimization stage 1 on DFFNC ....... Running optimization stage 1 on Core ....... Running optimization stage 1 on encoder83_2_2_0 ....... Running optimization stage 1 on encoder164_1 ....... Running optimization stage 1 on encoder83_2_2_1 ....... Running optimization stage 1 on encoder83_2_2_2 ....... Running optimization stage 1 on encoder164_1_0 ....... Running optimization stage 1 on encoder325_1 ....... Running optimization stage 1 on encoder83_0_1 ....... Running optimization stage 1 on encoder164_1_2 ....... Running optimization stage 1 on encoder83_2_2_3 ....... Running optimization stage 1 on encoder83_0_2 ....... Running optimization stage 1 on encoder164_1_1 ....... Running optimization stage 1 on encoder325_0 ....... Running optimization stage 1 on I3cPhy ....... @N:CG364 : i3c_hdr.v(20227) | Synthesizing module I3C_HDR in library work. Running optimization stage 1 on I3C_HDR ....... @N:CG364 : gw1n.v(1483) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gw_pll.v(13) | Synthesizing module GW_PLL in library work. Running optimization stage 1 on GW_PLL ....... @N:CG364 : slave.sv(1) | Synthesizing module topS in library work. @N:CG179 : slave.sv(228) | Removing redundant assignment. @N:CG179 : slave.sv(233) | Removing redundant assignment. @N:CG179 : slave.sv(281) | Removing redundant assignment. @N:CG179 : slave.sv(297) | Removing redundant assignment. @W:CG360 : slave.sv(16) | Removing wire led_4, as there is no assignment to it. @W:CG360 : slave.sv(17) | Removing wire led_5, as there is no assignment to it. @W:CG360 : slave.sv(18) | Removing wire led_6, as there is no assignment to it. @W:CG360 : slave.sv(22) | Removing wire j8_5, as there is no assignment to it. @W:CG360 : slave.sv(23) | Removing wire j8_6, as there is no assignment to it. @W:CG360 : slave.sv(24) | Removing wire j8_7, as there is no assignment to it. @W:CG360 : slave.sv(25) | Removing wire j8_8, as there is no assignment to it. @W:CG360 : slave.sv(38) | Removing wire j8_21, as there is no assignment to it. @W:CG360 : slave.sv(39) | Removing wire j8_22, as there is no assignment to it. @W:CG360 : slave.sv(40) | Removing wire j8_23, as there is no assignment to it. @W:CG360 : slave.sv(41) | Removing wire j8_24, as there is no assignment to it. @W:CG360 : slave.sv(42) | Removing wire j8_25, as there is no assignment to it. @W:CG360 : slave.sv(43) | Removing wire j8_26, as there is no assignment to it. @W:CG360 : slave.sv(44) | Removing wire j8_27, as there is no assignment to it. @W:CG360 : slave.sv(45) | Removing wire j8_28, as there is no assignment to it. @W:CG360 : slave.sv(46) | Removing wire j8_29, as there is no assignment to it. @W:CG360 : slave.sv(47) | Removing wire j8_30, as there is no assignment to it. @W:CG360 : slave.sv(48) | Removing wire j8_31, as there is no assignment to it. @W:CG360 : slave.sv(49) | Removing wire j8_32, as there is no assignment to it. @W:CG360 : slave.sv(50) | Removing wire j8_33, as there is no assignment to it. @W:CG360 : slave.sv(51) | Removing wire j8_34, as there is no assignment to it. @W:CG360 : slave.sv(52) | Removing wire j8_35, as there is no assignment to it. @W:CG360 : slave.sv(53) | Removing wire j8_36, as there is no assignment to it. @W:CG360 : slave.sv(54) | Removing wire j8_37, as there is no assignment to it. @W:CG360 : slave.sv(55) | Removing wire j8_38, as there is no assignment to it. @W:CG360 : slave.sv(60) | Removing wire j9_6, as there is no assignment to it. @W:CG360 : slave.sv(61) | Removing wire j9_7, as there is no assignment to it. @W:CG360 : slave.sv(62) | Removing wire j9_8, as there is no assignment to it. @W:CG360 : slave.sv(63) | Removing wire j9_9, as there is no assignment to it. @W:CG360 : slave.sv(72) | Removing wire j9_18, as there is no assignment to it. @W:CG360 : slave.sv(73) | Removing wire j9_19, as there is no assignment to it. @W:CG360 : slave.sv(74) | Removing wire j9_20, as there is no assignment to it. @W:CG360 : slave.sv(75) | Removing wire j9_21, as there is no assignment to it. @W:CG360 : slave.sv(76) | Removing wire j9_22, as there is no assignment to it. @W:CG360 : slave.sv(77) | Removing wire j9_23, as there is no assignment to it. @W:CG360 : slave.sv(78) | Removing wire j9_24, as there is no assignment to it. @W:CG360 : slave.sv(79) | Removing wire j9_25, as there is no assignment to it. @W:CG360 : slave.sv(80) | Removing wire j9_26, as there is no assignment to it. @W:CG360 : slave.sv(81) | Removing wire j9_27, as there is no assignment to it. @W:CG360 : slave.sv(82) | Removing wire j9_28, as there is no assignment to it. @W:CG360 : slave.sv(83) | Removing wire j9_29, as there is no assignment to it. @W:CG360 : slave.sv(84) | Removing wire j9_30, as there is no assignment to it. @W:CG360 : slave.sv(85) | Removing wire j9_31, as there is no assignment to it. @W:CG360 : slave.sv(86) | Removing wire j9_32, as there is no assignment to it. @W:CG360 : slave.sv(87) | Removing wire j9_33, as there is no assignment to it. @W:CG360 : slave.sv(88) | Removing wire j9_34, as there is no assignment to it. @W:CG360 : slave.sv(89) | Removing wire j9_35, as there is no assignment to it. @W:CG360 : slave.sv(90) | Removing wire j9_36, as there is no assignment to it. @W:CG360 : slave.sv(91) | Removing wire j9_37, as there is no assignment to it. @W:CG360 : slave.sv(92) | Removing wire j9_38, as there is no assignment to it. @W:CG360 : slave.sv(97) | Removing wire j10_6, as there is no assignment to it. @W:CG360 : slave.sv(98) | Removing wire j10_9, as there is no assignment to it. @W:CG360 : slave.sv(99) | Removing wire j10_10, as there is no assignment to it. @W:CG360 : slave.sv(181) | Removing wire key3, as there is no assignment to it. @W:CG360 : slave.sv(181) | Removing wire key4, as there is no assignment to it. Running optimization stage 1 on topS ....... @W:CL318 : slave.sv(16) | *Output led_4 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(17) | *Output led_5 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(18) | *Output led_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(22) | *Output j8_5 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(23) | *Output j8_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(24) | *Output j8_7 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(25) | *Output j8_8 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(38) | *Output j8_21 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(39) | *Output j8_22 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(40) | *Output j8_23 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(41) | *Output j8_24 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(42) | *Output j8_25 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(43) | *Output j8_26 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(44) | *Output j8_27 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(45) | *Output j8_28 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(46) | *Output j8_29 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(47) | *Output j8_30 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(48) | *Output j8_31 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(49) | *Output j8_32 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(50) | *Output j8_33 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(51) | *Output j8_34 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(52) | *Output j8_35 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(53) | *Output j8_36 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(54) | *Output j8_37 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(55) | *Output j8_38 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(60) | *Output j9_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(61) | *Output j9_7 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(62) | *Output j9_8 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(63) | *Output j9_9 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(72) | *Output j9_18 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(73) | *Output j9_19 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(74) | *Output j9_20 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(75) | *Output j9_21 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(76) | *Output j9_22 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(77) | *Output j9_23 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(78) | *Output j9_24 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(79) | *Output j9_25 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(80) | *Output j9_26 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(81) | *Output j9_27 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(82) | *Output j9_28 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(83) | *Output j9_29 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(84) | *Output j9_30 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(85) | *Output j9_31 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(86) | *Output j9_32 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(87) | *Output j9_33 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(88) | *Output j9_34 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(89) | *Output j9_35 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(90) | *Output j9_36 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(91) | *Output j9_37 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(92) | *Output j9_38 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(97) | *Output j10_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(98) | *Output j10_9 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : slave.sv(99) | *Output j10_10 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : slave.sv(244) | Pruning unused register ptr_SL[10:0]. Make sure that there are no unused intermediate registers. @W:CL169 : slave.sv(244) | Pruning unused register data_tmp[7:0]. Make sure that there are no unused intermediate registers. Running optimization stage 2 on topS ....... @W:CL190 : slave.sv(244) | Optimizing register bit addr[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : slave.sv(244) | Optimizing register bit addr[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : slave.sv(244) | Pruning register bits 9 to 8 of addr[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CL159 : slave.sv(2) | Input clk_ext is unused. @N:CL159 : slave.sv(7) | Input key_3 is unused. @N:CL159 : slave.sv(8) | Input key_4 is unused. @N:CL159 : slave.sv(10) | Input sw_4 is unused. @N:CL159 : slave.sv(11) | Input sw_5 is unused. @N:CL159 : slave.sv(12) | Input sw_6 is unused. @N:CL159 : slave.sv(13) | Input sw_7 is unused. @N:CL159 : slave.sv(100) | Input j10_13 is unused. @N:CL159 : slave.sv(101) | Input j10_14 is unused. @N:CL159 : slave.sv(102) | Input j10_17 is unused. @N:CL159 : slave.sv(103) | Input j10_18 is unused. @N:CL159 : slave.sv(105) | Input j11_1 is unused. @N:CL159 : slave.sv(106) | Input j11_2 is unused. @N:CL159 : slave.sv(107) | Input j11_5 is unused. @N:CL159 : slave.sv(108) | Input j11_6 is unused. @N:CL159 : slave.sv(109) | Input j11_9 is unused. @N:CL159 : slave.sv(110) | Input j11_10 is unused. @N:CL159 : slave.sv(111) | Input j11_13 is unused. @N:CL159 : slave.sv(112) | Input j11_14 is unused. @N:CL159 : slave.sv(113) | Input j11_17 is unused. @N:CL159 : slave.sv(114) | Input j11_18 is unused. Running optimization stage 2 on GW_PLL ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on I3C_HDR ....... Running optimization stage 2 on I3cPhy ....... Running optimization stage 2 on encoder325_0 ....... Running optimization stage 2 on encoder164_1_1 ....... Running optimization stage 2 on encoder83_0_2 ....... Running optimization stage 2 on encoder83_2_2_3 ....... Running optimization stage 2 on encoder164_1_2 ....... Running optimization stage 2 on encoder83_0_1 ....... Running optimization stage 2 on encoder325_1 ....... Running optimization stage 2 on encoder164_1_0 ....... Running optimization stage 2 on encoder83_2_2_2 ....... Running optimization stage 2 on encoder83_2_2_1 ....... Running optimization stage 2 on encoder164_1 ....... Running optimization stage 2 on encoder83_2_2_0 ....... Running optimization stage 2 on Core ....... Running optimization stage 2 on DFFNC ....... Running optimization stage 2 on DFFNP ....... Running optimization stage 2 on DFFNPE ....... Running optimization stage 2 on SclkGen ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on MUX2_LUT7 ....... Running optimization stage 2 on MUX2_LUT6 ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on Cache_0 ....... Running optimization stage 2 on Cache ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on DP ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFNCE ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on GSR ....... Running optimization stage 2 on deJitter_1s_15_3 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 84MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:21 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:22 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:22 2018 ###########################################################]