#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: C:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-032 # Thu Sep 27 09:29:26 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\gw_pll\gw_pll.v" (library work) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv" (library work) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\dejitter.sv" (library work) @I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\i3c_hdr.v" (library work) Verilog syntax check successful! File E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\i3c_hdr\i3c_hdr.v changed - recompiling Selecting top level module topM @N:CG364 : dejitter.sv(1) | Synthesizing module deJitter in library work. alwaysState=32'b00000000000000000000000000000001 keyInINI=32'b00000000000000000000000000001111 keyValueINI=32'b00000000000000000000000000000011 Generated name = deJitter_1s_15_3 Running optimization stage 1 on deJitter_1s_15_3 ....... @N:CG364 : gw1n.v(1547) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on LUT2 ....... Running optimization stage 1 on DFFNCE ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFPE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on DP ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on Cache ....... Running optimization stage 1 on Cache_0 ....... Running optimization stage 1 on MUX2_LUT5 ....... Running optimization stage 1 on MUX2_LUT6 ....... Running optimization stage 1 on MUX2_LUT7 ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on SclkGen ....... Running optimization stage 1 on DFFNPE ....... Running optimization stage 1 on DFFNP ....... Running optimization stage 1 on DFFNC ....... Running optimization stage 1 on Core ....... Running optimization stage 1 on encoder83_2_2_0 ....... Running optimization stage 1 on encoder164_1 ....... Running optimization stage 1 on encoder83_2_2_1 ....... Running optimization stage 1 on encoder83_2_2_2 ....... Running optimization stage 1 on encoder164_1_0 ....... Running optimization stage 1 on encoder325_1 ....... Running optimization stage 1 on encoder83_0_1 ....... Running optimization stage 1 on encoder164_1_2 ....... Running optimization stage 1 on encoder83_2_2_3 ....... Running optimization stage 1 on encoder83_0_2 ....... Running optimization stage 1 on encoder164_1_1 ....... Running optimization stage 1 on encoder325_0 ....... Running optimization stage 1 on I3cPhy ....... @N:CG364 : i3c_hdr.v(20227) | Synthesizing module I3C_HDR in library work. Running optimization stage 1 on I3C_HDR ....... @N:CG364 : gw1n.v(1483) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gw_pll.v(13) | Synthesizing module GW_PLL in library work. Running optimization stage 1 on GW_PLL ....... @N:CG364 : master.sv(2) | Synthesizing module topM in library work. @N:CG179 : master.sv(295) | Removing redundant assignment. @N:CG179 : master.sv(300) | Removing redundant assignment. @N:CG179 : master.sv(304) | Removing redundant assignment. @N:CG179 : master.sv(372) | Removing redundant assignment. @N:CG179 : master.sv(388) | Removing redundant assignment. @W:CG360 : master.sv(17) | Removing wire led_4, as there is no assignment to it. @W:CG360 : master.sv(18) | Removing wire led_5, as there is no assignment to it. @W:CG360 : master.sv(19) | Removing wire led_6, as there is no assignment to it. @W:CG360 : master.sv(49) | Removing wire j8_31, as there is no assignment to it. @W:CG360 : master.sv(50) | Removing wire j8_32, as there is no assignment to it. @W:CG360 : master.sv(51) | Removing wire j8_33, as there is no assignment to it. @W:CG360 : master.sv(52) | Removing wire j8_34, as there is no assignment to it. @W:CG360 : master.sv(53) | Removing wire j8_35, as there is no assignment to it. @W:CG360 : master.sv(54) | Removing wire j8_36, as there is no assignment to it. @W:CG360 : master.sv(55) | Removing wire j8_37, as there is no assignment to it. @W:CG360 : master.sv(56) | Removing wire j8_38, as there is no assignment to it. @W:CG360 : master.sv(60) | Removing wire j9_5, as there is no assignment to it. @W:CG360 : master.sv(61) | Removing wire j9_6, as there is no assignment to it. @W:CG360 : master.sv(62) | Removing wire j9_7, as there is no assignment to it. @W:CG360 : master.sv(63) | Removing wire j9_8, as there is no assignment to it. @W:CG360 : master.sv(64) | Removing wire j9_9, as there is no assignment to it. @W:CG360 : master.sv(65) | Removing wire j9_10, as there is no assignment to it. @W:CG360 : master.sv(66) | Removing wire j9_11, as there is no assignment to it. @W:CG360 : master.sv(67) | Removing wire j9_12, as there is no assignment to it. @W:CG360 : master.sv(68) | Removing wire j9_13, as there is no assignment to it. @W:CG360 : master.sv(69) | Removing wire j9_14, as there is no assignment to it. @W:CG360 : master.sv(70) | Removing wire j9_15, as there is no assignment to it. @W:CG360 : master.sv(71) | Removing wire j9_16, as there is no assignment to it. @W:CG360 : master.sv(72) | Removing wire j9_17, as there is no assignment to it. @W:CG360 : master.sv(73) | Removing wire j9_18, as there is no assignment to it. @W:CG360 : master.sv(74) | Removing wire j9_19, as there is no assignment to it. @W:CG360 : master.sv(75) | Removing wire j9_20, as there is no assignment to it. @W:CG360 : master.sv(76) | Removing wire j9_21, as there is no assignment to it. @W:CG360 : master.sv(77) | Removing wire j9_22, as there is no assignment to it. @W:CG360 : master.sv(78) | Removing wire j9_23, as there is no assignment to it. @W:CG360 : master.sv(79) | Removing wire j9_24, as there is no assignment to it. @W:CG360 : master.sv(80) | Removing wire j9_25, as there is no assignment to it. @W:CG360 : master.sv(81) | Removing wire j9_26, as there is no assignment to it. @W:CG360 : master.sv(82) | Removing wire j9_27, as there is no assignment to it. @W:CG360 : master.sv(83) | Removing wire j9_28, as there is no assignment to it. @W:CG360 : master.sv(84) | Removing wire j9_29, as there is no assignment to it. @W:CG360 : master.sv(85) | Removing wire j9_30, as there is no assignment to it. @W:CG360 : master.sv(86) | Removing wire j9_31, as there is no assignment to it. @W:CG360 : master.sv(87) | Removing wire j9_32, as there is no assignment to it. @W:CG360 : master.sv(88) | Removing wire j9_33, as there is no assignment to it. @W:CG360 : master.sv(89) | Removing wire j9_34, as there is no assignment to it. @W:CG360 : master.sv(90) | Removing wire j9_35, as there is no assignment to it. @W:CG360 : master.sv(91) | Removing wire j9_36, as there is no assignment to it. @W:CG360 : master.sv(92) | Removing wire j9_37, as there is no assignment to it. @W:CG360 : master.sv(93) | Removing wire j9_38, as there is no assignment to it. @W:CG360 : master.sv(98) | Removing wire j10_6, as there is no assignment to it. @W:CG360 : master.sv(99) | Removing wire j10_9, as there is no assignment to it. @W:CG360 : master.sv(100) | Removing wire j10_10, as there is no assignment to it. @W:CG360 : master.sv(205) | Removing wire key3, as there is no assignment to it. @W:CG360 : master.sv(205) | Removing wire key4, as there is no assignment to it. Running optimization stage 1 on topM ....... @W:CL318 : master.sv(17) | *Output led_4 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(18) | *Output led_5 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(19) | *Output led_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(49) | *Output j8_31 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(50) | *Output j8_32 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(51) | *Output j8_33 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(52) | *Output j8_34 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(53) | *Output j8_35 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(54) | *Output j8_36 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(55) | *Output j8_37 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(56) | *Output j8_38 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(60) | *Output j9_5 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(61) | *Output j9_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(62) | *Output j9_7 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(63) | *Output j9_8 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(64) | *Output j9_9 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(65) | *Output j9_10 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(66) | *Output j9_11 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(67) | *Output j9_12 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(68) | *Output j9_13 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(69) | *Output j9_14 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(70) | *Output j9_15 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(71) | *Output j9_16 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(72) | *Output j9_17 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(73) | *Output j9_18 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(74) | *Output j9_19 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(75) | *Output j9_20 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(76) | *Output j9_21 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(77) | *Output j9_22 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(78) | *Output j9_23 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(79) | *Output j9_24 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(80) | *Output j9_25 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(81) | *Output j9_26 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(82) | *Output j9_27 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(83) | *Output j9_28 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(84) | *Output j9_29 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(85) | *Output j9_30 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(86) | *Output j9_31 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(87) | *Output j9_32 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(88) | *Output j9_33 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(89) | *Output j9_34 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(90) | *Output j9_35 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(91) | *Output j9_36 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(92) | *Output j9_37 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(93) | *Output j9_38 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(98) | *Output j10_6 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(99) | *Output j10_9 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : master.sv(100) | *Output j10_10 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : master.sv(314) | Pruning unused register pcInc. Make sure that there are no unused intermediate registers. @A:CL282 : master.sv(314) | Feedback mux created for signal ptr_M[10:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. Running optimization stage 2 on topM ....... @N:CL159 : master.sv(3) | Input clk_ext is unused. @N:CL159 : master.sv(8) | Input key_3 is unused. @N:CL159 : master.sv(9) | Input key_4 is unused. @N:CL159 : master.sv(11) | Input sw_4 is unused. @N:CL159 : master.sv(12) | Input sw_5 is unused. @N:CL159 : master.sv(13) | Input sw_6 is unused. @N:CL159 : master.sv(14) | Input sw_7 is unused. @N:CL159 : master.sv(101) | Input j10_13 is unused. @N:CL159 : master.sv(102) | Input j10_14 is unused. @N:CL159 : master.sv(103) | Input j10_17 is unused. @N:CL159 : master.sv(104) | Input j10_18 is unused. @N:CL159 : master.sv(106) | Input j11_1 is unused. @N:CL159 : master.sv(107) | Input j11_2 is unused. @N:CL159 : master.sv(108) | Input j11_5 is unused. @N:CL159 : master.sv(109) | Input j11_6 is unused. @N:CL159 : master.sv(110) | Input j11_9 is unused. @N:CL159 : master.sv(111) | Input j11_10 is unused. @N:CL159 : master.sv(112) | Input j11_13 is unused. @N:CL159 : master.sv(113) | Input j11_14 is unused. @N:CL159 : master.sv(114) | Input j11_17 is unused. @N:CL159 : master.sv(115) | Input j11_18 is unused. Running optimization stage 2 on GW_PLL ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on I3C_HDR ....... Running optimization stage 2 on I3cPhy ....... Running optimization stage 2 on encoder325_0 ....... Running optimization stage 2 on encoder164_1_1 ....... Running optimization stage 2 on encoder83_0_2 ....... Running optimization stage 2 on encoder83_2_2_3 ....... Running optimization stage 2 on encoder164_1_2 ....... Running optimization stage 2 on encoder83_0_1 ....... Running optimization stage 2 on encoder325_1 ....... Running optimization stage 2 on encoder164_1_0 ....... Running optimization stage 2 on encoder83_2_2_2 ....... Running optimization stage 2 on encoder83_2_2_1 ....... Running optimization stage 2 on encoder164_1 ....... Running optimization stage 2 on encoder83_2_2_0 ....... Running optimization stage 2 on Core ....... Running optimization stage 2 on DFFNC ....... Running optimization stage 2 on DFFNP ....... Running optimization stage 2 on DFFNPE ....... Running optimization stage 2 on SclkGen ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on MUX2_LUT7 ....... Running optimization stage 2 on MUX2_LUT6 ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on Cache_0 ....... Running optimization stage 2 on Cache ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on DP ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFNCE ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on GSR ....... Running optimization stage 2 on deJitter_1s_15_3 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 85MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:27 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode File E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:28 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 27 09:29:28 2018 ###########################################################]