#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-032

# Wed Sep 26 16:46:34 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
@W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
@W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
@W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
@W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
@W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
@W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
@W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
@W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
@W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
@W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
@W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
@W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
@W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
@W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
@W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
@W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
@W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
@W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
@W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
Verilog syntax check successful!
@N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_23s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_1s_23s_0_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_1s_23s_0_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_23s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Sep 26 16:46:35 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Sep 26 16:46:35 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Sep 26 16:46:35 2018

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Database state : E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Sep 26 16:46:36 2018

###########################################################]


Premap Report



# Wed Sep 26 16:46:37 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  ao_0_scck.rpt
Printing clock  summary report in "E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

@N:BN133 :  | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

@N:MF974 :  | Total number of latches (multibit) processed = 0  
@N:MF975 :  | Total number of latches (bit blasted) processed = 0  
@N:MF976 :  | Total number of (multibit) opaque latches found = 0  
@N:MF977 :  | Total number of (bit blasted) opaque latches found = 0  

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)







Detailed report for transparent and observable latches in design:
Linked File:  ao_0_prem_latch_transparency_report.log
Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)

syn_allowed_resources : blockrams=24  set on top level netlist ao_top_0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     138.6 MHz     7.216         inferred     Autoconstr_clkgroup_1     270  
                                                                                                          
0 -       ao_top_0|clk_i          168.2 MHz     5.946         inferred     Autoconstr_clkgroup_0     87   
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     270       control[0](port)     data_register[43:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          87        clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 335 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
ClockId_0_0       ENCRYPTED           Unconstrained_port        65         ENCRYPTED      
ClockId_0_1       ENCRYPTED           Unconstrained_io_port     270        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Wed Sep 26 16:46:39 2018

###########################################################]


Map & Optimize Report



# Wed Sep 26 16:46:39 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 200MB peak: 200MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 199MB peak: 200MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -3.32ns		 473 /       305
   2		0h:00m:03s		    -3.32ns		 463 /       305
   3		0h:00m:03s		    -3.32ns		 463 /       305
   4		0h:00m:03s		    -3.06ns		 462 /       305
   5		0h:00m:03s		    -3.06ns		 462 /       305
   6		0h:00m:03s		    -3.32ns		 462 /       305
Timing driven replication report
Added 13 Registers via timing driven replication
Added 6 LUTs via timing driven replication

   7		0h:00m:03s		    -2.58ns		 493 /       318
   8		0h:00m:03s		    -2.58ns		 495 /       318
   9		0h:00m:03s		    -2.58ns		 495 /       318
  10		0h:00m:03s		    -2.58ns		 496 /       318
  11		0h:00m:03s		    -2.58ns		 496 /       318


  12		0h:00m:03s		    -2.58ns		 492 /       318
  13		0h:00m:03s		    -2.73ns		 492 /       318
  14		0h:00m:03s		    -2.58ns		 493 /       318
  15		0h:00m:03s		    -2.73ns		 493 /       318
  16		0h:00m:03s		    -2.73ns		 493 /       318

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 145MB peak: 217MB)

Writing Analyst data base E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\read\project_M\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 215MB peak: 218MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 218MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 214MB peak: 218MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 215MB peak: 218MB)

@W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 7.96ns. Please declare a user-defined clock on port clk_i. 
@W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 10.33ns. Please declare a user-defined clock on port control[0]. 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Sep 26 16:46:46 2018
#


Top view:               ao_top_0
Requested Frequency:    96.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.823

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          125.7 MHz     106.8 MHz     7.956         9.360         -1.404     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     96.8 MHz      82.3 MHz      10.332        12.155        -1.823     inferred     Autoconstr_clkgroup_1
System                  100.0 MHz     164.7 MHz     10.000        6.073         3.927      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  7.956       3.927   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  10.332      7.081   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  7.956       6.568   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  7.956       -1.404  |  7.956       6.435  |  No paths    -      |  3.978       2.457
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  10.332      8.883   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  10.332      -1.823  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                                  Arrival           
Instance                             Reference          Type      Pin     Net                                  Time        Slack 
                                     Clock                                                                                       
---------------------------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC      Q       internal_reg_force_triger_syn[1]     0.367       -1.404
genblk1\.u_ao_match_0.match_sep      ao_top_0|clk_i     DFFC      Q       match                                0.367       -1.337
triger_level_cnt[2]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]                  0.367       -1.127
u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC      Q       capture_length[0]                    0.367       -0.717
trigger_seq_start                    ao_top_0|clk_i     DFFCE     Q       trigger_seq_start                    0.367       -0.464
u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC      Q       capture_length[1]                    0.367       -0.440
u_ao_mem_ctrl.capture_loop           ao_top_0|clk_i     DFFCE     Q       capture_loop                         0.367       -0.397
triger_level_cnt[0]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[0]                  0.367       -0.397
triger_level_cnt[3]                  ao_top_0|clk_i     DFFC      Q       triger_level_cnt[3]                  0.367       -0.268
u_ao_mem_ctrl.capture_length[2]      ao_top_0|clk_i     DFFC      Q       capture_length[2]                    0.367       -0.244
=================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                         Required           
Instance                              Reference          Type      Pin     Net                         Time         Slack 
                                      Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       7.823        -1.404
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       7.823        -1.404
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     7.823        -1.216
triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       7.823        -1.208
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      capture_mem_wr_RNO          7.823        -0.547
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6        7.823        0.162 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]      7.823        0.162 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]      7.823        0.162 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]      7.823        0.162 
u_ao_mem_ctrl.capture_mem_addr[3]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[3]      7.823        0.162 
==========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      9.227
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.404

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                  Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]      DFFC     Q        Out     0.367     0.367       -         
internal_reg_force_triger_syn[1]      Net      -        -       1.021     -           2         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     I1       In      -         1.388       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     F        Out     1.099     2.487       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     I3       In      -         3.253       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     F        Out     0.626     3.879       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa             LUT4     I3       In      -         4.644       -         
triger_level_cnt_0_sqmuxa             LUT4     F        Out     0.626     5.270       -         
triger_level_cnt_0_sqmuxa             Net      -        -       1.082     -           16        
un1_triger_level_cnt12                LUT2     I0       In      -         6.352       -         
un1_triger_level_cnt12                LUT2     F        Out     1.032     7.384       -         
un1_triger_level_cnt12                Net      -        -       1.021     -           3         
triger_level_cnt_4[2]                 LUT4     I2       In      -         8.405       -         
triger_level_cnt_4[2]                 LUT4     F        Out     0.822     9.227       -         
triger_level_cnt_4[2]                 Net      -        -       0.000     -           1         
triger_level_cnt[2]                   DFFC     D        In      -         9.227       -         
================================================================================================
Total path delay (propagation time + setup) of 9.360 is 4.705(50.3%) logic and 4.655(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      9.227
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.404

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            triger_level_cnt[3] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                  Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]      DFFC     Q        Out     0.367     0.367       -         
internal_reg_force_triger_syn[1]      Net      -        -       1.021     -           2         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     I1       In      -         1.388       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     F        Out     1.099     2.487       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     I3       In      -         3.253       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     F        Out     0.626     3.879       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa             LUT4     I3       In      -         4.644       -         
triger_level_cnt_0_sqmuxa             LUT4     F        Out     0.626     5.270       -         
triger_level_cnt_0_sqmuxa             Net      -        -       1.082     -           16        
un1_triger_level_cnt12                LUT2     I0       In      -         6.352       -         
un1_triger_level_cnt12                LUT2     F        Out     1.032     7.384       -         
un1_triger_level_cnt12                Net      -        -       1.021     -           3         
triger_level_cnt_4[3]                 LUT4     I2       In      -         8.405       -         
triger_level_cnt_4[3]                 LUT4     F        Out     0.822     9.227       -         
triger_level_cnt_4[3]                 Net      -        -       0.000     -           1         
triger_level_cnt[3]                   DFFC     D        In      -         9.227       -         
================================================================================================
Total path delay (propagation time + setup) of 9.360 is 4.705(50.3%) logic and 4.655(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      9.160
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.337

    Number of logic level(s):                5
    Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                  Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
genblk1\.u_ao_match_0.match_sep       DFFC     Q        Out     0.367     0.367       -         
match                                 Net      -        -       1.021     -           2         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     I0       In      -         1.388       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     F        Out     1.032     2.420       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     I3       In      -         3.186       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     F        Out     0.626     3.812       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa             LUT4     I3       In      -         4.577       -         
triger_level_cnt_0_sqmuxa             LUT4     F        Out     0.626     5.203       -         
triger_level_cnt_0_sqmuxa             Net      -        -       1.082     -           16        
un1_triger_level_cnt12                LUT2     I0       In      -         6.285       -         
un1_triger_level_cnt12                LUT2     F        Out     1.032     7.317       -         
un1_triger_level_cnt12                Net      -        -       1.021     -           3         
triger_level_cnt_4[2]                 LUT4     I2       In      -         8.338       -         
triger_level_cnt_4[2]                 LUT4     F        Out     0.822     9.160       -         
triger_level_cnt_4[2]                 Net      -        -       0.000     -           1         
triger_level_cnt[2]                   DFFC     D        In      -         9.160       -         
================================================================================================
Total path delay (propagation time + setup) of 9.293 is 4.638(49.9%) logic and 4.655(50.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      9.160
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.337

    Number of logic level(s):                5
    Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
    Ending point:                            triger_level_cnt[3] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                  Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
genblk1\.u_ao_match_0.match_sep       DFFC     Q        Out     0.367     0.367       -         
match                                 Net      -        -       1.021     -           2         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     I0       In      -         1.388       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     LUT3     F        Out     1.032     2.420       -         
triger_level_cnt_0_sqmuxa_N_2L1_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     I3       In      -         3.186       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     LUT4     F        Out     0.626     3.812       -         
triger_level_cnt_0_sqmuxa_N_3L3_0     Net      -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa             LUT4     I3       In      -         4.577       -         
triger_level_cnt_0_sqmuxa             LUT4     F        Out     0.626     5.203       -         
triger_level_cnt_0_sqmuxa             Net      -        -       1.082     -           16        
un1_triger_level_cnt12                LUT2     I0       In      -         6.285       -         
un1_triger_level_cnt12                LUT2     F        Out     1.032     7.317       -         
un1_triger_level_cnt12                Net      -        -       1.021     -           3         
triger_level_cnt_4[3]                 LUT4     I2       In      -         8.338       -         
triger_level_cnt_4[3]                 LUT4     F        Out     0.822     9.160       -         
triger_level_cnt_4[3]                 Net      -        -       0.000     -           1         
triger_level_cnt[3]                   DFFC     D        In      -         9.160       -         
================================================================================================
Total path delay (propagation time + setup) of 9.293 is 4.638(49.9%) logic and 4.655(50.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      9.039
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.216

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                            Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]                DFFC      Q        Out     0.367     0.367       -         
internal_reg_force_triger_syn[1]                Net       -        -       1.021     -           2         
triger_level_cnt_0_sqmuxa_N_2L1_0               LUT3      I1       In      -         1.388       -         
triger_level_cnt_0_sqmuxa_N_2L1_0               LUT3      F        Out     1.099     2.487       -         
triger_level_cnt_0_sqmuxa_N_2L1_0               Net       -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa_N_3L3_0               LUT4      I3       In      -         3.253       -         
triger_level_cnt_0_sqmuxa_N_3L3_0               LUT4      F        Out     0.626     3.879       -         
triger_level_cnt_0_sqmuxa_N_3L3_0               Net       -        -       0.766     -           1         
triger_level_cnt_0_sqmuxa                       LUT4      I3       In      -         4.644       -         
triger_level_cnt_0_sqmuxa                       LUT4      F        Out     0.626     5.270       -         
triger_level_cnt_0_sqmuxa                       Net       -        -       1.082     -           16        
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1     LUT3      I1       In      -         6.352       -         
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1     LUT3      F        Out     1.099     7.451       -         
un1_capture_length_zero_1_0                     Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_length_zero           LUT4      I2       In      -         8.217       -         
u_ao_mem_ctrl.un1_capture_length_zero           LUT4      F        Out     0.822     9.039       -         
un1_capture_length_zero                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                   DFFCE     CE       In      -         9.039       -         
===========================================================================================================
Total path delay (propagation time + setup) of 9.172 is 4.772(52.0%) logic and 4.400(48.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                   Arrival           
Instance                         Reference               Type      Pin     Net                              Time        Slack 
                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------
internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.367       -1.823
internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.367       -1.756
bit_count[2]                     ao_top_0|control[0]     DFFCE     Q       bit_count[2]                     0.367       -1.560
internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.367       -1.546
internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.367       -1.546
internal_register_select[6]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[6]      0.367       -1.501
internal_register_select[4]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[4]      0.367       -1.495
bit_count[1]                     ao_top_0|control[0]     DFFCE     Q       bit_count[1]                     0.367       -1.493
internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.367       -1.479
internal_register_select[11]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[11]     0.367       -1.350
==============================================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                                Required           
Instance                   Reference               Type      Pin     Net                           Time         Slack 
                           Clock                                                                                      
----------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[0]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]       10.199       -1.823
bit_count[0]               ao_top_0|control[0]     DFFCE     D       bit_count_lm[0]               10.199       -1.560
bit_count[1]               ao_top_0|control[0]     DFFCE     D       bit_count_lm[1]               10.199       -1.560
bit_count[2]               ao_top_0|control[0]     DFFCE     D       bit_count_lm[2]               10.199       -1.560
bit_count[3]               ao_top_0|control[0]     DFFCE     D       bit_count_lm[3]               10.199       -1.560
bit_count[4]               ao_top_0|control[0]     DFFCE     D       bit_count_lm[4]               10.199       -1.560
data_out_shift_reg[1]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]       10.199       -0.801
capture_windows_num[0]     ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[0]     10.199       -0.479
capture_windows_num[1]     ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[1]     10.199       -0.479
capture_windows_num[2]     ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[2]     10.199       -0.479
======================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.332
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.199

    - Propagation time:                      12.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.823

    Number of logic level(s):                6
    Starting point:                          internal_register_select[9] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
internal_register_select[9]                         DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[9]                         Net       -        -       1.021     -           3         
match_unit_rd_en_2_4[0]                             LUT4      I1       In      -         1.388       -         
match_unit_rd_en_2_4[0]                             LUT4      F        Out     1.099     2.487       -         
match_unit_rd_en_2_4[0]                             Net       -        -       1.021     -           4         
match_unit_rd_en[0]                                 LUT3      I1       In      -         3.508       -         
match_unit_rd_en[0]                                 LUT3      F        Out     1.099     4.607       -         
match_unit_rd_en[0]                                 Net       -        -       1.021     -           1         
genblk1\.u_ao_match_0.match_unit_rd_en_RNIC8E01     LUT3      I2       In      -         5.628       -         
genblk1\.u_ao_match_0.match_unit_rd_en_RNIC8E01     LUT3      F        Out     0.822     6.450       -         
data_from_match_unit[0]                             Net       -        -       1.021     -           1         
data_from_ao_reg_7_1[0]                             LUT4      I2       In      -         7.471       -         
data_from_ao_reg_7_1[0]                             LUT4      F        Out     0.822     8.293       -         
data_from_ao_reg_7_1[0]                             Net       -        -       0.766     -           1         
data_from_ao_reg_7_3_0[0]                           LUT4      I1       In      -         9.059       -         
data_from_ao_reg_7_3_0[0]                           LUT4      F        Out     1.099     10.158      -         
data_from_ao_reg_7_3_0[0]                           Net       -        -       0.766     -           1         
data_out_shift_reg_4[0]                             LUT4      I1       In      -         10.923      -         
data_out_shift_reg_4[0]                             LUT4      F        Out     1.099     12.022      -         
data_out_shift_reg_4[0]                             Net       -        -       0.000     -           1         
data_out_shift_reg[0]                               DFFCE     D        In      -         12.022      -         
===============================================================================================================
Total path delay (propagation time + setup) of 12.155 is 6.540(53.8%) logic and 5.615(46.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.332
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.199

    - Propagation time:                      11.955
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.756

    Number of logic level(s):                6
    Starting point:                          internal_register_select[7] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
internal_register_select[7]                         DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[7]                         Net       -        -       1.021     -           3         
match_unit_rd_en_2_4[0]                             LUT4      I0       In      -         1.388       -         
match_unit_rd_en_2_4[0]                             LUT4      F        Out     1.032     2.420       -         
match_unit_rd_en_2_4[0]                             Net       -        -       1.021     -           4         
match_unit_rd_en[0]                                 LUT3      I1       In      -         3.441       -         
match_unit_rd_en[0]                                 LUT3      F        Out     1.099     4.540       -         
match_unit_rd_en[0]                                 Net       -        -       1.021     -           1         
genblk1\.u_ao_match_0.match_unit_rd_en_RNIC8E01     LUT3      I2       In      -         5.561       -         
genblk1\.u_ao_match_0.match_unit_rd_en_RNIC8E01     LUT3      F        Out     0.822     6.383       -         
data_from_match_unit[0]                             Net       -        -       1.021     -           1         
data_from_ao_reg_7_1[0]                             LUT4      I2       In      -         7.404       -         
data_from_ao_reg_7_1[0]                             LUT4      F        Out     0.822     8.226       -         
data_from_ao_reg_7_1[0]                             Net       -        -       0.766     -           1         
data_from_ao_reg_7_3_0[0]                           LUT4      I1       In      -         8.992       -         
data_from_ao_reg_7_3_0[0]                           LUT4      F        Out     1.099     10.091      -         
data_from_ao_reg_7_3_0[0]                           Net       -        -       0.766     -           1         
data_out_shift_reg_4[0]                             LUT4      I1       In      -         10.856      -         
data_out_shift_reg_4[0]                             LUT4      F        Out     1.099     11.955      -         
data_out_shift_reg_4[0]                             Net       -        -       0.000     -           1         
data_out_shift_reg[0]                               DFFCE     D        In      -         11.955      -         
===============================================================================================================
Total path delay (propagation time + setup) of 12.088 is 6.473(53.5%) logic and 5.615(46.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.332
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.199

    - Propagation time:                      11.759
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.560

    Number of logic level(s):                6
    Starting point:                          bit_count[2] / Q
    Ending point:                            bit_count[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
bit_count[2]                         DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                         Net       -        -       1.021     -           4         
module_state_ns_0_a2_RNO[10]         LUT2      I1       In      -         1.388       -         
module_state_ns_0_a2_RNO[10]         LUT2      F        Out     1.099     2.487       -         
module_state_ns_0_a2_2_0[10]         Net       -        -       0.766     -           1         
module_state_ns_0_a2[10]             LUT4      I3       In      -         3.253       -         
module_state_ns_0_a2[10]             LUT4      F        Out     0.626     3.879       -         
module_state_ns_0_a2[10]             Net       -        -       1.021     -           9         
module_state_ns_0_a2_RNI5P96[10]     LUT4      I1       In      -         4.900       -         
module_state_ns_0_a2_RNI5P96[10]     LUT4      F        Out     1.099     5.999       -         
N_36                                 Net       -        -       1.021     -           2         
data_register_RNICVNR2[41]           LUT4      I2       In      -         7.020       -         
data_register_RNICVNR2[41]           LUT4      F        Out     0.822     7.842       -         
g0_i_m2_0_1                          Net       -        -       0.766     -           1         
module_state_0_rep2_RNI9D776         LUT4      I0       In      -         8.607       -         
module_state_0_rep2_RNI9D776         LUT4      F        Out     1.032     9.639       -         
bit_ct_rst                           Net       -        -       1.021     -           5         
bit_count_lm_0[0]                    LUT2      I1       In      -         10.660      -         
bit_count_lm_0[0]                    LUT2      F        Out     1.099     11.759      -         
bit_count_lm[0]                      Net       -        -       0.000     -           1         
bit_count[0]                         DFFCE     D        In      -         11.759      -         
================================================================================================
Total path delay (propagation time + setup) of 11.892 is 6.277(52.8%) logic and 5.615(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.332
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.199

    - Propagation time:                      11.759
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.560

    Number of logic level(s):                6
    Starting point:                          bit_count[2] / Q
    Ending point:                            bit_count[4] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
bit_count[2]                         DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                         Net       -        -       1.021     -           4         
module_state_ns_0_a2_RNO[10]         LUT2      I1       In      -         1.388       -         
module_state_ns_0_a2_RNO[10]         LUT2      F        Out     1.099     2.487       -         
module_state_ns_0_a2_2_0[10]         Net       -        -       0.766     -           1         
module_state_ns_0_a2[10]             LUT4      I3       In      -         3.253       -         
module_state_ns_0_a2[10]             LUT4      F        Out     0.626     3.879       -         
module_state_ns_0_a2[10]             Net       -        -       1.021     -           9         
module_state_ns_0_a2_RNI5P96[10]     LUT4      I1       In      -         4.900       -         
module_state_ns_0_a2_RNI5P96[10]     LUT4      F        Out     1.099     5.999       -         
N_36                                 Net       -        -       1.021     -           2         
data_register_RNICVNR2[41]           LUT4      I2       In      -         7.020       -         
data_register_RNICVNR2[41]           LUT4      F        Out     0.822     7.842       -         
g0_i_m2_0_1                          Net       -        -       0.766     -           1         
module_state_0_rep2_RNI9D776         LUT4      I0       In      -         8.607       -         
module_state_0_rep2_RNI9D776         LUT4      F        Out     1.032     9.639       -         
bit_ct_rst                           Net       -        -       1.021     -           5         
bit_count_lm_0[4]                    LUT2      I1       In      -         10.660      -         
bit_count_lm_0[4]                    LUT2      F        Out     1.099     11.759      -         
bit_count_lm[4]                      Net       -        -       0.000     -           1         
bit_count[4]                         DFFCE     D        In      -         11.759      -         
================================================================================================
Total path delay (propagation time + setup) of 11.892 is 6.277(52.8%) logic and 5.615(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.332
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.199

    - Propagation time:                      11.759
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.560

    Number of logic level(s):                6
    Starting point:                          bit_count[2] / Q
    Ending point:                            bit_count[3] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
bit_count[2]                         DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                         Net       -        -       1.021     -           4         
module_state_ns_0_a2_RNO[10]         LUT2      I1       In      -         1.388       -         
module_state_ns_0_a2_RNO[10]         LUT2      F        Out     1.099     2.487       -         
module_state_ns_0_a2_2_0[10]         Net       -        -       0.766     -           1         
module_state_ns_0_a2[10]             LUT4      I3       In      -         3.253       -         
module_state_ns_0_a2[10]             LUT4      F        Out     0.626     3.879       -         
module_state_ns_0_a2[10]             Net       -        -       1.021     -           9         
module_state_ns_0_a2_RNI5P96[10]     LUT4      I1       In      -         4.900       -         
module_state_ns_0_a2_RNI5P96[10]     LUT4      F        Out     1.099     5.999       -         
N_36                                 Net       -        -       1.021     -           2         
data_register_RNICVNR2[41]           LUT4      I2       In      -         7.020       -         
data_register_RNICVNR2[41]           LUT4      F        Out     0.822     7.842       -         
g0_i_m2_0_1                          Net       -        -       0.766     -           1         
module_state_0_rep2_RNI9D776         LUT4      I0       In      -         8.607       -         
module_state_0_rep2_RNI9D776         LUT4      F        Out     1.032     9.639       -         
bit_ct_rst                           Net       -        -       1.021     -           5         
bit_count_lm_0[3]                    LUT2      I1       In      -         10.660      -         
bit_count_lm_0[3]                    LUT2      F        Out     1.099     11.759      -         
bit_count_lm[3]                      Net       -        -       0.000     -           1         
bit_count[3]                         DFFCE     D        In      -         11.759      -         
================================================================================================
Total path delay (propagation time + setup) of 11.892 is 6.277(52.8%) logic and 5.615(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       3.927
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       7.081
=============================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                         Required          
Instance                       Reference     Type      Pin     Net                              Time         Slack
                               Clock                                                                              
------------------------------------------------------------------------------------------------------------------
capture_window_sel[2]          System        DFFC      D       capture_window_sel_3[2]          7.823        3.927
capture_window_sel[3]          System        DFFC      D       capture_window_sel_3[3]          7.823        3.927
capture_window_sel[1]          System        DFFC      D       capture_window_sel_3[1]          7.823        4.123
capture_window_sel_fast[1]     System        DFFC      D       capture_window_sel_3_fast[1]     7.823        4.123
capture_window_sel[0]          System        DFFC      D       capture_window_sel_3[0]          7.823        5.770
capture_window_sel_fast[0]     System        DFFC      D       capture_window_sel_3_fast[0]     7.823        5.770
internal_reg_start_dly[0]      System        DFFC      D       internal_reg_start_dly_2[0]      7.823        5.770
capture_end_dly                System        DFFP      D       capture_end                      7.823        6.802
address_counter[9]             System        DFFCE     D       address_counter_s[9]             10.199       7.081
address_counter[8]             System        DFFCE     D       address_counter_s[8]             10.199       7.138
==================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      7.956
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.823

    - Propagation time:                      3.896
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.927

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       1.021     -           7         
un1_capture_window_sel_ac0_1             LUT4     I0       In      -         1.021       -         
un1_capture_window_sel_ac0_1             LUT4     F        Out     1.032     2.053       -         
un1_capture_window_sel_c2                Net      -        -       1.021     -           2         
capture_window_sel_3[2]                  LUT3     I2       In      -         3.074       -         
capture_window_sel_3[2]                  LUT3     F        Out     0.822     3.896       -         
capture_window_sel_3[2]                  Net      -        -       0.000     -           1         
capture_window_sel[2]                    DFFC     D        In      -         3.896       -         
===================================================================================================
Total path delay (propagation time + setup) of 4.029 is 1.987(49.3%) logic and 2.042(50.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 215MB peak: 218MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 215MB peak: 218MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw1n_9eslqfp144-6
Cell usage:
ALU             69 uses
DFF             22 uses
DFFC            46 uses
DFFCE           210 uses
DFFNP           2 uses
DFFP            6 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       9 uses
SDPX9           2 uses
LUT2            64 uses
LUT3            126 uses
LUT4            252 uses

I/O ports: 34
I/O primitives: 34
IBUF           32 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   318 of 6480 (4%)

RAM/ROM usage summary
Block Rams : 2 of 24 (8%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 254

@S |Mapping Summary:
Total  LUTs: 442 (5%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 45MB peak: 218MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Wed Sep 26 16:46:46 2018

###########################################################]