#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-032

# Thu Sep 27 09:29:49 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
@W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
@W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
@W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
@W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
@W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
@W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
@W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
@W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
@W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
@W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
@W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
@W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
@W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
@W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
@W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
@W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
@W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
@W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
@W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
Verilog syntax check successful!
@N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_24s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_1s_24s_0_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_1s_24s_0_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_24s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:50 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:50 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:50 2018

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Database state : E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:52 2018

###########################################################]


Premap Report



# Thu Sep 27 09:29:52 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  ao_0_scck.rpt
Printing clock  summary report in "E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

@N:BN133 :  | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

@N:MF974 :  | Total number of latches (multibit) processed = 0  
@N:MF975 :  | Total number of latches (bit blasted) processed = 0  
@N:MF976 :  | Total number of (multibit) opaque latches found = 0  
@N:MF977 :  | Total number of (bit blasted) opaque latches found = 0  

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)







Detailed report for transparent and observable latches in design:
Linked File:  ao_0_prem_latch_transparency_report.log
Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)

syn_allowed_resources : blockrams=24  set on top level netlist ao_top_0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     138.6 MHz     7.216         inferred     Autoconstr_clkgroup_1     273  
                                                                                                          
0 -       ao_top_0|clk_i          168.2 MHz     5.946         inferred     Autoconstr_clkgroup_0     89   
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     273       control[0](port)     data_register[44:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          89        clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 339 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
ClockId_0_0       ENCRYPTED           Unconstrained_port        66         ENCRYPTED      
ClockId_0_1       ENCRYPTED           Unconstrained_io_port     273        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Thu Sep 27 09:29:54 2018

###########################################################]


Map & Optimize Report



# Thu Sep 27 09:29:54 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 196MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 196MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 196MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 213MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -3.64ns		 412 /       308
   2		0h:00m:02s		    -3.64ns		 415 /       308
   3		0h:00m:02s		    -3.64ns		 415 /       308
   4		0h:00m:02s		    -3.64ns		 415 /       308
Timing driven replication report
Added 10 Registers via timing driven replication
Added 7 LUTs via timing driven replication

   5		0h:00m:03s		    -2.02ns		 448 /       318
   6		0h:00m:03s		    -2.27ns		 452 /       318
   7		0h:00m:03s		    -2.27ns		 451 /       318
   8		0h:00m:03s		    -1.98ns		 452 /       318
   9		0h:00m:03s		    -1.98ns		 452 /       318


  10		0h:00m:03s		    -1.98ns		 458 /       318
  11		0h:00m:03s		    -1.98ns		 458 /       318
  12		0h:00m:03s		    -1.98ns		 458 /       318
  13		0h:00m:03s		    -2.20ns		 458 /       318
  14		0h:00m:03s		    -1.98ns		 458 /       318

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 213MB peak: 214MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 213MB peak: 214MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 143MB peak: 215MB)

Writing Analyst data base E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 212MB peak: 215MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 213MB peak: 215MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 211MB peak: 215MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 212MB peak: 215MB)

@W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 8.10ns. Please declare a user-defined clock on port clk_i. 
@W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 9.32ns. Please declare a user-defined clock on port control[0]. 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Sep 27 09:30:02 2018
#


Top view:               ao_top_0
Requested Frequency:    107.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.645

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          123.5 MHz     104.9 MHz     8.099         9.529         -1.429     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     107.3 MHz     91.2 MHz      9.321         10.966        -1.645     inferred     Autoconstr_clkgroup_1
System                  100.0 MHz     162.9 MHz     10.000        6.139         3.861      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  8.099       3.861   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  9.321       6.070   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  8.099       6.711   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  8.099       -1.429  |  8.099       6.578  |  No paths    -      |  4.050       2.529
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  9.321       7.933   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  9.321       -1.645  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                        Arrival           
Instance                                 Reference          Type      Pin     Net                        Time        Slack 
                                         Clock                                                                             
---------------------------------------------------------------------------------------------------------------------------
triger_level_cnt[3]                      ao_top_0|clk_i     DFFC      Q       triger_level_cnt[3]        0.367       -1.429
triger_level_cnt[2]                      ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]        0.367       -1.362
u_ao_mem_ctrl.capture_length_fast[0]     ao_top_0|clk_i     DFFC      Q       capture_length_fast[0]     0.367       -0.913
u_ao_mem_ctrl.capture_length[1]          ao_top_0|clk_i     DFFC      Q       capture_length[1]          0.367       -0.780
u_ao_mem_ctrl.capture_length[2]          ao_top_0|clk_i     DFFC      Q       capture_length[2]          0.367       -0.723
u_ao_mem_ctrl.capture_length[3]          ao_top_0|clk_i     DFFP      Q       capture_length[3]          0.367       -0.666
u_ao_mem_ctrl.capture_length[4]          ao_top_0|clk_i     DFFC      Q       capture_length[4]          0.367       -0.609
trigger_seq_start                        ao_top_0|clk_i     DFFCE     Q       trigger_seq_start          0.367       -0.342
u_ao_mem_ctrl.capture_length[5]          ao_top_0|clk_i     DFFC      Q       capture_length[5]          0.367       -0.332
u_ao_mem_ctrl.capture_loop               ao_top_0|clk_i     DFFCE     Q       capture_loop               0.367       -0.275
===========================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                        Required           
Instance                              Reference          Type      Pin     Net                        Time         Slack 
                                      Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      capture_mem_wr_RNO         7.966        -1.429
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      mem_addr_inc_en_RNO        7.966        -0.913
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]      7.966        -0.085
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7           7.966        0.158 
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]      7.966        0.158 
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]      7.966        0.192 
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6       7.966        0.305 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]     7.966        0.305 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]     7.966        0.305 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]     7.966        0.305 
=========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      9.396
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.429

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[3] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
triger_level_cnt[3]                           DFFC          Q        Out     0.367     0.367       -         
triger_level_cnt[3]                           Net           -        -       1.021     -           4         
triger_level_cnt_RNI52BK[3]                   LUT2          I1       In      -         1.388       -         
triger_level_cnt_RNI52BK[3]                   LUT2          F        Out     1.099     2.487       -         
g0_0_1_0                                      Net           -        -       1.021     -           2         
internal_reg_force_triger_syn_RNIDFVF2[1]     MUX2_LUT5     S0       In      -         3.508       -         
internal_reg_force_triger_syn_RNIDFVF2[1]     MUX2_LUT5     O        Out     0.472     3.980       -         
g0_20_sx                                      Net           -        -       1.021     -           1         
u_ao_mem_ctrl_capture_loop_RNIGDJS4           LUT4          I3       In      -         5.001       -         
u_ao_mem_ctrl_capture_loop_RNIGDJS4           LUT4          F        Out     0.626     5.627       -         
triger_level_cnt_0_sqmuxa                     Net           -        -       1.082     -           16        
u_ao_mem_ctrl.capture_mem_wr_RNO_1            LUT3          I2       In      -         6.709       -         
u_ao_mem_ctrl.capture_mem_wr_RNO_1            LUT3          F        Out     0.822     7.531       -         
g0_1_0                                        Net           -        -       0.766     -           1         
u_ao_mem_ctrl.capture_mem_wr_RNO              LUT4          I1       In      -         8.297       -         
u_ao_mem_ctrl.capture_mem_wr_RNO              LUT4          F        Out     1.099     9.396       -         
capture_mem_wr_RNO                            Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr                  DFFCE         CE       In      -         9.396       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.529 is 4.618(48.5%) logic and 4.911(51.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      9.329
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.362

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[2] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
triger_level_cnt[2]                           DFFC          Q        Out     0.367     0.367       -         
triger_level_cnt[2]                           Net           -        -       1.021     -           5         
triger_level_cnt_RNI52BK[3]                   LUT2          I0       In      -         1.388       -         
triger_level_cnt_RNI52BK[3]                   LUT2          F        Out     1.032     2.420       -         
g0_0_1_0                                      Net           -        -       1.021     -           2         
internal_reg_force_triger_syn_RNIDFVF2[1]     MUX2_LUT5     S0       In      -         3.441       -         
internal_reg_force_triger_syn_RNIDFVF2[1]     MUX2_LUT5     O        Out     0.472     3.913       -         
g0_20_sx                                      Net           -        -       1.021     -           1         
u_ao_mem_ctrl_capture_loop_RNIGDJS4           LUT4          I3       In      -         4.934       -         
u_ao_mem_ctrl_capture_loop_RNIGDJS4           LUT4          F        Out     0.626     5.560       -         
triger_level_cnt_0_sqmuxa                     Net           -        -       1.082     -           16        
u_ao_mem_ctrl.capture_mem_wr_RNO_1            LUT3          I2       In      -         6.642       -         
u_ao_mem_ctrl.capture_mem_wr_RNO_1            LUT3          F        Out     0.822     7.464       -         
g0_1_0                                        Net           -        -       0.766     -           1         
u_ao_mem_ctrl.capture_mem_wr_RNO              LUT4          I1       In      -         8.230       -         
u_ao_mem_ctrl.capture_mem_wr_RNO              LUT4          F        Out     1.099     9.329       -         
capture_mem_wr_RNO                            Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr                  DFFCE         CE       In      -         9.329       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.462 is 4.551(48.1%) logic and 4.911(51.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      8.879
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.913

    Number of logic level(s):                6
    Starting point:                          u_ao_mem_ctrl.capture_length_fast[0] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_length_fast[0]                   DFFC          Q        Out     0.367     0.367       -         
capture_length_fast[0]                                 Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_0_0              ALU           I0       In      -         1.388       -         
u_ao_mem_ctrl.capture_length_zero_cry_0_0              ALU           COUT     Out     0.958     2.346       -         
capture_length_zero_cry_0                              Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_1_0              ALU           CIN      In      -         2.346       -         
u_ao_mem_ctrl.capture_length_zero_cry_1_0              ALU           SUM      Out     0.563     2.909       -         
capture_length_zero[1]                                 Net           -        -       1.021     -           2         
u_ao_mem_ctrl.capture_length_zero_cry_1_0_RNI09JN1     LUT4          I1       In      -         3.930       -         
u_ao_mem_ctrl.capture_length_zero_cry_1_0_RNI09JN1     LUT4          F        Out     1.099     5.029       -         
capture_length_zero_cry_1_0_RNI09JN1                   Net           -        -       1.021     -           2         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_3                    LUT4          I3       In      -         6.050       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_3                    LUT4          F        Out     0.626     6.676       -         
g0_0_1_0                                               Net           -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0                    MUX2_LUT5     I0       In      -         6.676       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0                    MUX2_LUT5     O        Out     0.150     6.826       -         
g0_0_1                                                 Net           -        -       1.021     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO                      LUT4          I0       In      -         7.847       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO                      LUT4          F        Out     1.032     8.879       -         
mem_addr_inc_en_RNO                                    Net           -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                          DFFCE         CE       In      -         8.879       -         
======================================================================================================================
Total path delay (propagation time + setup) of 9.012 is 4.928(54.7%) logic and 4.084(45.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      8.879
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.913

    Number of logic level(s):                6
    Starting point:                          u_ao_mem_ctrl.capture_length_fast[0] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_length_fast[0]                   DFFC          Q        Out     0.367     0.367       -         
capture_length_fast[0]                                 Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_0_0              ALU           I0       In      -         1.388       -         
u_ao_mem_ctrl.capture_length_zero_cry_0_0              ALU           COUT     Out     0.958     2.346       -         
capture_length_zero_cry_0                              Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_1_0              ALU           CIN      In      -         2.346       -         
u_ao_mem_ctrl.capture_length_zero_cry_1_0              ALU           SUM      Out     0.563     2.909       -         
capture_length_zero[1]                                 Net           -        -       1.021     -           2         
u_ao_mem_ctrl.capture_length_zero_cry_1_0_RNI09JN1     LUT4          I1       In      -         3.930       -         
u_ao_mem_ctrl.capture_length_zero_cry_1_0_RNI09JN1     LUT4          F        Out     1.099     5.029       -         
capture_length_zero_cry_1_0_RNI09JN1                   Net           -        -       1.021     -           2         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_4                    LUT4          I3       In      -         6.050       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_4                    LUT4          F        Out     0.626     6.676       -         
g0_0_1_1                                               Net           -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0                    MUX2_LUT5     I1       In      -         6.676       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0                    MUX2_LUT5     O        Out     0.150     6.826       -         
g0_0_1                                                 Net           -        -       1.021     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO                      LUT4          I0       In      -         7.847       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO                      LUT4          F        Out     1.032     8.879       -         
mem_addr_inc_en_RNO                                    Net           -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                          DFFCE         CE       In      -         8.879       -         
======================================================================================================================
Total path delay (propagation time + setup) of 9.012 is 4.928(54.7%) logic and 4.084(45.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      8.803
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.837

    Number of logic level(s):                9
    Starting point:                          u_ao_mem_ctrl.capture_length_fast[0] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_length_fast[0]          DFFC          Q        Out     0.367     0.367       -         
capture_length_fast[0]                        Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_0_0     ALU           I0       In      -         1.388       -         
u_ao_mem_ctrl.capture_length_zero_cry_0_0     ALU           COUT     Out     0.958     2.346       -         
capture_length_zero_cry_0                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_1_0     ALU           CIN      In      -         2.346       -         
u_ao_mem_ctrl.capture_length_zero_cry_1_0     ALU           COUT     Out     0.057     2.403       -         
capture_length_zero_cry_1                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_2_0     ALU           CIN      In      -         2.403       -         
u_ao_mem_ctrl.capture_length_zero_cry_2_0     ALU           COUT     Out     0.057     2.460       -         
capture_length_zero_cry_2                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_3_0     ALU           CIN      In      -         2.460       -         
u_ao_mem_ctrl.capture_length_zero_cry_3_0     ALU           COUT     Out     0.057     2.517       -         
capture_length_zero_cry_3                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_4_0     ALU           CIN      In      -         2.517       -         
u_ao_mem_ctrl.capture_length_zero_cry_4_0     ALU           COUT     Out     0.057     2.574       -         
capture_length_zero_cry_4                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.capture_length_zero_cry_5_0     ALU           CIN      In      -         2.574       -         
u_ao_mem_ctrl.capture_length_zero_cry_5_0     ALU           SUM      Out     0.563     3.137       -         
capture_length_zero[5]                        Net           -        -       1.021     -           2         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_5           LUT4          I1       In      -         4.158       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_5           LUT4          F        Out     1.099     5.257       -         
mem_addr_inc_en_RNO_5                         Net           -        -       1.021     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0           MUX2_LUT5     S0       In      -         6.278       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO_0           MUX2_LUT5     O        Out     0.472     6.750       -         
g0_0_1                                        Net           -        -       1.021     -           1         
u_ao_mem_ctrl.mem_addr_inc_en_RNO             LUT4          I0       In      -         7.771       -         
u_ao_mem_ctrl.mem_addr_inc_en_RNO             LUT4          F        Out     1.032     8.803       -         
mem_addr_inc_en_RNO                           Net           -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                 DFFCE         CE       In      -         8.803       -         
=============================================================================================================
Total path delay (propagation time + setup) of 8.936 is 4.852(54.3%) logic and 4.084(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                      Starting                                                        Arrival           
Instance              Reference               Type      Pin     Net                   Time        Slack 
                      Clock                                                                             
--------------------------------------------------------------------------------------------------------
bit_count[2]          ao_top_0|control[0]     DFFCE     Q       bit_count[2]          0.367       -1.645
bit_count[0]          ao_top_0|control[0]     DFFCE     Q       bit_count[0]          0.367       -1.578
data_register[40]     ao_top_0|control[0]     DFFCE     Q       data_register[40]     0.367       -1.496
bit_count[1]          ao_top_0|control[0]     DFFCE     Q       bit_count[1]          0.367       -1.451
data_register[43]     ao_top_0|control[0]     DFFCE     Q       data_register[43]     0.367       -1.435
word_count[13]        ao_top_0|control[0]     DFFCE     Q       word_count[13]        0.367       -1.427
bit_count[3]          ao_top_0|control[0]     DFFCE     Q       bit_count[3]          0.367       -1.384
data_register[41]     ao_top_0|control[0]     DFFCE     Q       data_register[41]     0.367       -1.368
bit_count[4]          ao_top_0|control[0]     DFFCE     Q       bit_count[4]          0.367       -1.368
word_count[1]         ao_top_0|control[0]     DFFCE     Q       word_count[1]         0.367       -1.360
========================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                                 Required           
Instance               Reference               Type      Pin     Net            Time         Slack 
                       Clock                                                                       
---------------------------------------------------------------------------------------------------
address_counter[0]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[1]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[2]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[3]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[4]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[5]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[6]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[7]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[8]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
address_counter[9]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en     9.188        -1.645
===================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      9.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.188

    - Propagation time:                      10.833
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.645

    Number of logic level(s):                5
    Starting point:                          bit_count[2] / Q
    Ending point:                            address_counter[0] / CE
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                        Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
bit_count[2]                DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                Net       -        -       1.021     -           4         
addr_ct_en_a1_9_N_2L1_1     LUT3      I1       In      -         1.388       -         
addr_ct_en_a1_9_N_2L1_1     LUT3      F        Out     1.099     2.487       -         
addr_ct_en_a1_9_N_2L1_1     Net       -        -       0.766     -           1         
addr_ct_en_a1_9_N_2L1       LUT4      I0       In      -         3.253       -         
addr_ct_en_a1_9_N_2L1       LUT4      F        Out     1.032     4.285       -         
addr_ct_en_a1_9_N_2L1       Net       -        -       0.766     -           1         
addr_ct_en_a1_15_N_4L6      LUT4      I0       In      -         5.050       -         
addr_ct_en_a1_15_N_4L6      LUT4      F        Out     1.032     6.082       -         
addr_ct_en_a1_15_N_4L6      Net       -        -       0.766     -           1         
addr_ct_en_a1_15            LUT4      I1       In      -         6.848       -         
addr_ct_en_a1_15            LUT4      F        Out     1.099     7.947       -         
addr_ct_en_1_1_0            Net       -        -       0.766     -           1         
addr_ct_en_1                LUT4      I1       In      -         8.713       -         
addr_ct_en_1                LUT4      F        Out     1.099     9.812       -         
addr_ct_en                  Net       -        -       1.021     -           10        
address_counter[0]          DFFCE     CE       In      -         10.833      -         
=======================================================================================
Total path delay (propagation time + setup) of 10.966 is 5.861(53.4%) logic and 5.105(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      9.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.188

    - Propagation time:                      10.833
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.645

    Number of logic level(s):                5
    Starting point:                          bit_count[2] / Q
    Ending point:                            address_counter[1] / CE
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                        Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
bit_count[2]                DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                Net       -        -       1.021     -           4         
addr_ct_en_a1_9_N_2L1_1     LUT3      I1       In      -         1.388       -         
addr_ct_en_a1_9_N_2L1_1     LUT3      F        Out     1.099     2.487       -         
addr_ct_en_a1_9_N_2L1_1     Net       -        -       0.766     -           1         
addr_ct_en_a1_9_N_2L1       LUT4      I0       In      -         3.253       -         
addr_ct_en_a1_9_N_2L1       LUT4      F        Out     1.032     4.285       -         
addr_ct_en_a1_9_N_2L1       Net       -        -       0.766     -           1         
addr_ct_en_a1_15_N_4L6      LUT4      I0       In      -         5.050       -         
addr_ct_en_a1_15_N_4L6      LUT4      F        Out     1.032     6.082       -         
addr_ct_en_a1_15_N_4L6      Net       -        -       0.766     -           1         
addr_ct_en_a1_15            LUT4      I1       In      -         6.848       -         
addr_ct_en_a1_15            LUT4      F        Out     1.099     7.947       -         
addr_ct_en_1_1_0            Net       -        -       0.766     -           1         
addr_ct_en_1                LUT4      I1       In      -         8.713       -         
addr_ct_en_1                LUT4      F        Out     1.099     9.812       -         
addr_ct_en                  Net       -        -       1.021     -           10        
address_counter[1]          DFFCE     CE       In      -         10.833      -         
=======================================================================================
Total path delay (propagation time + setup) of 10.966 is 5.861(53.4%) logic and 5.105(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      9.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.188

    - Propagation time:                      10.833
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.645

    Number of logic level(s):                5
    Starting point:                          bit_count[2] / Q
    Ending point:                            address_counter[2] / CE
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                        Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
bit_count[2]                DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                Net       -        -       1.021     -           4         
addr_ct_en_a1_9_N_2L1_1     LUT3      I1       In      -         1.388       -         
addr_ct_en_a1_9_N_2L1_1     LUT3      F        Out     1.099     2.487       -         
addr_ct_en_a1_9_N_2L1_1     Net       -        -       0.766     -           1         
addr_ct_en_a1_9_N_2L1       LUT4      I0       In      -         3.253       -         
addr_ct_en_a1_9_N_2L1       LUT4      F        Out     1.032     4.285       -         
addr_ct_en_a1_9_N_2L1       Net       -        -       0.766     -           1         
addr_ct_en_a1_15_N_4L6      LUT4      I0       In      -         5.050       -         
addr_ct_en_a1_15_N_4L6      LUT4      F        Out     1.032     6.082       -         
addr_ct_en_a1_15_N_4L6      Net       -        -       0.766     -           1         
addr_ct_en_a1_15            LUT4      I1       In      -         6.848       -         
addr_ct_en_a1_15            LUT4      F        Out     1.099     7.947       -         
addr_ct_en_1_1_0            Net       -        -       0.766     -           1         
addr_ct_en_1                LUT4      I1       In      -         8.713       -         
addr_ct_en_1                LUT4      F        Out     1.099     9.812       -         
addr_ct_en                  Net       -        -       1.021     -           10        
address_counter[2]          DFFCE     CE       In      -         10.833      -         
=======================================================================================
Total path delay (propagation time + setup) of 10.966 is 5.861(53.4%) logic and 5.105(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      9.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.188

    - Propagation time:                      10.833
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.645

    Number of logic level(s):                5
    Starting point:                          bit_count[2] / Q
    Ending point:                            address_counter[3] / CE
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                        Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
bit_count[2]                DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                Net       -        -       1.021     -           4         
addr_ct_en_a1_9_N_2L1_1     LUT3      I1       In      -         1.388       -         
addr_ct_en_a1_9_N_2L1_1     LUT3      F        Out     1.099     2.487       -         
addr_ct_en_a1_9_N_2L1_1     Net       -        -       0.766     -           1         
addr_ct_en_a1_9_N_2L1       LUT4      I0       In      -         3.253       -         
addr_ct_en_a1_9_N_2L1       LUT4      F        Out     1.032     4.285       -         
addr_ct_en_a1_9_N_2L1       Net       -        -       0.766     -           1         
addr_ct_en_a1_15_N_4L6      LUT4      I0       In      -         5.050       -         
addr_ct_en_a1_15_N_4L6      LUT4      F        Out     1.032     6.082       -         
addr_ct_en_a1_15_N_4L6      Net       -        -       0.766     -           1         
addr_ct_en_a1_15            LUT4      I1       In      -         6.848       -         
addr_ct_en_a1_15            LUT4      F        Out     1.099     7.947       -         
addr_ct_en_1_1_0            Net       -        -       0.766     -           1         
addr_ct_en_1                LUT4      I1       In      -         8.713       -         
addr_ct_en_1                LUT4      F        Out     1.099     9.812       -         
addr_ct_en                  Net       -        -       1.021     -           10        
address_counter[3]          DFFCE     CE       In      -         10.833      -         
=======================================================================================
Total path delay (propagation time + setup) of 10.966 is 5.861(53.4%) logic and 5.105(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      9.321
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.188

    - Propagation time:                      10.833
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.645

    Number of logic level(s):                5
    Starting point:                          bit_count[2] / Q
    Ending point:                            address_counter[4] / CE
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                        Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
bit_count[2]                DFFCE     Q        Out     0.367     0.367       -         
bit_count[2]                Net       -        -       1.021     -           4         
addr_ct_en_a1_9_N_2L1_1     LUT3      I1       In      -         1.388       -         
addr_ct_en_a1_9_N_2L1_1     LUT3      F        Out     1.099     2.487       -         
addr_ct_en_a1_9_N_2L1_1     Net       -        -       0.766     -           1         
addr_ct_en_a1_9_N_2L1       LUT4      I0       In      -         3.253       -         
addr_ct_en_a1_9_N_2L1       LUT4      F        Out     1.032     4.285       -         
addr_ct_en_a1_9_N_2L1       Net       -        -       0.766     -           1         
addr_ct_en_a1_15_N_4L6      LUT4      I0       In      -         5.050       -         
addr_ct_en_a1_15_N_4L6      LUT4      F        Out     1.032     6.082       -         
addr_ct_en_a1_15_N_4L6      Net       -        -       0.766     -           1         
addr_ct_en_a1_15            LUT4      I1       In      -         6.848       -         
addr_ct_en_a1_15            LUT4      F        Out     1.099     7.947       -         
addr_ct_en_1_1_0            Net       -        -       0.766     -           1         
addr_ct_en_1                LUT4      I1       In      -         8.713       -         
addr_ct_en_1                LUT4      F        Out     1.099     9.812       -         
addr_ct_en                  Net       -        -       1.021     -           10        
address_counter[4]          DFFCE     CE       In      -         10.833      -         
=======================================================================================
Total path delay (propagation time + setup) of 10.966 is 5.861(53.4%) logic and 5.105(46.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       3.861
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       6.070
=============================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                         Required          
Instance                       Reference     Type      Pin     Net                              Time         Slack
                               Clock                                                                              
------------------------------------------------------------------------------------------------------------------
capture_window_sel[1]          System        DFFC      D       capture_window_sel_3[1]          7.966        3.861
capture_window_sel_fast[1]     System        DFFC      D       capture_window_sel_3_fast[1]     7.966        3.861
capture_window_sel[2]          System        DFFC      D       capture_window_sel_3[2]          7.966        4.070
capture_window_sel[3]          System        DFFC      D       capture_window_sel_3[3]          7.966        4.070
capture_window_sel[0]          System        DFFC      D       capture_window_sel_3[0]          7.966        5.913
capture_window_sel_fast[0]     System        DFFC      D       capture_window_sel_3_fast[0]     7.966        5.913
internal_reg_start_dly[0]      System        DFFC      D       internal_reg_start_dly_2[0]      7.966        5.913
address_counter[9]             System        DFFCE     D       address_counter_s[9]             9.188        6.070
address_counter[8]             System        DFFCE     D       address_counter_s[8]             9.188        6.127
address_counter[7]             System        DFFCE     D       address_counter_s[7]             9.188        6.184
==================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.099
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.966

    - Propagation time:                      4.106
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.861

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[1] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       1.021     -           7         
un1_capture_window_sel_axbxc1            LUT4     I0       In      -         1.021       -         
un1_capture_window_sel_axbxc1            LUT4     F        Out     1.032     2.053       -         
un1_capture_window_sel_axbxc1            Net      -        -       1.021     -           2         
capture_window_sel_3[1]                  LUT2     I0       In      -         3.074       -         
capture_window_sel_3[1]                  LUT2     F        Out     1.032     4.106       -         
capture_window_sel_3[1]                  Net      -        -       0.000     -           1         
capture_window_sel[1]                    DFFC     D        In      -         4.106       -         
===================================================================================================
Total path delay (propagation time + setup) of 4.239 is 2.197(51.8%) logic and 2.042(48.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 212MB peak: 215MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 212MB peak: 215MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw1n_9eslqfp144-6
Cell usage:
ALU             69 uses
DFF             23 uses
DFFC            53 uses
DFFCE           203 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       2 uses
SDPX9           2 uses
LUT2            59 uses
LUT3            99 uses
LUT4            249 uses

I/O ports: 35
I/O primitives: 35
IBUF           33 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   318 of 6480 (4%)

RAM/ROM usage summary
Block Rams : 2 of 24 (8%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 252

@S |Mapping Summary:
Total  LUTs: 407 (4%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 45MB peak: 215MB)

Process took 0h:00m:07s realtime, 0h:00m:06s cputime
# Thu Sep 27 09:30:02 2018

###########################################################]