Project Settings |
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Project Name | master | Device Name | rev_1: GOWIN-GW1N : GW1N_9ES |
Implementation Name | rev_1 | Top Module | topM |
Pipelining | 1 | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
Clock Conversion | 1 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
37 |
99 |
0 |
- |
00m:02s |
- |
2018/9/27 9:29:28 |
(premap) | Complete |
29 |
2 |
0 |
0m:02s |
0m:02s |
198MB |
2018/9/27 9:29:32 |
(fpga_mapper) | Complete |
35 |
3 |
0 |
0m:07s |
0m:07s |
208MB |
2018/9/27 9:29:41 |
Multi-srs Generator |
Complete | | | | | | | 2018/9/27 9:29:29 |
Area Summary |
|
I/O ports
(io_port) | 106 |
Non I/O Register bits
(non_io_reg) | 418 (6%) |
I/O Register bits
(total_io_reg) | 0 |
Block Rams
(v_ram) | 2 (24) |
Block Multipliers
(dsp_used) | 0 (10) |
LUTs
(total_luts) | 1277 (14%) |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
GW_PLL|clkout_inferred_clock | 38.9 MHz | 33.1 MHz | -4.535 |
SclkGen|scl_i_i_1z_inferred_clock | 42.8 MHz | 120.3 MHz | 15.032 |
System | 39.5 MHz | 33.5 MHz | -4.471 |
Optimizations Summary |
Combined Clock Conversion | 0 / 7 |
| |
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