Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW1N : GW1N_9ES
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:01s - 2018/9/27
9:29:50
(premap)Complete 14 0 0 0m:01s 0m:02s 193MB 2018/9/27
9:29:54
(fpga_mapper)Complete 11 2 0 0m:06s 0m:07s 215MB 2018/9/27
9:30:02
Multi-srs Generator Complete00m:01s2018/9/27
9:29:52

Area Summary
I/O ports (io_port) 35 Non I/O Register bits (non_io_reg) 318 (4%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 2 (24)
Block Multipliers (dsp_used) 0 (10) LUTs (total_luts) 407 (4%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i123.5 MHz104.9 MHz-1.429
ao_top_0|control[0]107.3 MHz91.2 MHz-1.645
System100.0 MHz162.9 MHz3.861

Optimizations Summary
Combined Clock Conversion 2 / 0