Project Settings
Project Name slave Device Name rev_1: GOWIN-GW1N : GW1N_9ES
Implementation Name rev_1 Top Module topS
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 36 114 0 - 00m:02s - 2018/9/27
9:29:22
(premap)Complete 32 2 0 0m:02s 0m:02s 198MB 2018/9/27
9:29:26
(fpga_mapper)Complete 35 3 0 0m:07s 0m:07s 205MB 2018/9/27
9:29:34
Multi-srs Generator Complete2018/9/27
9:29:23

Area Summary
I/O ports (io_port) 106 Non I/O Register bits (non_io_reg) 411 (6%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 2 (24)
Block Multipliers (dsp_used) 0 (10) LUTs (total_luts) 1259 (14%)

Timing Summary
Clock NameReq FreqEst FreqSlack
GW_PLL|clkout_inferred_clock38.9 MHz33.1 MHz-4.535
SclkGen|scl_i_i_1z_inferred_clock42.8 MHz120.3 MHz15.032
System39.5 MHz33.5 MHz-4.471

Optimizations Summary
Combined Clock Conversion 0 / 7