Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW1N : GW1N_9ES
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:01s - 2018/9/26
18:17:50
(premap)Complete 14 0 0 0m:01s 0m:01s 193MB 2018/9/26
18:17:54
(fpga_mapper)Complete 11 2 0 0m:06s 0m:06s 218MB 2018/9/26
18:18:01
Multi-srs Generator Complete00m:01s2018/9/26
18:17:52

Area Summary
I/O ports (io_port) 38 Non I/O Register bits (non_io_reg) 328 (5%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 2 (24)
Block Multipliers (dsp_used) 0 (10) LUTs (total_luts) 422 (4%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i122.8 MHz104.4 MHz-1.437
ao_top_0|control[0]100.0 MHz86.7 MHz-1.532
System100.0 MHz169.8 MHz4.112

Optimizations Summary
Combined Clock Conversion 2 / 0