Project Settings |
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Project Name | I3C_HDR | Device Name | rev_1: GOWIN-GW1N : GW1N_9ES |
Implementation Name | rev_1 | Top Module | [auto] |
Pipelining | 1 | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 1 | Disable Sequential Optimizations | 0 |
Clock Conversion | 1 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
8 |
0 |
0 |
- |
00m:04s |
- |
2018/9/27 9:28:08 |
(premap) | Complete |
14 |
0 |
0 |
0m:01s |
0m:02s |
195MB |
2018/9/27 9:28:12 |
(fpga_mapper) | Complete |
11 |
3 |
0 |
0m:39s |
0m:39s |
311MB |
2018/9/27 9:28:52 |
Multi-srs Generator |
Complete | | | | | | | 2018/9/27 9:28:09 |
Area Summary |
|
Non I/O Register bits
(non_io_reg) | 343 (5%) |
I/O Register bits
(total_io_reg) | 0 |
Block Rams
(v_ram) | 2 (24) |
Block Multipliers
(dsp_used) | 0 (10) |
LUTs
(total_luts) | 1271 (14%) |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
I3C_HDR|scl_i | 39.5 MHz | 18.4 MHz | -14.458 |
I3C_HDR|sda_i | 114.8 MHz | 75.1 MHz | -2.305 |
I3C_HDR|sysClk_i | 38.9 MHz | 33.1 MHz | -4.535 |
System | 39.3 MHz | 33.4 MHz | -4.490 |
Optimizations Summary |
Combined Clock Conversion | 3 / 3 |
| |
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