#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-032

# Thu Sep 27 09:29:20 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\gw_pll\gw_pll.v" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv" (library work)
@W:CG921 : slave.sv(215) | pcInc is already declared in this scope.
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\dejitter.sv" (library work)
@I::"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\i3c_hdr\i3c_hdr.v" (library work)
Verilog syntax check successful!
Selecting top level module topS
@N:CG364 : dejitter.sv(1) | Synthesizing module deJitter in library work.

	alwaysState=32'b00000000000000000000000000000001
	keyInINI=32'b00000000000000000000000000001111
	keyValueINI=32'b00000000000000000000000000000011
   Generated name = deJitter_1s_15_3
Running optimization stage 1 on deJitter_1s_15_3 .......
@N:CG364 : gw1n.v(1547) | Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on DFFNCE .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on DP .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on Cache .......
Running optimization stage 1 on Cache_0 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on MUX2_LUT7 .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on SclkGen .......
Running optimization stage 1 on DFFNPE .......
Running optimization stage 1 on DFFNP .......
Running optimization stage 1 on DFFNC .......
Running optimization stage 1 on Core .......
Running optimization stage 1 on encoder83_2_2_0 .......
Running optimization stage 1 on encoder164_1 .......
Running optimization stage 1 on encoder83_2_2_1 .......
Running optimization stage 1 on encoder83_2_2_2 .......
Running optimization stage 1 on encoder164_1_0 .......
Running optimization stage 1 on encoder325_1 .......
Running optimization stage 1 on encoder83_0_1 .......
Running optimization stage 1 on encoder164_1_2 .......
Running optimization stage 1 on encoder83_2_2_3 .......
Running optimization stage 1 on encoder83_0_2 .......
Running optimization stage 1 on encoder164_1_1 .......
Running optimization stage 1 on encoder325_0 .......
Running optimization stage 1 on I3cPhy .......
@N:CG364 : i3c_hdr.v(20227) | Synthesizing module I3C_HDR in library work.
Running optimization stage 1 on I3C_HDR .......
@N:CG364 : gw1n.v(1483) | Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N:CG364 : gw_pll.v(13) | Synthesizing module GW_PLL in library work.
Running optimization stage 1 on GW_PLL .......
@N:CG364 : slave.sv(1) | Synthesizing module topS in library work.
@N:CG179 : slave.sv(228) | Removing redundant assignment.
@N:CG179 : slave.sv(233) | Removing redundant assignment.
@N:CG179 : slave.sv(281) | Removing redundant assignment.
@N:CG179 : slave.sv(297) | Removing redundant assignment.
@W:CG360 : slave.sv(16) | Removing wire led_4, as there is no assignment to it.
@W:CG360 : slave.sv(17) | Removing wire led_5, as there is no assignment to it.
@W:CG360 : slave.sv(18) | Removing wire led_6, as there is no assignment to it.
@W:CG360 : slave.sv(22) | Removing wire j8_5, as there is no assignment to it.
@W:CG360 : slave.sv(23) | Removing wire j8_6, as there is no assignment to it.
@W:CG360 : slave.sv(24) | Removing wire j8_7, as there is no assignment to it.
@W:CG360 : slave.sv(25) | Removing wire j8_8, as there is no assignment to it.
@W:CG360 : slave.sv(38) | Removing wire j8_21, as there is no assignment to it.
@W:CG360 : slave.sv(39) | Removing wire j8_22, as there is no assignment to it.
@W:CG360 : slave.sv(40) | Removing wire j8_23, as there is no assignment to it.
@W:CG360 : slave.sv(41) | Removing wire j8_24, as there is no assignment to it.
@W:CG360 : slave.sv(42) | Removing wire j8_25, as there is no assignment to it.
@W:CG360 : slave.sv(43) | Removing wire j8_26, as there is no assignment to it.
@W:CG360 : slave.sv(44) | Removing wire j8_27, as there is no assignment to it.
@W:CG360 : slave.sv(45) | Removing wire j8_28, as there is no assignment to it.
@W:CG360 : slave.sv(46) | Removing wire j8_29, as there is no assignment to it.
@W:CG360 : slave.sv(47) | Removing wire j8_30, as there is no assignment to it.
@W:CG360 : slave.sv(48) | Removing wire j8_31, as there is no assignment to it.
@W:CG360 : slave.sv(49) | Removing wire j8_32, as there is no assignment to it.
@W:CG360 : slave.sv(50) | Removing wire j8_33, as there is no assignment to it.
@W:CG360 : slave.sv(51) | Removing wire j8_34, as there is no assignment to it.
@W:CG360 : slave.sv(52) | Removing wire j8_35, as there is no assignment to it.
@W:CG360 : slave.sv(53) | Removing wire j8_36, as there is no assignment to it.
@W:CG360 : slave.sv(54) | Removing wire j8_37, as there is no assignment to it.
@W:CG360 : slave.sv(55) | Removing wire j8_38, as there is no assignment to it.
@W:CG360 : slave.sv(60) | Removing wire j9_6, as there is no assignment to it.
@W:CG360 : slave.sv(61) | Removing wire j9_7, as there is no assignment to it.
@W:CG360 : slave.sv(62) | Removing wire j9_8, as there is no assignment to it.
@W:CG360 : slave.sv(63) | Removing wire j9_9, as there is no assignment to it.
@W:CG360 : slave.sv(72) | Removing wire j9_18, as there is no assignment to it.
@W:CG360 : slave.sv(73) | Removing wire j9_19, as there is no assignment to it.
@W:CG360 : slave.sv(74) | Removing wire j9_20, as there is no assignment to it.
@W:CG360 : slave.sv(75) | Removing wire j9_21, as there is no assignment to it.
@W:CG360 : slave.sv(76) | Removing wire j9_22, as there is no assignment to it.
@W:CG360 : slave.sv(77) | Removing wire j9_23, as there is no assignment to it.
@W:CG360 : slave.sv(78) | Removing wire j9_24, as there is no assignment to it.
@W:CG360 : slave.sv(79) | Removing wire j9_25, as there is no assignment to it.
@W:CG360 : slave.sv(80) | Removing wire j9_26, as there is no assignment to it.
@W:CG360 : slave.sv(81) | Removing wire j9_27, as there is no assignment to it.
@W:CG360 : slave.sv(82) | Removing wire j9_28, as there is no assignment to it.
@W:CG360 : slave.sv(83) | Removing wire j9_29, as there is no assignment to it.
@W:CG360 : slave.sv(84) | Removing wire j9_30, as there is no assignment to it.
@W:CG360 : slave.sv(85) | Removing wire j9_31, as there is no assignment to it.
@W:CG360 : slave.sv(86) | Removing wire j9_32, as there is no assignment to it.
@W:CG360 : slave.sv(87) | Removing wire j9_33, as there is no assignment to it.
@W:CG360 : slave.sv(88) | Removing wire j9_34, as there is no assignment to it.
@W:CG360 : slave.sv(89) | Removing wire j9_35, as there is no assignment to it.
@W:CG360 : slave.sv(90) | Removing wire j9_36, as there is no assignment to it.
@W:CG360 : slave.sv(91) | Removing wire j9_37, as there is no assignment to it.
@W:CG360 : slave.sv(92) | Removing wire j9_38, as there is no assignment to it.
@W:CG360 : slave.sv(97) | Removing wire j10_6, as there is no assignment to it.
@W:CG360 : slave.sv(98) | Removing wire j10_9, as there is no assignment to it.
@W:CG360 : slave.sv(99) | Removing wire j10_10, as there is no assignment to it.
@W:CG360 : slave.sv(181) | Removing wire key3, as there is no assignment to it.
@W:CG360 : slave.sv(181) | Removing wire key4, as there is no assignment to it.
Running optimization stage 1 on topS .......
@W:CL318 : slave.sv(16) | *Output led_4 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(17) | *Output led_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(18) | *Output led_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(22) | *Output j8_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(23) | *Output j8_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(24) | *Output j8_7 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(25) | *Output j8_8 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(38) | *Output j8_21 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(39) | *Output j8_22 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(40) | *Output j8_23 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(41) | *Output j8_24 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(42) | *Output j8_25 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(43) | *Output j8_26 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(44) | *Output j8_27 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(45) | *Output j8_28 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(46) | *Output j8_29 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(47) | *Output j8_30 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(48) | *Output j8_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(49) | *Output j8_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(50) | *Output j8_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(51) | *Output j8_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(52) | *Output j8_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(53) | *Output j8_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(54) | *Output j8_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(55) | *Output j8_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(60) | *Output j9_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(61) | *Output j9_7 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(62) | *Output j9_8 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(63) | *Output j9_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(72) | *Output j9_18 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(73) | *Output j9_19 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(74) | *Output j9_20 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(75) | *Output j9_21 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(76) | *Output j9_22 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(77) | *Output j9_23 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(78) | *Output j9_24 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(79) | *Output j9_25 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(80) | *Output j9_26 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(81) | *Output j9_27 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(82) | *Output j9_28 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(83) | *Output j9_29 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(84) | *Output j9_30 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(85) | *Output j9_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(86) | *Output j9_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(87) | *Output j9_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(88) | *Output j9_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(89) | *Output j9_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(90) | *Output j9_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(91) | *Output j9_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(92) | *Output j9_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(97) | *Output j10_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(98) | *Output j10_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : slave.sv(99) | *Output j10_10 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL169 : slave.sv(244) | Pruning unused register ptr_SL[10:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : slave.sv(244) | Pruning unused register data_tmp[7:0]. Make sure that there are no unused intermediate registers.
Running optimization stage 2 on topS .......
@W:CL190 : slave.sv(244) | Optimizing register bit addr[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : slave.sv(244) | Optimizing register bit addr[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : slave.sv(244) | Pruning register bits 9 to 8 of addr[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL159 : slave.sv(2) | Input clk_ext is unused.
@N:CL159 : slave.sv(7) | Input key_3 is unused.
@N:CL159 : slave.sv(8) | Input key_4 is unused.
@N:CL159 : slave.sv(10) | Input sw_4 is unused.
@N:CL159 : slave.sv(11) | Input sw_5 is unused.
@N:CL159 : slave.sv(12) | Input sw_6 is unused.
@N:CL159 : slave.sv(13) | Input sw_7 is unused.
@N:CL159 : slave.sv(100) | Input j10_13 is unused.
@N:CL159 : slave.sv(101) | Input j10_14 is unused.
@N:CL159 : slave.sv(102) | Input j10_17 is unused.
@N:CL159 : slave.sv(103) | Input j10_18 is unused.
@N:CL159 : slave.sv(105) | Input j11_1 is unused.
@N:CL159 : slave.sv(106) | Input j11_2 is unused.
@N:CL159 : slave.sv(107) | Input j11_5 is unused.
@N:CL159 : slave.sv(108) | Input j11_6 is unused.
@N:CL159 : slave.sv(109) | Input j11_9 is unused.
@N:CL159 : slave.sv(110) | Input j11_10 is unused.
@N:CL159 : slave.sv(111) | Input j11_13 is unused.
@N:CL159 : slave.sv(112) | Input j11_14 is unused.
@N:CL159 : slave.sv(113) | Input j11_17 is unused.
@N:CL159 : slave.sv(114) | Input j11_18 is unused.
Running optimization stage 2 on GW_PLL .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on I3C_HDR .......
Running optimization stage 2 on I3cPhy .......
Running optimization stage 2 on encoder325_0 .......
Running optimization stage 2 on encoder164_1_1 .......
Running optimization stage 2 on encoder83_0_2 .......
Running optimization stage 2 on encoder83_2_2_3 .......
Running optimization stage 2 on encoder164_1_2 .......
Running optimization stage 2 on encoder83_0_1 .......
Running optimization stage 2 on encoder325_1 .......
Running optimization stage 2 on encoder164_1_0 .......
Running optimization stage 2 on encoder83_2_2_2 .......
Running optimization stage 2 on encoder83_2_2_1 .......
Running optimization stage 2 on encoder164_1 .......
Running optimization stage 2 on encoder83_2_2_0 .......
Running optimization stage 2 on Core .......
Running optimization stage 2 on DFFNC .......
Running optimization stage 2 on DFFNP .......
Running optimization stage 2 on DFFNPE .......
Running optimization stage 2 on SclkGen .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on MUX2_LUT7 .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on Cache_0 .......
Running optimization stage 2 on Cache .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on DP .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFNCE .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on deJitter_1s_15_3 .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 84MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:21 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:22 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:22 2018

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Database state : E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\synthesize\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Sep 27 09:29:23 2018

###########################################################]


Premap Report



# Thu Sep 27 09:29:24 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\fdc.fdc
Adding property syn_netlist_hierarchy, value 0 to view:work.topS(verilog)
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  slave_scck.rpt
Printing clock  summary report in "E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\synthesize\rev_1\slave_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 121MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MO111 : slave.sv(22) | Tristate driver j8_5 (in view: work.topS(verilog)) on net j8_5 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(23) | Tristate driver j8_6 (in view: work.topS(verilog)) on net j8_6 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(24) | Tristate driver j8_7 (in view: work.topS(verilog)) on net j8_7 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(25) | Tristate driver j8_8 (in view: work.topS(verilog)) on net j8_8 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(38) | Tristate driver j8_21 (in view: work.topS(verilog)) on net j8_21 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(39) | Tristate driver j8_22 (in view: work.topS(verilog)) on net j8_22 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(40) | Tristate driver j8_23 (in view: work.topS(verilog)) on net j8_23 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(41) | Tristate driver j8_24 (in view: work.topS(verilog)) on net j8_24 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(42) | Tristate driver j8_25 (in view: work.topS(verilog)) on net j8_25 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(43) | Tristate driver j8_26 (in view: work.topS(verilog)) on net j8_26 (in view: work.topS(verilog)) has its enable tied to GND.
@N:BN362 : dejitter.sv(51) | Removing sequential instance keyPos_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(51) | Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(51) | Removing sequential instance keyPos_0 (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(51) | Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(47) | Removing sequential instance keyValue[1] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(47) | Removing sequential instance keyValue[1] (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(47) | Removing sequential instance keyValue[0] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N:BN362 : dejitter.sv(47) | Removing sequential instance keyValue[0] (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
Netlist hierarchy reconstruction disabled for view:work.topS(verilog)
Netlist hierarchy reconstruction disabled for view:work.topS(verilog)

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)

@N:MF974 :  | Total number of latches (multibit) processed = 0  
@N:MF975 :  | Total number of latches (bit blasted) processed = 0  
@N:MF976 :  | Total number of (multibit) opaque latches found = 0  
@N:MF977 :  | Total number of (bit blasted) opaque latches found = 0  

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)







Detailed report for transparent and observable latches in design:
Linked File:  slave_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)

syn_allowed_resources : blockrams=24  set on top level netlist topS

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB)



Clock Summary
******************

          Start                                 Requested     Requested     Clock        Clock                     Clock
Level     Clock                                 Frequency     Period        Type         Group                     Load 
------------------------------------------------------------------------------------------------------------------------
0 -       System                                100.0 MHz     10.000        system       system_clkgroup           242  
                                                                                                                        
0 -       GW_PLL|clkout_inferred_clock          130.6 MHz     7.657         inferred     Autoconstr_clkgroup_0     171  
                                                                                                                        
0 -       SclkGen|scl_i_i_1z_inferred_clock     100.0 MHz     10.000        inferred     Autoconstr_clkgroup_1     2    
========================================================================================================================



Clock Load Summary
***********************

                                      Clock     Source                               Clock Pin                              Non-clock Pin     Non-clock Pin       
Clock                                 Load      Pin                                  Seq Example                            Seq Example       Comb Example        
------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                242       -                                    iPhy.iPhy.\\msgByte_cnt_Z\[7\].CLK     -                 -                   
                                                                                                                                                                  
GW_PLL|clkout_inferred_clock          171       myPll.pll_inst.CLKOUT(PLL)           len[7].C                               -                 un1_clk10M.I[0](inv)
                                                                                                                                                                  
SclkGen|scl_i_i_1z_inferred_clock     2         iPhy.iPhy.iSclGen.scl_i_i.O(INV)     iPhy.iPhy.iCacheP.bram_dp_0.CLKB       -                 -                   
==================================================================================================================================================================

@W:MT529 : dejitter.sv(42) | Found inferred clock GW_PLL|clkout_inferred_clock which controls 171 sequential elements including deKey1.keyO_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
7 gated/generated clock tree(s) driving 415 clock pin(s) of sequential element(s)
0 instances converted, 415 sequential instances remain driven by gated/generated clocks

========================================================== Gated/Generated Clocks ===========================================================
Clock Tree ID     Driving Element           Drive Element Type     Unconverted Fanout     Sample Instance     Explanation                    
---------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_1       j10_5                     IO_port                229                    ENCRYPTED           Clock source is invalid for GCC
ClockId_0_3       myPll.pll_inst.CLKOUT     PLL                    171                    pcInc_0             Black box on clock path        
ClockId_0_4       j10_1                     IO_port                9                      ENCRYPTED           Clock source is invalid for GCC
ClockId_0_5       ENCRYPTED                 DFFCE                  1                      ENCRYPTED           Clock source is invalid for GCC
ClockId_0_6       ENCRYPTED                 DFFNCE                 2                      ENCRYPTED           Clock source is invalid for GCC
ClockId_0_7       ENCRYPTED                 DFFNCE                 1                      ENCRYPTED           Clock source is invalid for GCC
ClockId_0_8       ENCRYPTED                 INV                    2                      ENCRYPTED           Black box on clock path        
=============================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\synthesize\rev_1\slave.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 198MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 198MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 198MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 111MB peak: 198MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Sep 27 09:29:26 2018

###########################################################]


Map & Optimize Report



# Thu Sep 27 09:29:27 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 194MB peak: 195MB)

@N:MO111 : slave.sv(99) | Tristate driver j10_10 (in view: work.topS(verilog)) on net j10_10 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(98) | Tristate driver j10_9 (in view: work.topS(verilog)) on net j10_9 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(97) | Tristate driver j10_6 (in view: work.topS(verilog)) on net j10_6 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(92) | Tristate driver j9_38 (in view: work.topS(verilog)) on net j9_38 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(91) | Tristate driver j9_37 (in view: work.topS(verilog)) on net j9_37 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(90) | Tristate driver j9_36 (in view: work.topS(verilog)) on net j9_36 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(89) | Tristate driver j9_35 (in view: work.topS(verilog)) on net j9_35 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(88) | Tristate driver j9_34 (in view: work.topS(verilog)) on net j9_34 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(87) | Tristate driver j9_33 (in view: work.topS(verilog)) on net j9_33 (in view: work.topS(verilog)) has its enable tied to GND.
@N:MO111 : slave.sv(86) | Tristate driver j9_32 (in view: work.topS(verilog)) on net j9_32 (in view: work.topS(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "1" on instance deKey2.keyO. 
@N:FX493 :  | Applying initial value "111" on instance deKey2.keyIn_r[2:0]. 
@N:FX493 :  | Applying initial value "00000000" on instance deKey2.counter[7:0]. 
@N:FX493 :  | Applying initial value "1" on instance deKey2.keyO. 
@N:FX493 :  | Applying initial value "111" on instance deKey2.keyIn_r[2:0]. 
@N:FX493 :  | Applying initial value "00000000" on instance deKey2.counter[7:0]. 
@N:FX493 :  | Applying initial value "1" on instance pcInc. 
@N:FX493 :  | Applying initial value "00000000" on instance cnt[7:0]. 
@N:FX493 :  | Applying initial value "00000000" on instance addr[7:0]. 
@N:FX493 :  | Applying initial value "00" on instance addr[11:10]. 
@N:FX493 :  | Applying initial value "0" on instance wre. 
@N:FX493 :  | Applying initial value "00000000" on instance dataNum[7:0]. 
@N:FX493 :  | Applying initial value "00000000" on instance dataNI[7:0]. 
@N:FX493 :  | Applying initial value "00000000" on instance len[7:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 197MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 197MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 197MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 197MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 201MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		   -41.49ns		1327 /        68
   2		0h:00m:02s		   -41.49ns		1326 /        68

   3		0h:00m:02s		   -41.49ns		1326 /        68


   4		0h:00m:02s		   -41.49ns		1326 /        68

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 201MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 201MB)


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 125MB peak: 202MB)

Writing Analyst data base E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\synthesize\rev_1\synwork\slave_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 200MB peak: 205MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 200MB peak: 205MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 198MB peak: 205MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 197MB peak: 205MB)

@W:MT246 : gw_pll.v(26) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock GW_PLL|clkout_inferred_clock with period 25.70ns. Please declare a user-defined clock on net j8_4_c. 
@W:MT420 :  | Found inferred clock SclkGen|scl_i_i_1z_inferred_clock with period 23.34ns. Please declare a user-defined clock on net iPhy.iPhy.scl_i_i. 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Sep 27 09:29:34 2018
#


Top view:               topS
Requested Frequency:    38.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\fdc.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -6.804

                                      Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                        Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------------
GW_PLL|clkout_inferred_clock          38.9 MHz      33.1 MHz      25.699        30.234        -4.535     inferred     Autoconstr_clkgroup_0
SclkGen|scl_i_i_1z_inferred_clock     42.8 MHz      120.3 MHz     23.345        8.313         15.032     inferred     Autoconstr_clkgroup_1
System                                39.5 MHz      33.5 MHz      25.336        29.807        -4.471     system       system_clkgroup      
===========================================================================================================================================





Clock Relationships
*******************

Clocks                                                                |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise  
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                           Ending                             |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack 
----------------------------------------------------------------------------------------------------------------------------------------------------------------
System                             System                             |  25.336      -1.574  |  25.336      -4.471  |  25.336      -4.135  |  25.336      -1.790
System                             GW_PLL|clkout_inferred_clock       |  25.699      -4.920  |  No paths    -       |  No paths    -       |  25.699      -5.257
System                             SclkGen|scl_i_i_1z_inferred_clock  |  23.345      -6.588  |  No paths    -       |  No paths    -       |  23.345      -6.804
GW_PLL|clkout_inferred_clock       System                             |  25.699      -0.436  |  No paths    -       |  25.699      -3.387  |  25.699      24.189
GW_PLL|clkout_inferred_clock       GW_PLL|clkout_inferred_clock       |  25.699      -4.535  |  25.699      21.214  |  No paths    -       |  12.849      8.582 
GW_PLL|clkout_inferred_clock       SclkGen|scl_i_i_1z_inferred_clock  |  Diff grp    -       |  No paths    -       |  No paths    -       |  No paths    -     
SclkGen|scl_i_i_1z_inferred_clock  System                             |  23.345      15.032  |  No paths    -       |  No paths    -       |  No paths    -     
SclkGen|scl_i_i_1z_inferred_clock  GW_PLL|clkout_inferred_clock       |  Diff grp    -       |  No paths    -       |  No paths    -       |  No paths    -     
================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_PLL|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                            Arrival           
Instance                         Reference                        Type      Pin     Net              Time        Slack 
                                 Clock                                                                                 
-----------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z          GW_PLL|clkout_inferred_clock     DFFCE     Q       ddrKeepExit      0.367       -4.535
iPhy.iPhy.\\msgLength_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[4]     0.367       -4.269
iPhy.iPhy.\\msgLength_Z\[6\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[6]     0.367       -4.202
iPhy.iPhy.\\msgLength_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[5]     0.367       -4.073
iPhy.iPhy.\\msgLength_Z\[7\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[7]     0.367       -4.006
iPhy.iPhy.\\msgLength_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[2]     0.367       -3.992
iPhy.iPhy.\\msgLength_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[0]     0.367       -3.796
iPhy.iPhy.\\msgLength_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[3]     0.367       -3.796
iPhy.iPhy.\\msgLength_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFCE     Q       msgLength[1]     0.367       -3.600
iPhy.iPhy.enMaster_Z             GW_PLL|clkout_inferred_clock     DFFCE     Q       enMaster         0.367       -1.137
=======================================================================================================================


Ending Points with Worst Slack
******************************

                                Starting                                                            Required           
Instance                        Reference                        Type       Pin     Net             Time         Slack 
                                Clock                                                                                  
-----------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.\\data_r_Z\[1\]       GW_PLL|clkout_inferred_clock     DFFCE      D       data_pre[1]     25.566       -4.535
iPhy.iPhy.\\data_r_Z\[0\]       GW_PLL|clkout_inferred_clock     DFFCE      D       data_pre[0]     25.566       -3.618
iPhy.iPhy.sdaOen_r_Z            GW_PLL|clkout_inferred_clock     DFFPE      D       sdaOen_r_3      25.566       -3.431
iPhy.iPhy.\\cnWr_cnt_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
iPhy.iPhy.\\cnWr_cnt_Z\[6\]     GW_PLL|clkout_inferred_clock     DFFNCE     CE      cnWr_cnte       25.566       -3.387
=======================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      25.699
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         25.566

    - Propagation time:                      30.101
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.535

    Number of logic level(s):                18
    Starting point:                          iPhy.iPhy.ddrKeepExit_Z / Q
    Ending point:                            iPhy.iPhy.\\data_r_Z\[1\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                       Pin      Pin               Arrival     No. of    
Name                                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z                                                DFFCE         Q        Out     0.367     0.367       -         
ddrKeepExit                                                            Net           -        -       1.021     -           9         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          I0       In      -         1.388       -         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          F        Out     1.032     2.420       -         
\\iCore\.state_0_sqmuxa_1                                              Net           -        -       1.021     -           3         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          I1       In      -         3.441       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          F        Out     1.099     4.540       -         
iSclGen.cacheN_wreb12_4_1_1                                            Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          I2       In      -         5.306       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          F        Out     0.822     6.128       -         
iSclGen.cacheN_wreb12_4_1                                              Net           -        -       1.021     -           8         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11                           LUT4          I1       In      -         7.149       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11                           LUT4          F        Out     1.099     8.248       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_0_1                                    Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2_0                         MUX2_LUT5     I1       In      -         8.248       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2_0                         MUX2_LUT5     O        Out     0.150     8.398       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_0                                      Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     I0       In      -         8.398       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     O        Out     0.177     8.575       -         
iSclGen.cacheN_wreb12_4_sx_RNIMQA05                                    Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          I1       In      -         9.596       -         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          F        Out     1.099     10.695      -         
iSclGen.sdaO_set284_s_RNIHVF06                                         Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          I2       In      -         11.460      -         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          F        Out     0.822     12.282      -         
\\iSclGen\.cacheN_m4_0_o3_rn_0                                         Net           -        -       1.021     -           5         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          I2       In      -         13.303      -         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          F        Out     0.822     14.125      -         
forceSrP_iv                                                            Net           -        -       1.265     -           46        
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          I1       In      -         15.390      -         
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          F        Out     1.099     16.489      -         
\\iSclGen\.sdaO_N_4_mux                                                Net           -        -       1.021     -           9         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          I2       In      -         17.510      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          F        Out     0.822     18.332      -         
iEncoNxtState.ie164_l.ie83_h.bin_o_0_a3_0_sx_0[1]                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          I0       In      -         19.098      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          F        Out     1.032     20.130      -         
iEncoNxtState.ie164_l.ie83_h.N_20                                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          I0       In      -         20.896      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          F        Out     1.032     21.927      -         
iEncoNxtState.ie164_l.bin_h[1]                                         Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          I1       In      -         22.948      -         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          F        Out     1.099     24.047      -         
iEncoNxtState.bin_l[1]                                                 Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          I0       In      -         25.069      -         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          F        Out     1.032     26.100      -         
nxtStateBin[1]                                                         Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     I1       In      -         26.100      -         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     O        Out     0.150     26.250      -         
iSclGen.N_59                                                           Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          I0       In      -         27.271      -         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          F        Out     1.032     28.303      -         
iSclGen.N_116                                                          Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          I0       In      -         29.069      -         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          F        Out     1.032     30.101      -         
data_pre[1]                                                            Net           -        -       0.000     -           1         
iPhy.iPhy.\\data_r_Z\[1\]                                              DFFCE         D        In      -         30.101      -         
======================================================================================================================================
Total path delay (propagation time + setup) of 30.234 is 15.951(52.8%) logic and 14.283(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      25.699
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         25.566

    - Propagation time:                      30.101
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.535

    Number of logic level(s):                18
    Starting point:                          iPhy.iPhy.ddrKeepExit_Z / Q
    Ending point:                            iPhy.iPhy.\\data_r_Z\[1\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                       Pin      Pin               Arrival     No. of    
Name                                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z                                                DFFCE         Q        Out     0.367     0.367       -         
ddrKeepExit                                                            Net           -        -       1.021     -           9         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          I0       In      -         1.388       -         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          F        Out     1.032     2.420       -         
\\iCore\.state_0_sqmuxa_1                                              Net           -        -       1.021     -           3         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          I1       In      -         3.441       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          F        Out     1.099     4.540       -         
iSclGen.cacheN_wreb12_4_1_1                                            Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          I2       In      -         5.306       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          F        Out     0.822     6.128       -         
iSclGen.cacheN_wreb12_4_1                                              Net           -        -       1.021     -           8         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_2                         LUT4          I1       In      -         7.149       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_2                         LUT4          F        Out     1.099     8.248       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_1_0                                    Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2                           MUX2_LUT5     I0       In      -         8.248       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2                           MUX2_LUT5     O        Out     0.150     8.398       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_1                                      Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     I1       In      -         8.398       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     O        Out     0.177     8.575       -         
iSclGen.cacheN_wreb12_4_sx_RNIMQA05                                    Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          I1       In      -         9.596       -         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          F        Out     1.099     10.695      -         
iSclGen.sdaO_set284_s_RNIHVF06                                         Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          I2       In      -         11.460      -         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          F        Out     0.822     12.282      -         
\\iSclGen\.cacheN_m4_0_o3_rn_0                                         Net           -        -       1.021     -           5         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          I2       In      -         13.303      -         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          F        Out     0.822     14.125      -         
forceSrP_iv                                                            Net           -        -       1.265     -           46        
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          I1       In      -         15.390      -         
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          F        Out     1.099     16.489      -         
\\iSclGen\.sdaO_N_4_mux                                                Net           -        -       1.021     -           9         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          I2       In      -         17.510      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          F        Out     0.822     18.332      -         
iEncoNxtState.ie164_l.ie83_h.bin_o_0_a3_0_sx_0[1]                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          I0       In      -         19.098      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          F        Out     1.032     20.130      -         
iEncoNxtState.ie164_l.ie83_h.N_20                                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          I0       In      -         20.896      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          F        Out     1.032     21.927      -         
iEncoNxtState.ie164_l.bin_h[1]                                         Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          I1       In      -         22.948      -         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          F        Out     1.099     24.047      -         
iEncoNxtState.bin_l[1]                                                 Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          I0       In      -         25.069      -         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          F        Out     1.032     26.100      -         
nxtStateBin[1]                                                         Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     I1       In      -         26.100      -         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     O        Out     0.150     26.250      -         
iSclGen.N_59                                                           Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          I0       In      -         27.271      -         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          F        Out     1.032     28.303      -         
iSclGen.N_116                                                          Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          I0       In      -         29.069      -         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          F        Out     1.032     30.101      -         
data_pre[1]                                                            Net           -        -       0.000     -           1         
iPhy.iPhy.\\data_r_Z\[1\]                                              DFFCE         D        In      -         30.101      -         
======================================================================================================================================
Total path delay (propagation time + setup) of 30.234 is 15.951(52.8%) logic and 14.283(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      25.699
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         25.566

    - Propagation time:                      30.101
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.535

    Number of logic level(s):                18
    Starting point:                          iPhy.iPhy.ddrKeepExit_Z / Q
    Ending point:                            iPhy.iPhy.\\data_r_Z\[1\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                       Pin      Pin               Arrival     No. of    
Name                                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z                                                DFFCE         Q        Out     0.367     0.367       -         
ddrKeepExit                                                            Net           -        -       1.021     -           9         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          I0       In      -         1.388       -         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          F        Out     1.032     2.420       -         
\\iCore\.state_0_sqmuxa_1                                              Net           -        -       1.021     -           3         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          I1       In      -         3.441       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          F        Out     1.099     4.540       -         
iSclGen.cacheN_wreb12_4_1_1                                            Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          I2       In      -         5.306       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          F        Out     0.822     6.128       -         
iSclGen.cacheN_wreb12_4_1                                              Net           -        -       1.021     -           8         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_1                         LUT4          I1       In      -         7.149       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_1                         LUT4          F        Out     1.099     8.248       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_1_1                                    Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2                           MUX2_LUT5     I1       In      -         8.248       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2                           MUX2_LUT5     O        Out     0.150     8.398       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_1                                      Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     I1       In      -         8.398       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     O        Out     0.177     8.575       -         
iSclGen.cacheN_wreb12_4_sx_RNIMQA05                                    Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          I1       In      -         9.596       -         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          F        Out     1.099     10.695      -         
iSclGen.sdaO_set284_s_RNIHVF06                                         Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          I2       In      -         11.460      -         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          F        Out     0.822     12.282      -         
\\iSclGen\.cacheN_m4_0_o3_rn_0                                         Net           -        -       1.021     -           5         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          I2       In      -         13.303      -         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          F        Out     0.822     14.125      -         
forceSrP_iv                                                            Net           -        -       1.265     -           46        
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          I1       In      -         15.390      -         
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          F        Out     1.099     16.489      -         
\\iSclGen\.sdaO_N_4_mux                                                Net           -        -       1.021     -           9         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          I2       In      -         17.510      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          F        Out     0.822     18.332      -         
iEncoNxtState.ie164_l.ie83_h.bin_o_0_a3_0_sx_0[1]                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          I0       In      -         19.098      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          F        Out     1.032     20.130      -         
iEncoNxtState.ie164_l.ie83_h.N_20                                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          I0       In      -         20.896      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          F        Out     1.032     21.927      -         
iEncoNxtState.ie164_l.bin_h[1]                                         Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          I1       In      -         22.948      -         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          F        Out     1.099     24.047      -         
iEncoNxtState.bin_l[1]                                                 Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          I0       In      -         25.069      -         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          F        Out     1.032     26.100      -         
nxtStateBin[1]                                                         Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     I1       In      -         26.100      -         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     O        Out     0.150     26.250      -         
iSclGen.N_59                                                           Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          I0       In      -         27.271      -         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          F        Out     1.032     28.303      -         
iSclGen.N_116                                                          Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          I0       In      -         29.069      -         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          F        Out     1.032     30.101      -         
data_pre[1]                                                            Net           -        -       0.000     -           1         
iPhy.iPhy.\\data_r_Z\[1\]                                              DFFCE         D        In      -         30.101      -         
======================================================================================================================================
Total path delay (propagation time + setup) of 30.234 is 15.951(52.8%) logic and 14.283(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      25.699
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         25.566

    - Propagation time:                      30.101
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.535

    Number of logic level(s):                18
    Starting point:                          iPhy.iPhy.ddrKeepExit_Z / Q
    Ending point:                            iPhy.iPhy.\\data_r_Z\[1\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                       Pin      Pin               Arrival     No. of    
Name                                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z                                                DFFCE         Q        Out     0.367     0.367       -         
ddrKeepExit                                                            Net           -        -       1.021     -           9         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          I0       In      -         1.388       -         
iPhy.iPhy.iCore.state_0_sqmuxa_1                                       LUT4          F        Out     1.032     2.420       -         
\\iCore\.state_0_sqmuxa_1                                              Net           -        -       1.021     -           3         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          I1       In      -         3.441       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_1_cZ                               LUT4          F        Out     1.099     4.540       -         
iSclGen.cacheN_wreb12_4_1_1                                            Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          I2       In      -         5.306       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_cZ                                 LUT4          F        Out     0.822     6.128       -         
iSclGen.cacheN_wreb12_4_1                                              Net           -        -       1.021     -           8         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_0                         LUT4          I1       In      -         7.149       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIQ2O11_0                         LUT4          F        Out     1.099     8.248       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_0_0                                    Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2_0                         MUX2_LUT5     I0       In      -         8.248       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_1_RNIPBSC2_0                         MUX2_LUT5     O        Out     0.150     8.398       -         
iSclGen.cacheN_m4_0_o3_rn_N_3L3_0                                      Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     I0       In      -         8.398       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_4_sx_RNIMQA05_cZ                       MUX2_LUT6     O        Out     0.177     8.575       -         
iSclGen.cacheN_wreb12_4_sx_RNIMQA05                                    Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          I1       In      -         9.596       -         
iPhy.iPhy.iSclGen.sdaO_set284_s_RNIHVF06_cZ                            LUT4          F        Out     1.099     10.695      -         
iSclGen.sdaO_set284_s_RNIHVF06                                         Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          I2       In      -         11.460      -         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          F        Out     0.822     12.282      -         
\\iSclGen\.cacheN_m4_0_o3_rn_0                                         Net           -        -       1.021     -           5         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          I2       In      -         13.303      -         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          F        Out     0.822     14.125      -         
forceSrP_iv                                                            Net           -        -       1.265     -           46        
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          I1       In      -         15.390      -         
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          F        Out     1.099     16.489      -         
\\iSclGen\.sdaO_N_4_mux                                                Net           -        -       1.021     -           9         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          I2       In      -         17.510      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          F        Out     0.822     18.332      -         
iEncoNxtState.ie164_l.ie83_h.bin_o_0_a3_0_sx_0[1]                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          I0       In      -         19.098      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          F        Out     1.032     20.130      -         
iEncoNxtState.ie164_l.ie83_h.N_20                                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          I0       In      -         20.896      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          F        Out     1.032     21.927      -         
iEncoNxtState.ie164_l.bin_h[1]                                         Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          I1       In      -         22.948      -         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          F        Out     1.099     24.047      -         
iEncoNxtState.bin_l[1]                                                 Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          I0       In      -         25.069      -         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          F        Out     1.032     26.100      -         
nxtStateBin[1]                                                         Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     I1       In      -         26.100      -         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     O        Out     0.150     26.250      -         
iSclGen.N_59                                                           Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          I0       In      -         27.271      -         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          F        Out     1.032     28.303      -         
iSclGen.N_116                                                          Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          I0       In      -         29.069      -         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          F        Out     1.032     30.101      -         
data_pre[1]                                                            Net           -        -       0.000     -           1         
iPhy.iPhy.\\data_r_Z\[1\]                                              DFFCE         D        In      -         30.101      -         
======================================================================================================================================
Total path delay (propagation time + setup) of 30.234 is 15.951(52.8%) logic and 14.283(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      25.699
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         25.566

    - Propagation time:                      29.882
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -4.316

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.ddrKeepExit_Z / Q
    Ending point:                            iPhy.iPhy.\\data_r_Z\[1\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                       Pin      Pin               Arrival     No. of    
Name                                                                   Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.ddrKeepExit_Z                                                DFFCE         Q        Out     0.367     0.367       -         
ddrKeepExit                                                            Net           -        -       1.021     -           9         
iPhy.iPhy.iSclGen.cacheN_wreb12_N_4L5_1_cZ                             LUT4          I0       In      -         1.388       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_N_4L5_1_cZ                             LUT4          F        Out     1.032     2.420       -         
iSclGen.cacheN_wreb12_N_4L5_1_0                                        Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_wreb12_N_4L5_cZ                               LUT4          I3       In      -         3.186       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_N_4L5_cZ                               LUT4          F        Out     0.626     3.812       -         
iSclGen.cacheN_wreb12_N_4L5                                            Net           -        -       1.021     -           2         
iPhy.iPhy.iSclGen.cacheN_wreb12_cZ                                     LUT4          I2       In      -         4.833       -         
iPhy.iPhy.iSclGen.cacheN_wreb12_cZ                                     LUT4          F        Out     0.822     5.655       -         
cacheN_wreb52_2                                                        Net           -        -       1.204     -           40        
iPhy.iPhy.iSclGen.sdaO_set284_s_1_RNIQKPD                              LUT4          I0       In      -         6.859       -         
iPhy.iPhy.iSclGen.sdaO_set284_s_1_RNIQKPD                              LUT4          F        Out     1.032     7.891       -         
iSclGen.cacheN_m4_0_o3_N_4L6_sx                                        Net           -        -       1.021     -           2         
iPhy.iPhy.iSclGen.forceSrP_m5_i_a3_1_RNICUQC3                          LUT4          I0       In      -         8.912       -         
iPhy.iPhy.iSclGen.forceSrP_m5_i_a3_1_RNICUQC3                          LUT4          F        Out     1.032     9.943       -         
\\iSclGen\.cacheN_m4_0_o3_rn_1                                         Net           -        -       1.021     -           3         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          I1       In      -         10.964      -         
iPhy.iPhy.iSclGen.forceSrP_m7_e_RNIAI1V9                               LUT4          F        Out     1.099     12.063      -         
\\iSclGen\.cacheN_m4_0_o3_rn_0                                         Net           -        -       1.021     -           5         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          I2       In      -         13.084      -         
iPhy.iPhy.iSclGen.sdaO_set284_x_RNI9UCB01                              LUT4          F        Out     0.822     13.906      -         
forceSrP_iv                                                            Net           -        -       1.265     -           46        
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          I1       In      -         15.171      -         
iPhy.iPhy.iSclGen.forceDdrSrP_RNIVB5T41                                LUT4          F        Out     1.099     16.270      -         
\\iSclGen\.sdaO_N_4_mux                                                Net           -        -       1.021     -           9         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          I2       In      -         17.291      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0_sx_0_cZ\[1\]     LUT4          F        Out     0.822     18.113      -         
iEncoNxtState.ie164_l.ie83_h.bin_o_0_a3_0_sx_0[1]                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          I0       In      -         18.879      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0_a3_0\[1\]             LUT4          F        Out     1.032     19.911      -         
iEncoNxtState.ie164_l.ie83_h.N_20                                      Net           -        -       0.766     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          I0       In      -         20.677      -         
iPhy.iPhy.iEncoNxtState.ie164_l.ie83_h.\\bin_o_0\[1\]                  LUT4          F        Out     1.032     21.709      -         
iEncoNxtState.ie164_l.bin_h[1]                                         Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          I1       In      -         22.730      -         
iPhy.iPhy.iEncoNxtState.ie164_l.\\bin_o_2\[1\]                         LUT4          F        Out     1.099     23.829      -         
iEncoNxtState.bin_l[1]                                                 Net           -        -       1.021     -           1         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          I0       In      -         24.850      -         
iPhy.iPhy.iEncoNxtState.\\bin_o_2\[1\]                                 LUT3          F        Out     1.032     25.881      -         
nxtStateBin[1]                                                         Net           -        -       0.000     -           1         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     I1       In      -         25.881      -         
iPhy.iPhy.iSclGen.\\data_pre_3\[1\]                                    MUX2_LUT5     O        Out     0.150     26.032      -         
iSclGen.N_59                                                           Net           -        -       1.021     -           1         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          I0       In      -         27.052      -         
iPhy.iPhy.iSclGen.\\data_pre_11\[1\]                                   LUT3          F        Out     1.032     28.084      -         
iSclGen.N_116                                                          Net           -        -       0.766     -           1         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          I0       In      -         28.850      -         
iPhy.iPhy.iSclGen.\\data_pre\[1\]                                      LUT4          F        Out     1.032     29.882      -         
data_pre[1]                                                            Net           -        -       0.000     -           1         
iPhy.iPhy.\\data_r_Z\[1\]                                              DFFCE         D        In      -         29.882      -         
======================================================================================================================================
Total path delay (propagation time + setup) of 30.015 is 15.294(51.0%) logic and 14.721(49.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: SclkGen|scl_i_i_1z_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                Starting                                                                 Arrival           
Instance                        Reference                             Type     Pin        Net            Time        Slack 
                                Clock                                                                                      
---------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCacheP.bram_dp_0     SclkGen|scl_i_i_1z_inferred_clock     DP       DOB[0]     cacheP_dbO     0.818       15.032
iPhy.iPhy.iCacheN.bram_dp_0     SclkGen|scl_i_i_1z_inferred_clock     DP       DOB[0]     cacheN_dbO     0.818       16.423
===========================================================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                                                       Required           
Instance                  Reference                             Type      Pin     Net                    Time         Slack 
                          Clock                                                                                             
----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.lostDtt_r_Z     SclkGen|scl_i_i_1z_inferred_clock     DFFCE     CE      un1_locRst_i_237_i     23.212       15.032
============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         23.212

    - Propagation time:                      8.180
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 15.032

    Number of logic level(s):                4
    Starting point:                          iPhy.iPhy.iCacheP.bram_dp_0 / DOB[0]
    Ending point:                            iPhy.iPhy.lostDtt_r_Z / CE
    The start point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB
    The end   point is clocked by            System [rising] on pin CLK

Instance / Net                                                    Pin        Pin               Arrival     No. of    
Name                                                    Type      Name       Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCacheP.bram_dp_0                             DP        DOB[0]     Out     0.818     0.818       -         
cacheP_dbO                                              Net       -          -       1.021     -           1         
iPhy.iPhy.iSclGen.\\un1_sdaO175_222_RNIJ3TA_cZ\[0\]     LUT3      I0         In      -         1.839       -         
iPhy.iPhy.iSclGen.\\un1_sdaO175_222_RNIJ3TA_cZ\[0\]     LUT3      F          Out     1.032     2.871       -         
iSclGen.un1_sdaO175_222_RNIJ3TA[0]                      Net       -          -       0.766     -           1         
iPhy.iPhy.iSclGen.\\un1_sdaO175_222_RNID6D4P\[0\]       LUT4      I3         In      -         3.637       -         
iPhy.iPhy.iSclGen.\\un1_sdaO175_222_RNID6D4P\[0\]       LUT4      F          Out     0.626     4.263       -         
iSclGen.sda_m4_5                                        Net       -          -       0.766     -           1         
iPhy.iPhy.iSclGen.sdaOen_4_sqmuxa_RNIA715U              LUT4      I1         In      -         5.028       -         
iPhy.iPhy.iSclGen.sdaOen_4_sqmuxa_RNIA715U              LUT4      F          Out     1.099     6.127       -         
iSclGen.sda_N_8_mux                                     Net       -          -       1.021     -           2         
iPhy.iPhy.iSclGen.un1_ce_i_234_s_RNIOLB6GA              LUT4      I0         In      -         7.148       -         
iPhy.iPhy.iSclGen.un1_ce_i_234_s_RNIOLB6GA              LUT4      F          Out     1.032     8.180       -         
un1_locRst_i_237_i                                      Net       -          -       0.000     -           1         
iPhy.iPhy.lostDtt_r_Z                                   DFFCE     CE         In      -         8.180       -         
=====================================================================================================================
Total path delay (propagation time + setup) of 8.313 is 4.740(57.0%) logic and 3.573(43.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                           Starting                                                         Arrival           
Instance                                   Reference     Type       Pin     Net                             Time        Slack 
                                           Clock                                                                              
------------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]           System        DFFNCE     Q       iCore.state_r[8]                0.367       -6.804
iPhy.iPhy.iCore.\\state_r\[12\]            System        DFFNCE     Q       ddrSrDone                       0.367       -6.737
iPhy.iPhy.iCore.\\state_r\[0\]             System        DFFNPE     Q       \\iCore\.state_r[0]             0.367       -6.712
iPhy.iPhy.iCore.staDec_sta_r               System        DFFNCE     Q       \\iCore\.staDec_sta_r           0.367       -6.645
iPhy.iPhy.iCore.inDdr_exitDly_r            System        DFFCE      Q       \\iCore\.inDdr_exitDly_r        0.367       -6.588
iPhy.iPhy.iCore.\\state_r\[5\]             System        DFFNCE     Q       state[5]                        0.367       -6.584
iPhy.iPhy.iCore.\\state_r_fast_Z\[0\]      System        DFFNPE     Q       iCore.state_r_fast[0]           0.367       -6.567
iPhy.iPhy.iCore.\\state_r\[16\]            System        DFFNCE     Q       \\iCore\.state_r[16]            0.367       -6.527
iPhy.iPhy.iCore.\\inDdr_exitCnt_r\[3\]     System        DFFNCE     Q       \\iCore\.inDdr_exitCnt_r[3]     0.367       -6.521
iPhy.iPhy.iCore.\\state_r\[4\]             System        DFFNCE     Q       state[4]                        0.367       -6.516
==============================================================================================================================


Ending Points with Worst Slack
******************************

                                Starting                                              Required           
Instance                        Reference     Type     Pin         Net                Time         Slack 
                                Clock                                                                    
---------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[0]      cacheN_adb[0]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[1]      cacheN_adb[1]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[2]      cacheN_adb[2]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[3]      cacheN_adb[3]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[4]      cacheN_adb[4]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[6]      cacheN_adb[6]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[7]      cacheN_adb[7]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[8]      cacheN_adb[8]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[9]      cacheN_adb[9]      23.212       -6.804
iPhy.iPhy.iCacheN.bram_dp_0     System        DP       ADB[10]     cacheN_adb[10]     23.212       -6.804
=========================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         23.212

    - Propagation time:                      30.016
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -6.804

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.iCore.\\state_r_Z\[8\] / Q
    Ending point:                            iPhy.iPhy.iCacheN.bram_dp_0 / ADB[8]
    The start point is clocked by            System [falling] on pin CLK
    The end   point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB

Instance / Net                                                            Pin        Pin               Arrival     No. of    
Name                                                        Type          Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]                            DFFNCE        Q          Out     0.367     0.367       -         
iCore.state_r[8]                                            Net           -          -       1.021     -           4         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          I1         In      -         1.388       -         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          F          Out     1.099     2.487       -         
\\iCore\.state_f0_i_a2_0[8]                                 Net           -          -       1.021     -           7         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_1                   LUT4          I1         In      -         3.508       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_1                   LUT4          F          Out     1.099     4.607       -         
iCore.state_f0_i_o3_N_2L1_0_0                               Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     I0         In      -         4.607       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     O          Out     0.150     4.757       -         
iCore.state_f0_i_o3_N_2L1_0                                 Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     I0         In      -         4.757       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     O          Out     0.177     4.934       -         
iCore.state_f0_i_o3_N_2L1                                   Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          I2         In      -         5.955       -         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          F          Out     0.822     6.777       -         
state_f0_i_o3_x[8]                                          Net           -          -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          I0         In      -         7.798       -         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          F          Out     1.032     8.830       -         
iSclGen.sdaO_set286_19                                      Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          I1         In      -         9.851       -         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          F          Out     1.099     10.950      -         
iSclGen.sdaO_set287                                         Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          I3         In      -         12.032      -         
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          F          Out     0.626     12.658      -         
forceDdrSrP                                                 Net           -          -       1.204     -           39        
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          I0         In      -         13.862      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          F          Out     1.032     14.894      -         
\\iCore\.nxtState_m1_e_0_rn_0                               Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          I1         In      -         15.915      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          F          Out     1.099     17.014      -         
nxtState[14]                                                Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          I2         In      -         18.096      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          F          Out     0.822     18.918      -         
cacheN_wreb51_13                                            Net           -          -       1.082     -           13        
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          I0         In      -         20.000      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          F          Out     1.032     21.032      -         
iSclGen.cacheN_wreb51_13_RNI97N1J5                          Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          I1         In      -         21.797      -         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          F          Out     1.099     22.896      -         
iSclGen.g0_28_1_0                                           Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          I1         In      -         23.917      -         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          F          Out     1.099     25.016      -         
iSclGen.g0_1_2                                              Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          I1         In      -         25.782      -         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          F          Out     1.099     26.881      -         
N_35                                                        Net           -          -       1.082     -           12        
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          I0         In      -         27.963      -         
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          F          Out     1.032     28.995      -         
cacheN_adb[8]                                               Net           -          -       1.021     -           1         
iPhy.iPhy.iCacheN.bram_dp_0                                 DP            ADB[8]     In      -         30.016      -         
=============================================================================================================================
Total path delay (propagation time + setup) of 30.149 is 14.918(49.5%) logic and 15.231(50.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         23.212

    - Propagation time:                      30.016
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -6.804

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.iCore.\\state_r_Z\[8\] / Q
    Ending point:                            iPhy.iPhy.iCacheN.bram_dp_0 / ADB[8]
    The start point is clocked by            System [falling] on pin CLK
    The end   point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB

Instance / Net                                                            Pin        Pin               Arrival     No. of    
Name                                                        Type          Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]                            DFFNCE        Q          Out     0.367     0.367       -         
iCore.state_r[8]                                            Net           -          -       1.021     -           4         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          I1         In      -         1.388       -         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          F          Out     1.099     2.487       -         
\\iCore\.state_f0_i_a2_0[8]                                 Net           -          -       1.021     -           7         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_2                   LUT4          I1         In      -         3.508       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_2                   LUT4          F          Out     1.099     4.607       -         
iCore.state_f0_i_o3_N_2L1_2_0                               Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_0                   MUX2_LUT5     I0         In      -         4.607       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_0                   MUX2_LUT5     O          Out     0.150     4.757       -         
iCore.state_f0_i_o3_N_2L1_2                                 Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     I1         In      -         4.757       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     O          Out     0.177     4.934       -         
iCore.state_f0_i_o3_N_2L1                                   Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          I2         In      -         5.955       -         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          F          Out     0.822     6.777       -         
state_f0_i_o3_x[8]                                          Net           -          -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          I0         In      -         7.798       -         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          F          Out     1.032     8.830       -         
iSclGen.sdaO_set286_19                                      Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          I1         In      -         9.851       -         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          F          Out     1.099     10.950      -         
iSclGen.sdaO_set287                                         Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          I3         In      -         12.032      -         
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          F          Out     0.626     12.658      -         
forceDdrSrP                                                 Net           -          -       1.204     -           39        
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          I0         In      -         13.862      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          F          Out     1.032     14.894      -         
\\iCore\.nxtState_m1_e_0_rn_0                               Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          I1         In      -         15.915      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          F          Out     1.099     17.014      -         
nxtState[14]                                                Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          I2         In      -         18.096      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          F          Out     0.822     18.918      -         
cacheN_wreb51_13                                            Net           -          -       1.082     -           13        
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          I0         In      -         20.000      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          F          Out     1.032     21.032      -         
iSclGen.cacheN_wreb51_13_RNI97N1J5                          Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          I1         In      -         21.797      -         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          F          Out     1.099     22.896      -         
iSclGen.g0_28_1_0                                           Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          I1         In      -         23.917      -         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          F          Out     1.099     25.016      -         
iSclGen.g0_1_2                                              Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          I1         In      -         25.782      -         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          F          Out     1.099     26.881      -         
N_35                                                        Net           -          -       1.082     -           12        
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          I0         In      -         27.963      -         
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          F          Out     1.032     28.995      -         
cacheN_adb[8]                                               Net           -          -       1.021     -           1         
iPhy.iPhy.iCacheN.bram_dp_0                                 DP            ADB[8]     In      -         30.016      -         
=============================================================================================================================
Total path delay (propagation time + setup) of 30.149 is 14.918(49.5%) logic and 15.231(50.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         23.212

    - Propagation time:                      30.016
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -6.804

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.iCore.\\state_r_Z\[8\] / Q
    Ending point:                            iPhy.iPhy.iCacheN.bram_dp_0 / ADB[8]
    The start point is clocked by            System [falling] on pin CLK
    The end   point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB

Instance / Net                                                            Pin        Pin               Arrival     No. of    
Name                                                        Type          Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]                            DFFNCE        Q          Out     0.367     0.367       -         
iCore.state_r[8]                                            Net           -          -       1.021     -           4         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          I1         In      -         1.388       -         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          F          Out     1.099     2.487       -         
\\iCore\.state_f0_i_a2_0[8]                                 Net           -          -       1.021     -           7         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_4                   LUT4          I1         In      -         3.508       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_4                   LUT4          F          Out     1.099     4.607       -         
iCore.state_f0_i_o3_N_2L1_2_1                               Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_0                   MUX2_LUT5     I1         In      -         4.607       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_0                   MUX2_LUT5     O          Out     0.150     4.757       -         
iCore.state_f0_i_o3_N_2L1_2                                 Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     I1         In      -         4.757       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     O          Out     0.177     4.934       -         
iCore.state_f0_i_o3_N_2L1                                   Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          I2         In      -         5.955       -         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          F          Out     0.822     6.777       -         
state_f0_i_o3_x[8]                                          Net           -          -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          I0         In      -         7.798       -         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          F          Out     1.032     8.830       -         
iSclGen.sdaO_set286_19                                      Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          I1         In      -         9.851       -         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          F          Out     1.099     10.950      -         
iSclGen.sdaO_set287                                         Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          I3         In      -         12.032      -         
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          F          Out     0.626     12.658      -         
forceDdrSrP                                                 Net           -          -       1.204     -           39        
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          I0         In      -         13.862      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          F          Out     1.032     14.894      -         
\\iCore\.nxtState_m1_e_0_rn_0                               Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          I1         In      -         15.915      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          F          Out     1.099     17.014      -         
nxtState[14]                                                Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          I2         In      -         18.096      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          F          Out     0.822     18.918      -         
cacheN_wreb51_13                                            Net           -          -       1.082     -           13        
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          I0         In      -         20.000      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          F          Out     1.032     21.032      -         
iSclGen.cacheN_wreb51_13_RNI97N1J5                          Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          I1         In      -         21.797      -         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          F          Out     1.099     22.896      -         
iSclGen.g0_28_1_0                                           Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          I1         In      -         23.917      -         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          F          Out     1.099     25.016      -         
iSclGen.g0_1_2                                              Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          I1         In      -         25.782      -         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          F          Out     1.099     26.881      -         
N_35                                                        Net           -          -       1.082     -           12        
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          I0         In      -         27.963      -         
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          F          Out     1.032     28.995      -         
cacheN_adb[8]                                               Net           -          -       1.021     -           1         
iPhy.iPhy.iCacheN.bram_dp_0                                 DP            ADB[8]     In      -         30.016      -         
=============================================================================================================================
Total path delay (propagation time + setup) of 30.149 is 14.918(49.5%) logic and 15.231(50.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         23.212

    - Propagation time:                      30.016
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -6.804

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.iCore.\\state_r_Z\[8\] / Q
    Ending point:                            iPhy.iPhy.iCacheN.bram_dp_0 / ADB[8]
    The start point is clocked by            System [falling] on pin CLK
    The end   point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB

Instance / Net                                                            Pin        Pin               Arrival     No. of    
Name                                                        Type          Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]                            DFFNCE        Q          Out     0.367     0.367       -         
iCore.state_r[8]                                            Net           -          -       1.021     -           4         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          I1         In      -         1.388       -         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          F          Out     1.099     2.487       -         
\\iCore\.state_f0_i_a2_0[8]                                 Net           -          -       1.021     -           7         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_3                   LUT4          I1         In      -         3.508       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_3                   LUT4          F          Out     1.099     4.607       -         
iCore.state_f0_i_o3_N_2L1_0_1                               Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     I1         In      -         4.607       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     O          Out     0.150     4.757       -         
iCore.state_f0_i_o3_N_2L1_0                                 Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     I0         In      -         4.757       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     O          Out     0.177     4.934       -         
iCore.state_f0_i_o3_N_2L1                                   Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          I2         In      -         5.955       -         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          F          Out     0.822     6.777       -         
state_f0_i_o3_x[8]                                          Net           -          -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          I0         In      -         7.798       -         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          F          Out     1.032     8.830       -         
iSclGen.sdaO_set286_19                                      Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          I1         In      -         9.851       -         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          F          Out     1.099     10.950      -         
iSclGen.sdaO_set287                                         Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          I3         In      -         12.032      -         
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          F          Out     0.626     12.658      -         
forceDdrSrP                                                 Net           -          -       1.204     -           39        
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          I0         In      -         13.862      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          F          Out     1.032     14.894      -         
\\iCore\.nxtState_m1_e_0_rn_0                               Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          I1         In      -         15.915      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          F          Out     1.099     17.014      -         
nxtState[14]                                                Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          I2         In      -         18.096      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          F          Out     0.822     18.918      -         
cacheN_wreb51_13                                            Net           -          -       1.082     -           13        
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          I0         In      -         20.000      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          F          Out     1.032     21.032      -         
iSclGen.cacheN_wreb51_13_RNI97N1J5                          Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          I1         In      -         21.797      -         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          F          Out     1.099     22.896      -         
iSclGen.g0_28_1_0                                           Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          I1         In      -         23.917      -         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          F          Out     1.099     25.016      -         
iSclGen.g0_1_2                                              Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          I1         In      -         25.782      -         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          F          Out     1.099     26.881      -         
N_35                                                        Net           -          -       1.082     -           12        
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          I0         In      -         27.963      -         
iPhy.iPhy.iCore.\\cacheN_adb_iv\[8\]                        LUT4          F          Out     1.032     28.995      -         
cacheN_adb[8]                                               Net           -          -       1.021     -           1         
iPhy.iPhy.iCacheN.bram_dp_0                                 DP            ADB[8]     In      -         30.016      -         
=============================================================================================================================
Total path delay (propagation time + setup) of 30.149 is 14.918(49.5%) logic and 15.231(50.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      23.345
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         23.212

    - Propagation time:                      30.016
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -6.804

    Number of logic level(s):                16
    Starting point:                          iPhy.iPhy.iCore.\\state_r_Z\[8\] / Q
    Ending point:                            iPhy.iPhy.iCacheN.bram_dp_0 / ADB[3]
    The start point is clocked by            System [falling] on pin CLK
    The end   point is clocked by            SclkGen|scl_i_i_1z_inferred_clock [rising] on pin CLKB

Instance / Net                                                            Pin        Pin               Arrival     No. of    
Name                                                        Type          Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
iPhy.iPhy.iCore.\\state_r_Z\[8\]                            DFFNCE        Q          Out     0.367     0.367       -         
iCore.state_r[8]                                            Net           -          -       1.021     -           4         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          I1         In      -         1.388       -         
iPhy.iPhy.iCore.\\state_f0_i_a2_0\[8\]                      LUT3          F          Out     1.099     2.487       -         
\\iCore\.state_f0_i_a2_0[8]                                 Net           -          -       1.021     -           7         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_1                   LUT4          I1         In      -         3.508       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO_1                   LUT4          F          Out     1.099     4.607       -         
iCore.state_f0_i_o3_N_2L1_0_0                               Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     I0         In      -         4.607       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_RNO                     MUX2_LUT5     O          Out     0.150     4.757       -         
iCore.state_f0_i_o3_N_2L1_0                                 Net           -          -       0.000     -           1         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     I0         In      -         4.757       -         
iPhy.iPhy.iCore.state_f0_i_o3_N_2L1_cZ                      MUX2_LUT6     O          Out     0.177     4.934       -         
iCore.state_f0_i_o3_N_2L1                                   Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          I2         In      -         5.955       -         
iPhy.iPhy.iCore.\\state_f0_i_o3_x\[8\]                      LUT3          F          Out     0.822     6.777       -         
state_f0_i_o3_x[8]                                          Net           -          -       1.021     -           1         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          I0         In      -         7.798       -         
iPhy.iPhy.iSclGen.sdaO_set286_19_cZ                         LUT4          F          Out     1.032     8.830       -         
iSclGen.sdaO_set286_19                                      Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          I1         In      -         9.851       -         
iPhy.iPhy.iSclGen.sdaO_set287_cZ                            LUT4          F          Out     1.099     10.950      -         
iSclGen.sdaO_set287                                         Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          I3         In      -         12.032      -         
iPhy.iPhy.iSclGen.forceDdrSrP                               LUT4          F          Out     0.626     12.658      -         
forceDdrSrP                                                 Net           -          -       1.204     -           39        
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          I0         In      -         13.862      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNIK6075              LUT4          F          Out     1.032     14.894      -         
\\iCore\.nxtState_m1_e_0_rn_0                               Net           -          -       1.021     -           2         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          I1         In      -         15.915      -         
iPhy.iPhy.iCore.un1_nxtState_2_sqmuxa_RNILJ7FS              LUT4          F          Out     1.099     17.014      -         
nxtState[14]                                                Net           -          -       1.082     -           17        
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          I2         In      -         18.096      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13                          LUT4          F          Out     0.822     18.918      -         
cacheN_wreb51_13                                            Net           -          -       1.082     -           13        
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          I0         In      -         20.000      -         
iPhy.iPhy.iSclGen.cacheN_wreb51_13_RNI97N1J5_cZ             LUT4          F          Out     1.032     21.032      -         
iSclGen.cacheN_wreb51_13_RNI97N1J5                          Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          I1         In      -         21.797      -         
iPhy.iPhy.iSclGen.cacheN_adb_1_sqmuxa_70_11_x_RNIEE51HB     LUT4          F          Out     1.099     22.896      -         
iSclGen.g0_28_1_0                                           Net           -          -       1.021     -           4         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          I1         In      -         23.917      -         
iPhy.iPhy.iSclGen.cacheN_wreb53_0_RNIM22P9B1                LUT4          F          Out     1.099     25.016      -         
iSclGen.g0_1_2                                              Net           -          -       0.766     -           1         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          I1         In      -         25.782      -         
iPhy.iPhy.iSclGen.cnWr_inc_2_d_RNI5BQORF2                   LUT4          F          Out     1.099     26.881      -         
N_35                                                        Net           -          -       1.082     -           12        
iPhy.iPhy.iSclGen.\\cacheN_adb_iv\[3\]                      LUT4          I0         In      -         27.963      -         
iPhy.iPhy.iSclGen.\\cacheN_adb_iv\[3\]                      LUT4          F          Out     1.032     28.995      -         
cacheN_adb[3]                                               Net           -          -       1.021     -           1         
iPhy.iPhy.iCacheN.bram_dp_0                                 DP            ADB[3]     In      -         30.016      -         
=============================================================================================================================
Total path delay (propagation time + setup) of 30.149 is 14.918(49.5%) logic and 15.231(50.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 198MB peak: 205MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 198MB peak: 205MB)

---------------------------------------
Resource Usage Report for topS 

Mapping to part: gw1n_9eslqfp144-6
Cell usage:
ALU             89 uses
DFFC            26 uses
DFFCE           106 uses
DFFNC           2 uses
DFFNCE          110 uses
DFFNP           14 uses
DFFNPE          47 uses
DFFNR           16 uses
DFFNS           6 uses
DFFNSE          2 uses
DFFP            9 uses
DFFPE           73 uses
DP              2 uses
GSR             1 use
INV             10 uses
MUX2_LUT5       29 uses
MUX2_LUT6       6 uses
MUX2_LUT7       1 use
PLL             1 use
LUT2            203 uses
LUT3            341 uses
LUT4            715 uses

I/O ports: 106
I/O primitives: 85
IBUF           3 uses
IOBUF          2 uses
OBUF           27 uses
TBUF           53 uses

I/O Register bits:                  0
Register bits not including I/Os:   411 of 6480 (6%)

RAM/ROM usage summary
Block Rams : 2 of 24 (8%)

Total load per clock:
   GW_PLL|clkout_inferred_clock: 172

@S |Mapping Summary:
Total  LUTs: 1259 (14%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 44MB peak: 205MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Thu Sep 27 09:29:34 2018

###########################################################]