Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I3C_SINGLE_CLK\data\i3c_single_clock.v C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I3C_SINGLE_CLK\data\i3c_single_clock_top.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.01 |
Part Number | GW1NS-LV4CQN48C7/I6 |
Device | GW1NS-4C |
Created Time | Mon Nov 01 14:18:15 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | I3C_Single_Clock_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.432s, Peak memory usage = 53.703MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 53.703MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 53.703MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.197s, Peak memory usage = 53.703MB Optimizing Phase 2: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 53.703MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 53.703MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 53.703MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 53.703MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 53.703MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s, Peak memory usage = 53.703MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 53.703MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 53.703MB Tech-Mapping Phase 3: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 67.500MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.412s, Peak memory usage = 67.500MB Generate output files: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 67.500MB |
Total Time and Memory Usage | CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 67.500MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 81 |
I/O Buf | 81 |
    IBUF | 45 |
    OBUF | 33 |
    TBUF | 1 |
    IOBUF | 2 |
Register | 1786 |
    DFFE | 512 |
    DFFP | 25 |
    DFFPE | 112 |
    DFFC | 495 |
    DFFCE | 642 |
LUT | 2568 |
    LUT2 | 327 |
    LUT3 | 879 |
    LUT4 | 1362 |
ALU | 141 |
    ALU | 141 |
INV | 4 |
    INV | 4 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2713(2572 LUTs, 141 ALUs) / 4608 | 59% |
Register | 1786 / 3570 | 50% |
  --Register as Latch | 0 / 3570 | 0% |
  --Register as FF | 1786 / 3570 | 50% |
BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
fclk | Base | 20.000 | 50.0 | 0.000 | 10.000 | fclk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | fclk | 50.0(MHz) | 91.0(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 9.014 |
Data Arrival Time | 11.686 |
Data Required Time | 20.700 |
From | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0 |
To | u_i3c_single_clock_top/u_i3c_reg/flag_m_ddr_waitrdata2ddrdatapre_s0 |
Launch Clk | fclk[R] |
Latch Clk | fclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | fclk | |||
0.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 9 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/I1 |
2.506 | 0.814 | tINS | FF | 16 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/F |
2.862 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/I1 |
3.676 | 0.814 | tINS | FF | 7 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/F |
4.032 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/I1 |
4.846 | 0.814 | tINS | FF | 3 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/F |
5.202 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/I1 |
6.016 | 0.814 | tINS | FF | 9 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/F |
6.372 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s0/I0 |
7.137 | 0.765 | tINS | FF | 10 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s0/F |
7.492 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s2/I0 |
8.257 | 0.765 | tINS | FF | 3 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s2/F |
8.613 | 0.356 | tNET | FF | 2 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/remain_data_count_rfifo_3_s/I0 |
9.341 | 0.728 | tINS | FF | 2 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/remain_data_count_rfifo_3_s/SUM |
9.697 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n797_s16/I3 |
10.161 | 0.464 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n797_s16/F |
10.516 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n797_s15/I1 |
11.331 | 0.814 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n797_s15/F |
11.686 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/flag_m_ddr_waitrdata2ddrdatapre_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | fclk | |||
20.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_reg/flag_m_ddr_waitrdata2ddrdatapre_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_i3c_single_clock_top/u_i3c_reg/flag_m_ddr_waitrdata2ddrdatapre_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 6.793, 63.551%; route: 3.557, 33.272%; tC2Q: 0.340, 3.177% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:Slack | 9.738 |
Data Arrival Time | 10.963 |
Data Required Time | 20.700 |
From | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0 |
To | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_RXEMPTY_s0 |
Launch Clk | fclk[R] |
Latch Clk | fclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | fclk | |||
0.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 9 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/I1 |
2.506 | 0.814 | tINS | FF | 16 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/F |
2.862 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/I1 |
3.676 | 0.814 | tINS | FF | 7 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/F |
4.032 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/I1 |
4.846 | 0.814 | tINS | FF | 3 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/F |
5.202 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/I1 |
6.016 | 0.814 | tINS | FF | 9 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/F |
6.372 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/mem_s250/I0 |
7.137 | 0.765 | tINS | FF | 11 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/mem_s250/F |
7.492 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_4_s/I1 |
8.307 | 0.814 | tINS | FF | 2 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_4_s/F |
8.662 | 0.356 | tNET | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n481_s0/I1 |
9.437 | 0.774 | tINS | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n481_s0/COUT |
9.792 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n739_s2/I1 |
10.607 | 0.814 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n739_s2/F |
10.963 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_RXEMPTY_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | fclk | |||
20.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_RXEMPTY_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_RXEMPTY_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 6.425, 64.471%; route: 3.201, 32.121%; tC2Q: 0.340, 3.408% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:Slack | 9.738 |
Data Arrival Time | 10.963 |
Data Required Time | 20.700 |
From | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0 |
To | u_i3c_single_clock_top/u_i3c_reg/MSTATUS_RXPEND_s0 |
Launch Clk | fclk[R] |
Latch Clk | fclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | fclk | |||
0.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 9 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/I1 |
2.506 | 0.814 | tINS | FF | 16 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/F |
2.862 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/I1 |
3.676 | 0.814 | tINS | FF | 7 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/F |
4.032 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/I1 |
4.846 | 0.814 | tINS | FF | 3 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/F |
5.202 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/I1 |
6.016 | 0.814 | tINS | FF | 9 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/F |
6.372 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/mem_s250/I0 |
7.137 | 0.765 | tINS | FF | 11 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/mem_s250/F |
7.492 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_4_s/I1 |
8.307 | 0.814 | tINS | FF | 2 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_4_s/F |
8.662 | 0.356 | tNET | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n481_s0/I1 |
9.437 | 0.774 | tINS | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n481_s0/COUT |
9.792 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n484_s1/I1 |
10.607 | 0.814 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n484_s1/F |
10.963 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/MSTATUS_RXPEND_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | fclk | |||
20.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_reg/MSTATUS_RXPEND_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_i3c_single_clock_top/u_i3c_reg/MSTATUS_RXPEND_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 6.425, 64.471%; route: 3.201, 32.121%; tC2Q: 0.340, 3.408% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:Slack | 10.098 |
Data Arrival Time | 10.602 |
Data Required Time | 20.700 |
From | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0 |
To | u_i3c_single_clock_top/u_i3c_reg/full_rcve_s0 |
Launch Clk | fclk[R] |
Latch Clk | fclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | fclk | |||
0.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 9 | u_i3c_single_clock_top/u_i3c_controller/c_state_20_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/I1 |
2.506 | 0.814 | tINS | FF | 16 | u_i3c_single_clock_top/u_i3c_controller/n4065_s6/F |
2.862 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/I1 |
3.676 | 0.814 | tINS | FF | 7 | u_i3c_single_clock_top/u_i3c_controller/n4875_s2/F |
4.032 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/I1 |
4.846 | 0.814 | tINS | FF | 3 | u_i3c_single_clock_top/u_i3c_controller/n4875_s1/F |
5.202 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/I1 |
6.016 | 0.814 | tINS | FF | 9 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_0_s0/F |
6.372 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s0/I0 |
7.137 | 0.765 | tINS | FF | 10 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s0/F |
7.492 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s2/I0 |
8.257 | 0.765 | tINS | FF | 3 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_rcve/rfifo_next_wr_ptr_3_s2/F |
8.613 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n791_s3/I1 |
9.427 | 0.814 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n791_s3/F |
9.783 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n791_s1/I3 |
10.247 | 0.464 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n791_s1/F |
10.602 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/full_rcve_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | fclk | |||
20.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_reg/full_rcve_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_i3c_single_clock_top/u_i3c_reg/full_rcve_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 6.065, 63.139%; route: 3.201, 33.325%; tC2Q: 0.340, 3.536% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 5
Path Summary:Slack | 10.209 |
Data Arrival Time | 10.491 |
Data Required Time | 20.700 |
From | u_i3c_single_clock_top/u_i3c_controller/c_state_10_s0 |
To | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_TXFULL_s0 |
Launch Clk | fclk[R] |
Latch Clk | fclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | fclk | |||
0.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_controller/c_state_10_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 11 | u_i3c_single_clock_top/u_i3c_controller/c_state_10_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n4065_s3/I1 |
2.506 | 0.814 | tINS | FF | 10 | u_i3c_single_clock_top/u_i3c_controller/n4065_s3/F |
2.862 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/n1523_s1/I1 |
3.676 | 0.814 | tINS | FF | 43 | u_i3c_single_clock_top/u_i3c_controller/n1523_s1/F |
4.032 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/rd_bus_Z_s1/I0 |
4.797 | 0.765 | tINS | FF | 12 | u_i3c_single_clock_top/u_i3c_controller/rd_bus_Z_s1/F |
5.152 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_controller/rd_bus_Z_s/I1 |
5.967 | 0.814 | tINS | FF | 16 | u_i3c_single_clock_top/u_i3c_controller/rd_bus_Z_s/F |
6.322 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_send/sfifo_next_rd_ptr_0_s/I1 |
7.137 | 0.814 | tINS | FF | 3 | u_i3c_single_clock_top/u_fifo_controller_master/u_fifo_send/sfifo_next_rd_ptr_0_s/F |
7.492 | 0.356 | tNET | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n489_s0/I1 |
8.267 | 0.774 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n489_s0/COUT |
8.267 | 0.000 | tNET | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n490_s0/CIN |
8.309 | 0.042 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n490_s0/COUT |
8.309 | 0.000 | tNET | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n491_s0/CIN |
8.351 | 0.042 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n491_s0/COUT |
8.707 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n752_s4/I2 |
9.316 | 0.609 | tINS | FF | 2 | u_i3c_single_clock_top/u_i3c_reg/n752_s4/F |
9.672 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n752_s1/I3 |
10.136 | 0.464 | tINS | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/n752_s1/F |
10.491 | 0.356 | tNET | FF | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_TXFULL_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | fclk | |||
20.000 | 0.000 | tCL | RR | 1 | fclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 1786 | fclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_TXFULL_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_i3c_single_clock_top/u_i3c_reg/MDATACTRL_TXFULL_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 5.954, 62.708%; route: 3.201, 33.715%; tC2Q: 0.340, 3.577% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |