Timing Messages

Report Title Gowin Timing Analysis Report
Tool Version v1.7.10Beta
Series, Device, Package, Speed, Operating Conditions GW2AR18, GW2AR-18, LQFP144, 8, COMMERCIAL
Design Name top
Design File E:\Editor_use\IDE\SDRAM\release\1.7.10\GW_LVDS71_LCD_Controller_RefDesign\GW_LVDS71_LCD_Controller_RefDesign\project\impl\synthesize\rev_1\LVDS71_LCD_Controller.vm
Timing Constraint File ---
Timing Report File E:\Editor_use\IDE\SDRAM\release\1.7.10\GW_LVDS71_LCD_Controller_RefDesign\GW_LVDS71_LCD_Controller_RefDesign\project\impl\pnr\LVDS71_LCD_Controller.tr.html
Created Time Fri Nov 03 16:18:44 2017
Command Line C:\Gowin\1.7\Pnr\bin\gowin.exe -do E:\Editor_use\IDE\SDRAM\release\1.7.10\GW_LVDS71_LCD_Controller_RefDesign\GW_LVDS71_LCD_Controller_RefDesign\project\impl\pnr\cmd.do
Legal Announcement Copyright (C)2014-2017 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C
Hold Delay Model Fast 1.05V 0C
Numbers of Paths Analyzed 290
Numbers of Endpoints Analyzed 146
Numbers of Falling Endpoints 5
Numbers of Setup Violated Endpoints 30
Numbers of Hold Violated Endpoints 10

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
pll_inst/CLKIN.default_clk Base 12.500 80.000 0.000 6.250
pll_inst/CLKOUTP.default_gen_clk Generated 3.571 280.000 0.714 2.500 pll_inst/CLKIN.default_clk
pll_inst/CLKOUTD.default_gen_clk Generated 7.143 140.000 0.000 3.571 pll_inst/CLKIN.default_clk
pll_inst/CLKOUTD3.default_gen_clk Generated 10.714 93.333 0.000 5.357 pll_inst/CLKIN.default_clk
pll_inst/CLKOUT.default_gen_clk Generated 3.571 280.000 0.000 1.786 pll_inst/CLKIN.default_clk

Max Frequency Summary:

NO. Clock Name Fmax Entity
1 pll_inst/CLKIN.default_clk 171.854(MHz) TOP
2 pll_inst/CLKOUT.default_gen_clk 475.887(MHz) TOP

No timing paths to get frequency of pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
pll_inst/CLKIN.default_clk Setup 0.000 0
pll_inst/CLKIN.default_clk Hold 0.000 0
pll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
pll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
pll_inst/CLKOUT.default_gen_clk Setup 0.000 0
pll_inst/CLKOUT.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 25

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -2.709 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.721
2 -2.705 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.717
3 -2.438 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.450
4 -2.434 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.446
5 -2.433 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.445
6 -2.342 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.721
7 -2.337 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.717
8 -2.071 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.450
9 -2.066 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.446
10 -2.066 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.445
11 -1.582 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/RESETN pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.223 2.715
12 -1.518 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D4 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.955
13 -1.517 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D6 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.954
14 -1.515 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D5 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.955
15 -1.514 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D2 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.951
16 -1.511 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D3 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.951
17 -1.511 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D1 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.951
18 -1.382 u_colorbar_gen/color_cnt_Z[9]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D0 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.819
19 -1.377 u_colorbar_gen/color_cnt_Z[9]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D6 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.814
20 -1.269 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.721
21 -1.265 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.717
22 -1.215 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D0 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.652
23 -1.212 u_colorbar_gen/color_cnt_Z[7]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D1 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.652
24 -1.144 u_colorbar_gen/color_cnt_Z[9]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D4 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.581
25 -1.144 u_colorbar_gen/color_cnt_Z[9]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D2 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.581

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 25

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.523 u_colorbar_gen/hsync_r_Z/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D2 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.071
2 -0.401 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.110
3 -0.368 u_colorbar_gen/lv_r_Z/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D0 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.227
4 -0.362 u_colorbar_gen/vsync_r_Z/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D1 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.221
5 -0.087 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D2 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.508
6 -0.075 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D1 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.508
7 -0.045 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D4 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.550
8 -0.043 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D6 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.552
9 -0.033 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D5 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.550
10 -0.033 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D3 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.550
11 0.057 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D6 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.652
12 0.058 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D4 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.653
13 0.058 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.711
14 0.061 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.713
15 0.062 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.715
16 0.068 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D0 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.663
17 0.070 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D5 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.653
18 0.071 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D3 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.654
19 0.080 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D1 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.663
20 0.136 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D4 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.731
21 0.136 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D2 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.731
22 0.148 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D5 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.731
23 0.148 u_colorbar_gen/color_cnt_Z[11]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D3 pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.731
24 0.210 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.863
25 0.211 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.864

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 25

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -2.709 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.721
2 -2.705 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.717
3 -2.438 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.450
4 -2.434 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.446
5 -2.433 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.221 3.445
6 -2.342 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.721
7 -2.337 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.717
8 -2.071 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.450
9 -2.066 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.446
10 -2.066 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 1.786 -0.145 3.445
11 -1.582 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/RESETN pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 0.223 2.715
12 -1.269 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.721
13 -1.265 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.717
14 -0.998 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.450
15 -0.994 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.446
16 -0.993 cnt_Z[4]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 1.786 -1.219 3.445
17 9.675 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[3]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.590
18 9.752 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[8]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.513
19 9.752 cnt_Z[4]/Q u_colorbar_gen/line_cnt_fast_Z[8]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.513
20 9.909 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[2]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.356
21 9.909 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[4]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.356
22 9.913 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[7]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.352
23 9.913 cnt_Z[4]/Q u_colorbar_gen/line_cnt_Z[9]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.352
24 9.918 cnt_Z[4]/Q u_colorbar_gen/color_cnt_Z[6]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.347
25 9.918 cnt_Z[4]/Q u_colorbar_gen/color_cnt_Z[7]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 12.500 0.000 2.347

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 25

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.058 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.711
2 0.061 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.713
3 0.062 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.715
4 0.210 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.863
5 0.211 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.100 1.864
6 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[0]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
7 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[1]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
8 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[2]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
9 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[3]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
10 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[4]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
11 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[6]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
12 0.949 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[9]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
13 0.949 cnt_Z[0]/Q u_colorbar_gen/hsync_r_Z/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.960
14 0.951 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[10]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.962
15 0.953 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[5]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.964
16 0.953 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[8]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.964
17 0.959 cnt_Z[0]/Q u_colorbar_gen/color_cnt_Z[1]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.970
18 0.959 cnt_Z[0]/Q u_colorbar_gen/color_cnt_Z[2]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.970
19 0.959 cnt_Z[0]/Q u_colorbar_gen/color_cnt_Z[4]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.970
20 0.959 cnt_Z[0]/Q u_colorbar_gen/color_cnt_Z[3]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.970
21 0.959 cnt_Z[0]/Q u_colorbar_gen/color_cnt_Z[0]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 0.970
22 1.033 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 0.000 -0.127 1.711
23 1.036 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 0.000 -0.127 1.713
24 1.037 cnt_Z[0]/Q tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET pll_inst/CLKIN.default_clk:[R] pll_inst/CLKOUT.default_gen_clk:[F] 0.000 -0.127 1.715
25 1.061 cnt_Z[0]/Q u_colorbar_gen/pix_cnt_Z[7]/CLEAR pll_inst/CLKIN.default_clk:[R] pll_inst/CLKIN.default_clk:[R] 0.000 0.000 1.072

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 -0.302 0.698 1.000 Low Pulse Width pll_inst/CLKOUT.default_gen_clk tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z
2 0.258 1.258 1.000 High Pulse Width pll_inst/CLKOUT.default_gen_clk tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z
3 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk cnt_Z[2]
4 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk cnt_Z[6]
5 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/color_cnt_Z[7]
6 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/pix_cnt_Z[7]
7 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/line_cnt_Z[2]
8 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/pix_cnt_Z[8]
9 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/color_cnt_Z[8]
10 4.370 5.370 1.000 Low Pulse Width pll_inst/CLKIN.default_clk u_colorbar_gen/pix_cnt_Z[9]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 25

Path1

Path Summary:

Slack -2.709
Data Arrival Time 19.241
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.241 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
16.532 -0.153 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path2

Path Summary:

Slack -2.705
Data Arrival Time 19.237
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.237 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
16.532 -0.153 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path3

Path Summary:

Slack -2.438
Data Arrival Time 18.970
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.970 1.969 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
16.532 -0.153 tSu 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.507%; route: 2.131, 61.769%; tC2Q: 0.232, 6.725%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path4

Path Summary:

Slack -2.434
Data Arrival Time 18.966
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.966 1.965 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
16.532 -0.153 tSu 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.545%; route: 2.127, 61.723%; tC2Q: 0.232, 6.733%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path5

Path Summary:

Slack -2.433
Data Arrival Time 18.965
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.965 1.964 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
16.532 -0.153 tSu 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.551%; route: 2.126, 61.715%; tC2Q: 0.232, 6.734%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path6

Path Summary:

Slack -2.342
Data Arrival Time 6.741
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.741 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
4.399 -0.151 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path7

Path Summary:

Slack -2.337
Data Arrival Time 6.737
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.737 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
4.399 -0.151 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path8

Path Summary:

Slack -2.071
Data Arrival Time 6.470
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.470 1.969 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
4.399 -0.151 tSu 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.507%; route: 2.131, 61.769%; tC2Q: 0.232, 6.725%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path9

Path Summary:

Slack -2.066
Data Arrival Time 6.466
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.466 1.965 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
4.399 -0.151 tSu 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.545%; route: 2.127, 61.723%; tC2Q: 0.232, 6.733%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path10

Path Summary:

Slack -2.066
Data Arrival Time 6.465
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.465 1.964 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
4.399 -0.151 tSu 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.551%; route: 2.126, 61.715%; tC2Q: 0.232, 6.734%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path11

Path Summary:

Slack -1.582
Data Arrival Time 18.235
Data Required Time 16.653
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst2_CLKDIVF
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.033 0.549 tINS RR 53 R27C25[3][A] un11_cnt_cZ/F
18.235 1.202 tNET RR 1 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/RESETN

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
16.683 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst2_CLKDIVF
16.653 -0.030 tSu 1 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF

Path Statistics:

Clock Skew -0.223
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.119, 41.208%; route: 1.364, 50.249%; tC2Q: 0.232, 8.544%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.699, 100.000%

Path12

Path Summary:

Slack -1.518
Data Arrival Time 19.475
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.475 2.131 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.957 -0.168 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.713%; route: 2.706, 68.421%; tC2Q: 0.232, 5.866%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path13

Path Summary:

Slack -1.517
Data Arrival Time 19.474
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.474 2.130 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.957 -0.168 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.718%; route: 2.705, 68.415%; tC2Q: 0.232, 5.867%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path14

Path Summary:

Slack -1.515
Data Arrival Time 19.475
Data Required Time 17.960
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.475 2.131 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.960 -0.165 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.713%; route: 2.706, 68.421%; tC2Q: 0.232, 5.866%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path15

Path Summary:

Slack -1.514
Data Arrival Time 19.471
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.471 2.127 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.957 -0.168 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.739%; route: 2.702, 68.389%; tC2Q: 0.232, 5.872%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path16

Path Summary:

Slack -1.511
Data Arrival Time 19.471
Data Required Time 17.960
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.471 2.127 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.960 -0.165 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.739%; route: 2.702, 68.389%; tC2Q: 0.232, 5.872%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path17

Path Summary:

Slack -1.511
Data Arrival Time 19.471
Data Required Time 17.960
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.326 0.574 tNET FF 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/I1
16.788 0.462 tINS FR 1 R27C28[1][B] u_colorbar_gen/color_cnt_RNI6IUM1_0[6]/F
16.789 0.001 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I1
17.344 0.555 tINS RF 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
19.471 2.127 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.960 -0.165 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.017, 25.739%; route: 2.702, 68.389%; tC2Q: 0.232, 5.872%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path18

Path Summary:

Slack -1.382
Data Arrival Time 19.339
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[9]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/CLK
15.752 0.232 tC2Q RF 5 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/Q
15.908 0.156 tNET FF 1 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/I1
16.478 0.570 tINS FR 3 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/F
16.653 0.175 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I0
17.208 0.555 tINS RF 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
19.339 2.131 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.957 -0.168 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.125, 29.456%; route: 2.462, 64.470%; tC2Q: 0.232, 6.074%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path19

Path Summary:

Slack -1.377
Data Arrival Time 19.333
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[9]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/CLK
15.752 0.232 tC2Q RF 5 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/Q
15.908 0.156 tNET FF 1 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/I1
16.478 0.570 tINS FR 3 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/F
16.653 0.175 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I0
17.208 0.555 tINS RF 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
19.333 2.125 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.957 -0.168 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.125, 29.500%; route: 2.457, 64.416%; tC2Q: 0.232, 6.084%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path20

Path Summary:

Slack -1.269
Data Arrival Time 19.241
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.241 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.972 -0.153 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path21

Path Summary:

Slack -1.265
Data Arrival Time 19.237
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.237 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.972 -0.153 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path22

Path Summary:

Slack -1.215
Data Arrival Time 19.172
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.176 0.424 tNET FF 1 R27C28[2][B] u_colorbar_gen/color_cnt_RNI6V691[7]/I0
16.746 0.570 tINS FR 1 R27C28[2][B] u_colorbar_gen/color_cnt_RNI6V691[7]/F
16.919 0.172 tNET RR 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I1
17.290 0.371 tINS RF 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
19.172 1.883 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.957 -0.168 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 0.941, 25.764%; route: 2.479, 67.884%; tC2Q: 0.232, 6.352%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path23

Path Summary:

Slack -1.212
Data Arrival Time 19.172
Data Required Time 17.960
From u_colorbar_gen/color_cnt_Z[7]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.752 0.232 tC2Q RF 4 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/Q
16.176 0.424 tNET FF 1 R27C28[2][B] u_colorbar_gen/color_cnt_RNI6V691[7]/I0
16.746 0.570 tINS FR 1 R27C28[2][B] u_colorbar_gen/color_cnt_RNI6V691[7]/F
16.919 0.172 tNET RR 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I1
17.290 0.371 tINS RF 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
19.172 1.883 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.960 -0.165 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 0.941, 25.764%; route: 2.479, 67.884%; tC2Q: 0.232, 6.352%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path24

Path Summary:

Slack -1.144
Data Arrival Time 19.101
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[9]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/CLK
15.752 0.232 tC2Q RF 5 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/Q
15.908 0.156 tNET FF 1 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/I1
16.478 0.570 tINS FR 3 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/F
16.653 0.175 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I0
17.208 0.555 tINS RF 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
19.101 1.893 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.957 -0.168 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.125, 31.412%; route: 2.224, 62.110%; tC2Q: 0.232, 6.478%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path25

Path Summary:

Slack -1.144
Data Arrival Time 19.101
Data Required Time 17.957
From u_colorbar_gen/color_cnt_Z[9]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/CLK
15.752 0.232 tC2Q RF 5 R26C28[2][A] u_colorbar_gen/color_cnt_Z[9]/Q
15.908 0.156 tNET FF 1 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/I1
16.478 0.570 tINS FR 3 R26C28[3][B] u_colorbar_gen/color_cnt_RNI5BFR[8]/F
16.653 0.175 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I0
17.208 0.555 tINS RF 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
19.101 1.893 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.957 -0.168 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.125, 31.412%; route: 2.224, 62.110%; tC2Q: 0.232, 6.478%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 25

Path1

Path Summary:

Slack -0.523
Data Arrival Time 3.472
Data Required Time 3.995
From u_colorbar_gen/hsync_r_Z
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C26[1][B] u_colorbar_gen/hsync_r_Z/CLK
2.602 0.202 tC2Q RR 1 R27C26[1][B] u_colorbar_gen/hsync_r_Z/Q
3.472 0.869 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.995 0.095 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.869, 81.148%; tC2Q: 0.202, 18.852%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path2

Path Summary:

Slack -0.401
Data Arrival Time 3.510
Data Required Time 3.911
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.510 0.554 tNET RR 1 R26C31[0][A] tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 R26C31[0][A] tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/CLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z
3.911 0.011 tHld 1 R26C31[0][A] tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 21.171%; route: 0.674, 60.722%; tC2Q: 0.201, 18.108%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path3

Path Summary:

Slack -0.368
Data Arrival Time 3.627
Data Required Time 3.995
From u_colorbar_gen/lv_r_Z
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R29C28[0][B] u_colorbar_gen/lv_r_Z/CLK
2.602 0.202 tC2Q RR 14 R29C28[0][B] u_colorbar_gen/lv_r_Z/Q
3.627 1.025 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.995 0.095 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.025, 83.535%; tC2Q: 0.202, 16.465%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path4

Path Summary:

Slack -0.362
Data Arrival Time 3.621
Data Required Time 3.983
From u_colorbar_gen/vsync_r_Z
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R29C28[0][A] u_colorbar_gen/vsync_r_Z/CLK
2.602 0.202 tC2Q RR 1 R29C28[0][A] u_colorbar_gen/vsync_r_Z/Q
3.621 1.019 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.983 0.083 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.019, 83.453%; tC2Q: 0.202, 16.547%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path5

Path Summary:

Slack -0.087
Data Arrival Time 3.908
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
3.908 0.868 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.995 0.095 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 20.558%; route: 0.997, 66.113%; tC2Q: 0.201, 13.329%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path6

Path Summary:

Slack -0.075
Data Arrival Time 3.908
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
3.908 0.868 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.983 0.083 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 20.558%; route: 0.997, 66.113%; tC2Q: 0.201, 13.329%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path7

Path Summary:

Slack -0.045
Data Arrival Time 3.950
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
3.950 0.847 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.995 0.095 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 15.165%; route: 1.113, 71.800%; tC2Q: 0.202, 13.035%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path8

Path Summary:

Slack -0.043
Data Arrival Time 3.952
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
3.952 0.849 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.995 0.095 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 15.143%; route: 1.115, 71.841%; tC2Q: 0.202, 13.016%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path9

Path Summary:

Slack -0.033
Data Arrival Time 3.950
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][A] u_colorbar_gen/color_cnt_RNI2PLS2_0[10]/F
3.950 0.847 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.983 0.083 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 15.165%; route: 1.113, 71.800%; tC2Q: 0.202, 13.035%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path10

Path Summary:

Slack -0.033
Data Arrival Time 3.950
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
3.950 0.847 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
3.983 0.083 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 15.165%; route: 1.113, 71.800%; tC2Q: 0.202, 13.035%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path11

Path Summary:

Slack 0.057
Data Arrival Time 4.052
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.052 1.012 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.995 0.095 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.766%; route: 1.141, 69.067%; tC2Q: 0.201, 12.168%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path12

Path Summary:

Slack 0.058
Data Arrival Time 4.053
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.053 1.013 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.995 0.095 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.757%; route: 1.142, 69.081%; tC2Q: 0.201, 12.162%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path13

Path Summary:

Slack 0.058
Data Arrival Time 4.112
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.112 1.155 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
4.053 0.153 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.733%; route: 1.275, 74.521%; tC2Q: 0.201, 11.746%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path14

Path Summary:

Slack 0.061
Data Arrival Time 4.114
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.114 1.157 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
4.053 0.153 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.715%; route: 1.277, 74.554%; tC2Q: 0.201, 11.731%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path15

Path Summary:

Slack 0.062
Data Arrival Time 4.115
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.115 1.158 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
4.053 0.153 tHld 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.706%; route: 1.279, 74.571%; tC2Q: 0.201, 11.723%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path16

Path Summary:

Slack 0.068
Data Arrival Time 4.063
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.063 1.023 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.995 0.095 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.646%; route: 1.152, 69.263%; tC2Q: 0.201, 12.090%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path17

Path Summary:

Slack 0.070
Data Arrival Time 4.053
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.053 1.013 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.983 0.083 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.757%; route: 1.142, 69.081%; tC2Q: 0.201, 12.162%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path18

Path Summary:

Slack 0.071
Data Arrival Time 4.055
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.055 1.015 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
3.983 0.083 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.740%; route: 1.143, 69.109%; tC2Q: 0.201, 12.151%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path19

Path Summary:

Slack 0.080
Data Arrival Time 4.063
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.601 0.201 tC2Q RF 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.730 0.128 tNET FF 1 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/I3
3.040 0.310 tINS FR 8 R26C28[3][A] u_colorbar_gen/color_cnt_RNI26UE2[10]/F
4.063 1.023 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.983 0.083 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.310, 18.646%; route: 1.152, 69.263%; tC2Q: 0.201, 12.090%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path20

Path Summary:

Slack 0.136
Data Arrival Time 4.132
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
4.132 1.029 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.995 0.095 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.573%; route: 1.294, 74.760%; tC2Q: 0.202, 11.667%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path21

Path Summary:

Slack 0.136
Data Arrival Time 4.132
Data Required Time 3.995
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
4.132 1.029 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.995 0.095 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.573%; route: 1.294, 74.760%; tC2Q: 0.202, 11.667%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path22

Path Summary:

Slack 0.148
Data Arrival Time 4.132
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
4.132 1.029 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.983 0.083 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.573%; route: 1.294, 74.760%; tC2Q: 0.202, 11.667%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path23

Path Summary:

Slack 0.148
Data Arrival Time 4.132
Data Required Time 3.983
From u_colorbar_gen/color_cnt_Z[11]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/CLK
2.602 0.202 tC2Q RR 4 R26C29[0][A] u_colorbar_gen/color_cnt_Z[11]/Q
2.868 0.266 tNET RR 1 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/I3
3.103 0.235 tINS RR 8 R27C28[3][B] u_colorbar_gen/color_cnt_RNI2PLS2[10]/F
4.132 1.029 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
3.983 0.083 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.573%; route: 1.294, 74.760%; tC2Q: 0.202, 11.667%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path24

Path Summary:

Slack 0.210
Data Arrival Time 4.263
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.263 1.306 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
4.053 0.153 tHld 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 12.616%; route: 1.427, 76.593%; tC2Q: 0.201, 10.791%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path25

Path Summary:

Slack 0.211
Data Arrival Time 4.264
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.264 1.308 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
4.053 0.153 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 12.609%; route: 1.428, 76.607%; tC2Q: 0.201, 10.784%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 25

Path1

Path Summary:

Slack -2.709
Data Arrival Time 19.241
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.241 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
16.532 -0.153 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path2

Path Summary:

Slack -2.705
Data Arrival Time 19.237
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.237 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
16.532 -0.153 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path3

Path Summary:

Slack -2.438
Data Arrival Time 18.970
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.970 1.969 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
16.532 -0.153 tSu 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.507%; route: 2.131, 61.769%; tC2Q: 0.232, 6.725%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path4

Path Summary:

Slack -2.434
Data Arrival Time 18.966
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.966 1.965 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
16.532 -0.153 tSu 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.545%; route: 2.127, 61.723%; tC2Q: 0.232, 6.733%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path5

Path Summary:

Slack -2.433
Data Arrival Time 18.965
Data Required Time 16.532
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.965 1.964 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.085 1.701 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/FCLK
16.685 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
16.532 -0.153 tSu 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew -0.221
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.551%; route: 2.126, 61.715%; tC2Q: 0.232, 6.734%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.701, 100.000%

Path6

Path Summary:

Slack -2.342
Data Arrival Time 6.741
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.741 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
4.399 -0.151 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path7

Path Summary:

Slack -2.337
Data Arrival Time 6.737
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.737 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
4.399 -0.151 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path8

Path Summary:

Slack -2.071
Data Arrival Time 6.470
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.470 1.969 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
4.399 -0.151 tSu 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.507%; route: 2.131, 61.769%; tC2Q: 0.232, 6.725%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path9

Path Summary:

Slack -2.066
Data Arrival Time 6.466
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.466 1.965 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
4.399 -0.151 tSu 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.545%; route: 2.127, 61.723%; tC2Q: 0.232, 6.733%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path10

Path Summary:

Slack -2.066
Data Arrival Time 6.465
Data Required Time 4.399
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
6.465 1.964 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1.786 1.786 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF 6 R10C1 pll_inst/CLKOUT
4.950 2.074 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/FCLK
4.550 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
4.399 -0.151 tSu 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 0.145
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.551%; route: 2.126, 61.715%; tC2Q: 0.232, 6.734%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.074, 100.000%

Path11

Path Summary:

Slack -1.582
Data Arrival Time 18.235
Data Required Time 16.653
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst2_CLKDIVF
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.033 0.549 tINS RR 53 R27C25[3][A] un11_cnt_cZ/F
18.235 1.202 tNET RR 1 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/RESETN

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
16.683 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst2_CLKDIVF
16.653 -0.030 tSu 1 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF

Path Statistics:

Clock Skew -0.223
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.119, 41.208%; route: 1.364, 50.249%; tC2Q: 0.232, 8.544%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.699, 100.000%

Path12

Path Summary:

Slack -1.269
Data Arrival Time 19.241
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.241 2.240 tNET FF 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
17.972 -0.153 tSu 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.213%; route: 2.402, 64.552%; tC2Q: 0.232, 6.235%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path13

Path Summary:

Slack -1.265
Data Arrival Time 19.237
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
19.237 2.235 tNET FF 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
17.972 -0.153 tSu 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 29.246%; route: 2.398, 64.512%; tC2Q: 0.232, 6.242%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path14

Path Summary:

Slack -0.998
Data Arrival Time 18.970
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.970 1.969 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
17.972 -0.153 tSu 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.507%; route: 2.131, 61.769%; tC2Q: 0.232, 6.725%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path15

Path Summary:

Slack -0.994
Data Arrival Time 18.966
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.966 1.965 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
17.972 -0.153 tSu 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.545%; route: 2.127, 61.723%; tC2Q: 0.232, 6.733%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path16

Path Summary:

Slack -0.993
Data Arrival Time 18.965
Data Required Time 17.972
From cnt_Z[4]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
15.752 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
15.913 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
16.483 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
16.484 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
17.001 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
18.965 1.964 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
14.286 14.286 active clock edge time
14.286 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
15.384 1.099 tCL RR 6 R10C1 pll_inst/CLKOUT
17.083 1.699 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
17.324 0.241 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
18.525 1.201 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
18.125 -0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
17.972 -0.153 tSu 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.219
Setup Relationship 1.786
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 31.551%; route: 2.126, 61.715%; tC2Q: 0.232, 6.734%
Required Clock Path Delay cell: 0.241, 7.684%; route: 2.899, 92.316%

Path17

Path Summary:

Slack 9.675
Data Arrival Time 5.609
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[3]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.609 1.108 tNET FF 1 R30C30[0][A] u_colorbar_gen/line_cnt_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R30C30[0][A] u_colorbar_gen/line_cnt_Z[3]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[3]
15.285 -0.035 tSu 1 R30C30[0][A] u_colorbar_gen/line_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 41.976%; route: 1.271, 49.065%; tC2Q: 0.232, 8.959%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path18

Path Summary:

Slack 9.752
Data Arrival Time 5.533
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[8]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.533 1.032 tNET FF 1 R29C31[0][A] u_colorbar_gen/line_cnt_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C31[0][A] u_colorbar_gen/line_cnt_Z[8]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[8]
15.285 -0.035 tSu 1 R29C31[0][A] u_colorbar_gen/line_cnt_Z[8]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 43.257%; route: 1.194, 47.511%; tC2Q: 0.232, 9.232%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path19

Path Summary:

Slack 9.752
Data Arrival Time 5.533
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_fast_Z[8]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.533 1.032 tNET FF 1 R29C31[0][B] u_colorbar_gen/line_cnt_fast_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C31[0][B] u_colorbar_gen/line_cnt_fast_Z[8]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_fast_Z[8]
15.285 -0.035 tSu 1 R29C31[0][B] u_colorbar_gen/line_cnt_fast_Z[8]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 43.257%; route: 1.194, 47.511%; tC2Q: 0.232, 9.232%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path20

Path Summary:

Slack 9.909
Data Arrival Time 5.376
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[2]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.376 0.875 tNET FF 1 R29C30[2][A] u_colorbar_gen/line_cnt_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C30[2][A] u_colorbar_gen/line_cnt_Z[2]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[2]
15.285 -0.035 tSu 1 R29C30[2][A] u_colorbar_gen/line_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.140%; route: 1.037, 44.013%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path21

Path Summary:

Slack 9.909
Data Arrival Time 5.376
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[4]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.376 0.875 tNET FF 1 R29C30[2][B] u_colorbar_gen/line_cnt_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C30[2][B] u_colorbar_gen/line_cnt_Z[4]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[4]
15.285 -0.035 tSu 1 R29C30[2][B] u_colorbar_gen/line_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.140%; route: 1.037, 44.013%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path22

Path Summary:

Slack 9.913
Data Arrival Time 5.372
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[7]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.372 0.870 tNET FF 1 R29C32[0][A] u_colorbar_gen/line_cnt_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C32[0][A] u_colorbar_gen/line_cnt_Z[7]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[7]
15.285 -0.035 tSu 1 R29C32[0][A] u_colorbar_gen/line_cnt_Z[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.221%; route: 1.033, 43.914%; tC2Q: 0.232, 9.865%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path23

Path Summary:

Slack 9.913
Data Arrival Time 5.372
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/line_cnt_Z[9]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.372 0.870 tNET FF 1 R29C32[0][B] u_colorbar_gen/line_cnt_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R29C32[0][B] u_colorbar_gen/line_cnt_Z[9]/CLK
15.320 -0.200 tUnc u_colorbar_gen/line_cnt_Z[9]
15.285 -0.035 tSu 1 R29C32[0][B] u_colorbar_gen/line_cnt_Z[9]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.221%; route: 1.033, 43.914%; tC2Q: 0.232, 9.865%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path24

Path Summary:

Slack 9.918
Data Arrival Time 5.367
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/color_cnt_Z[6]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.367 0.866 tNET FF 1 R26C28[0][B] u_colorbar_gen/color_cnt_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[0][B] u_colorbar_gen/color_cnt_Z[6]/CLK
15.320 -0.200 tUnc u_colorbar_gen/color_cnt_Z[6]
15.285 -0.035 tSu 1 R26C28[0][B] u_colorbar_gen/color_cnt_Z[6]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.308%; route: 1.028, 43.809%; tC2Q: 0.232, 9.884%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Path25

Path Summary:

Slack 9.918
Data Arrival Time 5.367
Data Required Time 15.285
From cnt_Z[4]
To u_colorbar_gen/color_cnt_Z[7]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.683 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
3.020 2.337 tNET RR 1 R27C25[2][B] cnt_Z[4]/CLK
3.252 0.232 tC2Q RF 2 R27C25[2][B] cnt_Z[4]/Q
3.413 0.161 tNET FF 1 R27C25[3][B] un11_cnt_4_cZ/I1
3.983 0.570 tINS FR 1 R27C25[3][B] un11_cnt_4_cZ/F
3.984 0.001 tNET RR 1 R27C25[3][A] un11_cnt_cZ/I3
4.501 0.517 tINS RF 53 R27C25[3][A] un11_cnt_cZ/F
5.367 0.866 tNET FF 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.182 0.683 tINS RR 47 IOL7[A] pix_clk_ibuf/O
15.520 2.337 tNET RR 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]/CLK
15.320 -0.200 tUnc u_colorbar_gen/color_cnt_Z[7]
15.285 -0.035 tSu 1 R26C28[1][A] u_colorbar_gen/color_cnt_Z[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.500
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%
Arrival Data Path Delay cell: 1.087, 46.308%; route: 1.028, 43.809%; tC2Q: 0.232, 9.884%
Required Clock Path Delay cell: 0.683, 22.601%; route: 2.337, 77.399%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 25

Path1

Path Summary:

Slack 0.058
Data Arrival Time 4.112
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.112 1.155 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
4.053 0.153 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.733%; route: 1.275, 74.521%; tC2Q: 0.201, 11.746%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path2

Path Summary:

Slack 0.061
Data Arrival Time 4.114
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.114 1.157 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
4.053 0.153 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.715%; route: 1.277, 74.554%; tC2Q: 0.201, 11.731%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path3

Path Summary:

Slack 0.062
Data Arrival Time 4.115
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.115 1.158 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
4.053 0.153 tHld 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.706%; route: 1.279, 74.571%; tC2Q: 0.201, 11.723%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path4

Path Summary:

Slack 0.210
Data Arrival Time 4.263
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.263 1.306 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z
4.053 0.153 tHld 1 IOT50[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B0_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 12.616%; route: 1.427, 76.593%; tC2Q: 0.201, 10.791%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path5

Path Summary:

Slack 0.211
Data Arrival Time 4.264
Data Required Time 4.053
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
4.264 1.308 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.071 1.071 tCL RR 6 R10C1 pll_inst/CLKOUT
2.391 1.320 tNET RR 5 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
2.598 0.207 tINS RR 6 TOPSIDE[0] tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
3.500 0.902 tNET RR 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z/PCLK
3.900 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z
4.053 0.153 tHld 1 IOT48[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B1_Z

Path Statistics:

Clock Skew 1.100
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 12.609%; route: 1.428, 76.607%; tC2Q: 0.201, 10.784%
Required Clock Path Delay cell: 0.207, 8.536%; route: 2.222, 91.464%

Path6

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[0]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R26C25[0][B] u_colorbar_gen/pix_cnt_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C25[0][B] u_colorbar_gen/pix_cnt_Z[0]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[0]
2.411 0.011 tHld 1 R26C25[0][B] u_colorbar_gen/pix_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path7

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[1]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R26C25[1][A] u_colorbar_gen/pix_cnt_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C25[1][A] u_colorbar_gen/pix_cnt_Z[1]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[1]
2.411 0.011 tHld 1 R26C25[1][A] u_colorbar_gen/pix_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path8

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[2]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R26C25[1][B] u_colorbar_gen/pix_cnt_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C25[1][B] u_colorbar_gen/pix_cnt_Z[2]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[2]
2.411 0.011 tHld 1 R26C25[1][B] u_colorbar_gen/pix_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path9

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[3]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R26C25[2][A] u_colorbar_gen/pix_cnt_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C25[2][A] u_colorbar_gen/pix_cnt_Z[3]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[3]
2.411 0.011 tHld 1 R26C25[2][A] u_colorbar_gen/pix_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path10

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[4]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R26C25[2][B] u_colorbar_gen/pix_cnt_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C25[2][B] u_colorbar_gen/pix_cnt_Z[4]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[4]
2.411 0.011 tHld 1 R26C25[2][B] u_colorbar_gen/pix_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path11

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[6]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R27C26[2][A] u_colorbar_gen/pix_cnt_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C26[2][A] u_colorbar_gen/pix_cnt_Z[6]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[6]
2.411 0.011 tHld 1 R27C26[2][A] u_colorbar_gen/pix_cnt_Z[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path12

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[9]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R27C26[1][A] u_colorbar_gen/pix_cnt_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C26[1][A] u_colorbar_gen/pix_cnt_Z[9]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[9]
2.411 0.011 tHld 1 R27C26[1][A] u_colorbar_gen/pix_cnt_Z[9]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path13

Path Summary:

Slack 0.949
Data Arrival Time 3.360
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/hsync_r_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.360 0.403 tNET RR 1 R27C26[1][B] u_colorbar_gen/hsync_r_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C26[1][B] u_colorbar_gen/hsync_r_Z/CLK
2.400 0.000 tUnc u_colorbar_gen/hsync_r_Z
2.411 0.011 tHld 1 R27C26[1][B] u_colorbar_gen/hsync_r_Z

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.492%; route: 0.524, 54.560%; tC2Q: 0.201, 20.948%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path14

Path Summary:

Slack 0.951
Data Arrival Time 3.362
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[10]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.362 0.406 tNET RR 1 R25C26[0][A] u_colorbar_gen/pix_cnt_Z[10]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R25C26[0][A] u_colorbar_gen/pix_cnt_Z[10]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[10]
2.411 0.011 tHld 1 R25C26[0][A] u_colorbar_gen/pix_cnt_Z[10]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.430%; route: 0.526, 54.675%; tC2Q: 0.201, 20.895%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path15

Path Summary:

Slack 0.953
Data Arrival Time 3.364
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[5]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.364 0.408 tNET RR 1 R26C26[0][A] u_colorbar_gen/pix_cnt_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C26[0][A] u_colorbar_gen/pix_cnt_Z[5]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[5]
2.411 0.011 tHld 1 R26C26[0][A] u_colorbar_gen/pix_cnt_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.383%; route: 0.528, 54.761%; tC2Q: 0.201, 20.856%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path16

Path Summary:

Slack 0.953
Data Arrival Time 3.364
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[8]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.364 0.408 tNET RR 1 R26C26[1][B] u_colorbar_gen/pix_cnt_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C26[1][B] u_colorbar_gen/pix_cnt_Z[8]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[8]
2.411 0.011 tHld 1 R26C26[1][B] u_colorbar_gen/pix_cnt_Z[8]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.383%; route: 0.528, 54.761%; tC2Q: 0.201, 20.856%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path17

Path Summary:

Slack 0.959
Data Arrival Time 3.370
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/color_cnt_Z[1]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.370 0.414 tNET RR 1 R26C27[1][A] u_colorbar_gen/color_cnt_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C27[1][A] u_colorbar_gen/color_cnt_Z[1]/CLK
2.400 0.000 tUnc u_colorbar_gen/color_cnt_Z[1]
2.411 0.011 tHld 1 R26C27[1][A] u_colorbar_gen/color_cnt_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.232%; route: 0.534, 55.041%; tC2Q: 0.201, 20.726%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path18

Path Summary:

Slack 0.959
Data Arrival Time 3.370
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/color_cnt_Z[2]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.370 0.414 tNET RR 1 R26C27[1][B] u_colorbar_gen/color_cnt_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C27[1][B] u_colorbar_gen/color_cnt_Z[2]/CLK
2.400 0.000 tUnc u_colorbar_gen/color_cnt_Z[2]
2.411 0.011 tHld 1 R26C27[1][B] u_colorbar_gen/color_cnt_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.232%; route: 0.534, 55.041%; tC2Q: 0.201, 20.726%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path19

Path Summary:

Slack 0.959
Data Arrival Time 3.370
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/color_cnt_Z[4]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.370 0.414 tNET RR 1 R26C27[2][B] u_colorbar_gen/color_cnt_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C27[2][B] u_colorbar_gen/color_cnt_Z[4]/CLK
2.400 0.000 tUnc u_colorbar_gen/color_cnt_Z[4]
2.411 0.011 tHld 1 R26C27[2][B] u_colorbar_gen/color_cnt_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.232%; route: 0.534, 55.041%; tC2Q: 0.201, 20.726%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path20

Path Summary:

Slack 0.959
Data Arrival Time 3.370
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/color_cnt_Z[3]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.370 0.414 tNET RR 1 R26C27[2][A] u_colorbar_gen/color_cnt_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C27[2][A] u_colorbar_gen/color_cnt_Z[3]/CLK
2.400 0.000 tUnc u_colorbar_gen/color_cnt_Z[3]
2.411 0.011 tHld 1 R26C27[2][A] u_colorbar_gen/color_cnt_Z[3]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.232%; route: 0.534, 55.041%; tC2Q: 0.201, 20.726%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path21

Path Summary:

Slack 0.959
Data Arrival Time 3.370
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/color_cnt_Z[0]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.370 0.414 tNET RR 1 R26C27[0][B] u_colorbar_gen/color_cnt_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R26C27[0][B] u_colorbar_gen/color_cnt_Z[0]/CLK
2.400 0.000 tUnc u_colorbar_gen/color_cnt_Z[0]
2.411 0.011 tHld 1 R26C27[0][B] u_colorbar_gen/color_cnt_Z[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 24.232%; route: 0.534, 55.041%; tC2Q: 0.201, 20.726%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Path22

Path Summary:

Slack 1.033
Data Arrival Time 16.612
Data Required Time 15.578
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.175 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
14.900 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
15.101 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
15.222 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
15.457 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
16.612 1.155 tNET RR 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
13.565 1.064 tCL FF 6 R10C1 pll_inst/CLKOUT
15.027 1.463 tNET FF 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z/FCLK
15.427 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z
15.578 0.151 tHld 1 IOT38[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B3_Z

Path Statistics:

Clock Skew 0.127
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.733%; route: 1.275, 74.521%; tC2Q: 0.201, 11.746%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%

Path23

Path Summary:

Slack 1.036
Data Arrival Time 16.614
Data Required Time 15.578
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.175 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
14.900 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
15.101 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
15.222 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
15.457 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
16.614 1.157 tNET RR 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
13.565 1.064 tCL FF 6 R10C1 pll_inst/CLKOUT
15.027 1.463 tNET FF 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z/FCLK
15.427 0.400 tUnc tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z
15.578 0.151 tHld 1 IOT42[A] tx_inst/LVDS_71_Tx/Inst5_ODDR71B2_Z

Path Statistics:

Clock Skew 0.127
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.715%; route: 1.277, 74.554%; tC2Q: 0.201, 11.731%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%

Path24

Path Summary:

Slack 1.037
Data Arrival Time 16.615
Data Required Time 15.578
From cnt_Z[0]
To tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
13.175 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
14.900 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
15.101 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
15.222 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
15.457 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
16.615 1.158 tNET RR 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.500 12.500 active clock edge time
12.500 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
13.565 1.064 tCL FF 6 R10C1 pll_inst/CLKOUT
15.027 1.463 tNET FF 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z/FCLK
15.427 0.400 tUnc tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z
15.578 0.151 tHld 1 IOT40[A] tx_inst/LVDS_71_Tx/Inst6_ODDR71B_Z

Path Statistics:

Clock Skew 0.127
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 13.706%; route: 1.279, 74.571%; tC2Q: 0.201, 11.723%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%

Path25

Path Summary:

Slack 1.061
Data Arrival Time 3.472
Data Required Time 2.411
From cnt_Z[0]
To u_colorbar_gen/pix_cnt_Z[7]
Launch Clk pll_inst/CLKIN.default_clk:[R]
Latch Clk pll_inst/CLKIN.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R27C25[0][B] cnt_Z[0]/CLK
2.601 0.201 tC2Q RF 2 R27C25[0][B] cnt_Z[0]/Q
2.722 0.120 tNET FF 1 R27C25[3][A] un11_cnt_cZ/I0
2.957 0.235 tINS FR 53 R27C25[3][A] un11_cnt_cZ/F
3.472 0.515 tNET RR 1 R29C27[0][A] u_colorbar_gen/pix_cnt_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKIN.default_clk(clock)
0.000 0.000 tCL RR 1 IOL7[A] pix_clk_ibuf/I
0.675 0.675 tINS RR 47 IOL7[A] pix_clk_ibuf/O
2.400 1.725 tNET RR 1 R29C27[0][A] u_colorbar_gen/pix_cnt_Z[7]/CLK
2.400 0.000 tUnc u_colorbar_gen/pix_cnt_Z[7]
2.411 0.011 tHld 1 R29C27[0][A] u_colorbar_gen/pix_cnt_Z[7]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%
Arrival Data Path Delay cell: 0.235, 21.930%; route: 0.636, 59.312%; tC2Q: 0.201, 18.757%
Required Clock Path Delay cell: 0.675, 28.141%; route: 1.725, 71.859%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: -0.302
Actual Width: 0.698
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKOUT.default_gen_clk
Objects: tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z

Late clock Path:

AT DELAY TYPE RF NODE
1.786 0.000 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.876 1.090 tCL FF pll_inst/CLKOUT
4.896 2.020 tNET FF tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
5.146 0.249 tINS FF tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
6.374 1.228 tNET FF tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.571 0.000 active clock edge time
3.571 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
4.643 1.071 tCL RR pll_inst/CLKOUT
5.963 1.320 tNET RR tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
6.170 0.207 tINS RR tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
7.072 0.902 tNET RR tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/CLK

MPW2

MPW Summary:

Slack: 0.258
Actual Width: 1.258
Required Width: 1.000
Type: High Pulse Width
Clock: pll_inst/CLKOUT.default_gen_clk
Objects: tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
1.099 1.099 tCL RR pll_inst/CLKOUT
2.797 1.699 tNET RR tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
3.038 0.241 tINS RR tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
4.239 1.201 tNET RR tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
1.786 0.000 active clock edge time
1.786 0.000 pll_inst/CLKOUT.default_gen_clk(shadow)
2.850 1.064 tCL FF pll_inst/CLKOUT
4.381 1.531 tNET FF tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/HCLKIN
4.584 0.203 tINS FF tx_inst/LVDS_71_Tx/Inst2_CLKDIVF/CLKOUT
5.497 0.913 tNET FF tx_inst/LVDS_71_Tx/Inst4_FD1S3DX_Z/CLK

MPW3

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: cnt_Z[2]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF cnt_Z[2]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR cnt_Z[2]/CLK

MPW4

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: cnt_Z[6]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF cnt_Z[6]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR cnt_Z[6]/CLK

MPW5

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/color_cnt_Z[7]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/color_cnt_Z[7]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/color_cnt_Z[7]/CLK

MPW6

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/pix_cnt_Z[7]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/pix_cnt_Z[7]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/pix_cnt_Z[7]/CLK

MPW7

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/line_cnt_Z[2]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/line_cnt_Z[2]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/line_cnt_Z[2]/CLK

MPW8

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/pix_cnt_Z[8]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/pix_cnt_Z[8]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/pix_cnt_Z[8]/CLK

MPW9

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/color_cnt_Z[8]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/color_cnt_Z[8]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/color_cnt_Z[8]/CLK

MPW10

MPW Summary:

Slack: 4.370
Actual Width: 5.370
Required Width: 1.000
Type: Low Pulse Width
Clock: pll_inst/CLKIN.default_clk
Objects: u_colorbar_gen/pix_cnt_Z[9]

Late clock Path:

AT DELAY TYPE RF NODE
6.250 0.000 active clock edge time
6.250 0.000 pll_inst/CLKIN.default_clk(clock)
6.250 0.000 tCL FF pix_clk_ibuf/I
6.938 0.688 tINS FF pix_clk_ibuf/O
9.531 2.593 tNET FF u_colorbar_gen/pix_cnt_Z[9]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.500 0.000 active clock edge time
12.500 0.000 pll_inst/CLKIN.default_clk(clock)
12.500 0.000 tCL RR pix_clk_ibuf/I
13.175 0.675 tINS RR pix_clk_ibuf/O
14.900 1.725 tNET RR u_colorbar_gen/pix_cnt_Z[9]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
47 pix_clk_c -2.709 2.593
14 t_DE 0.317 1.888
11 un42_line_cnt_1 6.681 0.945
10 un6_pix_cntlto10_0 9.572 0.949
9 un11_cnt -1.582 1.517
8 color_cnt_RNI2PLS2[10] -1.382 2.131
8 color_cnt_RNI26UE2[10] -1.215 1.883
8 color_cnt_RNI2PLS2_0[10] -1.518 2.131
7 line_cnt[9] 7.402 0.508
7 un5_line_cnt_6 9.198 0.444

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R29C30 0.403
R26C28 0.389
R29C29 0.347
R27C25 0.347
R27C26 0.347
R29C31 0.292
R26C27 0.278
R29C27 0.236
R26C25 0.208
R27C28 0.194

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 5

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 5

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 5

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 5

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command