#### START OF AREA REPORT #####[
Part:			GW2A_18LQFP144-8 (GoWin)

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lvds71_lvds41_top

LVDS_7_to_1_RX

LVDS71RX_1CLK8DATA

bus_sync_7s

bit_align_ctl

word_align_ctl

fifo48b_24b

LVDS41TX_1CLK6DATA_3

LVDS41TX_1CLK6DATA_2

LVDS41TX_1CLK6DATA_1

LVDS41TX_1CLK6DATA_0

--------------------------------------------------------------------------------- ######## Utilization report for Top level view: lvds71_lvds41_top ######## ================================================================================= SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 788 100 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top: 788 (27.37 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------------ LUTS 1556 100 % MUX2_LUT5 289 100 % MUX2_LUT6 55 100 % ALU 65 100 % ====================================================== Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top: 1965 (68.25 % Utilization)
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-------------------------------------------------------------------------- ######## Utilization report for cell: LVDS41TX_1CLK6DATA_0 ######## Instance path: lvds71_lvds41_top.LVDS41TX_1CLK6DATA_0 ========================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 4 0.5080 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_0: 4 (0.14 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 4 0.2570 % ================================================= Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_0: 4 (0.14 % Utilization)
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-------------------------------------------------------------------------- ######## Utilization report for cell: LVDS41TX_1CLK6DATA_1 ######## Instance path: lvds71_lvds41_top.LVDS41TX_1CLK6DATA_1 ========================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 4 0.5080 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_1: 4 (0.14 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 4 0.2570 % ================================================= Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_1: 4 (0.14 % Utilization)
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-------------------------------------------------------------------------- ######## Utilization report for cell: LVDS41TX_1CLK6DATA_2 ######## Instance path: lvds71_lvds41_top.LVDS41TX_1CLK6DATA_2 ========================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 4 0.5080 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_2: 4 (0.14 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 4 0.2570 % ================================================= Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_2: 4 (0.14 % Utilization)
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-------------------------------------------------------------------------- ######## Utilization report for cell: LVDS41TX_1CLK6DATA_3 ######## Instance path: lvds71_lvds41_top.LVDS41TX_1CLK6DATA_3 ========================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 4 0.5080 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_3: 4 (0.14 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 4 0.2570 % ================================================= Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.LVDS41TX_1CLK6DATA_3: 4 (0.14 % Utilization)
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-------------------------------------------------------------------- ######## Utilization report for cell: LVDS_7_to_1_RX ######## Instance path: lvds71_lvds41_top.LVDS_7_to_1_RX ==================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 175 22.2 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.LVDS_7_to_1_RX: 175 (6.08 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 211 13.6 % ALU 65 100 % ================================================= Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.LVDS_7_to_1_RX: 276 (9.59 % Utilization)
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------------------------------------------------------------------------ ######## Utilization report for cell: LVDS71RX_1CLK8DATA ######## Instance path: LVDS_7_to_1_RX.LVDS71RX_1CLK8DATA ======================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 15 1.9 % ====================================================== Total SEQUENTIAL ELEMENTS in the block LVDS_7_to_1_RX.LVDS71RX_1CLK8DATA: 15 (0.52 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 11 0.7070 % ALU 4 6.15 % ================================================= Total COMBINATIONAL LOGIC in the block LVDS_7_to_1_RX.LVDS71RX_1CLK8DATA: 15 (0.52 % Utilization)
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------------------------------------------------------------------- ######## Utilization report for cell: bit_align_ctl ######## Instance path: LVDS_7_to_1_RX.bit_align_ctl =================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 102 12.9 % ====================================================== Total SEQUENTIAL ELEMENTS in the block LVDS_7_to_1_RX.bit_align_ctl: 102 (3.54 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 188 12.1 % ALU 42 64.6 % ================================================= Total COMBINATIONAL LOGIC in the block LVDS_7_to_1_RX.bit_align_ctl: 230 (7.99 % Utilization)
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----------------------------------------------------------------- ######## Utilization report for cell: bus_sync_7s ######## Instance path: LVDS_7_to_1_RX.bus_sync_7s ================================================================= SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 26 3.3 % ====================================================== Total SEQUENTIAL ELEMENTS in the block LVDS_7_to_1_RX.bus_sync_7s: 26 (0.90 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 2 0.1290 % ================================================= Total COMBINATIONAL LOGIC in the block LVDS_7_to_1_RX.bus_sync_7s: 2 (0.07 % Utilization)
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-------------------------------------------------------------------- ######## Utilization report for cell: word_align_ctl ######## Instance path: LVDS_7_to_1_RX.word_align_ctl ==================================================================== SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 4 0.5080 % ====================================================== Total SEQUENTIAL ELEMENTS in the block LVDS_7_to_1_RX.word_align_ctl: 4 (0.14 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------- LUTS 9 0.5780 % ================================================= Total COMBINATIONAL LOGIC in the block LVDS_7_to_1_RX.word_align_ctl: 9 (0.31 % Utilization)
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----------------------------------------------------------------- ######## Utilization report for cell: fifo48b_24b ######## Instance path: lvds71_lvds41_top.fifo48b_24b ================================================================= SEQUENTIAL ELEMENTS Name Total elements Utilization Notes ------------------------------------------------------ REGISTERS 597 75.8 % ====================================================== Total SEQUENTIAL ELEMENTS in the block lvds71_lvds41_top.fifo48b_24b: 597 (20.74 % Utilization)
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COMBINATIONAL LOGIC Name Total elements Utilization Notes ------------------------------------------------------ LUTS 1329 85.4 % MUX2_LUT5 289 100 % MUX2_LUT6 55 100 % ====================================================== Total COMBINATIONAL LOGIC in the block lvds71_lvds41_top.fifo48b_24b: 1673 (58.11 % Utilization)
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##### END OF AREA REPORT #####]