Power Messages

Report Title Gowin Power Analysis Report
Design File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\LVDS71_RX_LVDS41_TX.vm
Physical Constraints File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71_RX_LVDS41_TX.cst
Timing Constraints File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71_RX_LVDS41_TX.sdc
GOWIN Version V1.9.1Beta
Part Number GW2A-LV18LQ144C8/I7
Created Time Fri May 24 16:29:02 2019
Legal Announcement Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 384.792
Quiescent Power (mW) 27.181
Dynamic Power (mW) 357.611

Thermal Information:

Junction Temperature 42.375
Theta JA 45.450
Max Allowed Ambient Temperature 67.511

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 293.961 19.245 313.206
VCCX 2.500 3.254 1.587 12.103
VCCO25 2.500 22.206 1.587 59.483

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 23.016 NA 11.461
IO 78.384 10.445 15.419
PLL 39.540 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW) Routing Dynamic Power(mW)
lvds71_lvds41_top 289.475 62.556(62.556) 226.919(225.094)
lvds71_lvds41_top/U_TX0/ 3.595 0.413(0.000) 3.182(0.000)
lvds71_lvds41_top/U_TX1/ 3.340 0.398(0.000) 2.942(0.000)
lvds71_lvds41_top/U_TX2/ 4.266 0.398(0.000) 3.867(0.000)
lvds71_lvds41_top/U_TX3/ 3.438 0.398(0.000) 3.039(0.000)
lvds71_lvds41_top/rx_inst/ 78.058 47.642(45.792) 30.416(28.472)
lvds71_lvds41_top/rx_inst/bit_aln_ctl_inst/ 14.598 4.183(0.000) 10.415(0.000)
lvds71_lvds41_top/rx_inst/bus_sync_inst/ 1.409 0.131(0.000) 1.279(0.000)
lvds71_lvds41_top/rx_inst/lvds_71_rx/ 57.549 41.396(0.000) 16.153(0.000)
lvds71_lvds41_top/rx_inst/wd_aln_ctl_inst/ 0.707 0.082(0.000) 0.626(0.000)
lvds71_lvds41_top/u0_fifo48b_24b/ 194.953 13.306(0.000) 181.647(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
sclk 74.250 144.852
clkop 148.500 92.779
pll_inst/CLKOUTP.default_gen_clk 148.500 4.450
rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk 378.000 7.365
U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk 74.250 0.171
U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk 74.250 0.171
U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk 74.250 0.171
U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk 74.250 0.171
rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk 108.000 39.540