#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019
#install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
#OS: Windows 8 6.2
#Hostname: GW-SW-041

# Thu May 23 15:10:09 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\bit_align_ctl.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\bus_sync.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\fifo48b_24b.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\lvds_7_to_1_rx.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS41TX_1CLK6DATA.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\lvds71_lvds41_top.v" (library work)
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71RX_1CLK8DATA.v" (library work)
@W:CG1337 : LVDS71RX_1CLK8DATA.v(130) | Net scuba_vhi is not declared.
@I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\word_align_ctl.v" (library work)
Verilog syntax check successful!
File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71RX_1CLK8DATA.v changed - recompiling
Selecting top level module lvds71_lvds41_top
@N:CG364 : gw2a.v(113) | Synthesizing module LUT4 in library work.
Running optimization stage 1 on LUT4 .......
@N:CG364 : gw2a.v(461) | Synthesizing module IVIDEO in library work.
Running optimization stage 1 on IVIDEO .......
@N:CG364 : gw2a.v(1671) | Synthesizing module CLKDIV in library work.
Running optimization stage 1 on CLKDIV .......
@N:CG364 : gw2a.v(1532) | Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N:CG364 : gw2a.v(1608) | Synthesizing module TLVDS_IBUF in library work.
Running optimization stage 1 on TLVDS_IBUF .......
@N:CG364 : LVDS71RX_1CLK8DATA.v(2) | Synthesizing module LVDS71RX_1CLK8DATA in library work.
@W:CG360 : LVDS71RX_1CLK8DATA.v(91) | Removing wire cdiv1, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(96) | Removing wire WBDATO0, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(97) | Removing wire WBDATO1, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(98) | Removing wire WBDATO2, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(99) | Removing wire WBDATO3, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(100) | Removing wire WBDATO4, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(101) | Removing wire WBDATO5, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(102) | Removing wire WBDATO6, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(103) | Removing wire WBDATO7, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(104) | Removing wire WBACK, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(105) | Removing wire DPHSRC, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(106) | Removing wire CLKINTFB, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(107) | Removing wire REFCLK, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(108) | Removing wire INTLOCK, as there is no assignment to it.
@W:CG360 : LVDS71RX_1CLK8DATA.v(115) | Removing wire buf_clkop, as there is no assignment to it.
Running optimization stage 1 on LVDS71RX_1CLK8DATA .......
@N:CG364 : bus_sync.v(1) | Synthesizing module bus_sync in library work.

	DATA_BITS=32'b00000000000000000000000000000111
   Generated name = bus_sync_7s
Running optimization stage 1 on bus_sync_7s .......
@N:CG364 : bit_align_ctl.v(2) | Synthesizing module bit_align_ctl in library work.
@A:CG412 : bit_align_ctl.v(76) | Treating === and !== as == and != -- possible simulation mismatch
@A:CG412 : bit_align_ctl.v(117) | Treating === and !== as == and != -- possible simulation mismatch
Running optimization stage 1 on bit_align_ctl .......
@N:CG364 : word_align_ctl.v(1) | Synthesizing module word_align_ctl in library work.
Running optimization stage 1 on word_align_ctl .......
@N:CG364 : lvds_7_to_1_rx.v(2) | Synthesizing module LVDS_7_to_1_RX in library work.
Running optimization stage 1 on LVDS_7_to_1_RX .......
@N:CG364 : fifo48b_24b.v(2) | Synthesizing module fifo48b_24b in library work.
@W:CG133 : fifo48b_24b.v(13) | Object full_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : fifo48b_24b.v(16) | Object empty_r is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on fifo48b_24b .......
@N:CG364 : gw2a.v(1613) | Synthesizing module TLVDS_OBUF in library work.
Running optimization stage 1 on TLVDS_OBUF .......
@N:CG364 : gw2a.v(492) | Synthesizing module OSER4 in library work.
Running optimization stage 1 on OSER4 .......
@N:CG364 : LVDS41TX_1CLK6DATA.v(3) | Synthesizing module LVDS41TX_1CLK6DATA in library work.
@W:CG360 : LVDS41TX_1CLK6DATA.v(50) | Removing wire cdiv1, as there is no assignment to it.
Running optimization stage 1 on LVDS41TX_1CLK6DATA .......
@N:CG364 : lvds71_lvds41_top.v(2) | Synthesizing module lvds71_lvds41_top in library work.
Running optimization stage 1 on lvds71_lvds41_top .......
Running optimization stage 2 on lvds71_lvds41_top .......
Running optimization stage 2 on LVDS41TX_1CLK6DATA .......
Running optimization stage 2 on OSER4 .......
Running optimization stage 2 on TLVDS_OBUF .......
Running optimization stage 2 on fifo48b_24b .......
@W:CL190 : fifo48b_24b.v(36) | Optimizing register bit wr_ptr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : fifo48b_24b.v(36) | Pruning register bit 0 of wr_ptr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on LVDS_7_to_1_RX .......
Running optimization stage 2 on word_align_ctl .......
Running optimization stage 2 on bit_align_ctl .......
@N:CL201 : bit_align_ctl.v(170) | Trying to extract state machine for register dphase_state.
Extracted state machine for register dphase_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Running optimization stage 2 on bus_sync_7s .......
Running optimization stage 2 on LVDS71RX_1CLK8DATA .......
@N:CL159 : LVDS71RX_1CLK8DATA.v(5) | Input clk_n is unused.
@N:CL159 : LVDS71RX_1CLK8DATA.v(7) | Input init is unused.
Running optimization stage 2 on TLVDS_IBUF .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on IVIDEO .......
Running optimization stage 2 on LUT4 .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 84MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu May 23 15:10:10 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
@N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level
@N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu May 23 15:10:10 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu May 23 15:10:10 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06

@N: :  | Running in 64-bit mode 
File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\synwork\LVDS71_RX_LVDS41_TX_comp.srs changed - recompiling
@N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level
@N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu May 23 15:10:12 2019

###########################################################]


# Thu May 23 15:10:12 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  LVDS71_RX_LVDS41_TX_scck.rpt
Printing clock  summary report in "E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\LVDS71_RX_LVDS41_TX_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 118MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@W:BN132 : lvds71_lvds41_top.v(175) | Removing user instance u3_fifo48b_24b because it is equivalent to instance u2_fifo48b_24b. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lvds71_lvds41_top.v(164) | Removing user instance u2_fifo48b_24b because it is equivalent to instance u1_fifo48b_24b. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lvds71_lvds41_top.v(153) | Removing user instance u1_fifo48b_24b because it is equivalent to instance u0_fifo48b_24b. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
Encoding state machine dphase_state[3:0] (in view: work.bit_align_ctl(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : bit_align_ctl.v(170) | There are no possible illegal states for state machine dphase_state[3:0] (in view: work.bit_align_ctl(verilog)); safe FSM implementation is not required.

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)

@N:MT611 :  | Automatically generated clock LVDS41TX_1CLK6DATA_0|eclkc_inferred_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock LVDS41TX_1CLK6DATA_1|eclkc_inferred_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock LVDS41TX_1CLK6DATA_2|eclkc_inferred_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock LVDS41TX_1CLK6DATA_3|eclkc_inferred_clock is not used and is being removed 


Clock Summary
******************

          Start                                        Requested     Requested     Clock        Clock                      Clock
Level     Clock                                        Frequency     Period        Type         Group                      Load 
--------------------------------------------------------------------------------------------------------------------------------
0 -       LVDS71RX_1CLK8DATA|sclk_inferred_clock       395.2 MHz     2.531         inferred     Autoconstr_clkgroup_5      511  
                                                                                                                                
0 -       lvds71_lvds41_top|RCLK_in                    194.0 MHz     5.154         inferred     Autoconstr_clkgroup_6      151  
                                                                                                                                
0 -       lvds71_lvds41_top|clkop_inferred_clock       357.5 MHz     2.797         inferred     Autoconstr_clkgroup_1      72   
                                                                                                                                
0 -       LVDS71RX_1CLK8DATA|eclk_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_11     9    
                                                                                                                                
0 -       LVDS41TX_1CLK6DATA_0|sclk_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_0      7    
                                                                                                                                
0 -       LVDS41TX_1CLK6DATA_1|sclk_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_2      7    
                                                                                                                                
0 -       LVDS41TX_1CLK6DATA_2|sclk_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_3      7    
                                                                                                                                
0 -       LVDS41TX_1CLK6DATA_3|sclk_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_4      7    
================================================================================================================================



Clock Load Summary
***********************

                                             Clock     Source                                              Clock Pin                                  Non-clock Pin                           Non-clock Pin        
Clock                                        Load      Pin                                                 Seq Example                                Seq Example                             Comb Example         
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
LVDS71RX_1CLK8DATA|sclk_inferred_clock       511       rx_inst.lvds_71_rx.Inst6_CLKDIVC.CLKOUT(CLKDIV)     u0_fifo48b_24b.mem\[0\][7:0].C             -                                       -                    
                                                                                                                                                                                                                   
lvds71_lvds41_top|RCLK_in                    151       RCLK_in(port)                                       rx_inst.pll_lock_sync.C                    rx_inst.lvds_71_rx.Inst8_IDDRX71A.D     -                    
                                                                                                                                                                                                                   
lvds71_lvds41_top|clkop_inferred_clock       72        pll_inst.CLKOUT(PLL)                                U_TX3.Inst5_ODDRX2E5.FCLK                  -                                       U_TX3.eclkd.I[0](and)
                                                                                                                                                                                                                   
LVDS71RX_1CLK8DATA|eclk_inferred_clock       9         rx_inst.lvds_71_rx.eclk.OUT(and)                    rx_inst.lvds_71_rx.Inst8_IDDRX71A.FCLK     -                                       -                    
                                                                                                                                                                                                                   
LVDS41TX_1CLK6DATA_0|sclk_inferred_clock     7         U_TX3.Inst3_CLKDIVC.CLKOUT(CLKDIV)                  U_TX3.Inst6_ODDRX2E.PCLK                   -                                       -                    
                                                                                                                                                                                                                   
LVDS41TX_1CLK6DATA_1|sclk_inferred_clock     7         U_TX2.Inst3_CLKDIVC.CLKOUT(CLKDIV)                  U_TX2.Inst6_ODDRX2E.PCLK                   -                                       -                    
                                                                                                                                                                                                                   
LVDS41TX_1CLK6DATA_2|sclk_inferred_clock     7         U_TX1.Inst3_CLKDIVC.CLKOUT(CLKDIV)                  U_TX1.Inst6_ODDRX2E.PCLK                   -                                       -                    
                                                                                                                                                                                                                   
LVDS41TX_1CLK6DATA_3|sclk_inferred_clock     7         U_TX0.Inst3_CLKDIVC.CLKOUT(CLKDIV)                  U_TX0.Inst6_ODDRX2E.PCLK                   -                                       -                    
===================================================================================================================================================================================================================

@W:MT531 : lvds41tx_1clk6data.v(99) | Found signal identified as System clock which controls 4 sequential elements including U_TX0.Inst6_ODDRX2E.  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. 
@W:MT529 : lvds41tx_1clk6data.v(185) | Found inferred clock LVDS41TX_1CLK6DATA_0|sclk_inferred_clock which controls 7 sequential elements including U_TX3.Inst5_ODDRX2E0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : fifo48b_24b.v(52) | Found inferred clock lvds71_lvds41_top|clkop_inferred_clock which controls 72 sequential elements including u0_fifo48b_24b.rd_ptr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds41tx_1clk6data.v(185) | Found inferred clock LVDS41TX_1CLK6DATA_1|sclk_inferred_clock which controls 7 sequential elements including U_TX2.Inst5_ODDRX2E0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds41tx_1clk6data.v(185) | Found inferred clock LVDS41TX_1CLK6DATA_2|sclk_inferred_clock which controls 7 sequential elements including U_TX1.Inst5_ODDRX2E0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds41tx_1clk6data.v(185) | Found inferred clock LVDS41TX_1CLK6DATA_3|sclk_inferred_clock which controls 7 sequential elements including U_TX0.Inst5_ODDRX2E0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds71rx_1clk8data.v(295) | Found inferred clock LVDS71RX_1CLK8DATA|sclk_inferred_clock which controls 511 sequential elements including rx_inst.lvds_71_rx.Inst7_IDDRX71A0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds71rx_1clk8data.v(321) | Found inferred clock lvds71_lvds41_top|RCLK_in which controls 151 sequential elements including rx_inst.lvds_71_rx.phase_step_vec[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : lvds71rx_1clk8data.v(295) | Found inferred clock LVDS71RX_1CLK8DATA|eclk_inferred_clock which controls 9 sequential elements including rx_inst.lvds_71_rx.Inst7_IDDRX71A0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 150 clock pin(s) of sequential element(s)
15 gated/generated clock tree(s) driving 624 clock pin(s) of sequential element(s)
0 instances converted, 624 sequential instances remain driven by gated/generated clocks

====================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                     
------------------------------------------------------------------------------------------------------------
ClockId_0_15      RCLK_in             Unconstrained_port     150        rx_inst.lvds_71_rx.phase_step_vec[0]
============================================================================================================
========================================================================= Gated/Generated Clocks =========================================================================
Clock Tree ID     Driving Element                             Drive Element Type     Unconverted Fanout     Sample Instance                        Explanation            
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_0       pll_inst.CLKOUT                             PLL                    48                     U_TX3.opensync[3:0]                    Black box on clock path
ClockId_0_1       U_TX3.uclk_eclkd.OUT                        and                    6                      U_TX3.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_2       U_TX3.Inst3_CLKDIVC.CLKOUT                  CLKDIV                 7                      U_TX3.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_3       U_TX3.uclk_eclkc.OUT                        and                    1                      U_TX3.Inst6_ODDRX2E                    Black box on clock path
ClockId_0_4       U_TX2.uclk_eclkd.OUT                        and                    6                      U_TX2.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_5       U_TX2.Inst3_CLKDIVC.CLKOUT                  CLKDIV                 7                      U_TX2.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_6       U_TX2.uclk_eclkc.OUT                        and                    1                      U_TX2.Inst6_ODDRX2E                    Black box on clock path
ClockId_0_7       U_TX1.uclk_eclkd.OUT                        and                    6                      U_TX1.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_8       U_TX1.Inst3_CLKDIVC.CLKOUT                  CLKDIV                 7                      U_TX1.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_9       U_TX1.uclk_eclkc.OUT                        and                    1                      U_TX1.Inst6_ODDRX2E                    Black box on clock path
ClockId_0_10      U_TX0.uclk_eclkd.OUT                        and                    6                      U_TX0.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_11      U_TX0.Inst3_CLKDIVC.CLKOUT                  CLKDIV                 7                      U_TX0.Inst5_ODDRX2E0                   Black box on clock path
ClockId_0_12      U_TX0.uclk_eclkc.OUT                        and                    1                      U_TX0.Inst6_ODDRX2E                    Black box on clock path
ClockId_0_14      rx_inst.lvds_71_rx.Inst6_CLKDIVC.CLKOUT     CLKDIV                 511                    rx_inst.lvds_71_rx.Inst7_IDDRX71A0     Black box on clock path
ClockId_0_16      rx_inst.lvds_71_rx.eclk.OUT                 and                    9                      rx_inst.lvds_71_rx.Inst7_IDDRX71A0     Black box on clock path
==========================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\LVDS71_RX_LVDS41_TX.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 195MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Thu May 23 15:10:14 2019

###########################################################]


# Thu May 23 15:10:14 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-1-Beta1
Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-041

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "0" on instance rx_inst.release_reset. 
@N:FX493 :  | Applying initial value "0000000000000000000" on instance rx_inst.delay_count[18:0]. 
@N:FX493 :  | Applying initial value "00" on instance rx_inst.bus_sync_inst.counter[1:0]. 
@N:FX493 :  | Applying initial value "000" on instance rx_inst.lvds_71_rx.phase_step_vec[2:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB)

@N:MO231 : bit_align_ctl.v(88) | Found counter in view:work.bit_align_ctl(verilog) instance data_change_cnt[7:0] 
@N:MO231 : bit_align_ctl.v(88) | Found counter in view:work.bit_align_ctl(verilog) instance rot_cnt[5:0] 
@N:MO231 : bit_align_ctl.v(52) | Found counter in view:work.bit_align_ctl(verilog) instance dphase_cnt[19:0] 
@N:MO231 : bit_align_ctl.v(88) | Found counter in view:work.bit_align_ctl(verilog) instance data_stable_cnt[7:0] 
@N:BN362 : bit_align_ctl.v(88) | Removing sequential instance dphase[3] (in view: work.bit_align_ctl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 200MB)


Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 224MB peak: 225MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 226MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 226MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 216MB peak: 226MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 215MB peak: 226MB)


Finished preparing to map (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 215MB peak: 226MB)


Finished technology mapping (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:15s; Memory used current: 232MB peak: 235MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:16s		    -2.35ns		1508 /       699
   2		0h:00m:16s		    -2.34ns		1501 /       699
   3		0h:00m:17s		    -2.51ns		1506 /       699
   4		0h:00m:17s		    -2.37ns		1507 /       699
   5		0h:00m:17s		    -2.37ns		1507 /       699
   6		0h:00m:18s		    -2.64ns		1507 /       699
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[1] (in view: work.lvds71_lvds41_top(verilog)) with 262 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[0] (in view: work.lvds71_lvds41_top(verilog)) with 281 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[3] (in view: work.lvds71_lvds41_top(verilog)) with 179 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[5] (in view: work.lvds71_lvds41_top(verilog)) with 232 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[2] (in view: work.lvds71_lvds41_top(verilog)) with 183 loads 3 times to improve timing.
@N:FX271 : lvds_7_to_1_rx.v(140) | Replicating instance rx_inst.pll_lock_sync (in view: work.lvds71_lvds41_top(verilog)) with 41 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[4] (in view: work.lvds71_lvds41_top(verilog)) with 150 loads 3 times to improve timing.
@N:FX271 : bit_align_ctl.v(52) | Replicating instance rx_inst.bit_aln_ctl_inst.data_change_cnt_en (in view: work.lvds71_lvds41_top(verilog)) with 19 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[1] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[0] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[3] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[6] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[2] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[4] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : bus_sync.v(37) | Replicating instance rx_inst.bus_sync_inst.datao[5] (in view: work.lvds71_lvds41_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : fifo48b_24b.v(36) | Replicating instance u0_fifo48b_24b.wr_ptr[1] (in view: work.lvds71_lvds41_top(verilog)) with 109 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(36) | Replicating instance u0_fifo48b_24b.wr_ptr[2] (in view: work.lvds71_lvds41_top(verilog)) with 47 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(36) | Replicating instance u0_fifo48b_24b.wr_ptr[4] (in view: work.lvds71_lvds41_top(verilog)) with 69 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(36) | Replicating instance u0_fifo48b_24b.wr_ptr[3] (in view: work.lvds71_lvds41_top(verilog)) with 62 loads 3 times to improve timing.
Timing driven replication report
Added 41 Registers via timing driven replication
Added 31 LUTs via timing driven replication

   7		0h:00m:19s		    -1.54ns		1538 /       740
   8		0h:00m:20s		    -1.85ns		1540 /       740
   9		0h:00m:20s		    -1.85ns		1547 /       740
  10		0h:00m:20s		    -1.85ns		1547 /       740
  11		0h:00m:20s		    -1.85ns		1547 /       740
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[0] (in view: work.lvds71_lvds41_top(verilog)) with 60 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_0_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 70 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[1] (in view: work.lvds71_lvds41_top(verilog)) with 64 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[3] (in view: work.lvds71_lvds41_top(verilog)) with 41 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[5] (in view: work.lvds71_lvds41_top(verilog)) with 53 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[2] (in view: work.lvds71_lvds41_top(verilog)) with 41 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_fast[4] (in view: work.lvds71_lvds41_top(verilog)) with 34 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_3_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 44 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_2_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 44 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_5_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 56 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_1_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 66 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_3_rep2 (in view: work.lvds71_lvds41_top(verilog)) with 47 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr[1] (in view: work.lvds71_lvds41_top(verilog)) with 82 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_4_rep1 (in view: work.lvds71_lvds41_top(verilog)) with 37 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_0_rep2 (in view: work.lvds71_lvds41_top(verilog)) with 74 loads 3 times to improve timing.
@N:FX271 : fifo48b_24b.v(52) | Replicating instance u0_fifo48b_24b.rd_ptr_5_rep2 (in view: work.lvds71_lvds41_top(verilog)) with 62 loads 3 times to improve timing.
Timing driven replication report
Added 48 Registers via timing driven replication
Added 48 LUTs via timing driven replication


  12		0h:00m:20s		    -1.54ns		1590 /       788
  13		0h:00m:20s		    -1.54ns		1590 /       788
  14		0h:00m:21s		    -1.55ns		1591 /       788
  15		0h:00m:21s		    -1.55ns		1592 /       788

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:21s; Memory used current: 237MB peak: 238MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@W:MT453 :  | clock period is too long for clock lvds71_lvds41_top|clkop_inferred_clock, changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock LVDS71RX_1CLK8DATA|sclk_inferred_clock, changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock lvds71_lvds41_top|RCLK_in, changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:21s; Memory used current: 237MB peak: 238MB)


Start Writing Netlists (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:22s; Memory used current: 162MB peak: 238MB)

Writing Analyst data base E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\synwork\LVDS71_RX_LVDS41_TX_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:22s; Memory used current: 235MB peak: 238MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:24s; Memory used current: 236MB peak: 238MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:24s; Memory used current: 234MB peak: 238MB)


Start final timing analysis (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:25s; Memory used current: 234MB peak: 238MB)

@W:MT246 : lvds71_lvds41_top.v(250) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : lvds41tx_1clk6data.v(203) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_0|sclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX3.sclk. 
@W:MT420 :  | Found inferred clock lvds71_lvds41_top|clkop_inferred_clock with period 5.61ns. Please declare a user-defined clock on net clkop. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_1|sclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX2.sclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_2|sclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX1.sclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_3|sclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX0.sclk. 
@W:MT420 :  | Found inferred clock LVDS71RX_1CLK8DATA|sclk_inferred_clock with period 2.90ns. Please declare a user-defined clock on net rx_inst.lvds_71_rx.sclk. 
@W:MT420 :  | Found inferred clock lvds71_lvds41_top|RCLK_in with period 3.87ns. Please declare a user-defined clock on port RCLK_in. 
@W:MT420 :  | Found inferred clock LVDS71RX_1CLK8DATA|eclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net rx_inst.lvds_71_rx.eclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_3|eclkc_i_uclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX0.eclkc_i_uclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_2|eclkc_i_uclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX1.eclkc_i_uclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_1|eclkc_i_uclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX2.eclkc_i_uclk. 
@W:MT420 :  | Found inferred clock LVDS41TX_1CLK6DATA_0|eclkc_i_uclk_inferred_clock with period 6.67ns. Please declare a user-defined clock on net U_TX3.eclkc_i_uclk. 


##### START OF TIMING REPORT #####[
# Timing report written on Thu May 23 15:10:42 2019
#


Top view:               lvds71_lvds41_top
Requested Frequency:    150.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.989

                                                     Requested     Estimated     Requested     Estimated                Clock        Clock                 
Starting Clock                                       Frequency     Frequency     Period        Period        Slack      Type         Group                 
-----------------------------------------------------------------------------------------------------------------------------------------------------------
LVDS41TX_1CLK6DATA_0|eclkc_i_uclk_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_10
LVDS41TX_1CLK6DATA_0|sclk_inferred_clock             150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_0 
LVDS41TX_1CLK6DATA_1|eclkc_i_uclk_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_9 
LVDS41TX_1CLK6DATA_1|sclk_inferred_clock             150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_2 
LVDS41TX_1CLK6DATA_2|eclkc_i_uclk_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_8 
LVDS41TX_1CLK6DATA_2|sclk_inferred_clock             150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_3 
LVDS41TX_1CLK6DATA_3|eclkc_i_uclk_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_7 
LVDS41TX_1CLK6DATA_3|sclk_inferred_clock             150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_4 
LVDS71RX_1CLK8DATA|eclk_inferred_clock               150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_11
LVDS71RX_1CLK8DATA|sclk_inferred_clock               345.0 MHz     293.2 MHz     2.899         3.410         -0.512     inferred     Autoconstr_clkgroup_5 
lvds71_lvds41_top|RCLK_in                            258.7 MHz     219.9 MHz     3.866         4.548         -0.682     inferred     Autoconstr_clkgroup_6 
lvds71_lvds41_top|clkop_inferred_clock               178.4 MHz     151.6 MHz     5.606         6.596         -0.989     inferred     Autoconstr_clkgroup_1 
System                                               539.9 MHz     458.9 MHz     1.852         2.179         -0.327     system       system_clkgroup       
===========================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                Ending                                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                  System                                    |  1.852       -0.327  |  No paths    -      |  No paths    -      |  No paths    -    
System                                  lvds71_lvds41_top|clkop_inferred_clock    |  5.606       3.926   |  No paths    -      |  No paths    -      |  No paths    -    
System                                  LVDS71RX_1CLK8DATA|sclk_inferred_clock    |  2.899       2.303   |  No paths    -      |  No paths    -      |  No paths    -    
System                                  lvds71_lvds41_top|RCLK_in                 |  3.866       1.600   |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  System                                    |  5.606       2.639   |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  LVDS41TX_1CLK6DATA_0|sclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  lvds71_lvds41_top|clkop_inferred_clock    |  5.606       -0.989  |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  LVDS41TX_1CLK6DATA_1|sclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  LVDS41TX_1CLK6DATA_2|sclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|clkop_inferred_clock  LVDS41TX_1CLK6DATA_3|sclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
LVDS71RX_1CLK8DATA|sclk_inferred_clock  System                                    |  2.899       2.121   |  No paths    -      |  No paths    -      |  No paths    -    
LVDS71RX_1CLK8DATA|sclk_inferred_clock  lvds71_lvds41_top|clkop_inferred_clock    |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
LVDS71RX_1CLK8DATA|sclk_inferred_clock  LVDS71RX_1CLK8DATA|sclk_inferred_clock    |  2.899       -0.512  |  No paths    -      |  No paths    -      |  No paths    -    
LVDS71RX_1CLK8DATA|sclk_inferred_clock  lvds71_lvds41_top|RCLK_in                 |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
LVDS71RX_1CLK8DATA|sclk_inferred_clock  LVDS71RX_1CLK8DATA|eclk_inferred_clock    |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|RCLK_in               System                                    |  3.866       2.844   |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|RCLK_in               LVDS71RX_1CLK8DATA|sclk_inferred_clock    |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
lvds71_lvds41_top|RCLK_in               lvds71_lvds41_top|RCLK_in                 |  3.866       -0.682  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: LVDS71RX_1CLK8DATA|sclk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                                       Arrival           
Instance                             Reference                                  Type     Pin     Net                Time        Slack 
                                     Clock                                                                                            
--------------------------------------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr[5]             LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr[5]          0.243       -0.512
u0_fifo48b_24b.wr_ptr_fast[1]        LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr_fast[1]     0.243       -0.413
u0_fifo48b_24b.wr_ptr[6]             LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr[6]          0.243       -0.411
rx_inst.wd_aln_ctl_inst.count[1]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       count[1]           0.243       -0.387
rx_inst.wd_aln_ctl_inst.count[0]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       CO0                0.243       -0.366
u0_fifo48b_24b.wr_ptr_fast[2]        LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr_fast[2]     0.243       -0.312
u0_fifo48b_24b.wr_ptr_fast[3]        LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr_fast[3]     0.243       -0.303
u0_fifo48b_24b.wr_ptr[7]             LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr[7]          0.243       -0.295
rx_inst.wd_aln_ctl_inst.count[2]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       count[2]           0.243       -0.279
u0_fifo48b_24b.wr_ptr_fast[4]        LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC     Q       wr_ptr_fast[4]     0.243       -0.273
======================================================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                                          Required           
Instance                       Reference                                  Type      Pin     Net                  Time         Slack 
                               Clock                                                                                                
------------------------------------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr[6]       LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFC      D       un22_wr_ptr_0[6]     2.838        -0.512
u0_fifo48b_24b.mem\[4\][0]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][1]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][2]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][3]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][4]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][5]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][6]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[4\][7]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
u0_fifo48b_24b.mem\[5\][0]     LVDS71RX_1CLK8DATA|sclk_inferred_clock     DFFCE     CE      N_21                 2.838        -0.413
====================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      2.899
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.838

    - Propagation time:                      3.349
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.512

    Number of logic level(s):                3
    Starting point:                          u0_fifo48b_24b.wr_ptr[5] / Q
    Ending point:                            u0_fifo48b_24b.wr_ptr[6] / D
    The start point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                    Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr[5]                DFFC     Q        Out     0.243     0.243       -         
wr_ptr[5]                               Net      -        -       0.657     -           26        
u0_fifo48b_24b.un22_wr_ptr_0_1_1[6]     LUT4     I0       In      -         0.900       -         
u0_fifo48b_24b.un22_wr_ptr_0_1_1[6]     LUT4     F        Out     0.549     1.449       -         
un22_wr_ptr_0_1_1[6]                    Net      -        -       0.401     -           1         
u0_fifo48b_24b.un22_wr_ptr_0_1_0[6]     LUT4     I0       In      -         1.850       -         
u0_fifo48b_24b.un22_wr_ptr_0_1_0[6]     LUT4     F        Out     0.549     2.399       -         
un22_wr_ptr_0_1_0[6]                    Net      -        -       0.401     -           1         
u0_fifo48b_24b.un22_wr_ptr_0[6]         LUT4     I0       In      -         2.800       -         
u0_fifo48b_24b.un22_wr_ptr_0[6]         LUT4     F        Out     0.549     3.349       -         
un22_wr_ptr_0[6]                        Net      -        -       0.000     -           1         
u0_fifo48b_24b.wr_ptr[6]                DFFC     D        In      -         3.349       -         
==================================================================================================
Total path delay (propagation time + setup) of 3.410 is 1.951(57.2%) logic and 1.459(42.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.899
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.838

    - Propagation time:                      3.251
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.413

    Number of logic level(s):                2
    Starting point:                          u0_fifo48b_24b.wr_ptr_fast[1] / Q
    Ending point:                            u0_fifo48b_24b.mem\[52\][0] / CE
    The start point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr_fast[1]                  DFFC      Q        Out     0.243     0.243       -         
wr_ptr_fast[1]                                 Net       -        -       0.657     -           21        
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2     LUT2      I0       In      -         0.900       -         
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2     LUT2      F        Out     0.549     1.449       -         
N_386                                          Net       -        -       0.657     -           23        
u0_fifo48b_24b.m27_0_a2                        LUT4      I0       In      -         2.106       -         
u0_fifo48b_24b.m27_0_a2                        LUT4      F        Out     0.549     2.655       -         
N_28                                           Net       -        -       0.596     -           16        
u0_fifo48b_24b.mem\[52\][0]                    DFFCE     CE       In      -         3.251       -         
==========================================================================================================
Total path delay (propagation time + setup) of 3.312 is 1.402(42.3%) logic and 1.910(57.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.899
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.838

    - Propagation time:                      3.251
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.413

    Number of logic level(s):                2
    Starting point:                          u0_fifo48b_24b.wr_ptr_fast[1] / Q
    Ending point:                            u0_fifo48b_24b.mem\[4\][0] / CE
    The start point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr_fast[1]                  DFFC      Q        Out     0.243     0.243       -         
wr_ptr_fast[1]                                 Net       -        -       0.657     -           21        
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2     LUT2      I0       In      -         0.900       -         
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2     LUT2      F        Out     0.549     1.449       -         
N_386                                          Net       -        -       0.657     -           23        
u0_fifo48b_24b.mem\[4\]_4_sqmuxa_i_0_0_a2      LUT4      I0       In      -         2.106       -         
u0_fifo48b_24b.mem\[4\]_4_sqmuxa_i_0_0_a2      LUT4      F        Out     0.549     2.655       -         
N_21                                           Net       -        -       0.596     -           16        
u0_fifo48b_24b.mem\[4\][0]                     DFFCE     CE       In      -         3.251       -         
==========================================================================================================
Total path delay (propagation time + setup) of 3.312 is 1.402(42.3%) logic and 1.910(57.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.899
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.838

    - Propagation time:                      3.251
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.413

    Number of logic level(s):                2
    Starting point:                          u0_fifo48b_24b.wr_ptr_fast[1] / Q
    Ending point:                            u0_fifo48b_24b.mem\[44\][0] / CE
    The start point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                            Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr_fast[1]                   DFFC      Q        Out     0.243     0.243       -         
wr_ptr_fast[1]                                  Net       -        -       0.657     -           21        
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2      LUT2      I0       In      -         0.900       -         
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2      LUT2      F        Out     0.549     1.449       -         
N_386                                           Net       -        -       0.657     -           23        
u0_fifo48b_24b.mem\[44\]_4_sqmuxa_i_a2_0_a2     LUT4      I0       In      -         2.106       -         
u0_fifo48b_24b.mem\[44\]_4_sqmuxa_i_a2_0_a2     LUT4      F        Out     0.549     2.655       -         
N_121                                           Net       -        -       0.596     -           16        
u0_fifo48b_24b.mem\[44\][0]                     DFFCE     CE       In      -         3.251       -         
===========================================================================================================
Total path delay (propagation time + setup) of 3.312 is 1.402(42.3%) logic and 1.910(57.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.899
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.838

    - Propagation time:                      3.251
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.413

    Number of logic level(s):                2
    Starting point:                          u0_fifo48b_24b.wr_ptr_fast[1] / Q
    Ending point:                            u0_fifo48b_24b.mem\[12\][0] / CE
    The start point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            LVDS71RX_1CLK8DATA|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                            Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.wr_ptr_fast[1]                   DFFC      Q        Out     0.243     0.243       -         
wr_ptr_fast[1]                                  Net       -        -       0.657     -           21        
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2      LUT2      I0       In      -         0.900       -         
u0_fifo48b_24b.mem\[34\]_4_sqmuxa_i_0_0_o2      LUT2      F        Out     0.549     1.449       -         
N_386                                           Net       -        -       0.657     -           23        
u0_fifo48b_24b.mem\[12\]_4_sqmuxa_i_a2_0_a2     LUT4      I0       In      -         2.106       -         
u0_fifo48b_24b.mem\[12\]_4_sqmuxa_i_a2_0_a2     LUT4      F        Out     0.549     2.655       -         
N_116                                           Net       -        -       0.596     -           16        
u0_fifo48b_24b.mem\[12\][0]                     DFFCE     CE       In      -         3.251       -         
===========================================================================================================
Total path delay (propagation time + setup) of 3.312 is 1.402(42.3%) logic and 1.910(57.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: lvds71_lvds41_top|RCLK_in
====================================



Starting Points with Worst Slack
********************************

                                               Starting                                                              Arrival           
Instance                                       Reference                     Type      Pin     Net                   Time        Slack 
                                               Clock                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[1]     lvds71_lvds41_top|RCLK_in     DFFCE     Q       rxclk_word_buf[1]     0.243       -0.682
rx_inst.bus_sync_inst.datao_fast[2]            lvds71_lvds41_top|RCLK_in     DFFE      Q       datao_fast[2]         0.243       -0.661
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[0]     lvds71_lvds41_top|RCLK_in     DFFCE     Q       rxclk_word_buf[0]     0.243       -0.661
rx_inst.bit_aln_ctl_inst.dphase_state[1]       lvds71_lvds41_top|RCLK_in     DFFCE     Q       dphase_state[1]       0.243       -0.644
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[2]     lvds71_lvds41_top|RCLK_in     DFFCE     Q       rxclk_word_buf[2]     0.243       -0.640
rx_inst.bus_sync_inst.datao_fast[0]            lvds71_lvds41_top|RCLK_in     DFFE      Q       datao_fast[0]         0.243       -0.574
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[6]     lvds71_lvds41_top|RCLK_in     DFFCE     Q       rxclk_word_buf[6]     0.243       -0.574
rx_inst.bit_aln_ctl_inst.unst_to_st_num[1]     lvds71_lvds41_top|RCLK_in     DFFC      Q       unst_to_st_num[1]     0.243       -0.574
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[5]     lvds71_lvds41_top|RCLK_in     DFFCE     Q       rxclk_word_buf[5]     0.243       -0.553
rx_inst.bit_aln_ctl_inst.unst_to_st_num[0]     lvds71_lvds41_top|RCLK_in     DFFC      Q       unst_to_st_num[0]     0.243       -0.553
=======================================================================================================================================


Ending Points with Worst Slack
******************************

                                               Starting                                                                Required           
Instance                                       Reference                     Type      Pin     Net                     Time         Slack 
                                               Clock                                                                                      
------------------------------------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.data_unstable         lvds71_lvds41_top|RCLK_in     DFFCE     D       data_unstable_3         3.805        -0.682
rx_inst.bit_aln_ctl_inst.stable_bit_num[3]     lvds71_lvds41_top|RCLK_in     DFFC      D       stable_bit_num_9[3]     3.805        -0.644
rx_inst.bit_aln_ctl_inst.dphase_cnt[19]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[19]        3.805        -0.506
rx_inst.bit_aln_ctl_inst.stable_bit_num[1]     lvds71_lvds41_top|RCLK_in     DFFC      D       stable_bit_num_9[1]     3.805        -0.483
rx_inst.bit_aln_ctl_inst.stable_bit_num[2]     lvds71_lvds41_top|RCLK_in     DFFC      D       stable_bit_num_9[2]     3.805        -0.483
rx_inst.bit_aln_ctl_inst.dphase_cnt[18]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[18]        3.805        -0.471
rx_inst.bit_aln_ctl_inst.dphase_cnt[17]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[17]        3.805        -0.436
rx_inst.bit_aln_ctl_inst.dphase_cnt[16]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[16]        3.805        -0.401
rx_inst.bit_aln_ctl_inst.dphase_cnt[15]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[15]        3.805        -0.366
rx_inst.bit_aln_ctl_inst.dphase_cnt[14]        lvds71_lvds41_top|RCLK_in     DFFCE     D       dphase_cnt_s[14]        3.805        -0.331
==========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      3.866
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.805

    - Propagation time:                      4.487
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.682

    Number of logic level(s):                4
    Starting point:                          rx_inst.bit_aln_ctl_inst.rxclk_word_buf[1] / Q
    Ending point:                            rx_inst.bit_aln_ctl_inst.data_unstable / D
    The start point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[1]          DFFCE     Q        Out     0.243     0.243       -         
rxclk_word_buf[1]                                   Net       -        -       0.535     -           1         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE_0       LUT4      I1       In      -         0.778       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE_0       LUT4      F        Out     0.570     1.348       -         
un1_data_change_NE_0                                Net       -        -       0.535     -           3         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      I1       In      -         1.883       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      F        Out     0.570     2.453       -         
data_change                                         Net       -        -       0.535     -           10        
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      I0       In      -         2.988       -         
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      F        Out     0.549     3.537       -         
N_287                                               Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      I0       In      -         3.938       -         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      F        Out     0.549     4.487       -         
data_unstable_3                                     Net       -        -       0.000     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable              DFFCE     D        In      -         4.487       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.548 is 2.542(55.9%) logic and 2.006(44.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      3.866
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.805

    - Propagation time:                      4.466
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.661

    Number of logic level(s):                4
    Starting point:                          rx_inst.bus_sync_inst.datao_fast[2] / Q
    Ending point:                            rx_inst.bit_aln_ctl_inst.data_unstable / D
    The start point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
rx_inst.bus_sync_inst.datao_fast[2]                 DFFE      Q        Out     0.243     0.243       -         
datao_fast[2]                                       Net       -        -       0.535     -           1         
rx_inst.bit_aln_ctl_inst.un1_data_change_2          LUT2      I1       In      -         0.778       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_2          LUT2      F        Out     0.570     1.348       -         
un1_data_change_2                                   Net       -        -       0.535     -           3         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      I0       In      -         1.883       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      F        Out     0.549     2.432       -         
data_change                                         Net       -        -       0.535     -           10        
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      I0       In      -         2.967       -         
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      F        Out     0.549     3.516       -         
N_287                                               Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      I0       In      -         3.917       -         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      F        Out     0.549     4.466       -         
data_unstable_3                                     Net       -        -       0.000     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable              DFFCE     D        In      -         4.466       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.527 is 2.521(55.7%) logic and 2.006(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.866
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.805

    - Propagation time:                      4.466
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.661

    Number of logic level(s):                4
    Starting point:                          rx_inst.bit_aln_ctl_inst.rxclk_word_buf[0] / Q
    Ending point:                            rx_inst.bit_aln_ctl_inst.data_unstable / D
    The start point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[0]          DFFCE     Q        Out     0.243     0.243       -         
rxclk_word_buf[0]                                   Net       -        -       0.535     -           1         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE_0       LUT4      I0       In      -         0.778       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE_0       LUT4      F        Out     0.549     1.327       -         
un1_data_change_NE_0                                Net       -        -       0.535     -           3         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      I1       In      -         1.862       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      F        Out     0.570     2.432       -         
data_change                                         Net       -        -       0.535     -           10        
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      I0       In      -         2.967       -         
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      F        Out     0.549     3.516       -         
N_287                                               Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      I0       In      -         3.917       -         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      F        Out     0.549     4.466       -         
data_unstable_3                                     Net       -        -       0.000     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable              DFFCE     D        In      -         4.466       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.527 is 2.521(55.7%) logic and 2.006(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.866
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.805

    - Propagation time:                      4.449
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.644

    Number of logic level(s):                4
    Starting point:                          rx_inst.bit_aln_ctl_inst.dphase_state[1] / Q
    Ending point:                            rx_inst.bit_aln_ctl_inst.stable_bit_num[3] / D
    The start point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.dphase_state[1]          DFFCE     Q        Out     0.243     0.243       -         
dphase_state[1]                                   Net       -        -       0.718     -           32        
rx_inst.bit_aln_ctl_inst.judge_cnt_RNII3BH[3]     LUT2      I0       In      -         0.961       -         
rx_inst.bit_aln_ctl_inst.judge_cnt_RNII3BH[3]     LUT2      F        Out     0.549     1.510       -         
stable_N_3_mux_0                                  Net       -        -       0.535     -           3         
rx_inst.bit_aln_ctl_inst.stable_m3_1              LUT4      I1       In      -         2.045       -         
rx_inst.bit_aln_ctl_inst.stable_m3_1              LUT4      F        Out     0.570     2.615       -         
stable_N_4                                        Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.stable_m5                LUT4      I1       In      -         3.016       -         
rx_inst.bit_aln_ctl_inst.stable_m5                LUT4      F        Out     0.570     3.586       -         
stable_N_7                                        Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.stable_m9                LUT4      I2       In      -         3.987       -         
rx_inst.bit_aln_ctl_inst.stable_m9                LUT4      F        Out     0.462     4.449       -         
stable_bit_num_9[3]                               Net       -        -       0.000     -           1         
rx_inst.bit_aln_ctl_inst.stable_bit_num[3]        DFFC      D        In      -         4.449       -         
=============================================================================================================
Total path delay (propagation time + setup) of 4.510 is 2.455(54.4%) logic and 2.055(45.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.866
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.805

    - Propagation time:                      4.445
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.640

    Number of logic level(s):                4
    Starting point:                          rx_inst.bit_aln_ctl_inst.rxclk_word_buf[2] / Q
    Ending point:                            rx_inst.bit_aln_ctl_inst.data_unstable / D
    The start point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|RCLK_in [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
rx_inst.bit_aln_ctl_inst.rxclk_word_buf[2]          DFFCE     Q        Out     0.243     0.243       -         
rxclk_word_buf[2]                                   Net       -        -       0.535     -           1         
rx_inst.bit_aln_ctl_inst.un1_data_change_2          LUT2      I0       In      -         0.778       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_2          LUT2      F        Out     0.549     1.327       -         
un1_data_change_2                                   Net       -        -       0.535     -           3         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      I0       In      -         1.862       -         
rx_inst.bit_aln_ctl_inst.un1_data_change_NE         LUT4      F        Out     0.549     2.411       -         
data_change                                         Net       -        -       0.535     -           10        
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      I0       In      -         2.946       -         
rx_inst.bit_aln_ctl_inst.data_m1_0_a2               LUT3      F        Out     0.549     3.495       -         
N_287                                               Net       -        -       0.401     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      I0       In      -         3.896       -         
rx_inst.bit_aln_ctl_inst.data_unstable_3_f0_0_0     LUT4      F        Out     0.549     4.445       -         
data_unstable_3                                     Net       -        -       0.000     -           1         
rx_inst.bit_aln_ctl_inst.data_unstable              DFFCE     D        In      -         4.445       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.506 is 2.500(55.5%) logic and 2.006(44.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: lvds71_lvds41_top|clkop_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                       Starting                                                                            Arrival           
Instance                               Reference                                  Type     Pin     Net                     Time        Slack 
                                       Clock                                                                                                 
---------------------------------------------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_fast_fast[3]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_fast[3]     0.243       -0.989
u0_fifo48b_24b.rd_ptr_fast_3_rep1      lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_3_rep1      0.243       -0.916
u0_fifo48b_24b.rd_ptr_3_rep1_fast      lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_3_rep1_fast      0.243       -0.876
u0_fifo48b_24b.rd_ptr_fast_0_rep1      lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_0_rep1      0.243       -0.504
u0_fifo48b_24b.rd_ptr_1_rep1_fast      lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_1_rep1_fast      0.243       -0.483
u0_fifo48b_24b.rd_ptr_fast_fast[0]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_fast[0]     0.243       -0.453
u0_fifo48b_24b.rd_ptr_fast_fast[1]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_fast[1]     0.243       -0.413
u0_fifo48b_24b.rd_ptr_fast_fast[5]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_fast[5]     0.243       -0.360
u0_fifo48b_24b.rd_ptr_fast_fast[4]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_fast[4]     0.243       -0.278
u0_fifo48b_24b.rd_ptr_fast_3_rep2      lvds71_lvds41_top|clkop_inferred_clock     DFFC     Q       rd_ptr_fast_3_rep2      0.243       -0.205
=============================================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                                        Required           
Instance                         Reference                                  Type     Pin     Net                 Time         Slack 
                                 Clock                                                                                              
------------------------------------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_data_r[2]      lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[2]      5.545        -0.989
u0_fifo48b_24b.rd_data_r[16]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[16]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[19]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[19]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[20]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[20]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[21]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[21]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[22]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[22]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[23]     lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[23]     5.545        -0.684
u0_fifo48b_24b.rd_data_r[0]      lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[0]      5.545        -0.504
u0_fifo48b_24b.rd_data_r[6]      lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[6]      5.545        -0.504
u0_fifo48b_24b.rd_data_r[1]      lvds71_lvds41_top|clkop_inferred_clock     DFFC     D       rd_data_r_2[1]      5.545        -0.226
====================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.606
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.545

    - Propagation time:                      6.535
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.989

    Number of logic level(s):                6
    Starting point:                          u0_fifo48b_24b.rd_ptr_fast_fast[3] / Q
    Ending point:                            u0_fifo48b_24b.rd_data_r[2] / D
    The start point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_fast_fast[3]         DFFC          Q        Out     0.243     0.243       -         
rd_ptr_fast_fast[3]                        Net           -        -       0.535     -           9         
u0_fifo48b_24b.rd_data_r_2_19[18]          LUT3          I2       In      -         0.778       -         
u0_fifo48b_24b.rd_data_r_2_19[18]          LUT3          F        Out     0.462     1.240       -         
N_2085                                     Net           -        -       0.535     -           2         
u0_fifo48b_24b.rd_data_r_2_45_mb_rn[2]     LUT3          I1       In      -         1.775       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_rn[2]     LUT3          F        Out     0.570     2.345       -         
rd_data_r_2_45_mb_rn_0[2]                  Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          I0       In      -         2.746       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          F        Out     0.549     3.295       -         
N_1312                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          I0       In      -         3.696       -         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          F        Out     0.549     4.245       -         
N_1370                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          I0       In      -         4.647       -         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          F        Out     0.549     5.196       -         
rd_data_r_2_rn_0[2]                        Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     S0       In      -         5.731       -         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     O        Out     0.269     6.000       -         
rd_data_r_2[2]                             Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r[2]                DFFC          D        In      -         6.535       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.596 is 3.252(49.3%) logic and 3.344(50.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.606
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.545

    - Propagation time:                      6.462
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.917

    Number of logic level(s):                6
    Starting point:                          u0_fifo48b_24b.rd_ptr_fast_3_rep1 / Q
    Ending point:                            u0_fifo48b_24b.rd_data_r[2] / D
    The start point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_fast_3_rep1          DFFC          Q        Out     0.243     0.243       -         
rd_ptr_fast_3_rep1                         Net           -        -       0.596     -           11        
u0_fifo48b_24b.rd_data_r_2_3[2]            LUT3          I2       In      -         0.839       -         
u0_fifo48b_24b.rd_data_r_2_3[2]            LUT3          F        Out     0.462     1.301       -         
N_970                                      Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_rn[2]        LUT3          I0       In      -         1.702       -         
u0_fifo48b_24b.rd_data_r_2_45_rn[2]        LUT3          F        Out     0.549     2.251       -         
rd_data_r_2_45_rn_0[2]                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          I1       In      -         2.652       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          F        Out     0.570     3.222       -         
N_1312                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          I0       In      -         3.624       -         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          F        Out     0.549     4.173       -         
N_1370                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          I0       In      -         4.574       -         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          F        Out     0.549     5.123       -         
rd_data_r_2_rn_0[2]                        Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     S0       In      -         5.658       -         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     O        Out     0.269     5.927       -         
rd_data_r_2[2]                             Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r[2]                DFFC          D        In      -         6.462       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.523 is 3.252(49.9%) logic and 3.271(50.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.606
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.545

    - Propagation time:                      6.422
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.877

    Number of logic level(s):                6
    Starting point:                          u0_fifo48b_24b.rd_ptr_3_rep1_fast / Q
    Ending point:                            u0_fifo48b_24b.rd_data_r[2] / D
    The start point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_3_rep1_fast          DFFC          Q        Out     0.243     0.243       -         
rd_ptr_3_rep1_fast                         Net           -        -       0.535     -           10        
u0_fifo48b_24b.rd_data_r_2_24[2]           LUT3          I2       In      -         0.778       -         
u0_fifo48b_24b.rd_data_r_2_24[2]           LUT3          F        Out     0.462     1.240       -         
N_1144                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_rn[2]        LUT3          I1       In      -         1.641       -         
u0_fifo48b_24b.rd_data_r_2_45_rn[2]        LUT3          F        Out     0.570     2.211       -         
rd_data_r_2_45_rn_0[2]                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          I1       In      -         2.612       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          F        Out     0.570     3.182       -         
N_1312                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          I0       In      -         3.584       -         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          F        Out     0.549     4.133       -         
N_1370                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          I0       In      -         4.534       -         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          F        Out     0.549     5.083       -         
rd_data_r_2_rn_0[2]                        Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     S0       In      -         5.618       -         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     O        Out     0.269     5.887       -         
rd_data_r_2[2]                             Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r[2]                DFFC          D        In      -         6.422       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.483 is 3.273(50.5%) logic and 3.210(49.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.606
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.545

    - Propagation time:                      6.380
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.835

    Number of logic level(s):                6
    Starting point:                          u0_fifo48b_24b.rd_ptr_fast_fast[3] / Q
    Ending point:                            u0_fifo48b_24b.rd_data_r[2] / D
    The start point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_fast_fast[3]         DFFC          Q        Out     0.243     0.243       -         
rd_ptr_fast_fast[3]                        Net           -        -       0.535     -           9         
u0_fifo48b_24b.rd_data_r_2_20[2]           LUT3          I2       In      -         0.778       -         
u0_fifo48b_24b.rd_data_r_2_20[2]           LUT3          F        Out     0.462     1.240       -         
N_1112                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_mb_rn[2]     LUT3          I0       In      -         1.641       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_rn[2]     LUT3          F        Out     0.549     2.190       -         
rd_data_r_2_45_mb_rn_0[2]                  Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          I0       In      -         2.591       -         
u0_fifo48b_24b.rd_data_r_2_45_mb_mb[2]     LUT3          F        Out     0.549     3.140       -         
N_1312                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          I0       In      -         3.542       -         
u0_fifo48b_24b.rd_data_r_2_52[2]           LUT3          F        Out     0.549     4.091       -         
N_1370                                     Net           -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          I0       In      -         4.492       -         
u0_fifo48b_24b.rd_data_r_2_rn[2]           LUT3          F        Out     0.549     5.041       -         
rd_data_r_2_rn_0[2]                        Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     S0       In      -         5.576       -         
u0_fifo48b_24b.rd_data_r_2_mb[2]           MUX2_LUT5     O        Out     0.269     5.845       -         
rd_data_r_2[2]                             Net           -        -       0.535     -           1         
u0_fifo48b_24b.rd_data_r[2]                DFFC          D        In      -         6.380       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.441 is 3.231(50.2%) logic and 3.210(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.606
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.545

    - Propagation time:                      6.230
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.684

    Number of logic level(s):                6
    Starting point:                          u0_fifo48b_24b.rd_ptr_fast_fast[3] / Q
    Ending point:                            u0_fifo48b_24b.rd_data_r[19] / D
    The start point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK
    The end   point is clocked by            lvds71_lvds41_top|clkop_inferred_clock [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                    Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u0_fifo48b_24b.rd_ptr_fast_fast[3]      DFFC     Q        Out     0.243     0.243       -         
rd_ptr_fast_fast[3]                     Net      -        -       0.535     -           9         
u0_fifo48b_24b.rd_data_r_2_19[19]       LUT3     I2       In      -         0.778       -         
u0_fifo48b_24b.rd_data_r_2_19[19]       LUT3     F        Out     0.462     1.240       -         
N_2086                                  Net      -        -       0.535     -           2         
u0_fifo48b_24b.rd_data_r_2_46_1[19]     LUT3     I1       In      -         1.775       -         
u0_fifo48b_24b.rd_data_r_2_46_1[19]     LUT3     F        Out     0.570     2.345       -         
rd_data_r_2_46_1[19]                    Net      -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52_1[19]     LUT3     I1       In      -         2.746       -         
u0_fifo48b_24b.rd_data_r_2_52_1[19]     LUT3     F        Out     0.570     3.316       -         
rd_data_r_2_52_1[19]                    Net      -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_52[19]       LUT3     I1       In      -         3.717       -         
u0_fifo48b_24b.rd_data_r_2_52[19]       LUT3     F        Out     0.570     4.287       -         
N_2355                                  Net      -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2_1_0[19]      LUT3     I1       In      -         4.689       -         
u0_fifo48b_24b.rd_data_r_2_1_0[19]      LUT3     F        Out     0.570     5.259       -         
rd_data_r_2_1[19]                       Net      -        -       0.401     -           1         
u0_fifo48b_24b.rd_data_r_2[19]          LUT3     I1       In      -         5.660       -         
u0_fifo48b_24b.rd_data_r_2[19]          LUT3     F        Out     0.570     6.230       -         
rd_data_r_2[19]                         Net      -        -       0.000     -           1         
u0_fifo48b_24b.rd_data_r[19]            DFFC     D        In      -         6.230       -         
==================================================================================================
Total path delay (propagation time + setup) of 6.291 is 3.616(57.5%) logic and 2.675(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                    Starting                                                Arrival           
Instance                                            Reference     Type     Pin        Net                   Time        Slack 
                                                    Clock                                                                     
------------------------------------------------------------------------------------------------------------------------------
pll_inst                                            System        PLL      CLKOUT     clkop_i               0.000       -0.327
U_TX0.GSRN_i                                        System        INV      O          GSRN_i                0.000       1.317 
rx_inst.lvds_71_rx.Inst6_CLKDIVC_RNO                System        INV      O          reset_sync_i          0.000       1.317 
rx_inst.lvds_71_rx.pll_inst                         System        PLL      LOCK       pll_lock              0.000       1.317 
rx_inst.bit_aln_ctl_inst.dphase_cnt_RNIMJAD[19]     System        INV      O          rot_cnt               0.000       1.600 
rx_inst.delay_count_3_cry_0_0_RNO                   System        INV      O          delay_count_i[18]     0.000       1.635 
rx_inst.bus_sync_inst.counter_RNO[0]                System        INV      O          CO0_i                 0.000       2.303 
rx_inst.bus_sync_inst.counter_RNO[1]                System        INV      O          counter_1[1]          0.000       2.303 
rx_inst.release_reset_0_RNI7M03                     System        INV      O          release_reset_i       0.000       3.270 
pll_inst                                            System        PLL      LOCK       lock_chk              0.000       3.926 
==============================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                                  Required           
Instance                                    Reference     Type       Pin        Net                   Time         Slack 
                                            Clock                                                                        
-------------------------------------------------------------------------------------------------------------------------
U_TX0.Inst3_CLKDIVC                         System        CLKDIV     HCLKIN     eclkd                 1.852        -0.327
U_TX3.Inst3_CLKDIVC                         System        CLKDIV     HCLKIN     eclkd                 1.852        -0.327
U_TX2.Inst3_CLKDIVC                         System        CLKDIV     HCLKIN     eclkd                 1.852        -0.327
U_TX1.Inst3_CLKDIVC                         System        CLKDIV     HCLKIN     eclkd                 1.852        -0.327
rx_inst.lvds_71_rx.Inst6_CLKDIVC            System        CLKDIV     RESETN     reset_sync_i          1.852        1.317 
pll_inst                                    System        PLL        RESET      GSRN_i                1.852        1.317 
rx_inst.lvds_71_rx.pll_inst_RNIHJEB         System        INV        I          pll_lock              1.852        1.317 
rx_inst.bit_aln_ctl_inst.dphase_cnt[19]     System        DFFCE      D          dphase_cnt_s[19]      3.805        1.600 
rx_inst.delay_count[18]                     System        DFF        D          delay_count_3[18]     3.805        1.635 
rx_inst.bit_aln_ctl_inst.dphase_cnt[18]     System        DFFCE      D          dphase_cnt_s[18]      3.805        1.635 
=========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1.852
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1.852

    - Propagation time:                      2.179
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.327

    Number of logic level(s):                1
    Starting point:                          pll_inst / CLKOUT
    Ending point:                            U_TX3.Inst3_CLKDIVC / HCLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                     Pin        Pin               Arrival     No. of    
Name                    Type       Name       Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pll_inst                PLL        CLKOUT     Out     0.000     0.000       -         
clkop_i                 Net        -          -       1.074     -           118       
U_TX3.eclkd             LUT2       I1         In      -         1.074       -         
U_TX3.eclkd             LUT2       F          Out     0.570     1.644       -         
eclkd                   Net        -          -       0.535     -           7         
U_TX3.Inst3_CLKDIVC     CLKDIV     HCLKIN     In      -         2.179       -         
======================================================================================
Total path delay (propagation time + setup) of 2.179 is 0.570(26.2%) logic and 1.609(73.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1.852
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1.852

    - Propagation time:                      2.179
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.327

    Number of logic level(s):                1
    Starting point:                          pll_inst / CLKOUT
    Ending point:                            U_TX2.Inst3_CLKDIVC / HCLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                     Pin        Pin               Arrival     No. of    
Name                    Type       Name       Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pll_inst                PLL        CLKOUT     Out     0.000     0.000       -         
clkop_i                 Net        -          -       1.074     -           118       
U_TX2.eclkd             LUT2       I1         In      -         1.074       -         
U_TX2.eclkd             LUT2       F          Out     0.570     1.644       -         
eclkd                   Net        -          -       0.535     -           7         
U_TX2.Inst3_CLKDIVC     CLKDIV     HCLKIN     In      -         2.179       -         
======================================================================================
Total path delay (propagation time + setup) of 2.179 is 0.570(26.2%) logic and 1.609(73.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1.852
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1.852

    - Propagation time:                      2.179
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.327

    Number of logic level(s):                1
    Starting point:                          pll_inst / CLKOUT
    Ending point:                            U_TX1.Inst3_CLKDIVC / HCLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                     Pin        Pin               Arrival     No. of    
Name                    Type       Name       Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pll_inst                PLL        CLKOUT     Out     0.000     0.000       -         
clkop_i                 Net        -          -       1.074     -           118       
U_TX1.eclkd             LUT2       I1         In      -         1.074       -         
U_TX1.eclkd             LUT2       F          Out     0.570     1.644       -         
eclkd                   Net        -          -       0.535     -           7         
U_TX1.Inst3_CLKDIVC     CLKDIV     HCLKIN     In      -         2.179       -         
======================================================================================
Total path delay (propagation time + setup) of 2.179 is 0.570(26.2%) logic and 1.609(73.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      1.852
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1.852

    - Propagation time:                      2.179
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.327

    Number of logic level(s):                1
    Starting point:                          pll_inst / CLKOUT
    Ending point:                            U_TX0.Inst3_CLKDIVC / HCLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                     Pin        Pin               Arrival     No. of    
Name                    Type       Name       Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
pll_inst                PLL        CLKOUT     Out     0.000     0.000       -         
clkop_i                 Net        -          -       1.074     -           118       
U_TX0.eclkd             LUT2       I1         In      -         1.074       -         
U_TX0.eclkd             LUT2       F          Out     0.570     1.644       -         
eclkd                   Net        -          -       0.535     -           7         
U_TX0.Inst3_CLKDIVC     CLKDIV     HCLKIN     In      -         2.179       -         
======================================================================================
Total path delay (propagation time + setup) of 2.179 is 0.570(26.2%) logic and 1.609(73.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      1.852
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1.852

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 1.317

    Number of logic level(s):                0
    Starting point:                          U_TX0.GSRN_i / O
    Ending point:                            pll_inst / RESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net              Pin       Pin               Arrival     No. of    
Name               Type     Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------
U_TX0.GSRN_i       INV      O         Out     0.000     0.000       -         
GSRN_i             Net      -         -       0.535     -           642       
pll_inst           PLL      RESET     In      -         0.535       -         
==============================================================================
Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:25s; Memory used current: 234MB peak: 238MB)


Finished timing report (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:25s; Memory used current: 234MB peak: 238MB)

---------------------------------------
Resource Usage Report for lvds71_lvds41_top 

Mapping to part: gw2a_18lqfp144-8
Cell usage:
ALU             65 uses
CLKDIV          5 uses
DFF             27 uses
DFFC            145 uses
DFFCE           586 uses
DFFE            23 uses
DFFPE           7 uses
GSR             1 use
INV             12 uses
IVIDEO          9 uses
MUX2_LUT5       289 uses
MUX2_LUT6       55 uses
OSER4           28 uses
PLL             2 uses
LUT2            104 uses
LUT3            1135 uses
LUT4            317 uses

I/O ports: 79
I/O primitives: 36
TLVDS_IBUF     8 uses
TLVDS_OBUF     28 uses

I/O Register bits:                  0
Register bits not including I/Os:   788 of 15552 (5%)
Total load per clock:
   lvds71_lvds41_top|clkop_inferred_clock: 118
   LVDS71RX_1CLK8DATA|sclk_inferred_clock: 524
   lvds71_lvds41_top|RCLK_in: 162

@S |Mapping Summary:
Total  LUTs: 1556 (7%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:25s; Memory used current: 50MB peak: 238MB)

Process took 0h:00m:28s realtime, 0h:00m:25s cputime
# Thu May 23 15:10:43 2019

###########################################################]