#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro #OS: Windows 8 6.2 #Hostname: GW-SW-041 # Thu May 23 15:10:09 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-041 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-041 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\bit_align_ctl.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\bus_sync.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\fifo48b_24b.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\lvds_7_to_1_rx.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS41TX_1CLK6DATA.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\lvds71_lvds41_top.v" (library work) @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71RX_1CLK8DATA.v" (library work) @W:CG1337 : LVDS71RX_1CLK8DATA.v(130) | Net scuba_vhi is not declared. @I::"E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\word_align_ctl.v" (library work) Verilog syntax check successful! File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71RX_1CLK8DATA.v changed - recompiling Selecting top level module lvds71_lvds41_top @N:CG364 : gw2a.v(113) | Synthesizing module LUT4 in library work. Running optimization stage 1 on LUT4 ....... @N:CG364 : gw2a.v(461) | Synthesizing module IVIDEO in library work. Running optimization stage 1 on IVIDEO ....... @N:CG364 : gw2a.v(1671) | Synthesizing module CLKDIV in library work. Running optimization stage 1 on CLKDIV ....... @N:CG364 : gw2a.v(1532) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gw2a.v(1608) | Synthesizing module TLVDS_IBUF in library work. Running optimization stage 1 on TLVDS_IBUF ....... @N:CG364 : LVDS71RX_1CLK8DATA.v(2) | Synthesizing module LVDS71RX_1CLK8DATA in library work. @W:CG360 : LVDS71RX_1CLK8DATA.v(91) | Removing wire cdiv1, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(96) | Removing wire WBDATO0, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(97) | Removing wire WBDATO1, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(98) | Removing wire WBDATO2, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(99) | Removing wire WBDATO3, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(100) | Removing wire WBDATO4, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(101) | Removing wire WBDATO5, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(102) | Removing wire WBDATO6, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(103) | Removing wire WBDATO7, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(104) | Removing wire WBACK, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(105) | Removing wire DPHSRC, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(106) | Removing wire CLKINTFB, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(107) | Removing wire REFCLK, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(108) | Removing wire INTLOCK, as there is no assignment to it. @W:CG360 : LVDS71RX_1CLK8DATA.v(115) | Removing wire buf_clkop, as there is no assignment to it. Running optimization stage 1 on LVDS71RX_1CLK8DATA ....... @N:CG364 : bus_sync.v(1) | Synthesizing module bus_sync in library work. DATA_BITS=32'b00000000000000000000000000000111 Generated name = bus_sync_7s Running optimization stage 1 on bus_sync_7s ....... @N:CG364 : bit_align_ctl.v(2) | Synthesizing module bit_align_ctl in library work. @A:CG412 : bit_align_ctl.v(76) | Treating === and !== as == and != -- possible simulation mismatch @A:CG412 : bit_align_ctl.v(117) | Treating === and !== as == and != -- possible simulation mismatch Running optimization stage 1 on bit_align_ctl ....... @N:CG364 : word_align_ctl.v(1) | Synthesizing module word_align_ctl in library work. Running optimization stage 1 on word_align_ctl ....... @N:CG364 : lvds_7_to_1_rx.v(2) | Synthesizing module LVDS_7_to_1_RX in library work. Running optimization stage 1 on LVDS_7_to_1_RX ....... @N:CG364 : fifo48b_24b.v(2) | Synthesizing module fifo48b_24b in library work. @W:CG133 : fifo48b_24b.v(13) | Object full_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fifo48b_24b.v(16) | Object empty_r is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on fifo48b_24b ....... @N:CG364 : gw2a.v(1613) | Synthesizing module TLVDS_OBUF in library work. Running optimization stage 1 on TLVDS_OBUF ....... @N:CG364 : gw2a.v(492) | Synthesizing module OSER4 in library work. Running optimization stage 1 on OSER4 ....... @N:CG364 : LVDS41TX_1CLK6DATA.v(3) | Synthesizing module LVDS41TX_1CLK6DATA in library work. @W:CG360 : LVDS41TX_1CLK6DATA.v(50) | Removing wire cdiv1, as there is no assignment to it. Running optimization stage 1 on LVDS41TX_1CLK6DATA ....... @N:CG364 : lvds71_lvds41_top.v(2) | Synthesizing module lvds71_lvds41_top in library work. Running optimization stage 1 on lvds71_lvds41_top ....... Running optimization stage 2 on lvds71_lvds41_top ....... Running optimization stage 2 on LVDS41TX_1CLK6DATA ....... Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on TLVDS_OBUF ....... Running optimization stage 2 on fifo48b_24b ....... @W:CL190 : fifo48b_24b.v(36) | Optimizing register bit wr_ptr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : fifo48b_24b.v(36) | Pruning register bit 0 of wr_ptr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on LVDS_7_to_1_RX ....... Running optimization stage 2 on word_align_ctl ....... Running optimization stage 2 on bit_align_ctl ....... @N:CL201 : bit_align_ctl.v(170) | Trying to extract state machine for register dphase_state. Extracted state machine for register dphase_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on bus_sync_7s ....... Running optimization stage 2 on LVDS71RX_1CLK8DATA ....... @N:CL159 : LVDS71RX_1CLK8DATA.v(5) | Input clk_n is unused. @N:CL159 : LVDS71RX_1CLK8DATA.v(7) | Input init is unused. Running optimization stage 2 on TLVDS_IBUF ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on IVIDEO ....... Running optimization stage 2 on LUT4 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 84MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu May 23 15:10:10 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: I:\workSpace\Gowin_setup\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-041 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level @N:NF107 : lvds71_lvds41_top.v(2) | Selected library: work cell: lvds71_lvds41_top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu May 23 15:10:10 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu May 23 15:10:10 2019 ###########################################################]