Project Settings
Project Name LVDS71_RX_LVDS41_TX Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 25 21 0 - 00m:01s - 2019/5/23
15:10:10
(premap)Complete 14 13 0 0m:01s 0m:02s 195MB 2019/5/23
15:10:14
(fpga_mapper)Complete 55 17 0 0m:25s 0m:28s 238MB 2019/5/23
15:10:43
Multi-srs Generator Complete00m:01s2019/5/23
15:10:12

Area Summary
I/O ports (io_port) 79 Non I/O Register bits (non_io_reg) 788 (5%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 0 (46)
Block Multipliers (dsp_used) 0 (24) LUTs (total_luts) 1556 (7%)

Timing Summary
Clock NameReq FreqEst FreqSlack
LVDS41TX_1CLK6DATA_0|eclkc_i_uclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_0|sclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_1|eclkc_i_uclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_1|sclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_2|eclkc_i_uclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_2|sclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_3|eclkc_i_uclk_inferred_clock150.0 MHzNANA
LVDS41TX_1CLK6DATA_3|sclk_inferred_clock150.0 MHzNANA
LVDS71RX_1CLK8DATA|eclk_inferred_clock150.0 MHzNANA
LVDS71RX_1CLK8DATA|sclk_inferred_clock345.0 MHz293.2 MHz-0.512
lvds71_lvds41_top|RCLK_in258.7 MHz219.9 MHz-0.682
lvds71_lvds41_top|clkop_inferred_clock178.4 MHz151.6 MHz-0.989
System539.9 MHz458.9 MHz-0.327

Optimizations Summary
Combined Clock Conversion 1 / 15