Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\synthesize\rev_1\LVDS71_RX_LVDS41_TX.vm
Physical Constraints File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71_RX_LVDS41_TX.cst
Timing Constraint File E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\src\LVDS71_RX_LVDS41_TX.sdc
Command Line I:/workSpace/Gowin_setup/Gowin_V1.9.1Beta/IDE/bin/gowin -do E:\Custom\Gowin_LVDS71_RX_LVDS41_TX_RefDesign\project\impl\pnr\cmd.do
GOWIN version V1.9.1Beta
Part Number GW2A-LV18LQ144C8/I7
Created Time Fri May 24 16:29:02 2019
Legal Announcement Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C
Hold Delay Model Fast 1.05V 0C
Numbers of Paths Analyzed 2460
Numbers of Endpoints Analyzed 2435
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 13
Numbers of Hold Violated Endpoints 106

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
sclk Base 13.468 74.250 0.000 6.734 sclk
clkop Base 6.734 148.500 0.000 3.367 clkop
pll_inst/CLKOUTD.default_gen_clk Generated 13.468 74.250 0.000 6.734 sclk
pll_inst/CLKOUTD3.default_gen_clk Generated 20.202 49.500 0.000 10.101 sclk
pll_inst/CLKOUTP.default_gen_clk Generated 6.734 148.500 2.458 5.825 sclk
rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk Base 9.259 108.000 0.000 4.630
rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk Generated 2.646 378.000 0.000 1.323 rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk
rx_inst/lvds_71_rx/pll_inst/CLKOUT.default_gen_clk Generated 2.646 378.000 0.000 1.323 rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk
rx_inst/lvds_71_rx/pll_inst/CLKOUTD.default_gen_clk Generated 5.291 189.000 0.000 2.646 rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk
rx_inst/lvds_71_rx/pll_inst/CLKOUTD3.default_gen_clk Generated 7.937 126.000 0.000 3.968 rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk
U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 clkop
U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 clkop
U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 clkop
U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 clkop

Max Frequency Summary:

NO. Clock Name Fmax Entity
1 sclk 115.196(MHz) TOP
2 clkop 134.048(MHz) TOP

No timing paths to get frequency of pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk!

No timing paths to get frequency of rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of rx_inst/lvds_71_rx/pll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of rx_inst/lvds_71_rx/pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of rx_inst/lvds_71_rx/pll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk!

No timing paths to get frequency of U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk!

No timing paths to get frequency of U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk!

No timing paths to get frequency of U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
sclk Setup 0.000 0
sclk Hold 0.000 0
clkop Setup -3.769 9
clkop Hold 0.000 0
pll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
pll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk Setup 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKIN.default_clk Hold 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUT.default_gen_clk Setup 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUT.default_gen_clk Hold 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
rx_inst/lvds_71_rx/pll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk Setup 0.000 0
U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk Hold 0.000 0
U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk Setup 0.000 0
U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk Hold 0.000 0
U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk Setup 0.000 0
U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk Hold 0.000 0
U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk Setup 0.000 0
U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.726 u0_fifo48b_24b/rd_ptr_fast_fast_Z[3]/Q u0_fifo48b_24b/rd_data_r[2]/D clkop:[R] clkop:[R] 6.734 0.000 7.225
2 -0.704 u0_fifo48b_24b/rd_ptr_3_rep2_fast_Z/Q u0_fifo48b_24b/rd_data_r[4]/D clkop:[R] clkop:[R] 6.734 0.000 7.203
3 -0.663 u0_fifo48b_24b/rd_ptr_4_rep1_rep1_Z/Q u0_fifo48b_24b/rd_data_r[14]/D clkop:[R] clkop:[R] 6.734 0.000 7.162
4 -0.637 u0_fifo48b_24b/rd_ptr_1_rep1_fast_Z/Q u0_fifo48b_24b/rd_data_r[6]/D clkop:[R] clkop:[R] 6.734 0.000 7.136
5 -0.575 u0_fifo48b_24b/rd_ptr_fast_5_rep1_Z/Q u0_fifo48b_24b/rd_data_r[21]/D clkop:[R] clkop:[R] 6.734 0.000 7.074
6 -0.333 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 2.291
7 -0.285 u0_fifo48b_24b/rd_ptr_fast_fast_Z[0]/Q u0_fifo48b_24b/rd_data_r[23]/D clkop:[R] clkop:[R] 6.734 0.000 6.784
8 -0.255 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A2/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 2.213
9 -0.167 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 2.125
10 -0.069 u0_fifo48b_24b/rd_ptr_4_rep1_Z/Q u0_fifo48b_24b/rd_data_r[19]/D clkop:[R] clkop:[R] 6.734 0.000 6.568
11 -0.059 u0_fifo48b_24b/rd_ptr_0_rep1_rep2_Z/Q u0_fifo48b_24b/rd_data_r[10]/D clkop:[R] clkop:[R] 6.734 0.000 6.558
12 -0.058 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A4/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 2.016
13 -0.050 u0_fifo48b_24b/rd_ptr_4_rep2_Z/Q u0_fifo48b_24b/rd_data_r[8]/D clkop:[R] clkop:[R] 6.734 0.000 6.549
14 0.000 u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/Q u0_fifo48b_24b/rd_data_r[18]/D clkop:[R] clkop:[R] 6.734 0.000 6.499
15 0.004 u0_fifo48b_24b/rd_ptr_3_rep1_Z/Q u0_fifo48b_24b/rd_data_r[5]/D clkop:[R] clkop:[R] 6.734 0.000 6.495
16 0.043 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A5/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 1.915
17 0.055 u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/Q u0_fifo48b_24b/rd_data_r[7]/D clkop:[R] clkop:[R] 6.734 0.000 6.444
18 0.075 u0_fifo48b_24b/rd_ptr_fast_Z[3]/Q u0_fifo48b_24b/rd_data_r[22]/D clkop:[R] clkop:[R] 6.734 0.000 6.424
19 0.104 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A3/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 1.855
20 0.145 u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/Q u0_fifo48b_24b/rd_data_r[0]/D clkop:[R] clkop:[R] 6.734 0.000 6.354
21 0.172 u0_fifo48b_24b/rd_ptr_3_rep1_rep1_Z/Q u0_fifo48b_24b/rd_data_r[16]/D clkop:[R] clkop:[R] 6.734 0.000 6.327
22 0.213 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst8_IDDRX71A/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 1.745
23 0.220 u0_fifo48b_24b/rd_ptr_4_rep1_Z/Q u0_fifo48b_24b/rd_data_r[9]/D clkop:[R] clkop:[R] 6.734 0.000 6.279
24 0.276 u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/Q u0_fifo48b_24b/rd_data_r[17]/D clkop:[R] clkop:[R] 6.734 0.000 6.223
25 0.282 rx_inst/wd_aln_ctl_inst/slip/Q rx_inst/lvds_71_rx/Inst7_IDDRX71A6/CALIB sclk:[R] rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R] 0.241 -2.117 1.676

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -3.455 u0_fifo48b_24b/rd_data_r[3]/Q U_TX3/Inst5_ODDRX2E3/D0 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.775
2 -3.452 u0_fifo48b_24b/rd_data_r[4]/Q U_TX3/Inst5_ODDRX2E4/D0 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.779
3 -3.442 u0_fifo48b_24b/rd_data_r[11]/Q U_TX3/Inst5_ODDRX2E5/D1 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.776
4 -3.319 u0_fifo48b_24b/rd_data_r[15]/Q U_TX3/Inst5_ODDRX2E3/D2 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.911
5 -3.318 u0_fifo48b_24b/rd_data_r[1]/Q U_TX3/Inst5_ODDRX2E1/D0 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.913
6 -3.316 u0_fifo48b_24b/rd_data_r[17]/Q U_TX3/Inst5_ODDRX2E5/D2 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.914
7 -3.305 u0_fifo48b_24b/rd_data_r[5]/Q U_TX3/Inst5_ODDRX2E5/D0 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.926
8 -3.304 u0_fifo48b_24b/rd_data_r[2]/Q U_TX3/Inst5_ODDRX2E2/D0 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.926
9 -3.277 u0_fifo48b_24b/rd_data_r[7]/Q U_TX3/Inst5_ODDRX2E1/D1 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 0.941
10 -3.238 u0_fifo48b_24b/rd_data_r[23]/Q U_TX0/Inst5_ODDRX2E5/D3 clkop:[R] U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.667 0.913
11 -3.163 u0_fifo48b_24b/rd_data_r[8]/Q U_TX1/Inst5_ODDRX2E2/D1 clkop:[R] U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.593 0.913
12 -3.159 u0_fifo48b_24b/rd_data_r[2]/Q U_TX2/Inst5_ODDRX2E2/D0 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.075
13 -3.158 u0_fifo48b_24b/rd_data_r[13]/Q U_TX2/Inst5_ODDRX2E1/D2 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.076
14 -3.158 u0_fifo48b_24b/rd_data_r[1]/Q U_TX2/Inst5_ODDRX2E1/D0 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.076
15 -3.156 u0_fifo48b_24b/rd_data_r[10]/Q U_TX3/Inst5_ODDRX2E4/D1 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 1.062
16 -3.156 u0_fifo48b_24b/rd_data_r[12]/Q U_TX3/Inst5_ODDRX2E0/D2 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 1.074
17 -3.152 u0_fifo48b_24b/rd_data_r[14]/Q U_TX3/Inst5_ODDRX2E2/D2 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 1.078
18 -3.147 u0_fifo48b_24b/rd_data_r[20]/Q U_TX2/Inst5_ODDRX2E2/D3 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.075
19 -3.143 u0_fifo48b_24b/rd_data_r[9]/Q U_TX3/Inst5_ODDRX2E3/D1 clkop:[R] U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.735 1.075
20 -3.143 u0_fifo48b_24b/rd_data_r[8]/Q U_TX2/Inst5_ODDRX2E2/D1 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.079
21 -3.129 u0_fifo48b_24b/rd_data_r[11]/Q U_TX2/Inst5_ODDRX2E5/D1 clkop:[R] U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.739 1.092
22 -3.105 u0_fifo48b_24b/rd_data_r[11]/Q U_TX0/Inst5_ODDRX2E5/D1 clkop:[R] U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.667 1.045
23 -3.099 u0_fifo48b_24b/rd_data_r[17]/Q U_TX0/Inst5_ODDRX2E5/D2 clkop:[R] U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.667 1.063
24 -3.097 u0_fifo48b_24b/rd_data_r[16]/Q U_TX0/Inst5_ODDRX2E4/D2 clkop:[R] U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.667 1.065
25 -3.079 u0_fifo48b_24b/rd_data_r[21]/Q U_TX0/Inst5_ODDRX2E3/D3 clkop:[R] U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R] 0.000 -3.667 1.071

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.367 3.367 1.000 High Pulse Width clkop u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z
2 2.367 3.367 1.000 Low Pulse Width clkop u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z
3 2.367 3.367 1.000 High Pulse Width clkop u0_fifo48b_24b/rd_ptr_5_rep2_rep1_Z
4 2.367 3.367 1.000 Low Pulse Width clkop u0_fifo48b_24b/rd_ptr_0_rep1_Z
5 2.367 3.367 1.000 Low Pulse Width clkop u0_fifo48b_24b/rd_data_r[4]
6 2.367 3.367 1.000 Low Pulse Width clkop U_TX2/opensync_Z[0]
7 2.367 3.367 1.000 High Pulse Width clkop U_TX3/opensync_Z[3]
8 2.367 3.367 1.000 Low Pulse Width clkop U_TX3/opensync_Z[0]
9 2.367 3.367 1.000 Low Pulse Width clkop U_TX3/opensync_Z[3]
10 2.367 3.367 1.000 Low Pulse Width clkop U_TX3/opensync_Z[2]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.726
Data Arrival Time 7.225
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_fast_fast_Z[3]
To u0_fifo48b_24b/rd_data_r[2]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R18C19[0][B] u0_fifo48b_24b/rd_ptr_fast_fast_Z[3]/CLK
0.232 0.232 tC2Q RF 9 R18C19[0][B] u0_fifo48b_24b/rd_ptr_fast_fast_Z[3]/Q
1.035 0.803 tNET FF 1 R22C25[1][B] u0_fifo48b_24b/rd_data_r_2_19[18]/I2
1.590 0.555 tINS FF 2 R22C25[1][B] u0_fifo48b_24b/rd_data_r_2_19[18]/F
2.235 0.645 tNET FF 1 R24C27[2][B] u0_fifo48b_24b/rd_data_r_2_45_mb_rn[2]/I1
2.606 0.371 tINS FF 1 R24C27[2][B] u0_fifo48b_24b/rd_data_r_2_45_mb_rn[2]/F
4.217 1.611 tNET FF 1 R25C30[2][A] u0_fifo48b_24b/rd_data_r_2_45_mb_mb[2]/I0
4.679 0.462 tINS FR 1 R25C30[2][A] u0_fifo48b_24b/rd_data_r_2_45_mb_mb[2]/F
4.680 0.001 tNET RR 1 R25C30[0][B] u0_fifo48b_24b/rd_data_r_2_52[2]/I0
5.142 0.462 tINS RR 1 R25C30[0][B] u0_fifo48b_24b/rd_data_r_2_52[2]/F
5.314 0.172 tNET RR 1 R26C30[2][A] u0_fifo48b_24b/rd_data_r_2_rn[2]/I0
5.767 0.453 tINS RF 1 R26C30[2][A] u0_fifo48b_24b/rd_data_r_2_rn[2]/F
6.949 1.181 tNET FF 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r_2_mb[2]/S0
7.218 0.269 tINS FR 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r_2_mb[2]/O
7.225 0.007 tNET RR 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[2]
6.499 -0.035 tSu 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.572, 35.599%; route: 4.421, 61.190%; tC2Q: 0.232, 3.211%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack -0.704
Data Arrival Time 7.203
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_3_rep2_fast_Z
To u0_fifo48b_24b/rd_data_r[4]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R34C33[2][A] u0_fifo48b_24b/rd_ptr_3_rep2_fast_Z/CLK
0.232 0.232 tC2Q RF 11 R34C33[2][A] u0_fifo48b_24b/rd_ptr_3_rep2_fast_Z/Q
1.761 1.529 tNET FF 1 R21C27[1][A] u0_fifo48b_24b/rd_data_r_2_40[4]/S0
2.012 0.251 tINS FF 1 R21C27[1][A] u0_fifo48b_24b/rd_data_r_2_40[4]/O
5.352 3.340 tNET FF 1 R33C25[2][A] u0_fifo48b_24b/rd_data_r_2_50[4]/I1
5.723 0.371 tINS FF 1 R33C25[2][A] u0_fifo48b_24b/rd_data_r_2_50[4]/F
5.723 0.000 tNET FF 1 R33C25[2][A] u0_fifo48b_24b/rd_data_r_2_54[4]/I0
5.826 0.103 tINS FF 2 R33C25[2][A] u0_fifo48b_24b/rd_data_r_2_54[4]/O
6.521 0.696 tNET FF 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r_2_7_cZ[4]/I0
7.091 0.570 tINS FR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r_2_7_cZ[4]/F
7.091 0.000 tNET RR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[4]/I0
7.196 0.105 tINS RR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[4]/O
7.203 0.007 tNET RR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r[4]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[4]
6.499 -0.035 tSu 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r[4]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.400, 19.435%; route: 5.571, 77.344%; tC2Q: 0.232, 3.221%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack -0.663
Data Arrival Time 7.162
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep1_rep1_Z
To u0_fifo48b_24b/rd_data_r[14]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R30C17[0][A] u0_fifo48b_24b/rd_ptr_4_rep1_rep1_Z/CLK
0.232 0.232 tC2Q RF 9 R30C17[0][A] u0_fifo48b_24b/rd_ptr_4_rep1_rep1_Z/Q
0.928 0.696 tNET FF 1 R29C24[0][B] u0_fifo48b_24b/rd_data_r_2_20[22]/I2
1.299 0.371 tINS FF 2 R29C24[0][B] u0_fifo48b_24b/rd_data_r_2_20[22]/F
3.572 2.273 tNET FF 1 R29C25[0][B] u0_fifo48b_24b/rd_data_r_2_40[14]/I1
4.127 0.555 tINS FF 1 R29C25[0][B] u0_fifo48b_24b/rd_data_r_2_40[14]/F
5.616 1.489 tNET FF 1 R31C21[3][B] u0_fifo48b_24b/rd_data_r_2_49[14]/I1
6.133 0.517 tINS FF 1 R31C21[3][B] u0_fifo48b_24b/rd_data_r_2_49[14]/F
6.133 0.000 tNET FF 1 R31C21[3][A] u0_fifo48b_24b/rd_data_r_2_54[14]/I1
6.236 0.103 tINS FF 1 R31C21[3][A] u0_fifo48b_24b/rd_data_r_2_54[14]/O
6.236 0.000 tNET FF 1 R31C21[2][B] u0_fifo48b_24b/rd_data_r_2_56[14]/I0
6.339 0.103 tINS FF 1 R31C21[2][B] u0_fifo48b_24b/rd_data_r_2_56[14]/O
6.592 0.253 tNET FF 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r_2_cZ[14]/I1
7.162 0.570 tINS FR 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r_2_cZ[14]/F
7.162 0.000 tNET RR 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r[14]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r[14]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[14]
6.499 -0.035 tSu 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r[14]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.219, 30.982%; route: 4.711, 65.779%; tC2Q: 0.232, 3.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack -0.637
Data Arrival Time 7.136
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_1_rep1_fast_Z
To u0_fifo48b_24b/rd_data_r[6]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R32C34[2][A] u0_fifo48b_24b/rd_ptr_1_rep1_fast_Z/CLK
0.232 0.232 tC2Q RF 20 R32C34[2][A] u0_fifo48b_24b/rd_ptr_1_rep1_fast_Z/Q
1.314 1.082 tNET FF 1 R26C22[1][B] u0_fifo48b_24b/rd_data_r_2_51_1_N_2L1_0/I2
1.776 0.462 tINS FR 1 R26C22[1][B] u0_fifo48b_24b/rd_data_r_2_51_1_N_2L1_0/F
1.948 0.172 tNET RR 1 R27C22[0][B] u0_fifo48b_24b/rd_data_r_2_51_1_cZ[6]/I2
2.503 0.555 tINS RF 1 R27C22[0][B] u0_fifo48b_24b/rd_data_r_2_51_1_cZ[6]/F
3.992 1.489 tNET FF 1 R27C23[3][B] u0_fifo48b_24b/rd_data_r_2_57_1_1_mb[6]/I0
4.547 0.555 tINS FF 1 R27C23[3][B] u0_fifo48b_24b/rd_data_r_2_57_1_1_mb[6]/F
4.960 0.413 tNET FF 1 R26C24[1][A] u0_fifo48b_24b/rd_data_r_2_1_0_1[6]/I1
5.530 0.570 tINS FR 1 R26C24[1][A] u0_fifo48b_24b/rd_data_r_2_1_0_1[6]/F
5.532 0.001 tNET RR 1 R26C24[1][B] u0_fifo48b_24b/rd_data_r_2_1_0[6]/I1
5.903 0.371 tINS RF 1 R26C24[1][B] u0_fifo48b_24b/rd_data_r_2_1_0[6]/F
6.587 0.684 tNET FF 1 R29C20[1][B] u0_fifo48b_24b/rd_data_r_2_cZ[6]/I1
7.136 0.549 tINS FR 1 R29C20[1][B] u0_fifo48b_24b/rd_data_r_2_cZ[6]/F
7.136 0.000 tNET RR 1 R29C20[1][B] u0_fifo48b_24b/rd_data_r[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R29C20[1][B] u0_fifo48b_24b/rd_data_r[6]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[6]
6.499 -0.035 tSu 1 R29C20[1][B] u0_fifo48b_24b/rd_data_r[6]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 3.062, 42.912%; route: 3.842, 53.837%; tC2Q: 0.232, 3.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack -0.575
Data Arrival Time 7.074
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_fast_5_rep1_Z
To u0_fifo48b_24b/rd_data_r[21]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R35C34[0][B] u0_fifo48b_24b/rd_ptr_fast_5_rep1_Z/CLK
0.232 0.232 tC2Q RF 14 R35C34[0][B] u0_fifo48b_24b/rd_ptr_fast_5_rep1_Z/Q
1.664 1.432 tNET FF 1 R24C21[2][B] u0_fifo48b_24b/rd_data_r_2_10_cZ[13]/I2
2.219 0.555 tINS FF 2 R24C21[2][B] u0_fifo48b_24b/rd_data_r_2_10_cZ[13]/F
2.908 0.688 tNET FF 1 R32C21[3][B] u0_fifo48b_24b/rd_data_r_2_44_1_cZ[21]/I0
3.425 0.517 tINS FF 1 R32C21[3][B] u0_fifo48b_24b/rd_data_r_2_44_1_cZ[21]/F
4.081 0.656 tNET FF 1 R35C20[1][A] u0_fifo48b_24b/rd_data_r_2_44[21]/I1
4.452 0.371 tINS FF 1 R35C20[1][A] u0_fifo48b_24b/rd_data_r_2_44[21]/F
4.452 0.000 tNET FF 1 R35C20[1][A] u0_fifo48b_24b/rd_data_r_2_50[21]/I0
4.555 0.103 tINS FF 1 R35C20[1][A] u0_fifo48b_24b/rd_data_r_2_50[21]/O
5.245 0.690 tNET FF 1 R25C21[3][A] u0_fifo48b_24b/rd_data_r_2_1_0[21]/I0
5.762 0.517 tINS FF 1 R25C21[3][A] u0_fifo48b_24b/rd_data_r_2_1_0[21]/F
6.612 0.850 tNET FF 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[21]/I1
7.074 0.462 tINS FR 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[21]/F
7.074 0.000 tNET RR 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r[21]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r[21]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[21]
6.499 -0.035 tSu 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r[21]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.525, 35.695%; route: 4.317, 61.025%; tC2Q: 0.232, 3.280%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack -0.333
Data Arrival Time 138.172
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A1
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
138.172 2.059 tNET FF 1 IOT6[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT6[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A1/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A1
137.839 0.000 tSu 1 IOT6[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A1

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.059, 89.875%; tC2Q: 0.232, 10.125%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path7

Path Summary:

Slack -0.285
Data Arrival Time 6.784
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_fast_fast_Z[0]
To u0_fifo48b_24b/rd_data_r[23]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R24C18[2][B] u0_fifo48b_24b/rd_ptr_fast_fast_Z[0]/CLK
0.232 0.232 tC2Q RF 23 R24C18[2][B] u0_fifo48b_24b/rd_ptr_fast_fast_Z[0]/Q
1.751 1.519 tNET FF 1 R29C26[0][B] u0_fifo48b_24b/rd_data_r_2_23[7]/I2
2.306 0.555 tINS FF 1 R29C26[0][B] u0_fifo48b_24b/rd_data_r_2_23[7]/F
4.231 1.926 tNET FF 1 R31C27[3][B] u0_fifo48b_24b/rd_data_r_2_29[23]/I1
4.684 0.453 tINS FF 1 R31C27[3][B] u0_fifo48b_24b/rd_data_r_2_29[23]/F
4.684 0.000 tNET FF 1 R31C27[3][A] u0_fifo48b_24b/rd_data_r_2_45[23]/I1
4.787 0.103 tINS FF 1 R31C27[3][A] u0_fifo48b_24b/rd_data_r_2_45[23]/O
4.787 0.000 tNET FF 1 R31C27[2][B] u0_fifo48b_24b/rd_data_r_2_51[23]/I0
4.890 0.103 tINS FF 1 R31C27[2][B] u0_fifo48b_24b/rd_data_r_2_51[23]/O
5.552 0.662 tNET FF 1 R26C27[0][A] u0_fifo48b_24b/rd_data_r_2_55[23]/I0
5.923 0.371 tINS FF 1 R26C27[0][A] u0_fifo48b_24b/rd_data_r_2_55[23]/F
6.413 0.490 tNET FF 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[23]/I0
6.784 0.371 tINS FF 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[23]/F
6.784 0.000 tNET FF 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r[23]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r[23]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[23]
6.499 -0.035 tSu 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r[23]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.956, 28.833%; route: 4.596, 67.747%; tC2Q: 0.232, 3.420%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack -0.255
Data Arrival Time 138.094
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A2
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
138.094 1.981 tNET FF 1 IOT7[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A2/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT7[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A2/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A2
137.839 0.000 tSu 1 IOT7[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A2

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.981, 89.517%; tC2Q: 0.232, 10.483%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path9

Path Summary:

Slack -0.167
Data Arrival Time 138.006
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A0
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
138.006 1.893 tNET FF 1 IOT4[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT4[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A0/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A0
137.839 0.000 tSu 1 IOT4[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A0

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.893, 89.084%; tC2Q: 0.232, 10.916%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path10

Path Summary:

Slack -0.069
Data Arrival Time 6.568
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep1_Z
To u0_fifo48b_24b/rd_data_r[19]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R34C34[2][A] u0_fifo48b_24b/rd_ptr_4_rep1_Z/CLK
0.232 0.232 tC2Q RF 11 R34C34[2][A] u0_fifo48b_24b/rd_ptr_4_rep1_Z/Q
1.207 0.975 tNET FF 1 R30C28[1][B] u0_fifo48b_24b/rd_data_r_2_11[19]/I2
1.660 0.453 tINS FF 1 R30C28[1][B] u0_fifo48b_24b/rd_data_r_2_11[19]/F
3.392 1.732 tNET FF 1 R31C30[1][A] u0_fifo48b_24b/rd_data_r_2_34[19]/I1
3.947 0.555 tINS FF 1 R31C30[1][A] u0_fifo48b_24b/rd_data_r_2_34[19]/F
3.947 0.000 tNET FF 1 R31C30[1][A] u0_fifo48b_24b/rd_data_r_2_45[19]/I0
4.050 0.103 tINS FF 1 R31C30[1][A] u0_fifo48b_24b/rd_data_r_2_45[19]/O
4.050 0.000 tNET FF 1 R31C30[0][B] u0_fifo48b_24b/rd_data_r_2_51[19]/I0
4.153 0.103 tINS FF 1 R31C30[0][B] u0_fifo48b_24b/rd_data_r_2_51[19]/O
5.478 1.325 tNET FF 1 R25C30[3][A] u0_fifo48b_24b/rd_data_r_2_55[19]/I0
5.849 0.371 tINS FF 1 R25C30[3][A] u0_fifo48b_24b/rd_data_r_2_55[19]/F
6.019 0.170 tNET FF 1 R25C31[0][B] u0_fifo48b_24b/rd_data_r_2_cZ[19]/I0
6.568 0.549 tINS FR 1 R25C31[0][B] u0_fifo48b_24b/rd_data_r_2_cZ[19]/F
6.568 0.000 tNET RR 1 R25C31[0][B] u0_fifo48b_24b/rd_data_r[19]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R25C31[0][B] u0_fifo48b_24b/rd_data_r[19]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[19]
6.499 -0.035 tSu 1 R25C31[0][B] u0_fifo48b_24b/rd_data_r[19]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.134, 32.489%; route: 4.202, 63.979%; tC2Q: 0.232, 3.532%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack -0.059
Data Arrival Time 6.558
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_0_rep1_rep2_Z
To u0_fifo48b_24b/rd_data_r[10]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R25C18[1][A] u0_fifo48b_24b/rd_ptr_0_rep1_rep2_Z/CLK
0.232 0.232 tC2Q RF 21 R25C18[1][A] u0_fifo48b_24b/rd_ptr_0_rep1_rep2_Z/Q
1.735 1.503 tNET FF 1 R21C30[1][B] u0_fifo48b_24b/rd_data_r_2_15[10]/I2
2.252 0.517 tINS FF 1 R21C30[1][B] u0_fifo48b_24b/rd_data_r_2_15[10]/F
2.252 0.000 tNET FF 1 R21C30[1][A] u0_fifo48b_24b/rd_data_r_2_34[10]/I1
2.355 0.103 tINS FF 1 R21C30[1][A] u0_fifo48b_24b/rd_data_r_2_34[10]/O
2.355 0.000 tNET FF 1 R21C30[0][B] u0_fifo48b_24b/rd_data_r_2_45[10]/I0
2.458 0.103 tINS FF 1 R21C30[0][B] u0_fifo48b_24b/rd_data_r_2_45[10]/O
4.980 2.522 tNET FF 1 R27C27[2][B] u0_fifo48b_24b/rd_data_r_2_51[10]/I1
5.497 0.517 tINS FF 1 R27C27[2][B] u0_fifo48b_24b/rd_data_r_2_51[10]/F
5.497 0.000 tNET FF 1 R27C27[2][A] u0_fifo48b_24b/rd_data_r_2_55[10]/I1
5.600 0.103 tINS FF 1 R27C27[2][A] u0_fifo48b_24b/rd_data_r_2_55[10]/O
6.096 0.496 tNET FF 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[10]/I0
6.558 0.462 tINS FR 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[10]/F
6.558 0.000 tNET RR 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r[10]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r[10]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[10]
6.499 -0.035 tSu 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r[10]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.805, 27.523%; route: 4.521, 68.939%; tC2Q: 0.232, 3.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack -0.058
Data Arrival Time 137.896
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A4
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
137.896 1.784 tNET FF 1 IOT14[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT14[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A4/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A4
137.839 0.000 tSu 1 IOT14[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A4

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.784, 88.490%; tC2Q: 0.232, 11.510%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path13

Path Summary:

Slack -0.050
Data Arrival Time 6.549
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep2_Z
To u0_fifo48b_24b/rd_data_r[8]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R35C26[0][B] u0_fifo48b_24b/rd_ptr_4_rep2_Z/CLK
0.232 0.232 tC2Q RF 40 R35C26[0][B] u0_fifo48b_24b/rd_ptr_4_rep2_Z/Q
1.848 1.616 tNET FF 1 R25C23[3][A] u0_fifo48b_24b/rd_data_r_2_17[8]/I2
2.301 0.453 tINS FF 1 R25C23[3][A] u0_fifo48b_24b/rd_data_r_2_17[8]/F
2.301 0.000 tNET FF 1 R25C23[3][A] u0_fifo48b_24b/rd_data_r_2_32[8]/I0
2.404 0.103 tINS FF 1 R25C23[3][A] u0_fifo48b_24b/rd_data_r_2_32[8]/O
4.501 2.098 tNET FF 1 R35C26[2][B] u0_fifo48b_24b/rd_data_r_2_48[8]/I0
4.954 0.453 tINS FF 1 R35C26[2][B] u0_fifo48b_24b/rd_data_r_2_48[8]/F
4.954 0.000 tNET FF 1 R35C26[2][A] u0_fifo48b_24b/rd_data_r_2_52[8]/I1
5.057 0.103 tINS FF 1 R35C26[2][A] u0_fifo48b_24b/rd_data_r_2_52[8]/O
5.057 0.000 tNET FF 1 R35C26[2][B] u0_fifo48b_24b/rd_data_r_2_56[8]/I1
5.160 0.103 tINS FF 1 R35C26[2][B] u0_fifo48b_24b/rd_data_r_2_56[8]/O
6.000 0.840 tNET FF 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[8]/I1
6.549 0.549 tINS FR 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[8]/F
6.549 0.000 tNET RR 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[8]
6.499 -0.035 tSu 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.764, 26.935%; route: 4.553, 69.523%; tC2Q: 0.232, 3.542%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 0.000
Data Arrival Time 6.499
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z
To u0_fifo48b_24b/rd_data_r[18]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R35C23[1][B] u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/CLK
0.232 0.232 tC2Q RF 11 R35C23[1][B] u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/Q
1.626 1.394 tNET FF 1 R20C30[3][A] u0_fifo48b_24b/rd_data_r_2_33[18]/S0
1.877 0.251 tINS FF 1 R20C30[3][A] u0_fifo48b_24b/rd_data_r_2_33[18]/O
3.129 1.252 tNET FF 1 R22C30[3][A] u0_fifo48b_24b/rd_data_r_2_46[18]/I1
3.582 0.453 tINS FF 1 R22C30[3][A] u0_fifo48b_24b/rd_data_r_2_46[18]/F
3.995 0.413 tNET FF 1 R21C31[2][A] u0_fifo48b_24b/rd_data_r_2_52[18]/I0
4.550 0.555 tINS FF 1 R21C31[2][A] u0_fifo48b_24b/rd_data_r_2_52[18]/F
4.550 0.000 tNET FF 1 R21C31[2][A] u0_fifo48b_24b/rd_data_r_2_54[18]/I0
4.653 0.103 tINS FF 1 R21C31[2][A] u0_fifo48b_24b/rd_data_r_2_54[18]/O
6.128 1.474 tNET FF 1 R22C22[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[18]/I0
6.499 0.371 tINS FF 1 R22C22[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[18]/F
6.499 0.000 tNET FF 1 R22C22[1][A] u0_fifo48b_24b/rd_data_r[18]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R22C22[1][A] u0_fifo48b_24b/rd_data_r[18]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[18]
6.499 -0.035 tSu 1 R22C22[1][A] u0_fifo48b_24b/rd_data_r[18]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.733, 26.667%; route: 4.534, 69.763%; tC2Q: 0.232, 3.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 0.004
Data Arrival Time 6.495
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_3_rep1_Z
To u0_fifo48b_24b/rd_data_r[5]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R34C33[0][B] u0_fifo48b_24b/rd_ptr_3_rep1_Z/CLK
0.232 0.232 tC2Q RF 12 R34C33[0][B] u0_fifo48b_24b/rd_ptr_3_rep1_Z/Q
2.050 1.818 tNET FF 1 R20C22[3][A] u0_fifo48b_24b/rd_data_r_2_24[5]/I2
2.567 0.517 tINS FF 1 R20C22[3][A] u0_fifo48b_24b/rd_data_r_2_24[5]/F
2.567 0.000 tNET FF 1 R20C22[3][A] u0_fifo48b_24b/rd_data_r_2_31[5]/I0
2.670 0.103 tINS FF 1 R20C22[3][A] u0_fifo48b_24b/rd_data_r_2_31[5]/O
4.039 1.370 tNET FF 1 R26C20[1][B] u0_fifo48b_24b/rd_data_r_2_45[5]/I0
4.492 0.453 tINS FF 1 R26C20[1][B] u0_fifo48b_24b/rd_data_r_2_45[5]/F
5.176 0.684 tNET FF 1 R31C19[1][B] u0_fifo48b_24b/rd_data_r_2_52[5]/I0
5.547 0.371 tINS FF 1 R31C19[1][B] u0_fifo48b_24b/rd_data_r_2_52[5]/F
5.547 0.000 tNET FF 1 R31C19[1][A] u0_fifo48b_24b/rd_data_r_2_56[5]/I1
5.650 0.103 tINS FF 1 R31C19[1][A] u0_fifo48b_24b/rd_data_r_2_56[5]/O
6.219 0.569 tNET FF 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[5]/S0
6.488 0.269 tINS FR 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[5]/O
6.495 0.007 tNET RR 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r[5]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[5]
6.499 -0.035 tSu 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r[5]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.816, 27.958%; route: 4.447, 68.470%; tC2Q: 0.232, 3.572%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 0.043
Data Arrival Time 137.796
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A5
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
137.796 1.683 tNET FF 1 IOT17[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A5/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT17[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A5/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A5
137.839 0.000 tSu 1 IOT17[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A5

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.683, 87.885%; tC2Q: 0.232, 12.115%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path17

Path Summary:

Slack 0.055
Data Arrival Time 6.444
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z
To u0_fifo48b_24b/rd_data_r[7]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R36C33[2][B] u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/CLK
0.232 0.232 tC2Q RF 13 R36C33[2][B] u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/Q
1.547 1.315 tNET FF 1 R25C28[1][A] u0_fifo48b_24b/rd_data_r_2_33[7]/S0
1.798 0.251 tINS FF 1 R25C28[1][A] u0_fifo48b_24b/rd_data_r_2_33[7]/O
4.437 2.639 tNET FF 1 R29C25[3][B] u0_fifo48b_24b/rd_data_r_2_48[7]/I0
4.992 0.555 tINS FF 1 R29C25[3][B] u0_fifo48b_24b/rd_data_r_2_48[7]/F
4.992 0.000 tNET FF 1 R29C25[3][A] u0_fifo48b_24b/rd_data_r_2_54[7]/I1
5.095 0.103 tINS FF 2 R29C25[3][A] u0_fifo48b_24b/rd_data_r_2_54[7]/O
5.960 0.865 tNET FF 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r_2_1_cZ[7]/I0
6.331 0.371 tINS FF 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r_2_1_cZ[7]/F
6.331 0.000 tNET FF 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[7]/I0
6.434 0.103 tINS FF 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[7]/O
6.444 0.010 tNET FF 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r[7]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[7]
6.499 -0.035 tSu 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r[7]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.383, 21.460%; route: 4.829, 74.940%; tC2Q: 0.232, 3.600%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 0.075
Data Arrival Time 6.424
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_fast_Z[3]
To u0_fifo48b_24b/rd_data_r[22]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R35C29[1][B] u0_fifo48b_24b/rd_ptr_fast_Z[3]/CLK
0.232 0.232 tC2Q RF 12 R35C29[1][B] u0_fifo48b_24b/rd_ptr_fast_Z[3]/Q
1.387 1.155 tNET FF 1 R27C22[1][B] u0_fifo48b_24b/rd_data_r_2_17[22]/I2
1.840 0.453 tINS FF 1 R27C22[1][B] u0_fifo48b_24b/rd_data_r_2_17[22]/F
2.087 0.247 tNET FF 1 R29C22[0][A] u0_fifo48b_24b/rd_data_r_2_43_1_cZ[22]/I1
2.642 0.555 tINS FF 1 R29C22[0][A] u0_fifo48b_24b/rd_data_r_2_43_1_cZ[22]/F
3.326 0.684 tNET FF 1 R35C21[3][B] u0_fifo48b_24b/rd_data_r_2_43[22]/I1
3.881 0.555 tINS FF 1 R35C21[3][B] u0_fifo48b_24b/rd_data_r_2_43[22]/F
3.881 0.000 tNET FF 1 R35C21[3][A] u0_fifo48b_24b/rd_data_r_2_50[22]/I1
3.984 0.103 tINS FF 1 R35C21[3][A] u0_fifo48b_24b/rd_data_r_2_50[22]/O
4.945 0.961 tNET FF 1 R25C29[1][A] u0_fifo48b_24b/rd_data_r_2_1_0[22]/I0
5.462 0.517 tINS FF 1 R25C29[1][A] u0_fifo48b_24b/rd_data_r_2_1_0[22]/F
5.875 0.413 tNET FF 1 R24C31[2][B] u0_fifo48b_24b/rd_data_r_2_cZ[22]/I1
6.424 0.549 tINS FR 1 R24C31[2][B] u0_fifo48b_24b/rd_data_r_2_cZ[22]/F
6.424 0.000 tNET RR 1 R24C31[2][B] u0_fifo48b_24b/rd_data_r[22]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R24C31[2][B] u0_fifo48b_24b/rd_data_r[22]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[22]
6.499 -0.035 tSu 1 R24C31[2][B] u0_fifo48b_24b/rd_data_r[22]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.732, 42.527%; route: 3.460, 53.862%; tC2Q: 0.232, 3.611%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 0.104
Data Arrival Time 137.735
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A3
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
137.735 1.623 tNET FF 1 IOT12[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A3/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT12[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A3/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A3
137.839 0.000 tSu 1 IOT12[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A3

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.623, 87.490%; tC2Q: 0.232, 12.510%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path20

Path Summary:

Slack 0.145
Data Arrival Time 6.354
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z
To u0_fifo48b_24b/rd_data_r[0]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R36C33[2][B] u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/CLK
0.232 0.232 tC2Q RF 13 R36C33[2][B] u0_fifo48b_24b/rd_ptr_5_rep1_fast_Z/Q
2.137 1.905 tNET FF 1 R25C23[2][A] u0_fifo48b_24b/rd_data_r_2_33[0]/S0
2.388 0.251 tINS FF 1 R25C23[2][A] u0_fifo48b_24b/rd_data_r_2_33[0]/O
4.077 1.689 tNET FF 1 R33C22[2][B] u0_fifo48b_24b/rd_data_r_2_48[0]/I0
4.448 0.371 tINS FF 1 R33C22[2][B] u0_fifo48b_24b/rd_data_r_2_48[0]/F
4.448 0.000 tNET FF 1 R33C22[2][A] u0_fifo48b_24b/rd_data_r_2_54[0]/I1
4.551 0.103 tINS FF 1 R33C22[2][A] u0_fifo48b_24b/rd_data_r_2_54[0]/O
5.213 0.662 tNET FF 1 R30C20[0][B] u0_fifo48b_24b/rd_data_r_2_1_0[0]/I0
5.783 0.570 tINS FR 1 R30C20[0][B] u0_fifo48b_24b/rd_data_r_2_1_0[0]/F
5.784 0.001 tNET RR 1 R30C20[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[0]/I1
6.354 0.570 tINS RR 1 R30C20[0][A] u0_fifo48b_24b/rd_data_r_2_cZ[0]/F
6.354 0.000 tNET RR 1 R30C20[0][A] u0_fifo48b_24b/rd_data_r[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R30C20[0][A] u0_fifo48b_24b/rd_data_r[0]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[0]
6.499 -0.035 tSu 1 R30C20[0][A] u0_fifo48b_24b/rd_data_r[0]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.865, 29.352%; route: 4.257, 66.997%; tC2Q: 0.232, 3.651%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack 0.172
Data Arrival Time 6.327
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_3_rep1_rep1_Z
To u0_fifo48b_24b/rd_data_r[16]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R34C34[0][A] u0_fifo48b_24b/rd_ptr_3_rep1_rep1_Z/CLK
0.232 0.232 tC2Q RF 12 R34C34[0][A] u0_fifo48b_24b/rd_ptr_3_rep1_rep1_Z/Q
1.633 1.401 tNET FF 1 R21C23[1][A] u0_fifo48b_24b/rd_data_r_2_sn_m9_1/I0
2.086 0.453 tINS FF 8 R21C23[1][A] u0_fifo48b_24b/rd_data_r_2_sn_m9_1/F
3.333 1.248 tNET FF 1 R34C30[2][B] u0_fifo48b_24b/rd_data_r_2_49[16]/S0
3.584 0.251 tINS FF 1 R34C30[2][B] u0_fifo48b_24b/rd_data_r_2_49[16]/O
4.743 1.159 tNET FF 1 R26C32[0][B] u0_fifo48b_24b/rd_data_r_2_53[16]/I1
5.205 0.462 tINS FR 1 R26C32[0][B] u0_fifo48b_24b/rd_data_r_2_53[16]/F
5.207 0.001 tNET RR 1 R26C32[2][B] u0_fifo48b_24b/rd_data_r_2_55[16]/I1
5.777 0.570 tINS RR 1 R26C32[2][B] u0_fifo48b_24b/rd_data_r_2_55[16]/F
5.778 0.001 tNET RR 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[16]/I0
6.327 0.549 tINS RR 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r_2_cZ[16]/F
6.327 0.000 tNET RR 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r[16]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r[16]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[16]
6.499 -0.035 tSu 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r[16]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.285, 36.114%; route: 3.810, 60.219%; tC2Q: 0.232, 3.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack 0.213
Data Arrival Time 137.625
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst8_IDDRX71A
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
137.625 1.513 tNET FF 1 IOR7[A] rx_inst/lvds_71_rx/Inst8_IDDRX71A/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOR7[A] rx_inst/lvds_71_rx/Inst8_IDDRX71A/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst8_IDDRX71A
137.839 0.000 tSu 1 IOR7[A] rx_inst/lvds_71_rx/Inst8_IDDRX71A

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.513, 86.703%; tC2Q: 0.232, 13.297%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Path23

Path Summary:

Slack 0.220
Data Arrival Time 6.279
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep1_Z
To u0_fifo48b_24b/rd_data_r[9]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R34C34[2][A] u0_fifo48b_24b/rd_ptr_4_rep1_Z/CLK
0.232 0.232 tC2Q RF 11 R34C34[2][A] u0_fifo48b_24b/rd_ptr_4_rep1_Z/Q
2.367 2.135 tNET FF 1 R25C24[1][B] u0_fifo48b_24b/rd_data_r_2_5[9]/I2
2.820 0.453 tINS FF 1 R25C24[1][B] u0_fifo48b_24b/rd_data_r_2_5[9]/F
2.820 0.000 tNET FF 1 R25C24[1][A] u0_fifo48b_24b/rd_data_r_2_32[9]/I1
2.923 0.103 tINS FF 1 R25C24[1][A] u0_fifo48b_24b/rd_data_r_2_32[9]/O
4.689 1.766 tNET FF 1 R31C25[2][B] u0_fifo48b_24b/rd_data_r_2_48[9]/I0
5.206 0.517 tINS FF 1 R31C25[2][B] u0_fifo48b_24b/rd_data_r_2_48[9]/F
5.206 0.000 tNET FF 1 R31C25[2][A] u0_fifo48b_24b/rd_data_r_2_52[9]/I1
5.309 0.103 tINS FF 1 R31C25[2][A] u0_fifo48b_24b/rd_data_r_2_52[9]/O
5.309 0.000 tNET FF 1 R31C25[2][B] u0_fifo48b_24b/rd_data_r_2_56[9]/I1
5.412 0.103 tINS FF 1 R31C25[2][B] u0_fifo48b_24b/rd_data_r_2_56[9]/O
5.908 0.496 tNET FF 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[9]/I1
6.279 0.371 tINS FF 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[9]/F
6.279 0.000 tNET FF 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r[9]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r[9]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[9]
6.499 -0.035 tSu 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r[9]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.650, 26.280%; route: 4.397, 70.025%; tC2Q: 0.232, 3.695%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack 0.276
Data Arrival Time 6.223
Data Required Time 6.499
From u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z
To u0_fifo48b_24b/rd_data_r[17]
Launch Clk clkop:[R]
Latch Clk clkop:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
0.000 0.000 tNET RR 1 R35C23[1][B] u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/CLK
0.232 0.232 tC2Q RF 11 R35C23[1][B] u0_fifo48b_24b/rd_ptr_4_rep1_rep2_Z/Q
1.719 1.487 tNET FF 1 R25C32[0][A] u0_fifo48b_24b/rd_data_r_2_sn_m14_1_xx_mm/I2
2.090 0.371 tINS FF 1 R25C32[0][A] u0_fifo48b_24b/rd_data_r_2_sn_m14_1_xx_mm/F
2.095 0.004 tNET FF 1 R25C32[0][B] u0_fifo48b_24b/rd_data_r_2_sn_m16_1/I0
2.466 0.371 tINS FF 8 R25C32[0][B] u0_fifo48b_24b/rd_data_r_2_sn_m16_1/F
4.028 1.563 tNET FF 1 R31C32[0][B] u0_fifo48b_24b/rd_data_r_2_53[17]/I2
4.583 0.555 tINS FF 1 R31C32[0][B] u0_fifo48b_24b/rd_data_r_2_53[17]/F
4.996 0.413 tNET FF 1 R32C31[2][A] u0_fifo48b_24b/rd_data_r_2_55[17]/I1
5.513 0.517 tINS FF 1 R32C31[2][A] u0_fifo48b_24b/rd_data_r_2_55[17]/F
5.761 0.247 tNET FF 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[17]/I1
6.223 0.462 tINS FR 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r_2_cZ[17]/F
6.223 0.000 tNET RR 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
6.734 0.000 tNET RR 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/CLK
6.534 -0.200 tUnc u0_fifo48b_24b/rd_data_r[17]
6.499 -0.035 tSu 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.734
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.276, 36.576%; route: 3.715, 59.695%; tC2Q: 0.232, 3.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack 0.282
Data Arrival Time 137.556
Data Required Time 137.839
From rx_inst/wd_aln_ctl_inst/slip
To rx_inst/lvds_71_rx/Inst7_IDDRX71A6
Launch Clk sclk:[R]
Latch Clk rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.680 134.680 active clock edge time
134.680 0.000 sclk(clock)
134.680 0.000 tCL RR 524 TOPSIDE[0] rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT
135.881 1.201 tNET RR 1 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/CLK
136.113 0.232 tC2Q RF 10 R18C36[2][A] rx_inst/wd_aln_ctl_inst/slip/Q
137.556 1.444 tNET FF 1 IOT23[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A6/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
134.921 134.921 active clock edge time
134.921 0.000 rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk(shadow)
134.921 0.000 tCL RR 1 PLL_R[0] rx_inst/lvds_71_rx/pll_inst/CLKOUTP
136.545 1.624 tNET RR 1 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/I0
136.872 0.327 tINS RR 10 R11C37[0][A] rx_inst/lvds_71_rx/eclk_cZ/F
138.239 1.367 tNET RR 1 IOT23[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A6/FCLK
137.839 -0.400 tUnc rx_inst/lvds_71_rx/Inst7_IDDRX71A6
137.839 0.000 tSu 1 IOT23[A] rx_inst/lvds_71_rx/Inst7_IDDRX71A6

Path Statistics:

Clock Skew 2.117
Setup Relationship 0.241
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.444, 86.154%; tC2Q: 0.232, 13.846%
Required Clock Path Delay cell: 0.327, 9.855%; route: 2.991, 90.145%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -3.455
Data Arrival Time 14.243
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[3]
To U_TX3/Inst5_ODDRX2E3
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R35C18[1][A] u0_fifo48b_24b/rd_data_r[3]/CLK
13.670 0.202 tC2Q RR 4 R35C18[1][A] u0_fifo48b_24b/rd_data_r[3]/Q
14.243 0.573 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E3
17.698 0.095 tHld 1 IOB20[A] U_TX3/Inst5_ODDRX2E3

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.573, 73.950%; tC2Q: 0.202, 26.050%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path2

Path Summary:

Slack -3.452
Data Arrival Time 14.247
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[4]
To U_TX3/Inst5_ODDRX2E4
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R35C20[2][A] u0_fifo48b_24b/rd_data_r[4]/CLK
13.670 0.202 tC2Q RR 4 R35C20[2][A] u0_fifo48b_24b/rd_data_r[4]/Q
14.247 0.577 tNET RR 1 IOB22[A] U_TX3/Inst5_ODDRX2E4/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB22[A] U_TX3/Inst5_ODDRX2E4/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E4
17.698 0.095 tHld 1 IOB22[A] U_TX3/Inst5_ODDRX2E4

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.577, 74.060%; tC2Q: 0.202, 25.940%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path3

Path Summary:

Slack -3.442
Data Arrival Time 14.244
Data Required Time 17.686
From u0_fifo48b_24b/rd_data_r[11]
To U_TX3/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/CLK
13.670 0.202 tC2Q RR 4 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/Q
14.244 0.574 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E5
17.686 0.083 tHld 1 IOB30[A] U_TX3/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.574, 73.985%; tC2Q: 0.202, 26.015%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path4

Path Summary:

Slack -3.319
Data Arrival Time 14.379
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[15]
To U_TX3/Inst5_ODDRX2E3
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R30C21[1][A] u0_fifo48b_24b/rd_data_r[15]/CLK
13.670 0.202 tC2Q RR 4 R30C21[1][A] u0_fifo48b_24b/rd_data_r[15]/Q
14.379 0.709 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E3
17.698 0.095 tHld 1 IOB20[A] U_TX3/Inst5_ODDRX2E3

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.709, 77.836%; tC2Q: 0.202, 22.164%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path5

Path Summary:

Slack -3.318
Data Arrival Time 14.381
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[1]
To U_TX3/Inst5_ODDRX2E1
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R36C20[1][A] u0_fifo48b_24b/rd_data_r[1]/CLK
13.670 0.202 tC2Q RR 4 R36C20[1][A] u0_fifo48b_24b/rd_data_r[1]/Q
14.381 0.711 tNET RR 1 IOB12[A] U_TX3/Inst5_ODDRX2E1/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB12[A] U_TX3/Inst5_ODDRX2E1/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E1
17.698 0.095 tHld 1 IOB12[A] U_TX3/Inst5_ODDRX2E1

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.711, 77.865%; tC2Q: 0.202, 22.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path6

Path Summary:

Slack -3.316
Data Arrival Time 14.382
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[17]
To U_TX3/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/CLK
13.670 0.202 tC2Q RR 4 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/Q
14.382 0.712 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E5
17.698 0.095 tHld 1 IOB30[A] U_TX3/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.712, 77.895%; tC2Q: 0.202, 22.105%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path7

Path Summary:

Slack -3.305
Data Arrival Time 14.394
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[5]
To U_TX3/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R31C20[1][A] u0_fifo48b_24b/rd_data_r[5]/CLK
13.670 0.202 tC2Q RR 4 R31C20[1][A] u0_fifo48b_24b/rd_data_r[5]/Q
14.394 0.724 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB30[A] U_TX3/Inst5_ODDRX2E5/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E5
17.698 0.095 tHld 1 IOB30[A] U_TX3/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.724, 78.179%; tC2Q: 0.202, 21.821%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path8

Path Summary:

Slack -3.304
Data Arrival Time 14.394
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[2]
To U_TX3/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/CLK
13.670 0.202 tC2Q RR 4 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/Q
14.394 0.724 tNET RR 1 IOB14[A] U_TX3/Inst5_ODDRX2E2/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB14[A] U_TX3/Inst5_ODDRX2E2/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E2
17.698 0.095 tHld 1 IOB14[A] U_TX3/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.724, 78.184%; tC2Q: 0.202, 21.816%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path9

Path Summary:

Slack -3.277
Data Arrival Time 14.409
Data Required Time 17.686
From u0_fifo48b_24b/rd_data_r[7]
To U_TX3/Inst5_ODDRX2E1
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R30C20[1][A] u0_fifo48b_24b/rd_data_r[7]/CLK
13.670 0.202 tC2Q RR 4 R30C20[1][A] u0_fifo48b_24b/rd_data_r[7]/Q
14.409 0.739 tNET RR 1 IOB12[A] U_TX3/Inst5_ODDRX2E1/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB12[A] U_TX3/Inst5_ODDRX2E1/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E1
17.686 0.083 tHld 1 IOB12[A] U_TX3/Inst5_ODDRX2E1

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.739, 78.531%; tC2Q: 0.202, 21.469%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path10

Path Summary:

Slack -3.238
Data Arrival Time 14.381
Data Required Time 17.618
From u0_fifo48b_24b/rd_data_r[23]
To U_TX0/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R26C31[0][A] u0_fifo48b_24b/rd_data_r[23]/CLK
13.670 0.202 tC2Q RR 4 R26C31[0][A] u0_fifo48b_24b/rd_data_r[23]/Q
14.381 0.711 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.234 2.766 tCL RR 7 TOPSIDE[1] U_TX0/Inst3_CLKDIVC/CLKOUT
17.135 0.902 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/PCLK
17.535 0.400 tUnc U_TX0/Inst5_ODDRX2E5
17.618 0.083 tHld 1 IOT30[A] U_TX0/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.667
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.711, 77.865%; tC2Q: 0.202, 22.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path11

Path Summary:

Slack -3.163
Data Arrival Time 14.381
Data Required Time 17.544
From u0_fifo48b_24b/rd_data_r[8]
To U_TX1/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/CLK
13.670 0.202 tC2Q RR 4 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/Q
14.381 0.711 tNET RR 1 IOR35[A] U_TX1/Inst5_ODDRX2E2/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.159 2.691 tCL RR 7 RIGHTSIDE[0] U_TX1/Inst3_CLKDIVC/CLKOUT
17.061 0.902 tNET RR 1 IOR35[A] U_TX1/Inst5_ODDRX2E2/PCLK
17.461 0.400 tUnc U_TX1/Inst5_ODDRX2E2
17.544 0.083 tHld 1 IOR35[A] U_TX1/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.593
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.711, 77.865%; tC2Q: 0.202, 22.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path12

Path Summary:

Slack -3.159
Data Arrival Time 14.543
Data Required Time 17.702
From u0_fifo48b_24b/rd_data_r[2]
To U_TX2/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/CLK
13.670 0.202 tC2Q RR 4 R32C24[2][A] u0_fifo48b_24b/rd_data_r[2]/Q
14.543 0.873 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E2
17.702 0.095 tHld 1 IOB38[A] U_TX2/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.873, 81.212%; tC2Q: 0.202, 18.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path13

Path Summary:

Slack -3.158
Data Arrival Time 14.544
Data Required Time 17.702
From u0_fifo48b_24b/rd_data_r[13]
To U_TX2/Inst5_ODDRX2E1
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R27C24[2][A] u0_fifo48b_24b/rd_data_r[13]/CLK
13.670 0.202 tC2Q RR 4 R27C24[2][A] u0_fifo48b_24b/rd_data_r[13]/Q
14.544 0.874 tNET RR 1 IOB34[A] U_TX2/Inst5_ODDRX2E1/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB34[A] U_TX2/Inst5_ODDRX2E1/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E1
17.702 0.095 tHld 1 IOB34[A] U_TX2/Inst5_ODDRX2E1

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.874, 81.230%; tC2Q: 0.202, 18.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path14

Path Summary:

Slack -3.158
Data Arrival Time 14.544
Data Required Time 17.702
From u0_fifo48b_24b/rd_data_r[1]
To U_TX2/Inst5_ODDRX2E1
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R36C20[1][A] u0_fifo48b_24b/rd_data_r[1]/CLK
13.670 0.202 tC2Q RR 4 R36C20[1][A] u0_fifo48b_24b/rd_data_r[1]/Q
14.544 0.874 tNET RR 1 IOB34[A] U_TX2/Inst5_ODDRX2E1/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB34[A] U_TX2/Inst5_ODDRX2E1/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E1
17.702 0.095 tHld 1 IOB34[A] U_TX2/Inst5_ODDRX2E1

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.874, 81.230%; tC2Q: 0.202, 18.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path15

Path Summary:

Slack -3.156
Data Arrival Time 14.530
Data Required Time 17.686
From u0_fifo48b_24b/rd_data_r[10]
To U_TX3/Inst5_ODDRX2E4
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R29C29[2][A] u0_fifo48b_24b/rd_data_r[10]/CLK
13.670 0.202 tC2Q RR 4 R29C29[2][A] u0_fifo48b_24b/rd_data_r[10]/Q
14.530 0.860 tNET RR 1 IOB22[A] U_TX3/Inst5_ODDRX2E4/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB22[A] U_TX3/Inst5_ODDRX2E4/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E4
17.686 0.083 tHld 1 IOB22[A] U_TX3/Inst5_ODDRX2E4

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.860, 80.977%; tC2Q: 0.202, 19.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path16

Path Summary:

Slack -3.156
Data Arrival Time 14.542
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[12]
To U_TX3/Inst5_ODDRX2E0
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R30C22[1][A] u0_fifo48b_24b/rd_data_r[12]/CLK
13.670 0.202 tC2Q RR 4 R30C22[1][A] u0_fifo48b_24b/rd_data_r[12]/Q
14.542 0.872 tNET RR 1 IOB6[A] U_TX3/Inst5_ODDRX2E0/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB6[A] U_TX3/Inst5_ODDRX2E0/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E0
17.698 0.095 tHld 1 IOB6[A] U_TX3/Inst5_ODDRX2E0

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.872, 81.191%; tC2Q: 0.202, 18.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path17

Path Summary:

Slack -3.152
Data Arrival Time 14.546
Data Required Time 17.698
From u0_fifo48b_24b/rd_data_r[14]
To U_TX3/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R30C21[2][B] u0_fifo48b_24b/rd_data_r[14]/CLK
13.670 0.202 tC2Q RR 4 R30C21[2][B] u0_fifo48b_24b/rd_data_r[14]/Q
14.546 0.876 tNET RR 1 IOB14[A] U_TX3/Inst5_ODDRX2E2/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB14[A] U_TX3/Inst5_ODDRX2E2/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E2
17.698 0.095 tHld 1 IOB14[A] U_TX3/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.876, 81.265%; tC2Q: 0.202, 18.735%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path18

Path Summary:

Slack -3.147
Data Arrival Time 14.543
Data Required Time 17.690
From u0_fifo48b_24b/rd_data_r[20]
To U_TX2/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R25C30[0][A] u0_fifo48b_24b/rd_data_r[20]/CLK
13.670 0.202 tC2Q RR 4 R25C30[0][A] u0_fifo48b_24b/rd_data_r[20]/Q
14.543 0.873 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E2
17.690 0.083 tHld 1 IOB38[A] U_TX2/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.873, 81.209%; tC2Q: 0.202, 18.791%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path19

Path Summary:

Slack -3.143
Data Arrival Time 14.543
Data Required Time 17.686
From u0_fifo48b_24b/rd_data_r[9]
To U_TX3/Inst5_ODDRX2E3
Launch Clk clkop:[R]
Latch Clk U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R27C25[1][A] u0_fifo48b_24b/rd_data_r[9]/CLK
13.670 0.202 tC2Q RR 4 R27C25[1][A] u0_fifo48b_24b/rd_data_r[9]/Q
14.543 0.873 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.301 2.833 tCL RR 7 BOTTOMSIDE[1] U_TX3/Inst3_CLKDIVC/CLKOUT
17.203 0.902 tNET RR 1 IOB20[A] U_TX3/Inst5_ODDRX2E3/PCLK
17.603 0.400 tUnc U_TX3/Inst5_ODDRX2E3
17.686 0.083 tHld 1 IOB20[A] U_TX3/Inst5_ODDRX2E3

Path Statistics:

Clock Skew 3.735
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.873, 81.212%; tC2Q: 0.202, 18.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path20

Path Summary:

Slack -3.143
Data Arrival Time 14.547
Data Required Time 17.690
From u0_fifo48b_24b/rd_data_r[8]
To U_TX2/Inst5_ODDRX2E2
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/CLK
13.670 0.202 tC2Q RR 4 R34C31[2][A] u0_fifo48b_24b/rd_data_r[8]/Q
14.547 0.877 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB38[A] U_TX2/Inst5_ODDRX2E2/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E2
17.690 0.083 tHld 1 IOB38[A] U_TX2/Inst5_ODDRX2E2

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.877, 81.284%; tC2Q: 0.202, 18.716%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path21

Path Summary:

Slack -3.129
Data Arrival Time 14.560
Data Required Time 17.690
From u0_fifo48b_24b/rd_data_r[11]
To U_TX2/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/CLK
13.670 0.202 tC2Q RR 4 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/Q
14.560 0.890 tNET RR 1 IOB48[A] U_TX2/Inst5_ODDRX2E5/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.305 2.837 tCL RR 7 BOTTOMSIDE[0] U_TX2/Inst3_CLKDIVC/CLKOUT
17.207 0.902 tNET RR 1 IOB48[A] U_TX2/Inst5_ODDRX2E5/PCLK
17.607 0.400 tUnc U_TX2/Inst5_ODDRX2E5
17.690 0.083 tHld 1 IOB48[A] U_TX2/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.739
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.890, 81.508%; tC2Q: 0.202, 18.492%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path22

Path Summary:

Slack -3.105
Data Arrival Time 14.513
Data Required Time 17.618
From u0_fifo48b_24b/rd_data_r[11]
To U_TX0/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/CLK
13.670 0.202 tC2Q RR 4 R31C32[0][A] u0_fifo48b_24b/rd_data_r[11]/Q
14.513 0.843 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.234 2.766 tCL RR 7 TOPSIDE[1] U_TX0/Inst3_CLKDIVC/CLKOUT
17.135 0.902 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/PCLK
17.535 0.400 tUnc U_TX0/Inst5_ODDRX2E5
17.618 0.083 tHld 1 IOT30[A] U_TX0/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.667
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.843, 80.678%; tC2Q: 0.202, 19.322%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path23

Path Summary:

Slack -3.099
Data Arrival Time 14.531
Data Required Time 17.630
From u0_fifo48b_24b/rd_data_r[17]
To U_TX0/Inst5_ODDRX2E5
Launch Clk clkop:[R]
Latch Clk U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/CLK
13.670 0.202 tC2Q RR 4 R34C31[1][A] u0_fifo48b_24b/rd_data_r[17]/Q
14.531 0.861 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.234 2.766 tCL RR 7 TOPSIDE[1] U_TX0/Inst3_CLKDIVC/CLKOUT
17.135 0.902 tNET RR 1 IOT30[A] U_TX0/Inst5_ODDRX2E5/PCLK
17.535 0.400 tUnc U_TX0/Inst5_ODDRX2E5
17.630 0.095 tHld 1 IOT30[A] U_TX0/Inst5_ODDRX2E5

Path Statistics:

Clock Skew 3.667
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.861, 80.998%; tC2Q: 0.202, 19.002%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path24

Path Summary:

Slack -3.097
Data Arrival Time 14.533
Data Required Time 17.630
From u0_fifo48b_24b/rd_data_r[16]
To U_TX0/Inst5_ODDRX2E4
Launch Clk clkop:[R]
Latch Clk U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R26C32[2][A] u0_fifo48b_24b/rd_data_r[16]/CLK
13.670 0.202 tC2Q RR 4 R26C32[2][A] u0_fifo48b_24b/rd_data_r[16]/Q
14.533 0.863 tNET RR 1 IOT38[A] U_TX0/Inst5_ODDRX2E4/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.234 2.766 tCL RR 7 TOPSIDE[1] U_TX0/Inst3_CLKDIVC/CLKOUT
17.135 0.902 tNET RR 1 IOT38[A] U_TX0/Inst5_ODDRX2E4/PCLK
17.535 0.400 tUnc U_TX0/Inst5_ODDRX2E4
17.630 0.095 tHld 1 IOT38[A] U_TX0/Inst5_ODDRX2E4

Path Statistics:

Clock Skew 3.667
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.863, 81.035%; tC2Q: 0.202, 18.965%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path25

Path Summary:

Slack -3.079
Data Arrival Time 14.539
Data Required Time 17.618
From u0_fifo48b_24b/rd_data_r[21]
To U_TX0/Inst5_ODDRX2E3
Launch Clk clkop:[R]
Latch Clk U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 clkop(clock)
13.468 0.000 tCL RR 118 PLL_L[0] pll_inst/CLKOUT
13.468 0.000 tNET RR 1 R22C28[0][A] u0_fifo48b_24b/rd_data_r[21]/CLK
13.670 0.202 tC2Q RR 4 R22C28[0][A] u0_fifo48b_24b/rd_data_r[21]/Q
14.539 0.869 tNET RR 1 IOT40[A] U_TX0/Inst5_ODDRX2E3/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk(shadow)
16.234 2.766 tCL RR 7 TOPSIDE[1] U_TX0/Inst3_CLKDIVC/CLKOUT
17.135 0.902 tNET RR 1 IOT40[A] U_TX0/Inst5_ODDRX2E3/PCLK
17.535 0.400 tUnc U_TX0/Inst5_ODDRX2E3
17.618 0.083 tHld 1 IOT40[A] U_TX0/Inst5_ODDRX2E3

Path Statistics:

Clock Skew 3.667
Hold Relationship 0.000
Logic Level 0
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.869, 81.148%; tC2Q: 0.202, 18.852%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: High Pulse Width
Clock: clkop
Objects: u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR pll_inst/CLKOUT
0.000 0.000 tNET RR u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z/CLK

MPW2

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR u0_fifo48b_24b/rd_ptr_5_rep2_rep2_Z/CLK

MPW3

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: High Pulse Width
Clock: clkop
Objects: u0_fifo48b_24b/rd_ptr_5_rep2_rep1_Z

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR pll_inst/CLKOUT
0.000 0.000 tNET RR u0_fifo48b_24b/rd_ptr_5_rep2_rep1_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF u0_fifo48b_24b/rd_ptr_5_rep2_rep1_Z/CLK

MPW4

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: u0_fifo48b_24b/rd_ptr_0_rep1_Z

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF u0_fifo48b_24b/rd_ptr_0_rep1_Z/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR u0_fifo48b_24b/rd_ptr_0_rep1_Z/CLK

MPW5

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: u0_fifo48b_24b/rd_data_r[4]

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF u0_fifo48b_24b/rd_data_r[4]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR u0_fifo48b_24b/rd_data_r[4]/CLK

MPW6

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: U_TX2/opensync_Z[0]

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF U_TX2/opensync_Z[0]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR U_TX2/opensync_Z[0]/CLK

MPW7

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: High Pulse Width
Clock: clkop
Objects: U_TX3/opensync_Z[3]

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clkop(clock)
0.000 0.000 tCL RR pll_inst/CLKOUT
0.000 0.000 tNET RR U_TX3/opensync_Z[3]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF U_TX3/opensync_Z[3]/CLK

MPW8

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: U_TX3/opensync_Z[0]

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF U_TX3/opensync_Z[0]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR U_TX3/opensync_Z[0]/CLK

MPW9

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: U_TX3/opensync_Z[3]

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF U_TX3/opensync_Z[3]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR U_TX3/opensync_Z[3]/CLK

MPW10

MPW Summary:

Slack: 2.367
Actual Width: 3.367
Required Width: 1.000
Type: Low Pulse Width
Clock: clkop
Objects: U_TX3/opensync_Z[2]

Late clock Path:

AT DELAY TYPE RF NODE
3.367 0.000 active clock edge time
3.367 0.000 clkop(clock)
3.367 0.000 tCL FF pll_inst/CLKOUT
3.367 0.000 tNET FF U_TX3/opensync_Z[2]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 clkop(clock)
6.734 0.000 tCL RR pll_inst/CLKOUT
6.734 0.000 tNET RR U_TX3/opensync_Z[2]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
524 sclk -0.333 1.228
118 clkop -0.726 1.223
92 rd_ptr[0] 0.626 2.285
72 un14_rd_ptr 0.939 2.001
68 rd_ptr_1_rep2 0.575 1.298
64 rd_ptr[5] 0.579 1.935
59 rd_ptr[3] 0.290 3.056
52 rd_ptr[2] 0.222 2.384
49 rd_ptr_2_rep2 0.433 2.099
45 wr_ptr[1] 10.991 1.534

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R22C22 0.875
R30C27 0.861
R31C27 0.847
R22C24 0.847
R26C25 0.847
R22C28 0.847
R21C22 0.833
R26C22 0.833
R20C26 0.833
R22C29 0.833

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name sclk -period 13.468 -waveform {0 6.734} [get_nets {sclk}]
TC_CLOCK Actived create_clock -name clkop -period 6.734 -waveform {0 3.367} [get_nets {clkop}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sclk}] -to [get_clocks {clkop}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clkop}] -to [get_clocks {sclk}]