Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\LVDS_RX\data\lvds_7to1_rx_top.v D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\LVDS_RX\data\lvds_7to1_rx_wrapper.vp |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Mon Mar 08 17:00:21 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | LVDS_7to1_RX_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 35.102MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.102MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.102MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 35.102MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 35.102MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.102MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 35.102MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.102MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 35.102MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.102MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 35.102MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 35.102MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.074MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 51.074MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 51.074MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 51.074MB |
Resource
Resource Usage Summary
| I/O Port | 39 |
| I/O Buf | 34 |
| IBUF | 1 |
| OBUF | 28 |
| TLVDS_IBUF | 5 |
| Register | 129 |
| DFFP | 1 |
| DFFC | 55 |
| DFFCE | 71 |
| DLC | 2 |
| LUT | 223 |
| LUT2 | 36 |
| LUT3 | 54 |
| LUT4 | 133 |
| ALU | 24 |
| ALU | 24 |
| INV | 4 |
| INV | 4 |
| IOLOGIC | 9 |
| IVIDEO | 5 |
| IODELAY | 4 |
| CLOCK | 2 |
| CLKDIV | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Logic | 251(227 LUTs, 24 ALUs) / 20736 | 1% |
| Register | 129 / 16173 | 1% |
| --Register as Latch | 2 / 16173 | 1% |
| --Register as FF | 127 / 16173 | 1% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_clkin_p | Base | 11.976 | 83.5 | 0.000 | 5.988 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I | ||
| lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 3.422 | 292.3 | 0.000 | 1.711 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I | I_clkin_p | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUT |
| lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 3.422 | 292.3 | 0.642 | 2.352 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I | I_clkin_p | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 6.843 | 146.1 | 0.000 | 3.422 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I | I_clkin_p | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTD |
| lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 10.265 | 97.4 | 0.000 | 5.133 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I | I_clkin_p | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTD3 |
| lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk | Generated | 11.976 | 83.5 | 0.642 | 6.630 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk | 83.5(MHz) | 243.8(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.932 |
| Data Arrival Time | 0.862 |
| Data Required Time | 1.794 |
| From | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| To | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| Launch Clk | I_clkin_p[R] |
| Latch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clkin_p | |||
| 0.000 | 0.000 | tCL | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I |
| 0.683 | 0.683 | tINS | RR | 2 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/O |
| 0.863 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.642 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 1.668 | 1.027 | tCL | RR | 6 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| 1.848 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A/FCLK |
| 1.813 | -0.035 | tUnc | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A | ||
| 1.794 | -0.019 | tSu | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| Clock Skew: | 0.524 |
| Setup Relationship: | 0.642 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.683, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.180, 100.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | 0.987 |
| Data Arrival Time | 12.839 |
| Data Required Time | 13.825 |
| From | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| To | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| Launch Clk | I_clkin_p[F] |
| Latch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 11.976 | 0.000 | I_clkin_p | |||
| 11.976 | 0.000 | tCL | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/I |
| 12.659 | 0.683 | tINS | RR | 2 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/IB_clk_inst/O |
| 12.839 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.618 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 13.644 | 1.027 | tCL | FF | 6 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| 13.881 | 0.237 | tNET | FF | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A/FCLK |
| 13.846 | -0.035 | tUnc | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A | ||
| 13.825 | -0.021 | tSu | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst8_IDDRX71A |
| Clock Skew: | 0.581 |
| Setup Relationship: | 0.642 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.683, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.180, 100.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Path 3
Path Summary:| Slack | 2.063 |
| Data Arrival Time | 13.437 |
| Data Required Time | 15.500 |
| From | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1 |
| To | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A0 |
| Launch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.618 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk | |||
| 12.788 | 0.170 | tCL | RR | 133 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT |
| 12.968 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/CLK |
| 13.200 | 0.232 | tC2Q | RF | 5 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/Q |
| 13.437 | 0.237 | tNET | FF | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A0/CALIB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 14.328 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 15.355 | 1.027 | tCL | RR | 6 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| 15.535 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A0/FCLK |
| 15.500 | -0.035 | tUnc | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A0 | ||
| 15.500 | 0.000 | tSu | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A0 |
| Clock Skew: | 0.856 |
| Setup Relationship: | 1.711 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | 2.063 |
| Data Arrival Time | 13.437 |
| Data Required Time | 15.500 |
| From | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1 |
| To | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A1 |
| Launch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.618 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk | |||
| 12.788 | 0.170 | tCL | RR | 133 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT |
| 12.968 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/CLK |
| 13.200 | 0.232 | tC2Q | RF | 5 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/Q |
| 13.437 | 0.237 | tNET | FF | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A1/CALIB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 14.328 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 15.355 | 1.027 | tCL | RR | 6 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| 15.535 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A1/FCLK |
| 15.500 | -0.035 | tUnc | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A1 | ||
| 15.500 | 0.000 | tSu | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A1 |
| Clock Skew: | 0.856 |
| Setup Relationship: | 1.711 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | 2.063 |
| Data Arrival Time | 13.437 |
| Data Required Time | 15.500 |
| From | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1 |
| To | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A2 |
| Launch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.618 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT.default_gen_clk | |||
| 12.788 | 0.170 | tCL | RR | 133 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst6_CLKDIVC/CLKOUT |
| 12.968 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/CLK |
| 13.200 | 0.232 | tC2Q | RF | 5 | lvds_7to1_rx_wrapper_inst/word_align_ctl_inst/slip_s1/Q |
| 13.437 | 0.237 | tNET | FF | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A2/CALIB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 14.328 | 0.000 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 15.355 | 1.027 | tCL | RR | 6 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/rpll_inst/CLKOUTP |
| 15.535 | 0.180 | tNET | RR | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A2/FCLK |
| 15.500 | -0.035 | tUnc | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A2 | ||
| 15.500 | 0.000 | tSu | 1 | lvds_7to1_rx_wrapper_inst/LVDS71RX_1CLK8DATA_inst/Inst7_IDDRX71A2 |
| Clock Skew: | 0.856 |
| Setup Relationship: | 1.711 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |