Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\LVDS_TX\data\lvds_7to1_tx_top.v D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\LVDS_TX\data\lvds_7to1_tx_wrapper.vp |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Mon Mar 08 15:52:36 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | LVDS_7to1_TX_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 34.164MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 34.164MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.164MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 46.938MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 46.938MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.938MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.938MB |
Resource
Resource Usage Summary
I/O Port | 39 |
I/O Buf | 34 |
    IBUF | 29 |
    TLVDS_OBUF | 5 |
LUT | 1 |
    LUT2 | 1 |
IOLOGIC | 5 |
    OVIDEO | 5 |
CLOCK | 1 |
    rPLL | 1 |
Resource Utilization Summary
Logic | 1(1 LUTs, 0 ALUs) / 20736 | 1% |
Register | 0 / 16173 | 0% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 0 / 16173 | 0% |
BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_pix_clk | Base | 11.976 | 83.5 | 0.000 | 5.988 | I_pix_clk_ibuf/I | ||
lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 3.422 | 292.3 | 0.000 | 1.711 | I_pix_clk_ibuf/I | I_pix_clk | lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUT |
lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 3.422 | 292.3 | 0.000 | 1.711 | I_pix_clk_ibuf/I | I_pix_clk | lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTP |
lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 6.843 | 146.1 | 0.000 | 3.422 | I_pix_clk_ibuf/I | I_pix_clk | lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTD |
lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 10.265 | 97.4 | 0.000 | 5.133 | I_pix_clk_ibuf/I | I_pix_clk | lvds_7to1_tx_wrapper_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
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