Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7Beta_GowinSynthesis-only\IDE\ipcore\MIPI_TX_Advance\data\DPHY_TX.v
C:\Gowin\Gowin_V1.9.7Beta_GowinSynthesis-only\IDE\ipcore\MIPI_TX_Advance\data\DPHY_TX_TOP.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Thu Nov 12 10:48:40 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: MIPI_TX_Advance_Top
Part Number: GW1N-LV9PG256C5/I4
Device: GW1N-9

Resource

Resource Usage Summary

I/O Port 96
I/O Buf 90
    IBUF 85
    ELVDS_TBUF 5
INV 2
    INV 2
IOLOGIC 5
    OSER16 5

Resource Utilization Summary

Logic 2(2 LUTs, 0 ALUs) / 8640 1%
Register 0 / 7104 0%
BSRAM 0 / 26 0%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sclk Base 10.000 100.0 0.000 5.000 sclk_ibuf/I
clk_bit_90 Base 10.000 100.0 0.000 5.000 clk_bit_90_ibuf/I
clk_bit Base 10.000 100.0 0.000 5.000 clk_bit_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity

No timing path found in the netlist.


Synthesis completed successfully!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
Memory peak: 37.3MB