Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\V1.9.7.05\Gowin_MIPI_DPHY_Advance_refDesign\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign\src\DPHY_TOP.v
E:\myWork\IP\releaseVerify\V1.9.7.05\Gowin_MIPI_DPHY_Advance_refDesign\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign\src\ROM549X17.v
E:\myWork\IP\releaseVerify\V1.9.7.05\Gowin_MIPI_DPHY_Advance_refDesign\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign\src\mipi_rx_advance\mipi_rx_advance.v
E:\myWork\IP\releaseVerify\V1.9.7.05\Gowin_MIPI_DPHY_Advance_refDesign\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign\src\mipi_tx_advance\mipi_tx_advance.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.05Beta
Part Number GW1N-LV9PG256C6/I5
Device GW1N-9
Created Time Tue May 11 15:51:50 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DPHY_TOP
Synthesis Process Running parser:
    CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.492s, Peak memory usage = 249.418MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 249.418MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 249.418MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 249.418MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 249.418MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 249.418MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 249.418MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 249.418MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 249.418MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 249.418MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 249.418MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.71s, Peak memory usage = 249.418MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 249.418MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 249.418MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 249.418MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 26
I/O Buf 16
    IBUF 2
    OBUF 4
    ELVDS_IBUF 5
    ELVDS_TBUF 5
Register 837
    DFF 8
    DFFR 3
    DFFPE 1
    DFFC 746
    DFFCE 79
LUT 1531
    LUT2 122
    LUT3 202
    LUT4 1207
ALU 9
    ALU 9
INV 5
    INV 5
IOLOGIC 13
    IDES16 4
    OSER16 5
    IODELAY 4
CLOCK 4
    CLKDIV 2
    DHCEN 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1545(1536 LUTs, 9 ALUs) / 8640 18%
Register 837 / 7104 12%
  --Register as Latch 0 / 7104 0%
  --Register as FF 837 / 7104 12%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clkx2x4 Base 20.000 50.0 0.000 10.000 clkx2x4_ibuf/I
HS_CLK_RX_P Base 10.000 100.0 0.000 5.000 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
pll_mipi_tx/CLKOUT.default_gen_clk Generated 2.500 400.0 0.000 1.250 clkx2x4_ibuf/I clkx2x4 pll_mipi_tx/CLKOUT
pll_mipi_tx/CLKOUTP.default_gen_clk Generated 2.500 400.0 0.625 1.875 clkx2x4_ibuf/I clkx2x4 pll_mipi_tx/CLKOUTP
pll_mipi_tx/CLKOUTD.default_gen_clk Generated 5.000 200.0 0.000 2.500 clkx2x4_ibuf/I clkx2x4 pll_mipi_tx/CLKOUTD
pll_mipi_tx/CLKOUTD3.default_gen_clk Generated 7.500 133.3 0.000 3.750 clkx2x4_ibuf/I clkx2x4 pll_mipi_tx/CLKOUTD3
u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 80.000 12.5 0.000 40.000 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I HS_CLK_RX_P u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
U3_CLKDIV/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 pll_mipi_tx/CLKOUT pll_mipi_tx/CLKOUT.default_gen_clk U3_CLKDIV/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HS_CLK_RX_P 100.0(MHz) 210.6(MHz) 2 TOP
2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 12.5(MHz) 131.8(MHz) 5 TOP
3 U3_CLKDIV/CLKOUT.default_gen_clk 50.0(MHz) 164.6(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.626
Data Arrival Time 3.585
Data Required Time 6.211
From u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk HS_CLK_RX_P[F]
Latch Clk HS_CLK_RX_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_RX_P
0.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
0.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
1.803 0.458 tC2Q RF 2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
2.283 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2
3.105 0.822 tINS FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
3.585 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 HS_CLK_RX_P
5.000 0.000 tCL FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
5.984 0.984 tINS FF 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.464 0.480 tNET FF 3 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
6.211 -0.254 tSu 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Path Statistics:
Clock Skew: 0.120
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.822, 36.691%; route: 0.960, 42.851%; tC2Q: 0.458, 20.458%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 7.853
Data Arrival Time 3.448
Data Required Time 11.302
From u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK_RX_P[R]
Latch Clk HS_CLK_RX_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_RX_P
0.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
0.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.803 0.458 tC2Q RF 2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.283 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.085 0.802 tINS FR 4 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.448 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_RX_P
10.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
10.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
11.302 -0.043 tSu 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.802, 38.130%; route: 0.843, 40.079%; tC2Q: 0.458, 21.791%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 7.853
Data Arrival Time 3.448
Data Required Time 11.302
From u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK_RX_P[R]
Latch Clk HS_CLK_RX_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_RX_P
0.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
0.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.803 0.458 tC2Q RF 2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.283 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.085 0.802 tINS FR 4 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.448 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_RX_P
10.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
10.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
11.302 -0.043 tSu 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.802, 38.130%; route: 0.843, 40.079%; tC2Q: 0.458, 21.791%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 7.853
Data Arrival Time 3.448
Data Required Time 11.302
From u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK_RX_P[R]
Latch Clk HS_CLK_RX_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_RX_P
0.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
0.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.803 0.458 tC2Q RF 2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.283 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.085 0.802 tINS FR 4 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.448 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_RX_P
10.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
10.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
11.302 -0.043 tSu 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.802, 38.130%; route: 0.843, 40.079%; tC2Q: 0.458, 21.791%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 7.853
Data Arrival Time 3.448
Data Required Time 11.302
From u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK_RX_P[R]
Latch Clk HS_CLK_RX_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_RX_P
0.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
0.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.803 0.458 tC2Q RF 2 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.283 0.480 tNET FF 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.085 0.802 tINS FR 4 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.448 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_RX_P
10.000 0.000 tCL RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
10.982 0.982 tINS RR 5 u_MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.345 0.363 tNET RR 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
11.302 -0.043 tSu 1 u_MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.802, 38.130%; route: 0.843, 40.079%; tC2Q: 0.458, 21.791%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%