Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX_TOP.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.05Beta
Part Number GW1N-LV9PG256C5/I4
Device GW1N-9
Created Time Tue May 11 15:07:38 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module MIPI_RX_Advance_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 1s, Peak memory usage = 40.527MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 40.527MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 40.527MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 40.527MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 40.527MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 40.527MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 40.527MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 40.527MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 40.527MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 40.527MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 40.527MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 40.527MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 55.859MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.156s, Peak memory usage = 55.859MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 55.859MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 55.859MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 80
I/O Buf 73
    IBUF 2
    OBUF 66
    ELVDS_IBUF 5
Register 741
    DFFPE 1
    DFFC 661
    DFFCE 79
LUT 1481
    LUT2 119
    LUT3 192
    LUT4 1170
INV 1
    INV 1
IOLOGIC 8
    IDES16 4
    IODELAY 4
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1482(1482 LUTs, 0 ALUs) / 8640 17%
Register 741 / 7104 10%
  --Register as Latch 0 / 7104 0%
  --Register as FF 741 / 7104 10%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HS_CLK_P Base 10.000 100.0 0.000 5.000 DPHY_RX_INST/U0_IB/I
DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 80.000 12.5 0.000 40.000 DPHY_RX_INST/U0_IB/I HS_CLK_P DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HS_CLK_P 100.0(MHz) 168.5(MHz) 2 TOP
2 DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 12.5(MHz) 105.4(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.032
Data Arrival Time 4.482
Data Required Time 6.513
From DPHY_RX_INST/u_idesx8/opensync_1_s0
To DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk HS_CLK_P[F]
Latch Clk HS_CLK_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_P
0.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
1.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
1.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
2.254 0.573 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
2.854 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_0/I2
3.882 1.028 tINS FF 1 DPHY_RX_INST/u_idesx8/LUT4_0/F
4.482 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/u_DHCEN/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 HS_CLK_P
5.000 0.000 tCL FF 1 DPHY_RX_INST/U0_IB/I
6.230 1.230 tINS FF 5 DPHY_RX_INST/U0_IB/O
6.830 0.600 tNET FF 3 DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
6.513 -0.317 tSu 1 DPHY_RX_INST/u_idesx8/u_DHCEN
Path Statistics:
Clock Skew: 0.149
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 1.028, 36.691%; route: 1.200, 42.851%; tC2Q: 0.573, 20.458%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 2

Path Summary:
Slack 7.317
Data Arrival Time 4.310
Data Required Time 11.627
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_P
0.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
1.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
1.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.254 0.573 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.854 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.857 1.002 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
4.310 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_P
10.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
11.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
11.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
11.627 -0.054 tSu 1 DPHY_RX_INST/u_idesx8/opensync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 1.002, 38.130%; route: 1.054, 40.079%; tC2Q: 0.573, 21.791%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 3

Path Summary:
Slack 7.317
Data Arrival Time 4.310
Data Required Time 11.627
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_P
0.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
1.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
1.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.254 0.573 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.854 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.857 1.002 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
4.310 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_P
10.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
11.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
11.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
11.627 -0.054 tSu 1 DPHY_RX_INST/u_idesx8/opensync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 1.002, 38.130%; route: 1.054, 40.079%; tC2Q: 0.573, 21.791%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 4

Path Summary:
Slack 7.317
Data Arrival Time 4.310
Data Required Time 11.627
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_P
0.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
1.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
1.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.254 0.573 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.854 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.857 1.002 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
4.310 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_P
10.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
11.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
11.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
11.627 -0.054 tSu 1 DPHY_RX_INST/u_idesx8/opensync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 1.002, 38.130%; route: 1.054, 40.079%; tC2Q: 0.573, 21.791%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%

Path 5

Path Summary:
Slack 7.317
Data Arrival Time 4.310
Data Required Time 11.627
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HS_CLK_P
0.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
1.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
1.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.254 0.573 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.854 0.600 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
3.857 1.002 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
4.310 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HS_CLK_P
10.000 0.000 tCL RR 1 DPHY_RX_INST/U0_IB/I
11.227 1.227 tINS RR 5 DPHY_RX_INST/U0_IB/O
11.681 0.454 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
11.627 -0.054 tSu 1 DPHY_RX_INST/u_idesx8/opensync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%
Arrival Data Path Delay: cell: 1.002, 38.130%; route: 1.054, 40.079%; tC2Q: 0.573, 21.791%
Required Clock Path Delay: cell: 1.227, 73.009%; route: 0.454, 26.991%