@N: CD630 :"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\src\nlms_adaptive_filter\temp\NLMS_Adaptive_Filter\rev_1\syntmp\gentmp4998a14120":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a14120":696:7:696:11|Synthesizing work.smult.cell_level.
@W: CD638 :"syng0a14120":751:8:751:13|Signal result is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"syng0a14120":523:7:523:15|Synthesizing work.smallmult.arch1.
@W: CD285 :"syng0a14120":662:7:662:11|Port map width mismatch (18 => 36) on port B of component FirstProducts 
@W: CD285 :"syng0a14120":661:7:661:11|Port map width mismatch (36 => 18) on port A of component FirstProducts 
@N: CD630 :"syng0a14120":319:7:319:16|Synthesizing work.addertree2.arch1.
@N: CD630 :"syng0a14120":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a14120":58:10:58:16|Synthesizing work.pipebuf.syn_black_box.
Post processing for work.pipebuf.syn_black_box
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a14120":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a14120":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a14120":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a14120":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a14120":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
Post processing for work.addertree2.arch1
Running optimization stage 1 on adderTree2 .......
@N: CD630 :"syng0a14120":17:7:17:19|Synthesizing work.firstproducts.arch1.
@W: CD638 :"syng0a14120":32:10:32:14|Signal a_aux is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"syng0a14120":33:10:33:14|Signal b_aux is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.firstproducts.arch1
Running optimization stage 1 on FirstProducts .......
Post processing for work.smallmult.arch1
Running optimization stage 1 on smallMult .......
Post processing for work.smult.cell_level
Running optimization stage 1 on SMULT .......
Post processing for work.top.gen
Running optimization stage 1 on top .......
Running optimization stage 2 on FirstProducts .......
Running optimization stage 2 on addreg_54_18_1_18_1 .......
Running optimization stage 2 on addreg_52_18_2_18_1 .......
Running optimization stage 2 on addreg_50_18_3_18_1 .......
Running optimization stage 2 on addreg_48_18_4_18_1 .......
Running optimization stage 2 on addreg_46_18_5_18_1 .......
Running optimization stage 2 on addreg_44_18_6_18_1 .......
Running optimization stage 2 on addreg_42_18_7_18_1 .......
Running optimization stage 2 on addreg_40_18_8_18_1 .......
Running optimization stage 2 on addreg_38_18_9_18_1 .......
Running optimization stage 2 on floor_1008_504_18_18_1 .......
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 969 to 953 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 912 to 896 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 855 to 841 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 798 to 784 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 741 to 729 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 684 to 672 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 627 to 617 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 570 to 560 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 513 to 505 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 456 to 448 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 399 to 393 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 342 to 336 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 285 to 281 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 228 to 224 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 171 to 169 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 114 to 112 of input(1007 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 57 of input(1007 downto 0) is unused 
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 0 of input(1007 downto 0) is unused 
Running optimization stage 2 on addreg_53_18_1_9_2 .......
Running optimization stage 2 on addreg_49_18_2_9_2 .......
Running optimization stage 2 on addreg_45_18_3_9_2 .......
Running optimization stage 2 on addreg_41_18_4_9_2 .......
Running optimization stage 2 on floor_504_280_9_18_2 .......
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 406 to 393 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 348 to 336 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 290 to 281 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 232 to 224 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 174 to 169 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 116 to 112 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 58 to 57 of input(503 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 0 of input(503 downto 0) is unused 
Running optimization stage 2 on addreg_51_18_1_5_3 .......
Running optimization stage 2 on addreg_43_18_2_5_3 .......
Running optimization stage 2 on floor_280_168_5_18_3 .......
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 180 to 169 of input(279 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 120 to 112 of input(279 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 60 to 57 of input(279 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 0 of input(279 downto 0) is unused 
Running optimization stage 2 on addreg_47_18_1_3_4 .......
Running optimization stage 2 on floor_168_112_3_18_4 .......
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 64 to 57 of input(167 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 0 of input(167 downto 0) is unused 
Running optimization stage 2 on addreg_39_18_1_2_5 .......
Running optimization stage 2 on floor_112_56_2_18_5 .......
@W: CL246 :"syng0a14120":172:4:172:8|Input port bits 72 to 57 of input(111 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a14120":172:4:172:8|Input port bit 0 of input(111 downto 0) is unused 
Running optimization stage 2 on adderTree2 .......
Running optimization stage 2 on smallMult .......
Running optimization stage 2 on SMULT .......
Running optimization stage 2 on top .......
