//`define 
`timescale 1ns / 1ps

module tb();
parameter idata_width = 18;
//--------------I/O PORT of basic_FIR_top-------------
reg clkin = 0;
reg key_begin_n = 1;
reg key_rst_n = 1;
reg key_ini_n = 1;
wire done;
wire input_rdy;
wire signed [idata_width - 1 : 0] o_err;
wire signed [idata_width - 1 : 0] out_err_gather;

always #10 clkin=~clkin;

GSR GSR(1'b1);

initial begin
    # 100000;
    # 100;
    key_rst_n = 0;
    # 10000;
    key_rst_n = 1;
    # 1000;
    key_ini_n = 0;
    # 50000;
    key_ini_n = 1;
    # 1000;
    key_begin_n =0;
    # 10000;
    key_begin_n =1;
    # 30000000;
    $finish;
end

//--------------fir_onboard---------------

nlms_example_top 
	#(.sim_en(1))
uut_nlms_onboard(
    .clkin(clkin),
    .key_begin_n(key_begin_n),
    .o_err(o_err),
    .done(done),
    .key_ini_n(key_ini_n),
    .key_rst_n(key_rst_n),
    .input_rdy(input_rdy),
    .out_err_gather(out_err_gather)
    );
initial begin
    $fsdbDumpfile("tb.fsdb");
    $fsdbDumpvars;
end

endmodule