`

    #Build: Synplify Pro (R) O-2018.09G-SP1, Build 099R, Feb 12 2019
    #install: C:\Gowin\1.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-049

    # Mon Mar  4 15:08:37 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\gw_ao_expression.v" (library work)
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
    @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
    @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
    @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
    @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
    @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
    @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
    @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
    @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
    @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
    @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
    @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
    @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
    @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
    @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
    @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
    @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
    @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
    @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
    @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
    @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
    @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top_0
    Running optimization stage 1 on ao_mem_ctrl_0_1024s_33s_10s .......
    Running optimization stage 1 on ao_crc32_0 .......
    Running optimization stage 1 on ao_match_0_0s_1s_33s_0_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_match_0_0s_13s_33s_0_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_top_0 .......
    Running optimization stage 2 on ao_match_0_0s_13s_33s_0_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_match_0_0s_1s_33s_0_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_top_0 .......
    Extracted state machine for register module_state
    State machine has 11 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1001
       1010
       1011
    Running optimization stage 2 on ao_crc32_0 .......
    Running optimization stage 2 on ao_mem_ctrl_0_1024s_33s_10s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 79MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:38 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:38 2019

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:38 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:40 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Mar  4 15:08:40 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    @N:MF284 :  | Setting synthesis effort to medium for the design
    Linked File:  ao_0_scck.rpt
    Printing clock  summary report in "E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\rev_1\ao_0_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 103MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
    original code -> new code
       0000 -> 00000000001
       0001 -> 00000000010
       0010 -> 00000000100
       0011 -> 00000001000
       0100 -> 00000010000
       0101 -> 00000100000
       0110 -> 00001000000
       0111 -> 00010000000
       1001 -> 00100000000
       1010 -> 01000000000
       1011 -> 10000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)

    Clock Summary
    ******************

              Start                   Requested     Requested     Clock        Clock                     Clock
    Level     Clock                   Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------------------
    0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     328

    0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     108
    ==========================================================================================================

    Clock Load Summary
    ***********************

                            Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|control[0]     328       control[0](port)     data_register[53:0].C                    -                 -

    ao_top_0|clk_i          108       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    ======================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 404 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ============================= Non-Gated/Non-Generated Clocks =============================
    Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
    ------------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           Unconstrained_port        76         ENCRYPTED
    ClockId_0_1       ENCRYPTED           Unconstrained_io_port     328        ENCRYPTED
    ==========================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar  4 15:08:42 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Mar  4 15:08:42 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 193MB)

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 198MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 198MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)

    Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 214MB peak: 216MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -2.87ns		 478 /       364
       2		0h:00m:02s		    -2.87ns		 474 /       364
       3		0h:00m:02s		    -2.60ns		 474 /       364
    Timing driven replication report
    Added 3 Registers via timing driven replication
    Added 3 LUTs via timing driven replication

       4		0h:00m:03s		    -2.46ns		 502 /       367
       5		0h:00m:03s		    -2.73ns		 504 /       367
       6		0h:00m:03s		    -2.60ns		 504 /       367
       7		0h:00m:03s		    -2.60ns		 504 /       367

       8		0h:00m:03s		    -2.46ns		 503 /       367

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 146MB peak: 219MB)

    Writing Analyst data base E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 219MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 217MB peak: 219MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 215MB peak: 219MB)

    Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 215MB peak: 219MB)

    @W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.36ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 6.19ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Mar  4 15:08:48 2019
    #

    Top view:               ao_top_0
    Requested Frequency:    161.5 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.092

                            Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i          229.5 MHz     195.0 MHz     4.358         5.127         -0.769     inferred     Autoconstr_clkgroup_0
    ao_top_0|control[0]     161.5 MHz     137.3 MHz     6.190         7.283         -1.092     inferred     Autoconstr_clkgroup_1
    System                  150.0 MHz     224.7 MHz     6.667         4.450         2.216      system       system_clkgroup
    =============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------
    Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------
    System               ao_top_0|clk_i       |  4.358       2.216   |  No paths    -      |  No paths    -      |  No paths    -
    System               ao_top_0|control[0]  |  6.190       4.274   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       System               |  4.358       3.580   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       ao_top_0|clk_i       |  4.358       -0.769  |  4.358       3.519  |  No paths    -      |  2.179       1.340
    ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  System               |  6.190       5.412   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|control[0]  |  6.190       -1.092  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top_0|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                        Starting                                                    Arrival
    Instance                            Reference          Type     Pin     Net                     Time        Slack
                                        Clock
    ------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[1]                 ao_top_0|clk_i     DFFC     Q       triger_level_cnt[1]     0.243       -0.769
    triger_level_cnt[0]                 ao_top_0|clk_i     DFFC     Q       triger_level_cnt[0]     0.243       -0.748
    u_ao_mem_ctrl.capture_length[0]     ao_top_0|clk_i     DFFC     Q       capture_length[0]       0.243       -0.735
    u_ao_mem_ctrl.capture_length[1]     ao_top_0|clk_i     DFFC     Q       capture_length[1]       0.243       -0.700
    u_ao_mem_ctrl.capture_length[2]     ao_top_0|clk_i     DFFC     Q       capture_length[2]       0.243       -0.665
    triger_level_cnt[2]                 ao_top_0|clk_i     DFFC     Q       triger_level_cnt[2]     0.243       -0.661
    u_ao_mem_ctrl.capture_length[3]     ao_top_0|clk_i     DFFP     Q       capture_length[3]       0.243       -0.630
    u_ao_mem_ctrl.capture_length[4]     ao_top_0|clk_i     DFFC     Q       capture_length[4]       0.243       -0.595
    triger_level_cnt[3]                 ao_top_0|clk_i     DFFC     Q       triger_level_cnt[3]     0.243       -0.570
    u_ao_mem_ctrl.capture_length[5]     ao_top_0|clk_i     DFFC     Q       capture_length[5]       0.243       -0.560
    ==================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                        Required
    Instance                              Reference          Type      Pin     Net                        Time         Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      g0_0                       4.297        -0.769
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      g0_3                       4.297        -0.735
    triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]      4.297        -0.211
    triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]      4.297        -0.211
    triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]      4.297        -0.103
    u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7           4.297        -0.018
    u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6       4.297        0.007
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]     4.297        0.007
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]     4.297        0.007
    u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]     4.297        0.007
    =========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      5.066
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.769

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[1] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                             Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    triger_level_cnt[1]              DFFC          Q        Out     0.243     0.243       -
    triger_level_cnt[1]              Net           -        -       0.535     -           5
    un1_match_final_3                LUT4          I1       In      -         0.778       -
    un1_match_final_3                LUT4          F        Out     0.570     1.348       -
    un1_match_final_3                Net           -        -       0.535     -           2
    triger_level_cnt_0_sqmuxa_1      MUX2_LUT5     S0       In      -         1.883       -
    triger_level_cnt_0_sqmuxa_1      MUX2_LUT5     O        Out     0.269     2.152       -
    triger_level_cnt_0_sqmuxa_1      Net           -        -       0.535     -           1
    triger_level_cnt_0_sqmuxa        LUT4          I2       In      -         2.687       -
    triger_level_cnt_0_sqmuxa        LUT4          F        Out     0.462     3.149       -
    triger_level_cnt_0_sqmuxa        Net           -        -       0.596     -           15
    u_ao_mem_ctrl.g0_0_1             LUT4          I3       In      -         3.745       -
    u_ao_mem_ctrl.g0_0_1             LUT4          F        Out     0.371     4.116       -
    g0_0_1                           Net           -        -       0.401     -           1
    u_ao_mem_ctrl.g0_0               LUT4          I0       In      -         4.517       -
    u_ao_mem_ctrl.g0_0               LUT4          F        Out     0.549     5.066       -
    g0_0                             Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE         CE       In      -         5.066       -
    ================================================================================================
    Total path delay (propagation time + setup) of 5.127 is 2.525(49.2%) logic and 2.602(50.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      5.045
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.748

        Number of logic level(s):                5
        Starting point:                          triger_level_cnt[0] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                             Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    triger_level_cnt[0]              DFFC          Q        Out     0.243     0.243       -
    triger_level_cnt[0]              Net           -        -       0.535     -           4
    un1_match_final_3                LUT4          I0       In      -         0.778       -
    un1_match_final_3                LUT4          F        Out     0.549     1.327       -
    un1_match_final_3                Net           -        -       0.535     -           2
    triger_level_cnt_0_sqmuxa_1      MUX2_LUT5     S0       In      -         1.862       -
    triger_level_cnt_0_sqmuxa_1      MUX2_LUT5     O        Out     0.269     2.131       -
    triger_level_cnt_0_sqmuxa_1      Net           -        -       0.535     -           1
    triger_level_cnt_0_sqmuxa        LUT4          I2       In      -         2.666       -
    triger_level_cnt_0_sqmuxa        LUT4          F        Out     0.462     3.128       -
    triger_level_cnt_0_sqmuxa        Net           -        -       0.596     -           15
    u_ao_mem_ctrl.g0_0_1             LUT4          I3       In      -         3.724       -
    u_ao_mem_ctrl.g0_0_1             LUT4          F        Out     0.371     4.095       -
    g0_0_1                           Net           -        -       0.401     -           1
    u_ao_mem_ctrl.g0_0               LUT4          I0       In      -         4.496       -
    u_ao_mem_ctrl.g0_0               LUT4          F        Out     0.549     5.045       -
    g0_0                             Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr     DFFCE         CE       In      -         5.045       -
    ================================================================================================
    Total path delay (propagation time + setup) of 5.106 is 2.504(49.0%) logic and 2.602(51.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      5.032
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.735

        Number of logic level(s):                14
        Starting point:                          u_ao_mem_ctrl.capture_length[0] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_length[0]                     DFFC          Q        Out     0.243     0.243       -
    capture_length[0]                                   Net           -        -       0.535     -           4
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           I0       In      -         0.778       -
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           COUT     Out     0.549     1.327       -
    capture_length_zero_cry_0                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           CIN      In      -         1.327       -
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           COUT     Out     0.035     1.362       -
    capture_length_zero_cry_1                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           CIN      In      -         1.362       -
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           COUT     Out     0.035     1.397       -
    capture_length_zero_cry_2                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           CIN      In      -         1.397       -
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           COUT     Out     0.035     1.432       -
    capture_length_zero_cry_3                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           CIN      In      -         1.432       -
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           COUT     Out     0.035     1.467       -
    capture_length_zero_cry_4                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           CIN      In      -         1.467       -
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           COUT     Out     0.035     1.502       -
    capture_length_zero_cry_5                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           CIN      In      -         1.502       -
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           COUT     Out     0.035     1.537       -
    capture_length_zero_cry_6                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           CIN      In      -         1.537       -
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           COUT     Out     0.035     1.572       -
    capture_length_zero_cry_7                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           CIN      In      -         1.572       -
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           COUT     Out     0.035     1.607       -
    capture_length_zero_cry_8                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           CIN      In      -         1.607       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           SUM      Out     0.470     2.077       -
    capture_length_zero[9]                              Net           -        -       0.535     -           2
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          I1       In      -         2.612       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          F        Out     0.570     3.182       -
    g3_4_0                                              Net           -        -       0.535     -           4
    u_ao_mem_ctrl.g0_3_0_0                              LUT4          I1       In      -         3.717       -
    u_ao_mem_ctrl.g0_3_0_0                              LUT4          F        Out     0.570     4.287       -
    g0_3_0_0                                            Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3_0                                MUX2_LUT5     I0       In      -         4.287       -
    u_ao_mem_ctrl.g0_3_0                                MUX2_LUT5     O        Out     0.105     4.392       -
    g0_3_0                                              Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     I0       In      -         4.392       -
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     O        Out     0.105     4.497       -
    g0_3                                                Net           -        -       0.535     -           1
    u_ao_mem_ctrl.mem_addr_inc_en                       DFFCE         CE       In      -         5.032       -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      5.032
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.735

        Number of logic level(s):                14
        Starting point:                          u_ao_mem_ctrl.capture_length[0] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_length[0]                     DFFC          Q        Out     0.243     0.243       -
    capture_length[0]                                   Net           -        -       0.535     -           4
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           I0       In      -         0.778       -
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           COUT     Out     0.549     1.327       -
    capture_length_zero_cry_0                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           CIN      In      -         1.327       -
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           COUT     Out     0.035     1.362       -
    capture_length_zero_cry_1                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           CIN      In      -         1.362       -
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           COUT     Out     0.035     1.397       -
    capture_length_zero_cry_2                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           CIN      In      -         1.397       -
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           COUT     Out     0.035     1.432       -
    capture_length_zero_cry_3                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           CIN      In      -         1.432       -
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           COUT     Out     0.035     1.467       -
    capture_length_zero_cry_4                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           CIN      In      -         1.467       -
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           COUT     Out     0.035     1.502       -
    capture_length_zero_cry_5                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           CIN      In      -         1.502       -
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           COUT     Out     0.035     1.537       -
    capture_length_zero_cry_6                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           CIN      In      -         1.537       -
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           COUT     Out     0.035     1.572       -
    capture_length_zero_cry_7                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           CIN      In      -         1.572       -
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           COUT     Out     0.035     1.607       -
    capture_length_zero_cry_8                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           CIN      In      -         1.607       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           SUM      Out     0.470     2.077       -
    capture_length_zero[9]                              Net           -        -       0.535     -           2
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          I1       In      -         2.612       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          F        Out     0.570     3.182       -
    g3_4_0                                              Net           -        -       0.535     -           4
    u_ao_mem_ctrl.g0_3_0_1                              LUT4          I1       In      -         3.717       -
    u_ao_mem_ctrl.g0_3_0_1                              LUT4          F        Out     0.570     4.287       -
    g0_3_0_1                                            Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3_0                                MUX2_LUT5     I1       In      -         4.287       -
    u_ao_mem_ctrl.g0_3_0                                MUX2_LUT5     O        Out     0.105     4.392       -
    g0_3_0                                              Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     I0       In      -         4.392       -
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     O        Out     0.105     4.497       -
    g0_3                                                Net           -        -       0.535     -           1
    u_ao_mem_ctrl.mem_addr_inc_en                       DFFCE         CE       In      -         5.032       -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      5.032
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.735

        Number of logic level(s):                14
        Starting point:                          u_ao_mem_ctrl.capture_length[0] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_length[0]                     DFFC          Q        Out     0.243     0.243       -
    capture_length[0]                                   Net           -        -       0.535     -           4
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           I0       In      -         0.778       -
    u_ao_mem_ctrl.capture_length_zero_cry_0_0           ALU           COUT     Out     0.549     1.327       -
    capture_length_zero_cry_0                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           CIN      In      -         1.327       -
    u_ao_mem_ctrl.capture_length_zero_cry_1_0           ALU           COUT     Out     0.035     1.362       -
    capture_length_zero_cry_1                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           CIN      In      -         1.362       -
    u_ao_mem_ctrl.capture_length_zero_cry_2_0           ALU           COUT     Out     0.035     1.397       -
    capture_length_zero_cry_2                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           CIN      In      -         1.397       -
    u_ao_mem_ctrl.capture_length_zero_cry_3_0           ALU           COUT     Out     0.035     1.432       -
    capture_length_zero_cry_3                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           CIN      In      -         1.432       -
    u_ao_mem_ctrl.capture_length_zero_cry_4_0           ALU           COUT     Out     0.035     1.467       -
    capture_length_zero_cry_4                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           CIN      In      -         1.467       -
    u_ao_mem_ctrl.capture_length_zero_cry_5_0           ALU           COUT     Out     0.035     1.502       -
    capture_length_zero_cry_5                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           CIN      In      -         1.502       -
    u_ao_mem_ctrl.capture_length_zero_cry_6_0           ALU           COUT     Out     0.035     1.537       -
    capture_length_zero_cry_6                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           CIN      In      -         1.537       -
    u_ao_mem_ctrl.capture_length_zero_cry_7_0           ALU           COUT     Out     0.035     1.572       -
    capture_length_zero_cry_7                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           CIN      In      -         1.572       -
    u_ao_mem_ctrl.capture_length_zero_cry_8_0           ALU           COUT     Out     0.035     1.607       -
    capture_length_zero_cry_8                           Net           -        -       0.000     -           1
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           CIN      In      -         1.607       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0             ALU           SUM      Out     0.470     2.077       -
    capture_length_zero[9]                              Net           -        -       0.535     -           2
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          I1       In      -         2.612       -
    u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M     LUT2          F        Out     0.570     3.182       -
    g3_4_0                                              Net           -        -       0.535     -           4
    u_ao_mem_ctrl.g0_3_1_1                              LUT4          I1       In      -         3.717       -
    u_ao_mem_ctrl.g0_3_1_1                              LUT4          F        Out     0.570     4.287       -
    g0_3_1_1                                            Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3_1                                MUX2_LUT5     I1       In      -         4.287       -
    u_ao_mem_ctrl.g0_3_1                                MUX2_LUT5     O        Out     0.105     4.392       -
    g0_3_1                                              Net           -        -       0.000     -           1
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     I1       In      -         4.392       -
    u_ao_mem_ctrl.g0_3                                  MUX2_LUT6     O        Out     0.105     4.497       -
    g0_3                                                Net           -        -       0.535     -           1
    u_ao_mem_ctrl.mem_addr_inc_en                       DFFCE         CE       In      -         5.032       -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top_0|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                   Arrival
    Instance                         Reference               Type      Pin     Net                              Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -1.092
    internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -1.071
    internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.984
    data_register[53]                ao_top_0|control[0]     DFFCE     Q       data_register[53]                0.243       -0.929
    data_register[49]                ao_top_0|control[0]     DFFCE     Q       data_register[49]                0.243       -0.908
    internal_register_select[11]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[11]     0.243       -0.893
    bit_count[1]                     ao_top_0|control[0]     DFFCE     Q       bit_count[1]                     0.243       -0.878
    bit_count[0]                     ao_top_0|control[0]     DFFCE     Q       bit_count[0]                     0.243       -0.857
    module_state_fast[0]             ao_top_0|control[0]     DFFP      Q       module_state_fast[0]             0.243       -0.821
    word_count[10]                   ao_top_0|control[0]     DFFCE     Q       word_count[10]                   0.243       -0.814
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                              Starting                                                              Required
    Instance                  Reference               Type      Pin     Net                         Time         Slack
                              Clock
    -------------------------------------------------------------------------------------------------------------------
    data_out_shift_reg[2]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]     6.129        -1.092
    data_out_shift_reg[1]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]     6.129        -1.031
    bit_count[0]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    bit_count[1]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    bit_count[2]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    bit_count[3]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    bit_count[4]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    bit_count[5]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.129        -0.929
    data_out_shift_reg[0]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]     6.129        -0.879
    address_counter[0]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.129        -0.814
    ===================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.190
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.129

        - Propagation time:                      7.222
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.092

        Number of logic level(s):                7
        Starting point:                          internal_register_select[9] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                            Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    internal_register_select[9]     DFFCE         Q        Out     0.243     0.243       -
    internal_register_select[9]     Net           -        -       0.535     -           1
    match_unit_rd_en_2_4[0]         LUT4          I1       In      -         0.778       -
    match_unit_rd_en_2_4[0]         LUT4          F        Out     0.570     1.348       -
    match_unit_rd_en_2_4[0]         Net           -        -       0.535     -           1
    match_unit_rd_en_2[0]           MUX2_LUT5     S0       In      -         1.883       -
    match_unit_rd_en_2[0]           MUX2_LUT5     O        Out     0.269     2.152       -
    match_unit_rd_en_2[1]           Net           -        -       0.657     -           26
    data_from_internal_reg77        LUT3          I2       In      -         2.809       -
    data_from_internal_reg77        LUT3          F        Out     0.462     3.271       -
    data_from_internal_reg77        Net           -        -       0.596     -           16
    data_from_ao_reg_2[2]           LUT3          I0       In      -         3.867       -
    data_from_ao_reg_2[2]           LUT3          F        Out     0.549     4.416       -
    data_from_ao_reg_2[2]           Net           -        -       0.401     -           1
    data_from_ao_reg_4[2]           LUT4          I1       In      -         4.817       -
    data_from_ao_reg_4[2]           LUT4          F        Out     0.570     5.387       -
    data_from_ao_reg_4[2]           Net           -        -       0.401     -           1
    data_from_ao_reg_5[2]           LUT4          I2       In      -         5.788       -
    data_from_ao_reg_5[2]           LUT4          F        Out     0.462     6.250       -
    data_from_ao_reg_5[2]           Net           -        -       0.401     -           1
    data_out_shift_reg_4[2]         LUT4          I1       In      -         6.652       -
    data_out_shift_reg_4[2]         LUT4          F        Out     0.570     7.222       -
    data_out_shift_reg_4[2]         Net           -        -       0.000     -           1
    data_out_shift_reg[2]           DFFCE         D        In      -         7.222       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 7.283 is 3.756(51.6%) logic and 3.527(48.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.190
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.129

        - Propagation time:                      7.201
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.071

        Number of logic level(s):                7
        Starting point:                          internal_register_select[7] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                            Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    internal_register_select[7]     DFFCE         Q        Out     0.243     0.243       -
    internal_register_select[7]     Net           -        -       0.535     -           1
    match_unit_rd_en_2_4[0]         LUT4          I0       In      -         0.778       -
    match_unit_rd_en_2_4[0]         LUT4          F        Out     0.549     1.327       -
    match_unit_rd_en_2_4[0]         Net           -        -       0.535     -           1
    match_unit_rd_en_2[0]           MUX2_LUT5     S0       In      -         1.862       -
    match_unit_rd_en_2[0]           MUX2_LUT5     O        Out     0.269     2.131       -
    match_unit_rd_en_2[1]           Net           -        -       0.657     -           26
    data_from_internal_reg77        LUT3          I2       In      -         2.788       -
    data_from_internal_reg77        LUT3          F        Out     0.462     3.250       -
    data_from_internal_reg77        Net           -        -       0.596     -           16
    data_from_ao_reg_2[2]           LUT3          I0       In      -         3.846       -
    data_from_ao_reg_2[2]           LUT3          F        Out     0.549     4.395       -
    data_from_ao_reg_2[2]           Net           -        -       0.401     -           1
    data_from_ao_reg_4[2]           LUT4          I1       In      -         4.796       -
    data_from_ao_reg_4[2]           LUT4          F        Out     0.570     5.366       -
    data_from_ao_reg_4[2]           Net           -        -       0.401     -           1
    data_from_ao_reg_5[2]           LUT4          I2       In      -         5.767       -
    data_from_ao_reg_5[2]           LUT4          F        Out     0.462     6.229       -
    data_from_ao_reg_5[2]           Net           -        -       0.401     -           1
    data_out_shift_reg_4[2]         LUT4          I1       In      -         6.631       -
    data_out_shift_reg_4[2]         LUT4          F        Out     0.570     7.201       -
    data_out_shift_reg_4[2]         Net           -        -       0.000     -           1
    data_out_shift_reg[2]           DFFCE         D        In      -         7.201       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 7.262 is 3.735(51.4%) logic and 3.527(48.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.190
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.129

        - Propagation time:                      7.161
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.031

        Number of logic level(s):                7
        Starting point:                          internal_register_select[9] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                            Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    internal_register_select[9]     DFFCE         Q        Out     0.243     0.243       -
    internal_register_select[9]     Net           -        -       0.535     -           1
    match_unit_rd_en_2_4[0]         LUT4          I1       In      -         0.778       -
    match_unit_rd_en_2_4[0]         LUT4          F        Out     0.570     1.348       -
    match_unit_rd_en_2_4[0]         Net           -        -       0.535     -           1
    match_unit_rd_en_2[0]           MUX2_LUT5     S0       In      -         1.883       -
    match_unit_rd_en_2[0]           MUX2_LUT5     O        Out     0.269     2.152       -
    match_unit_rd_en_2[1]           Net           -        -       0.657     -           26
    data_from_internal_reg78        LUT3          I2       In      -         2.809       -
    data_from_internal_reg78        LUT3          F        Out     0.462     3.271       -
    data_from_internal_reg78        Net           -        -       0.535     -           8
    data_from_ao_reg_0[1]           LUT4          I1       In      -         3.806       -
    data_from_ao_reg_0[1]           LUT4          F        Out     0.570     4.376       -
    data_from_ao_reg_0[1]           Net           -        -       0.401     -           1
    data_from_ao_reg_4[1]           LUT4          I0       In      -         4.777       -
    data_from_ao_reg_4[1]           LUT4          F        Out     0.549     5.326       -
    data_from_ao_reg_4[1]           Net           -        -       0.401     -           1
    data_from_ao_reg_5[1]           LUT4          I2       In      -         5.727       -
    data_from_ao_reg_5[1]           LUT4          F        Out     0.462     6.189       -
    data_from_ao_reg_5[1]           Net           -        -       0.401     -           1
    data_out_shift_reg_4[1]         LUT4          I1       In      -         6.591       -
    data_out_shift_reg_4[1]         LUT4          F        Out     0.570     7.161       -
    data_out_shift_reg_4[1]         Net           -        -       0.000     -           1
    data_out_shift_reg[1]           DFFCE         D        In      -         7.161       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 7.222 is 3.756(52.0%) logic and 3.466(48.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.190
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.129

        - Propagation time:                      7.140
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.010

        Number of logic level(s):                7
        Starting point:                          internal_register_select[7] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                            Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    internal_register_select[7]     DFFCE         Q        Out     0.243     0.243       -
    internal_register_select[7]     Net           -        -       0.535     -           1
    match_unit_rd_en_2_4[0]         LUT4          I0       In      -         0.778       -
    match_unit_rd_en_2_4[0]         LUT4          F        Out     0.549     1.327       -
    match_unit_rd_en_2_4[0]         Net           -        -       0.535     -           1
    match_unit_rd_en_2[0]           MUX2_LUT5     S0       In      -         1.862       -
    match_unit_rd_en_2[0]           MUX2_LUT5     O        Out     0.269     2.131       -
    match_unit_rd_en_2[1]           Net           -        -       0.657     -           26
    data_from_internal_reg78        LUT3          I2       In      -         2.788       -
    data_from_internal_reg78        LUT3          F        Out     0.462     3.250       -
    data_from_internal_reg78        Net           -        -       0.535     -           8
    data_from_ao_reg_0[1]           LUT4          I1       In      -         3.785       -
    data_from_ao_reg_0[1]           LUT4          F        Out     0.570     4.355       -
    data_from_ao_reg_0[1]           Net           -        -       0.401     -           1
    data_from_ao_reg_4[1]           LUT4          I0       In      -         4.756       -
    data_from_ao_reg_4[1]           LUT4          F        Out     0.549     5.305       -
    data_from_ao_reg_4[1]           Net           -        -       0.401     -           1
    data_from_ao_reg_5[1]           LUT4          I2       In      -         5.706       -
    data_from_ao_reg_5[1]           LUT4          F        Out     0.462     6.168       -
    data_from_ao_reg_5[1]           Net           -        -       0.401     -           1
    data_out_shift_reg_4[1]         LUT4          I1       In      -         6.570       -
    data_out_shift_reg_4[1]         LUT4          F        Out     0.570     7.140       -
    data_out_shift_reg_4[1]         Net           -        -       0.000     -           1
    data_out_shift_reg[1]           DFFCE         D        In      -         7.140       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 7.201 is 3.735(51.9%) logic and 3.466(48.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.190
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.129

        - Propagation time:                      7.114
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.984

        Number of logic level(s):                7
        Starting point:                          internal_register_select[10] / Q
        Ending point:                            data_out_shift_reg[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                             Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    internal_register_select[10]     DFFCE         Q        Out     0.243     0.243       -
    internal_register_select[10]     Net           -        -       0.535     -           1
    match_unit_rd_en_2_4[0]          LUT4          I2       In      -         0.778       -
    match_unit_rd_en_2_4[0]          LUT4          F        Out     0.462     1.240       -
    match_unit_rd_en_2_4[0]          Net           -        -       0.535     -           1
    match_unit_rd_en_2[0]            MUX2_LUT5     S0       In      -         1.775       -
    match_unit_rd_en_2[0]            MUX2_LUT5     O        Out     0.269     2.044       -
    match_unit_rd_en_2[1]            Net           -        -       0.657     -           26
    data_from_internal_reg77         LUT3          I2       In      -         2.701       -
    data_from_internal_reg77         LUT3          F        Out     0.462     3.163       -
    data_from_internal_reg77         Net           -        -       0.596     -           16
    data_from_ao_reg_2[2]            LUT3          I0       In      -         3.759       -
    data_from_ao_reg_2[2]            LUT3          F        Out     0.549     4.308       -
    data_from_ao_reg_2[2]            Net           -        -       0.401     -           1
    data_from_ao_reg_4[2]            LUT4          I1       In      -         4.709       -
    data_from_ao_reg_4[2]            LUT4          F        Out     0.570     5.279       -
    data_from_ao_reg_4[2]            Net           -        -       0.401     -           1
    data_from_ao_reg_5[2]            LUT4          I2       In      -         5.680       -
    data_from_ao_reg_5[2]            LUT4          F        Out     0.462     6.142       -
    data_from_ao_reg_5[2]            Net           -        -       0.401     -           1
    data_out_shift_reg_4[2]          LUT4          I1       In      -         6.544       -
    data_out_shift_reg_4[2]          LUT4          F        Out     0.570     7.114       -
    data_out_shift_reg_4[2]          Net           -        -       0.000     -           1
    data_out_shift_reg[2]            DFFCE         D        In      -         7.114       -
    ================================================================================================
    Total path delay (propagation time + setup) of 7.175 is 3.648(50.8%) logic and 3.527(49.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                             Starting                                           Arrival
    Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                             Clock
    -------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.216
    address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       4.274
    =============================================================================================================

    Ending Points with Worst Slack
    ******************************

                                  Starting                                                        Required
    Instance                      Reference     Type      Pin     Net                             Time         Slack
                                  Clock
    ----------------------------------------------------------------------------------------------------------------
    capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.297        2.216
    capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.297        2.216
    capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.297        2.441
    capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.297        3.213
    internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.297        3.213
    capture_end_dly               System        DFFP      D       capture_end                     4.297        3.762
    address_counter[9]            System        DFFCE     D       address_counter_s[9]            6.129        4.274
    address_counter[8]            System        DFFCE     D       address_counter_s[8]            6.129        4.309
    address_counter[7]            System        DFFCE     D       address_counter_s[7]            6.129        4.344
    address_counter[6]            System        DFFCE     D       address_counter_s[6]            6.129        4.379
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.358
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.297

        - Propagation time:                      2.081
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 2.216

        Number of logic level(s):                2
        Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
        Ending point:                            capture_window_sel[2] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -
    capture_end                              Net      -        -       0.535     -           6
    un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -
    un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -
    un1_capture_window_sel_c2                Net      -        -       0.535     -           2
    capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -
    capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -
    capture_window_sel_3[2]                  Net      -        -       0.000     -           1
    capture_window_sel[2]                    DFFC     D        In      -         2.081       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 216MB peak: 219MB)

    Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 216MB peak: 219MB)

    ---------------------------------------
    Resource Usage Report for ao_top_0

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             70 uses
    DFF             32 uses
    DFFC            38 uses
    DFFCE           258 uses
    DFFNP           2 uses
    DFFP            5 uses
    DFFPE           32 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       6 uses
    MUX2_LUT6       1 use
    SDPX9           2 uses
    LUT2            57 uses
    LUT3            108 uses
    LUT4            288 uses

    I/O ports: 75
    I/O primitives: 57
    IBUF           55 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   367 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 2 of 140 (1%)

    Total load per clock:
       ao_top_0|clk_i: 1
       ao_top_0|control[0]: 294

    @S |Mapping Summary:
    Total  LUTs: 453 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 45MB peak: 219MB)

    Process took 0h:00m:06s realtime, 0h:00m:06s cputime
    # Mon Mar  4 15:08:49 2019

    ###########################################################]

`