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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
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Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-049

Implementation : rev_1

# Written on Mon Mar  4 13:44:22 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                            Requested     Requested     Clock        Clock                     Clock
Level     Clock                            Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------
0 -       NLMS_Adaptive_Filter_Top|clk     180.0 MHz     5.556         inferred     Autoconstr_clkgroup_0     1387 
===================================================================================================================


Clock Load Summary
******************

                                 Clock     Source        Clock Pin                            Non-clock Pin     Non-clock Pin
Clock                            Load      Pin           Seq Example                          Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter_Top|clk     1387      clk(port)     NLMS_Adaptive_Filter.sub_begin.C     -                 -            
=============================================================================================================================
