@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "00000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[52:0].
@N: FX493 |Applying initial value "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividor_copy[105:0].
@N: FX493 |Applying initial value "1" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.done.
@N: FX493 |Applying initial value "000000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.quotient[53:0].
@N: FX493 |Applying initial value "0000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.bi[6:0].
@N: FX493 |Applying initial value "0" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_inv.inv_start.
@N: MF794 |RAM coeffi_memb[35:0] required 2 registers during mapping 
@N: MF794 |RAM data_mem[17:0] required 19 registers during mapping 
@N: MF794 |RAM coeffi_memb[35:0] required 2 registers during mapping 
@N: MF794 |RAM data_mem[17:0] required 19 registers during mapping 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
