library verilog;
use verilog.vl_types.all;
entity IDDR_MEM is
    generic(
        GSREN           : string  := "false";
        LSREN           : string  := "true"
    );
    port(
        Q0              : out    vl_logic;
        Q1              : out    vl_logic;
        D               : in     vl_logic;
        WADDR           : in     vl_logic_vector(2 downto 0);
        RADDR           : in     vl_logic_vector(2 downto 0);
        PCLK            : in     vl_logic;
        ICLK            : in     vl_logic;
        RESET           : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of GSREN : constant is 1;
    attribute mti_svvh_generic_type of LSREN : constant is 1;
end IDDR_MEM;
