`

    #Build: Synplify Pro (R) O-2018.09G-SP1, Build 099R, Feb 12 2019
    #install: C:\Gowin\1.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-049

    # Mon Mar  4 15:08:20 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\gw_con_parameter.v" (library work)
    @I::"E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\gw_con_top_define.v" (library work)
    @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v" (library work)
    @W:CG1337 : gw_con_top.v(194) | Net capture_dr is not declared.
    @W:CG1337 : gw_con_top.v(208) | Net enable_i_delay is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_con_parameter.v(1) | Synthesizing module work_E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\gw_con_parameter.v_unit in library work.
    Selecting top level module gw_con_top
    Running optimization stage 1 on MUX16 .......
    Running optimization stage 1 on gw_con_top .......
    Running optimization stage 2 on gw_con_top .......
    Running optimization stage 2 on MUX16 .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:21 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:21 2019

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:21 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar  4 15:08:22 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Mar  4 15:08:23 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    @N:MF284 :  | Setting synthesis effort to medium for the design
    Linked File:  ao_control_scck.rpt
    Printing clock  summary report in "E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\rev_1\ao_control_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.

    Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 192MB)

    Clock Summary
    ******************

              Start      Requested      Requested     Clock      Clock               Clock
    Level     Clock      Frequency      Period        Type       Group               Load
    --------------------------------------------------------------------------------------
    0 -       System     1521.8 MHz     0.657         system     system_clkgroup     14
    ======================================================================================

    Clock Load Summary
    ***********************

               Clock     Source     Clock Pin                        Non-clock Pin     Non-clock Pin
    Clock      Load      Pin        Seq Example                      Seq Example       Comb Example
    ------------------------------------------------------------------------------------------------
    System     14        -          shift_dr_capture_dr_dly[0].C     -                 -
    ================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 14 clock pin(s) of sequential element(s)
    0 instances converted, 14 sequential instances remain driven by gated/generated clocks

    ======================================================= Gated/Generated Clocks ========================================================
    Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    ---------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           IO_port                14                     ENCRYPTED           Clock source is invalid for GCC
    =======================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\rev_1\ao_control.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 192MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar  4 15:08:25 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Mar  4 15:08:25 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-SP1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-049

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -1.33ns		  17 /        14

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 191MB)

    Writing Analyst data base E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\impl\gao\ao_control\rev_1\synwork\ao_control_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    @W:MT420 :  | Found inferred clock gw_con_top|tck_i with period 1.65ns. Please declare a user-defined clock on port tck_i.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Mar  4 15:08:28 2019
    #

    Top view:               gw_con_top
    Requested Frequency:    605.2 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.118

                         Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock       Frequency     Frequency     Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------
    gw_con_top|tck_i     605.2 MHz     257.2 MHz     1.652         3.888         -1.118     inferred     Autoconstr_clkgroup_0
    System               150.0 MHz     NA            6.667         NA            NA         system       system_clkgroup
    ==========================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------
    Starting          Ending            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------
    gw_con_top|tck_i  gw_con_top|tck_i  |  1.652       0.243  |  1.652       0.813  |  No paths    -      |  0.826       -1.118
    ===========================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: gw_con_top|tck_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                                      Arrival
    Instance                       Reference            Type      Pin     Net                    Time        Slack
                                   Clock
    ---------------------------------------------------------------------------------------------------------------
    enable_reg[1]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[1]          0.243       -1.118
    enable_reg[0]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[0]          0.243       -1.097
    enable_reg[2]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[2]          0.243       -1.010
    tdi_d                          gw_con_top|tck_i     DFFNC     Q       control0_c[2]          0.243       -0.562
    input_shift_reg[0]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[0]     0.243       0.243
    input_shift_reg[1]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[1]     0.243       0.243
    input_shift_reg[2]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[2]     0.243       0.243
    input_shift_reg[3]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[3]     0.243       0.243
    shift_dr_capture_dr_dly[0]     gw_con_top|tck_i     DFFC      Q       control0_c[4]          0.243       0.243
    input_shift_reg[4]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[4]     0.243       0.351
    ===============================================================================================================

    Ending Points with Worst Slack
    ******************************

                           Starting                                                           Required
    Instance               Reference            Type      Pin     Net                         Time         Slack
                           Clock
    -------------------------------------------------------------------------------------------------------------
    input_shift_reg[0]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    input_shift_reg[1]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    input_shift_reg[2]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    input_shift_reg[3]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    input_shift_reg[4]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    module_id_reg[0]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    module_id_reg[1]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    module_id_reg[2]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    module_id_reg[3]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              0.765        -1.118
    input_shift_reg[4]     gw_con_top|tck_i     DFFCE     D       input_shift_reg_ldmx[4]     0.765        -0.562
    =============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.826
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.765

        - Propagation time:                      1.883
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.118

        Number of logic level(s):                1
        Starting point:                          enable_reg[1] / Q
        Ending point:                            input_shift_reg[0] / CE
        The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
        The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    enable_reg[1]          DFFNC     Q        Out     0.243     0.243       -
    enable_reg[1]          Net       -        -       0.535     -           2
    enable_i_delay         LUT3      I1       In      -         0.778       -
    enable_i_delay         LUT3      F        Out     0.570     1.348       -
    enable_i_delay         Net       -        -       0.535     -           9
    input_shift_reg[0]     DFFCE     CE       In      -         1.883       -
    ==================================================================================
    Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.826
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.765

        - Propagation time:                      1.883
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.118

        Number of logic level(s):                1
        Starting point:                          enable_reg[1] / Q
        Ending point:                            input_shift_reg[1] / CE
        The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
        The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    enable_reg[1]          DFFNC     Q        Out     0.243     0.243       -
    enable_reg[1]          Net       -        -       0.535     -           2
    enable_i_delay         LUT3      I1       In      -         0.778       -
    enable_i_delay         LUT3      F        Out     0.570     1.348       -
    enable_i_delay         Net       -        -       0.535     -           9
    input_shift_reg[1]     DFFCE     CE       In      -         1.883       -
    ==================================================================================
    Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      0.826
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.765

        - Propagation time:                      1.883
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.118

        Number of logic level(s):                1
        Starting point:                          enable_reg[1] / Q
        Ending point:                            input_shift_reg[2] / CE
        The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
        The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    enable_reg[1]          DFFNC     Q        Out     0.243     0.243       -
    enable_reg[1]          Net       -        -       0.535     -           2
    enable_i_delay         LUT3      I1       In      -         0.778       -
    enable_i_delay         LUT3      F        Out     0.570     1.348       -
    enable_i_delay         Net       -        -       0.535     -           9
    input_shift_reg[2]     DFFCE     CE       In      -         1.883       -
    ==================================================================================
    Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      0.826
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.765

        - Propagation time:                      1.883
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.118

        Number of logic level(s):                1
        Starting point:                          enable_reg[1] / Q
        Ending point:                            input_shift_reg[3] / CE
        The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
        The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    enable_reg[1]          DFFNC     Q        Out     0.243     0.243       -
    enable_reg[1]          Net       -        -       0.535     -           2
    enable_i_delay         LUT3      I1       In      -         0.778       -
    enable_i_delay         LUT3      F        Out     0.570     1.348       -
    enable_i_delay         Net       -        -       0.535     -           9
    input_shift_reg[3]     DFFCE     CE       In      -         1.883       -
    ==================================================================================
    Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      0.826
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.765

        - Propagation time:                      1.883
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.118

        Number of logic level(s):                1
        Starting point:                          enable_reg[1] / Q
        Ending point:                            input_shift_reg[4] / CE
        The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
        The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    enable_reg[1]          DFFNC     Q        Out     0.243     0.243       -
    enable_reg[1]          Net       -        -       0.535     -           2
    enable_i_delay         LUT3      I1       In      -         0.778       -
    enable_i_delay         LUT3      F        Out     0.570     1.348       -
    enable_i_delay         Net       -        -       0.535     -           9
    input_shift_reg[4]     DFFCE     CE       In      -         1.883       -
    ==================================================================================
    Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    ---------------------------------------
    Resource Usage Report for gw_con_top

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    DFFC            1 use
    DFFCE           9 uses
    DFFNC           4 uses
    GSR             1 use
    INV             1 use
    MUX16           1 use
    LUT2            2 uses
    LUT3            6 uses
    LUT4            5 uses

    I/O ports: 17
    I/O primitives: 16
    IBUF           7 uses
    OBUF           9 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   14 of 41040 (0%)
    Total load per clock:
       gw_con_top|tck_i: 15

    @S |Mapping Summary:
    Total  LUTs: 13 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 191MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Mon Mar  4 15:08:28 2019

    ###########################################################]

`