library verilog;
use verilog.vl_types.all;
entity nlms_example_top is
    generic(
        idata_width     : integer := 18;
        coeffi_addr_width: integer := 5;
        tapsize         : integer := 32;
        sim_en          : integer := 0
    );
    port(
        clkin           : in     vl_logic;
        key_begin_n     : in     vl_logic;
        o_err           : out    vl_logic_vector;
        done            : out    vl_logic;
        key_ini_n       : in     vl_logic;
        key_rst_n       : in     vl_logic;
        input_rdy       : out    vl_logic;
        out_err_gather  : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of idata_width : constant is 1;
    attribute mti_svvh_generic_type of coeffi_addr_width : constant is 1;
    attribute mti_svvh_generic_type of tapsize : constant is 1;
    attribute mti_svvh_generic_type of sim_en : constant is 1;
end nlms_example_top;
