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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-049

Implementation : rev_1

# Written on Mon Mar  4 15:08:40 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     328  
                                                                                                          
0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     108  
==========================================================================================================


Clock Load Summary
******************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     328       control[0](port)     data_register[53:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          108       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================
