# Mon Mar  4 13:44:24 2019


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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-049

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 194MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "00000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[52:0].
@N: FX493 |Applying initial value "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividor_copy[105:0].
@N: FX493 |Applying initial value "1" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.done.
@N: FX493 |Applying initial value "000000000000000000000000000000000000000000000000000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.quotient[53:0].
@N: FX493 |Applying initial value "0000000" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.bi[6:0].
@N: FX493 |Applying initial value "0" on instance NLMS_Adaptive_Filter.pre_coeffi.pre_coe_inv.inv_start.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 195MB)

@N: MF794 |RAM coeffi_memb[35:0] required 2 registers during mapping 
@N: MF794 |RAM data_mem[17:0] required 19 registers during mapping 

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 226MB)


Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 221MB peak: 226MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 225MB peak: 249MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 226MB peak: 249MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 227MB peak: 249MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 227MB peak: 249MB)

@N: MF794 |RAM coeffi_memb[35:0] required 2 registers during mapping 
@N: MF794 |RAM data_mem[17:0] required 19 registers during mapping 

Finished preparing to map (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 227MB peak: 249MB)


Finished technology mapping (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 231MB peak: 249MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:18s		    -2.34ns		 969 /      1036
   2		0h:00m:18s		    -2.34ns		 975 /      1036
   3		0h:00m:18s		    -2.11ns		 975 /      1036
Timing driven replication report
Added 9 Registers via timing driven replication
Added 9 LUTs via timing driven replication

   4		0h:00m:19s		    -2.11ns		 984 /      1045


   5		0h:00m:19s		    -2.11ns		 984 /      1045

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:20s; Memory used current: 231MB peak: 249MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:25s; Memory used current: 231MB peak: 249MB)


Start Writing Netlists (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 150MB peak: 249MB)

Writing Analyst data base E:\IP_PROJECT\NLMS\RefDesign_03_04\NLMS_REF_03_04\Gowin_NLMS_Adaptive_Filter_RefDesign\project\src\nlms_adaptive_filter\temp\NLMS_Adaptive_Filter\rev_1\synwork\nlms_adaptive_filter_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 222MB peak: 249MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 222MB peak: 249MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 220MB peak: 249MB)


Start final timing analysis (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:30s; Memory used current: 219MB peak: 249MB)

@W: MT246 :"c:\gowin\1.8\ide\ipcore\nlms\data\nlms_adaptive_filter.v":322:32:322:55|Blackbox MULTALU36X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\gowin\1.8\ide\ipcore\nlms\data\nlms_adaptive_filter.v":322:32:322:55|Blackbox MULTALU36X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock NLMS_Adaptive_Filter_Top|clk with period 5.61ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing report written on Mon Mar  4 13:44:57 2019
#


Top view:               NLMS_Adaptive_Filter_Top
Requested Frequency:    178.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.990

                                 Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                   Frequency     Frequency     Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter_Top|clk     178.3 MHz     151.5 MHz     5.609         6.599         -0.990     inferred     Autoconstr_clkgroup_0
System                           150.0 MHz     563.3 MHz     6.667         1.775         4.891      system       system_clkgroup      
======================================================================================================================================





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------
System                        NLMS_Adaptive_Filter_Top|clk  |  5.609       4.891   |  No paths    -      |  No paths    -      |  No paths    -    
NLMS_Adaptive_Filter_Top|clk  System                        |  5.609       3.651   |  No paths    -      |  No paths    -      |  No paths    -    
NLMS_Adaptive_Filter_Top|clk  NLMS_Adaptive_Filter_Top|clk  |  5.609       -0.990  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: NLMS_Adaptive_Filter_Top|clk
====================================



Starting Points with Worst Slack
********************************

                                                                  Starting                                                                 Arrival           
Instance                                                          Reference                        Type      Pin     Net                   Time        Slack 
                                                                  Clock                                                                                      
-------------------------------------------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_idx[2]                       NLMS_Adaptive_Filter_Top|clk     DFF       Q       wr_idx[2]             0.243       -0.990
NLMS_Adaptive_Filter.data_control.wr_en_flag                      NLMS_Adaptive_Filter_Top|clk     DFFR      Q       wr_en_flag            0.243       -0.908
NLMS_Adaptive_Filter.data_control.wr_idx[3]                       NLMS_Adaptive_Filter_Top|clk     DFF       Q       wr_idx[3]             0.243       -0.882
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[17]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[17]     0.243       -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[16]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[16]     0.243       -0.795
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[19]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[19]     0.243       -0.781
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[18]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[18]     0.243       -0.760
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[21]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[21]     0.243       -0.746
NLMS_Adaptive_Filter.data_control.input_rdy                       NLMS_Adaptive_Filter_Top|clk     DFFSE     Q       input_rdy_datactr     0.243       -0.730
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[20]     NLMS_Adaptive_Filter_Top|clk     DFFE      Q       dividend_copy[20]     0.243       -0.725
=============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                             Required           
Instance                                                         Reference                        Type     Pin     Net                Time         Slack 
                                                                 Clock                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_idx[2]                      NLMS_Adaptive_Filter_Top|clk     DFF      D       N_25_0_i           5.548        -0.990
NLMS_Adaptive_Filter.data_control.wr_idx[3]                      NLMS_Adaptive_Filter_Top|clk     DFF      D       N_22_0_i           5.548        -0.990
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[0]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[1]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[2]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[3]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[4]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[5]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[6]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.dividend_copy[7]     NLMS_Adaptive_Filter_Top|clk     DFFE     CE      un1_done14_2_i     5.548        -0.816
=========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      6.538
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.990

    Number of logic level(s):                6
    Starting point:                          NLMS_Adaptive_Filter.data_control.wr_idx[2] / Q
    Ending point:                            NLMS_Adaptive_Filter.data_control.wr_idx[3] / D
    The start point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_idx[2]                      DFF      Q        Out     0.243     0.243       -         
wr_idx[2]                                                        Net      -        -       0.596     -           15        
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     I1       In      -         0.839       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     F        Out     0.570     1.409       -         
r_m4_e_0_0                                                       Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     I3       In      -         1.944       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     F        Out     0.371     2.315       -         
N_67                                                             Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     I0       In      -         2.850       -         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     F        Out     0.549     3.399       -         
N_21                                                             Net      -        -       0.535     -           3         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     I0       In      -         3.934       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     F        Out     0.549     4.483       -         
un1_wr_idx_c2                                                    Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     I1       In      -         5.018       -         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     F        Out     0.570     5.588       -         
N_20_0                                                           Net      -        -       0.401     -           1         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     I0       In      -         5.989       -         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     F        Out     0.549     6.538       -         
N_22_0_i                                                         Net      -        -       0.000     -           1         
NLMS_Adaptive_Filter.data_control.wr_idx[3]                      DFF      D        In      -         6.538       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 6.599 is 3.462(52.5%) logic and 3.137(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      6.538
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.990

    Number of logic level(s):                6
    Starting point:                          NLMS_Adaptive_Filter.data_control.wr_idx[2] / Q
    Ending point:                            NLMS_Adaptive_Filter.data_control.wr_idx[2] / D
    The start point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_idx[2]                      DFF      Q        Out     0.243     0.243       -         
wr_idx[2]                                                        Net      -        -       0.596     -           15        
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     I1       In      -         0.839       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     F        Out     0.570     1.409       -         
r_m4_e_0_0                                                       Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     I3       In      -         1.944       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     F        Out     0.371     2.315       -         
N_67                                                             Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     I0       In      -         2.850       -         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     F        Out     0.549     3.399       -         
N_21                                                             Net      -        -       0.535     -           3         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     I0       In      -         3.934       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     F        Out     0.549     4.483       -         
un1_wr_idx_c2                                                    Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.m22                            LUT3     I1       In      -         5.018       -         
NLMS_Adaptive_Filter.data_control.m22                            LUT3     F        Out     0.570     5.588       -         
N_23_0                                                           Net      -        -       0.401     -           1         
NLMS_Adaptive_Filter.data_control.N_25_0_i                       LUT4     I0       In      -         5.989       -         
NLMS_Adaptive_Filter.data_control.N_25_0_i                       LUT4     F        Out     0.549     6.538       -         
N_25_0_i                                                         Net      -        -       0.000     -           1         
NLMS_Adaptive_Filter.data_control.wr_idx[2]                      DFF      D        In      -         6.538       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 6.599 is 3.462(52.5%) logic and 3.137(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      6.456
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.908

    Number of logic level(s):                6
    Starting point:                          NLMS_Adaptive_Filter.data_control.wr_en_flag / Q
    Ending point:                            NLMS_Adaptive_Filter.data_control.wr_idx[3] / D
    The start point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_en_flag                     DFFR     Q        Out     0.243     0.243       -         
wr_en_flag                                                       Net      -        -       0.535     -           4         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     I0       In      -         0.778       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     F        Out     0.549     1.327       -         
r_m4_e_0_0                                                       Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     I3       In      -         1.862       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     F        Out     0.371     2.233       -         
N_67                                                             Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     I0       In      -         2.768       -         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     F        Out     0.549     3.317       -         
N_21                                                             Net      -        -       0.535     -           3         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     I0       In      -         3.852       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     F        Out     0.549     4.401       -         
un1_wr_idx_c2                                                    Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     I1       In      -         4.936       -         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     F        Out     0.570     5.506       -         
N_20_0                                                           Net      -        -       0.401     -           1         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     I0       In      -         5.907       -         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     F        Out     0.549     6.456       -         
N_22_0_i                                                         Net      -        -       0.000     -           1         
NLMS_Adaptive_Filter.data_control.wr_idx[3]                      DFF      D        In      -         6.456       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 6.517 is 3.441(52.8%) logic and 3.076(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      6.456
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.908

    Number of logic level(s):                6
    Starting point:                          NLMS_Adaptive_Filter.data_control.wr_en_flag / Q
    Ending point:                            NLMS_Adaptive_Filter.data_control.wr_idx[2] / D
    The start point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_en_flag                     DFFR     Q        Out     0.243     0.243       -         
wr_en_flag                                                       Net      -        -       0.535     -           4         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     I0       In      -         0.778       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     F        Out     0.549     1.327       -         
r_m4_e_0_0                                                       Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     I3       In      -         1.862       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     F        Out     0.371     2.233       -         
N_67                                                             Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     I0       In      -         2.768       -         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     F        Out     0.549     3.317       -         
N_21                                                             Net      -        -       0.535     -           3         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     I0       In      -         3.852       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     F        Out     0.549     4.401       -         
un1_wr_idx_c2                                                    Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.m22                            LUT3     I1       In      -         4.936       -         
NLMS_Adaptive_Filter.data_control.m22                            LUT3     F        Out     0.570     5.506       -         
N_23_0                                                           Net      -        -       0.401     -           1         
NLMS_Adaptive_Filter.data_control.N_25_0_i                       LUT4     I0       In      -         5.907       -         
NLMS_Adaptive_Filter.data_control.N_25_0_i                       LUT4     F        Out     0.549     6.456       -         
N_25_0_i                                                         Net      -        -       0.000     -           1         
NLMS_Adaptive_Filter.data_control.wr_idx[2]                      DFF      D        In      -         6.456       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 6.517 is 3.441(52.8%) logic and 3.076(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      6.430
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.882

    Number of logic level(s):                6
    Starting point:                          NLMS_Adaptive_Filter.data_control.wr_idx[3] / Q
    Ending point:                            NLMS_Adaptive_Filter.data_control.wr_idx[3] / D
    The start point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.wr_idx[3]                      DFF      Q        Out     0.243     0.243       -         
wr_idx[3]                                                        Net      -        -       0.596     -           14        
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     I2       In      -         0.839       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2_2     LUT4     F        Out     0.462     1.301       -         
r_m4_e_0_0                                                       Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     I3       In      -         1.836       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_1_sqmuxa_i_a2       LUT4     F        Out     0.371     2.207       -         
N_67                                                             Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     I0       In      -         2.742       -         
NLMS_Adaptive_Filter.data_control.wr_idx_1_sqmuxa_1_i            LUT4     F        Out     0.549     3.291       -         
N_21                                                             Net      -        -       0.535     -           3         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     I0       In      -         3.826       -         
NLMS_Adaptive_Filter.data_control.un1_wr_idx_ac0_1               LUT3     F        Out     0.549     4.375       -         
un1_wr_idx_c2                                                    Net      -        -       0.535     -           2         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     I1       In      -         4.910       -         
NLMS_Adaptive_Filter.data_control.m19                            LUT4     F        Out     0.570     5.480       -         
N_20_0                                                           Net      -        -       0.401     -           1         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     I0       In      -         5.881       -         
NLMS_Adaptive_Filter.data_control.N_22_0_i                       LUT4     F        Out     0.549     6.430       -         
N_22_0_i                                                         Net      -        -       0.000     -           1         
NLMS_Adaptive_Filter.data_control.wr_idx[3]                      DFF      D        In      -         6.430       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 6.491 is 3.354(51.7%) logic and 3.137(48.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                              Starting                                                   Arrival          
Instance                                                      Reference     Type             Pin         Net             Time        Slack
                                                              Clock                                                                       
------------------------------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.rst_n_i           System        INV              O           rst_n_i         0.000       4.891
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[0]     accu_reg[0]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[0]     accu_reg[0]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[1]     accu_reg[1]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[1]     accu_reg[1]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[2]     accu_reg[2]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[2]     accu_reg[2]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[3]     accu_reg[3]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[3]     accu_reg[3]     0.000       5.013
NLMS_Adaptive_Filter.mult_accu_y.Mult_Signed_A18_B36_Sync     System        MULTALU36X18     DOUT[4]     accu_reg[4]     0.000       5.013
==========================================================================================================================================


Ending Points with Worst Slack
******************************

                                                   Starting                                     Required          
Instance                                           Reference     Type     Pin       Net         Time         Slack
                                                   Clock                                                          
------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.data_control.ce               System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.cea            System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.ceb            System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.ini_flag       System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.ini_flip2      System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.ini_idx[0]     System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.data_control.ini_idx[0]       System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.data_control.ini_idx[1]       System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.coeffi_control.ini_idx[1]     System        DFFR     RESET     rst_n_i     5.548        4.891
NLMS_Adaptive_Filter.data_control.ini_idx[2]       System        DFFR     RESET     rst_n_i     5.548        4.891
==================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      5.609
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.548

    - Propagation time:                      0.657
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.891

    Number of logic level(s):                0
    Starting point:                          NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.rst_n_i / O
    Ending point:                            NLMS_Adaptive_Filter.data_control.ce / RESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            NLMS_Adaptive_Filter_Top|clk [rising] on pin CLK

Instance / Net                                                   Pin       Pin               Arrival     No. of    
Name                                                    Type     Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
NLMS_Adaptive_Filter.pre_coeffi.pre_coe_div.rst_n_i     INV      O         Out     0.000     0.000       -         
rst_n_i                                                 Net      -         -       0.657     -           29        
NLMS_Adaptive_Filter.data_control.ce                    DFFR     RESET     In      -         0.657       -         
===================================================================================================================
Total path delay (propagation time + setup) of 0.718 is 0.061(8.5%) logic and 0.657(91.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 222MB peak: 249MB)


Finished timing report (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 222MB peak: 249MB)

---------------------------------------
Resource Usage Report for NLMS_Adaptive_Filter_Top 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             135 uses
ALU54D          2 uses
DFF             41 uses
DFFE            159 uses
DFFR            227 uses
DFFRE           603 uses
DFFS            6 uses
DFFSE           9 uses
GSR             1 use
INV             10 uses
MUX2_LUT5       13 uses
MUX2_LUT6       6 uses
MUX2_LUT7       2 uses
MUX2_LUT8       1 use
RAM16SDP4       10 uses
SPX9            2 uses
LUT2            196 uses
LUT3            252 uses
LUT4            357 uses
MULTALU36X18   2 uses
MULTADDALU18X18 1 use

I/O Register bits:                  0
Register bits not including I/Os:   1045 of 41040 (2%)

RAM/ROM usage summary
Block Rams : 2 of 140 (1%)


Block Multipliers: 3 of 20 (15%)
Total load per clock:
   NLMS_Adaptive_Filter_Top|clk: 1061

@S |Mapping Summary:
Total  LUTs: 805 (1%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 56MB peak: 249MB)

Process took 0h:00m:34s realtime, 0h:00m:32s cputime
# Mon Mar  4 13:44:59 2019

###########################################################]
