library verilog;
use verilog.vl_types.all;
entity DQS is
    generic(
        FIFO_MODE_SEL   : vl_logic := Hi0;
        RD_PNTR         : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
        DQS_MODE        : string  := "X1";
        HWL             : string  := "false";
        GSREN           : string  := "false"
    );
    port(
        DQSR90          : out    vl_logic;
        DQSW0           : out    vl_logic;
        DQSW270         : out    vl_logic;
        RPOINT          : out    vl_logic_vector(2 downto 0);
        WPOINT          : out    vl_logic_vector(2 downto 0);
        RVALID          : out    vl_logic;
        RBURST          : out    vl_logic;
        RFLAG           : out    vl_logic;
        WFLAG           : out    vl_logic;
        DQSIN           : in     vl_logic;
        DLLSTEP         : in     vl_logic_vector(7 downto 0);
        WSTEP           : in     vl_logic_vector(7 downto 0);
        READ            : in     vl_logic_vector(3 downto 0);
        RLOADN          : in     vl_logic;
        RMOVE           : in     vl_logic;
        RDIR            : in     vl_logic;
        WLOADN          : in     vl_logic;
        WMOVE           : in     vl_logic;
        WDIR            : in     vl_logic;
        HOLD            : in     vl_logic;
        RCLKSEL         : in     vl_logic_vector(2 downto 0);
        PCLK            : in     vl_logic;
        FCLK            : in     vl_logic;
        RESET           : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FIFO_MODE_SEL : constant is 1;
    attribute mti_svvh_generic_type of RD_PNTR : constant is 1;
    attribute mti_svvh_generic_type of DQS_MODE : constant is 1;
    attribute mti_svvh_generic_type of HWL : constant is 1;
    attribute mti_svvh_generic_type of GSREN : constant is 1;
end DQS;
