Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_define.vh
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_static_macro_define.vh
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_define.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_name.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_top.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\triple_speed_mac_name.v
C:\Users\liukai\Desktop\mjb_npu\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v
C:\Users\liukai\Desktop\mjb_npu\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v
C:\Users\liukai\Desktop\mjb_npu\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh
C:\Users\liukai\Desktop\mjb_npu\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v
C:\Users\liukai\Desktop\mjb_npu\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18C
Created Time Thu Jul 28 08:12:08 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M1_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 95.391MB
Running netlist conversion:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.201s, Peak memory usage = 95.391MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.736s, Peak memory usage = 95.391MB
    Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 95.391MB
    Optimizing Phase 2: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.641s, Peak memory usage = 95.391MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 95.391MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 95.391MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 95.391MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 95.391MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.451s, Peak memory usage = 95.391MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 95.391MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 95.391MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 20s, Elapsed time = 0h 0m 21s, Peak memory usage = 95.391MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.706s, Peak memory usage = 95.391MB
Generate output files:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 1s, Peak memory usage = 95.391MB
Total Time and Memory Usage CPU time = 0h 0m 28s, Elapsed time = 0h 0m 31s, Peak memory usage = 95.391MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 176
I/O Buf 175
    IBUF 53
    OBUF 120
    IOBUF 2
Register 1561
    DFF 11
    DFFE 1
    DFFSE 1
    DFFR 3
    DFFRE 1
    DFFP 26
    DFFPE 93
    DFFC 355
    DFFCE 1070
LUT 3829
    LUT2 346
    LUT3 1137
    LUT4 2346
ALU 43
    ALU 43
SSRAM 20
    RAM16S4 4
    RAM16SDP4 16
INV 2
    INV 2
DSP 1
    MULT36X36 1
BSRAM 12
    SP 12

Resource Utilization Summary

Resource Usage Utilization
Logic 3994(3831 LUTs, 43 ALUs, 20 SSRAMs) / 20736 19%
Register 1561 / 15750 10%
  --Register as Latch 0 / 15750 0%
  --Register as FF 1561 / 15750 10%
BSRAM 12 / 46 26%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.0(MHz) 94.8(MHz) 16 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.553
Data Arrival Time 11.380
Data Required Time 10.828
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1595 HCLK_ibuf/O
0.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
1.095 0.232 tC2Q RF 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.332 0.237 tNET FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.849 0.517 tINS FF 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.086 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
2.602 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
2.839 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.395 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.632 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.187 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.424 0.237 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
4.994 0.570 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
4.994 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.029 0.035 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.029 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.064 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.064 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.099 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.099 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.134 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.134 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.170 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.170 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.205 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.205 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.240 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.240 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.275 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.275 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.310 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.346 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.346 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.381 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.381 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.416 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.416 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.451 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
5.451 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
5.486 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
5.486 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
5.522 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
5.522 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
5.557 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
5.557 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
5.592 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
5.592 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
5.627 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
5.627 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
5.662 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
5.662 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
5.698 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
5.698 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
5.733 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
5.733 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
5.768 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
5.768 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
5.803 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
5.803 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
6.273 0.470 tINS FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM
6.510 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1
7.065 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
7.302 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/I3
7.673 0.371 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/F
7.910 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2
8.363 0.453 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
8.600 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I1
9.155 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F
9.392 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s6/I3
9.763 0.371 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s6/F
10.000 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s1/I2
10.453 0.453 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s1/F
10.690 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I2
11.143 0.453 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F
11.380 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1595 HCLK_ibuf/O
10.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK
10.828 -0.035 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.205, 68.500%; route: 3.081, 29.294%; tC2Q: 0.232, 2.206%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 0.793
Data Arrival Time 10.034
Data Required Time 10.828
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1595 HCLK_ibuf/O
0.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
1.095 0.232 tC2Q RF 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.332 0.237 tNET FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.849 0.517 tINS FF 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.086 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
2.602 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
2.839 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.395 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.632 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.187 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.424 0.237 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
4.994 0.570 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
4.994 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.029 0.035 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.029 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.064 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.064 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.099 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.099 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.134 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.134 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.170 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.170 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.205 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.205 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.240 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.240 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.275 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.275 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.310 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.346 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.346 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.381 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.381 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.416 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.416 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.451 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
5.451 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
5.486 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
5.486 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
5.522 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
5.522 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
5.557 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
5.557 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
5.592 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
5.592 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
5.627 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
5.627 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
5.662 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
5.662 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
5.698 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
5.698 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
5.733 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
5.733 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
5.768 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
5.768 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
5.803 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
5.803 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
6.273 0.470 tINS FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM
6.510 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1
7.065 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
7.302 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/I3
7.673 0.371 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/F
7.910 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2
8.363 0.453 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
8.600 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I0
9.117 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F
9.354 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0
9.457 0.103 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O
9.694 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0
9.797 0.103 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O
10.034 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1595 HCLK_ibuf/O
10.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK
10.828 -0.035 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 6.096, 66.461%; route: 2.844, 31.009%; tC2Q: 0.232, 2.530%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 0.827
Data Arrival Time 10.000
Data Required Time 10.828
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1595 HCLK_ibuf/O
0.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
1.095 0.232 tC2Q RF 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.332 0.237 tNET FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.849 0.517 tINS FF 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.086 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
2.602 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
2.839 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.395 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.632 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.187 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.424 0.237 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
4.994 0.570 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
4.994 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.029 0.035 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.029 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.064 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.064 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.099 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.099 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.134 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.134 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.170 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.170 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.205 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.205 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.240 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.240 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.275 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.275 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.310 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.346 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.346 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.381 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.381 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.416 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.416 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.451 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
5.451 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
5.486 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
5.486 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
5.522 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
5.522 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
5.557 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
5.557 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
5.592 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
5.592 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
5.627 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
5.627 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
5.662 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
5.662 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
5.698 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
5.698 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
5.733 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
5.733 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
5.768 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
5.768 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
5.803 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
5.803 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
6.273 0.470 tINS FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM
6.510 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1
7.065 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
7.302 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/I3
7.673 0.371 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/F
7.910 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2
8.363 0.453 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
8.600 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I1
9.155 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F
9.392 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I3
9.763 0.371 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F
10.000 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1595 HCLK_ibuf/O
10.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK
10.828 -0.035 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 6.299, 68.931%; route: 2.607, 28.530%; tC2Q: 0.232, 2.539%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 1.297
Data Arrival Time 9.531
Data Required Time 10.828
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1595 HCLK_ibuf/O
0.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
1.095 0.232 tC2Q RF 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.332 0.237 tNET FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.849 0.517 tINS FF 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.086 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
2.602 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
2.839 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.395 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.632 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.187 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.424 0.237 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
4.994 0.570 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
4.994 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.029 0.035 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.029 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.064 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.064 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.099 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.099 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.134 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.134 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.170 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.170 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.205 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.205 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.240 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.240 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.275 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.275 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.310 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.346 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.346 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.381 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.381 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.416 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.416 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.886 0.470 tINS FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/SUM
6.123 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s10/I1
6.678 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s10/F
6.915 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I3
7.286 0.371 tINS FF 3 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F
7.523 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I1
8.078 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F
8.315 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I3
8.686 0.371 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F
8.923 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I3
9.294 0.371 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F
9.531 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1595 HCLK_ibuf/O
10.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK
10.828 -0.035 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.829, 67.249%; route: 2.607, 30.075%; tC2Q: 0.232, 2.676%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 2.595
Data Arrival Time 8.232
Data Required Time 10.828
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 1595 HCLK_ibuf/O
0.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
1.095 0.232 tC2Q RF 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.332 0.237 tNET FF 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.849 0.517 tINS FF 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.086 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
2.602 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
2.839 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.395 0.555 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.632 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.187 0.555 tINS FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.424 0.237 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
4.994 0.570 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
4.994 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.029 0.035 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.029 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.064 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.064 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.099 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.099 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.134 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.134 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.170 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.170 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.205 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.205 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.240 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.240 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.275 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.275 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.310 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.346 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.346 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.381 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.381 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.416 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.416 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.451 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
5.451 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
5.486 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
5.486 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
5.522 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
5.522 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
5.557 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
5.557 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
5.592 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
5.592 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
5.627 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
5.627 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
5.662 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
5.662 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
5.698 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
5.698 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
5.733 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
5.733 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
5.768 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
5.768 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
5.803 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
5.803 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
5.838 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT
5.838 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN
5.874 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT
5.874 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN
5.909 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT
5.909 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN
5.944 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT
5.944 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN
5.979 0.035 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT
5.979 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN
6.449 0.470 tINS FF 6 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM
6.686 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/I1
7.241 0.555 tINS FF 3 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/F
7.478 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/I0
7.995 0.517 tINS FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/F
8.232 0.237 tNET FF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 1595 HCLK_ibuf/O
10.863 0.180 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/CLK
10.828 -0.035 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.242, 71.125%; route: 1.896, 25.727%; tC2Q: 0.232, 3.148%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%