C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1   -part GW1N_9  -package LQFP144  -grade -6    -maxfan 10000 -RWCheckOnRam 1 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synlog\report\Ref_design_premap.xml -merge_inferred_clocks 0  -top_level_module  Top  -implementation  rev_1  -ovm  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.vm  -conchk_prepass  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design_cck.rpt   -autoconstraint  -freq 100.000   E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\Ref_design_mult.srs  -flow prepass  -gcc_prepass  -osrd  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\Ref_design_prem.srd  -qsap  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.sap  -devicelib  C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v  -ologparam  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\syntmp\Ref_design.plg  -osyn  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\Ref_design_prem.srd  -prjdir  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\  -prjname  Ref_design  -log  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synlog\Ref_design_premap.srr  -sn  2019.03  -jobname  "premap" 
relcom:C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rev_1 -part GW1N_9 -package LQFP144 -grade -6 -maxfan 10000 -RWCheckOnRam 1 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\Ref_design_premap.xml -merge_inferred_clocks 0 -top_level_module Top -implementation rev_1 -ovm ..\Ref_design.vm -conchk_prepass ..\Ref_design_cck.rpt -autoconstraint -freq 100.000 ..\synwork\Ref_design_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\Ref_design_prem.srd -qsap ..\Ref_design.sap -devicelib C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v -ologparam Ref_design.plg -osyn ..\synwork\Ref_design_prem.srd -prjdir ..\..\ -prjname Ref_design -log ..\synlog\Ref_design_premap.srr -sn 2019.03 -jobname "premap"
rc:0 success:1 runtime:8
file:..\Ref_design.vm|io:o|time:1575878806|size:816795|exec:0|csum:
file:..\Ref_design_cck.rpt|io:o|time:1576487071|size:4505|exec:0|csum:
file:..\synwork\Ref_design_mult.srs|io:i|time:1576487063|size:5917|exec:0|csum:6A36F28CE7DAF777E200C97C0827240C
file:..\synwork\Ref_design_prem.srd|io:o|time:1576487068|size:2135258|exec:0|csum:
file:..\Ref_design.sap|io:o|time:1576487071|size:708|exec:0|csum:
file:C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v|io:i|time:1575572956|size:163365|exec:0|csum:72413FD6C24A44A1AD96655FFF460C2D
file:Ref_design.plg|io:o|time:1576487064|size:0|exec:0|csum:
file:..\synwork\Ref_design_prem.srd|io:o|time:1576487068|size:2135258|exec:0|csum:
file:..\synlog\Ref_design_premap.srr|io:o|time:1576487071|size:8388|exec:0|csum:
file:C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe|io:i|time:1575571358|size:39936512|exec:1|csum:350A231ED38336BB11E83024B56EB85B
