C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1   -part GW1N_9  -package LQFP144  -grade -6    -maxfan 10000 -RWCheckOnRam 1 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synlog\report\Ref_design_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  Top  -implementation  rev_1  -flow mapping  -multisrs  -ovm  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.vm   -autoconstraint  -freq 100.000   E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\Ref_design_prem.srd  -sap  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.sap  -otap  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.tap  -omap  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.map  -devicelib  C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v  -ologparam  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\syntmp\Ref_design.plg  -osyn  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.srm  -prjdir  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\  -prjname  Ref_design  -log  E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synlog\Ref_design_fpga_mapper.srr  -sn  2019.03  -jobname  "fpga_mapper" 
relcom:C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rev_1 -part GW1N_9 -package LQFP144 -grade -6 -maxfan 10000 -RWCheckOnRam 1 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\Ref_design_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module Top -implementation rev_1 -flow mapping -multisrs -ovm ..\Ref_design.vm -autoconstraint -freq 100.000 ..\synwork\Ref_design_prem.srd -sap ..\Ref_design.sap -otap ..\Ref_design.tap -omap ..\Ref_design.map -devicelib C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v -ologparam Ref_design.plg -osyn ..\Ref_design.srm -prjdir ..\..\ -prjname Ref_design -log ..\synlog\Ref_design_fpga_mapper.srr -sn 2019.03 -jobname "fpga_mapper"
rc:1 success:1 runtime:90
file:..\Ref_design.vm|io:o|time:1576487117|size:816100|exec:0|csum:
file:..\synwork\Ref_design_prem.srd|io:i|time:1576487068|size:2135258|exec:0|csum:8D69340A32E2B4AD5C661B1EDF558F24
file:..\Ref_design.sap|io:o|time:1576487071|size:708|exec:0|csum:
file:..\Ref_design.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\Ref_design.map|io:o|time:1576487161|size:28|exec:0|csum:
file:C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v|io:i|time:1575572956|size:163365|exec:0|csum:72413FD6C24A44A1AD96655FFF460C2D
file:Ref_design.plg|io:o|time:1576487161|size:1117|exec:0|csum:
file:..\Ref_design.srm|io:o|time:1576487116|size:17624|exec:0|csum:
file:..\synlog\Ref_design_fpga_mapper.srr|io:o|time:1576487161|size:195994|exec:0|csum:
file:C:\Gowin\1.9\SynplifyPro\bin64\m_generic.exe|io:i|time:1575571358|size:39936512|exec:1|csum:350A231ED38336BB11E83024B56EB85B
