Project Status Summary Page

Project Settings
Project Name | Ref_design | Device Name | rev_1: GOWIN-GW1N : GW1N_9
Implementation Name | rev_1 | Top Module | Top
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Clock Conversion | 1 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 11 | 3 | 0 | - | 00m:06s | - | 2019/12/16 17:04:21
(premap) | Complete | 5 | 0 | 0 | 0m:05s | 0m:06s | 232MB | 2019/12/16 17:04:31
(fpga_mapper) | Complete | 9 | 4 | 0 | 01m:10s | 01m:28s | 239MB | 2019/12/16 17:06:01
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 2019/12/16 17:04:23

Area Summary
I/O ports (io_port) | 30 | Non I/O Register bits (non_io_reg) | 1258 (19%)
I/O Register bits (total_io_reg) | 0 | Ultra Rams | 0
Block Rams (v_ram) | 4 (26) | Block Multipliers (dsp_used) | 4 (10)
LUTs (total_luts) | 1265 (14%) |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
Top|SYM_CLK | 65.6 MHz | 56.4 MHz | -2.492
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock | 225.2 MHz | 191.4 MHz | -0.784
System | 1152.2 MHz | 979.4 MHz | -0.153

Optimizations Summary
Combined Clock Conversion | 1 / 1 |  |