
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

Modified Files: 10
FID:  path (prevtimestamp, timestamp)
0        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33)
1        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33)
2        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25)
3        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25)
4        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25)
5        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\generic\gw1n.v (N/A, 2019-09-26 01:52:32)
6        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\hypermods.v (N/A, 2019-09-26 00:18:26)
7        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_objects.v (N/A, 2019-09-26 00:18:26)
8        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_pipes.svh (N/A, 2019-09-26 00:18:26)
9        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\umr_capim.v (N/A, 2019-09-26 00:18:26)

*******************************************************************
Modules that may have changed as a result of file changes: 17
MID:  lib.cell.view
0        work.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
1        work.\~Gowin_PLL.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
2        work.\~Gowin_SDP.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
3        work.\~cic_cmp_rom.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
4        work.\~cic_comb.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
5        work.\~cic_compensation_filter.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
6        work.\~cic_decimator.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
7        work.\~cic_down_sample.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
8        work.\~cic_filter.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
9        work.\~cic_integrator.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
10       work.\~clk_div_even.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
11       work.\~data_round.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
12       work.\~delay.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
13       work.\~edge_detect.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
14       work.\~parallel2series.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
15       work.\~pdm2pcm.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
16       work.\~syn_signal.PDM2PCM_Top.verilog may have changed because the following files changed:
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v (N/A, 2019-12-02 10:15:33) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v (N/A, 2019-11-26 14:40:25) <-- (module definition)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)
                        C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v (N/A, 2019-11-26 14:40:25) <-- (may instantiate this module)

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Unmodified files: 0
FID:  path (timestamp)

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Unchanged modules: 0
MID:  lib.cell.view
