#OPTIONS:"|-modgen|-top|ALU54D|-I|C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib|-devicelib|C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\xilinx\\unisim.v|-encrypt|-pro|-sysv|-dw|-primux|-ram|-fixsmult|-tri_compatible|-autosm|-fid2|-sharing|on|-ll|2000|-params|C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\rev_1\\syntmp\\ALU54D.param"
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\bin64\\c_ver.exe":1569428574
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\hypermods.v":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\umr_capim.v":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1569428306
#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\rev_1\\syntmp\\ALU54D.v":1569433956
#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\rev_1\\syntmp\\ALU54D.param":1575252974
#numinternalfiles:4
#defaultlanguage:verilog
0			"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\syntmp\ALU54D.v" verilog
#Dependency Lists(Uses List)
0 -1
#Dependency Lists(Users Of)
0 -1
#Design Unit to File Association
module work MULTADDALU18X18 0
module work ALU54D 0
module work PADD18 0
module work PADD9 0
