#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
#OS: Windows 8 6.2
#Hostname: DESKTOP-8MH08IC

# Fri Dec  6 15:51:21 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\pdm2pcm\pdm2pcm.v" (library work)
@I::"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\Top.v" (library work)
@I:"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\Top.v":"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v" (library work)
@I::"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\data_rom.v" (library work)
@W: CS141 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\data_rom.v":3:7:3:11|Unrecognized synthesis directive title. Verify the correct directive name.
Verilog syntax check successful!
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v":1:0:1:8|Synthesizing module work_C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\pdm2pcm\pdm2pcm.v_unit in library work.
Selecting top level module Top
@N: CG364 :"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\generic\gw1n.v":1864:7:1864:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~syn_signal.PDM2PCM_Top_  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__4s_2s  .......
Running optimization stage 1 on PLL .......
Running optimization stage 1 on \~Gowin_PLL.PDM2PCM_Top_  .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on \~clk_div_even.PDM2PCM_Top_  .......
Running optimization stage 1 on \~edge_detect.PDM2PCM_Top__1_4s  .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on \~parallel2series.PDM2PCM_Top__1_4s_4s_1s_2s  .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on RAM16SDP4 .......
Running optimization stage 1 on RAM16S4 .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_2  .......
Running optimization stage 1 on DFFE .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s  .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_0  .......
Running optimization stage 1 on \~cic_down_sample.PDM2PCM_Top__4s_32s_46s_2s  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_0  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_1  .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top__46s_24s_22s_23s_47s_0s  .......
Running optimization stage 1 on \~cic_decimator.PDM2PCM_Top__4s_64s_3s_1s_24s_24s_46s  .......
Running optimization stage 1 on \~cic_filter.PDM2PCM_Top__4s_64s_3s_1s_24s_24s  .......
Running optimization stage 1 on ALU54D .......
Running optimization stage 1 on MULT36X36 .......
Running optimization stage 1 on rROM .......
Running optimization stage 1 on \~cic_cmp_rom.PDM2PCM_Top__96s_24s  .......
Running optimization stage 1 on SDP .......
Running optimization stage 1 on \~Gowin_SDP.PDM2PCM_Top_  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__6s_3s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__2s_5s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__6s_2s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__1s_59s  .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top__48s_24s_9s_23s_34s_15s  .......
Running optimization stage 1 on \~cic_compensation_filter.PDM2PCM_Top__Z1  .......
Running optimization stage 1 on \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s  .......
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\pdm2pcm\pdm2pcm.v":26441:7:26441:17|Synthesizing module PDM2PCM_Top in library work.
Running optimization stage 1 on PDM2PCM_Top .......
@W: CL168 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\pdm2pcm\pdm2pcm.v":26486:6:26486:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\generic\gw1n.v":1407:7:1407:9|Synthesizing module ROM in library work.
Running optimization stage 1 on ROM .......
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\data_rom.v":8:7:8:14|Synthesizing module Data_ROM in library work.
@W: CS263 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\data_rom.v":23:8:23:15|Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on Data_ROM .......
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\Top.v":2:7:2:9|Synthesizing module Top in library work.
@N: CG179 :"C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\src\Top.v":137:54:137:60|Removing redundant assignment.
Running optimization stage 1 on Top .......
Running optimization stage 2 on Top .......
Running optimization stage 2 on Data_ROM .......
Running optimization stage 2 on ROM .......
Running optimization stage 2 on PDM2PCM_Top .......
Running optimization stage 2 on \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s  .......
Running optimization stage 2 on \~cic_compensation_filter.PDM2PCM_Top__Z1  .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top__48s_24s_9s_23s_34s_15s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__1s_59s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__6s_2s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__2s_5s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__6s_3s  .......
Running optimization stage 2 on \~Gowin_SDP.PDM2PCM_Top_  .......
Running optimization stage 2 on SDP .......
Running optimization stage 2 on \~cic_cmp_rom.PDM2PCM_Top__96s_24s  .......
Running optimization stage 2 on rROM .......
Running optimization stage 2 on MULT36X36 .......
Running optimization stage 2 on ALU54D .......
Running optimization stage 2 on \~cic_filter.PDM2PCM_Top__4s_64s_3s_1s_24s_24s  .......
Running optimization stage 2 on \~cic_decimator.PDM2PCM_Top__4s_64s_3s_1s_24s_24s_46s  .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top__46s_24s_22s_23s_47s_0s  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_1  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_0  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s  .......
Running optimization stage 2 on \~cic_down_sample.PDM2PCM_Top__4s_32s_46s_2s  .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_0  .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s  .......
Running optimization stage 2 on DFFE .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_2  .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on RAM16S4 .......
Running optimization stage 2 on RAM16SDP4 .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on \~parallel2series.PDM2PCM_Top__1_4s_4s_1s_2s  .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on \~edge_detect.PDM2PCM_Top__1_4s  .......
Running optimization stage 2 on \~clk_div_even.PDM2PCM_Top_  .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on \~Gowin_PLL.PDM2PCM_Top_  .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__4s_2s  .......
Running optimization stage 2 on \~syn_signal.PDM2PCM_Top_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 110MB peak: 110MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime

Process completed successfully.
# Fri Dec  6 15:51:29 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Dec  6 15:51:29 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\synwork\Ref_design_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:08s realtime, 0h:00m:07s cputime

Process completed successfully.
# Fri Dec  6 15:51:29 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Dec  6 15:51:31 2019

###########################################################]
Premap Report

# Fri Dec  6 15:51:31 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 116MB)

@A: MF827 |No constraint file specified.
@L: C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\Ref_design_scck.rpt 
Printing clock  summary report in "C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\Ref_design_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)



Clock Summary
******************

          Start                                                Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                               100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                                                                       
0 -       Top|SYM_CLK                                          35.2 MHz      28.407        inferred     Autoconstr_clkgroup_0     1399 
                                                                                                                                       
0 -       _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     417.6 MHz     2.395         inferred     Autoconstr_clkgroup_1     6    
=======================================================================================================================================



Clock Load Summary
***********************

                                                     Clock     Source                                               Clock Pin                                                Non-clock Pin     Non-clock Pin
Clock                                                Load      Pin                                                  Seq Example                                              Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                               0         -                                                    -                                                        -                 -            
                                                                                                                                                                                                            
Top|SYM_CLK                                          1399      SYM_CLK(port)                                        pdm_sclk_r1.C                                            -                 -            
                                                                                                                                                                                                            
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     6         PDM2PCM_Top.pdm2pcm.iSysClk.pll_inst.CLKOUT(PLL)     PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\].CLK     -                 -            
============================================================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 1399 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 6 clock pin(s) of sequential element(s)
0 instances converted, 6 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       SYM_CLK             port                   1399       cnt_addr[11:0] 
=======================================================================================
=================================================== Gated/Generated Clocks ====================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation            
-------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_1       ENCRYPTED           PLL                    6                      ENCRYPTED           Black box on clock path
===============================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\Ref_design.sap.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 229MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 229MB)


Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 143MB peak: 230MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Fri Dec  6 15:51:36 2019

###########################################################]
Map & Optimize Report

# Fri Dec  6 15:51:36 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 116MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 121MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)


Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 236MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 236MB peak: 236MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 236MB peak: 236MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 236MB peak: 236MB)


Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 236MB peak: 236MB)


Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 236MB peak: 236MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:07s		    -6.27ns		1279 /        48
   2		0h:00m:07s		    -6.27ns		1278 /        48

   3		0h:00m:07s		    -6.27ns		1278 /        48

   4		0h:00m:07s		    -6.27ns		1278 /        48

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 237MB peak: 237MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port

Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 237MB peak: 237MB)


Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 154MB peak: 237MB)

Writing Analyst data base C:\Users\Noa\Desktop\Myworkplace\Gowin\Project\PDM2PCM\RefDesign\project\Ref_design\impl\synthesize\rev_1\synwork\Ref_design_m.srm
Warning: Found 48 combinational loops!
1) instance \\un2_acc_dsp_out\[47\:0\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net N_1 (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.N_1
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[0\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[0]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[0]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.N_1
2) instance \\acc_dsp_out_4_cZ\[1\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[1\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[1\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[1]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[1]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[1]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[1\]
3) instance \\acc_dsp_out_4_cZ\[2\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[2\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[2\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[2]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[2]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[2]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[2\]
4) instance \\acc_dsp_out_4_cZ\[3\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[3\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[3\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[3]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[3]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[3]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[3\]
5) instance \\acc_dsp_out_4_cZ\[4\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[4\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[4\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[4]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[4]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.acc_dsp_out_4_RNO[4]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[4\]
6) instance \\acc_dsp_out_4_cZ\[5\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[5\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[5\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[5]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[5]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[5]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[5\]
7) instance \\acc_dsp_out_4_cZ\[6\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[6\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[6\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[6]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[6]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[6]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[6\]
8) instance \\acc_dsp_out_4_cZ\[7\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[7\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[7\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[7]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[7]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[7]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[7\]
9) instance \\acc_dsp_out_4_cZ\[8\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[8\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[8\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[8]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[8]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[8]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[8\]
10) instance \\acc_dsp_out_4_cZ\[9\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[9\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[9\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[9]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[9]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[9]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[9\]
11) instance \\acc_dsp_out_4_cZ\[10\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[10\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[10\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[10]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[10]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[10]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[10\]
12) instance \\acc_dsp_out_4_cZ\[11\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[11\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[11\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[11]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[11]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[11]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[11\]
13) instance \\acc_dsp_out_4_cZ\[12\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[12\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[12\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[12]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[12]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[12]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[12\]
14) instance \\acc_dsp_out_4_cZ\[13\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[13\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[13\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[13]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[13]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[13]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[13\]
15) instance \\acc_dsp_out_4_cZ\[14\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[14\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[14\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[14]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[14]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[14]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[14\]
16) instance \\acc_dsp_out_4_cZ\[15\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[15\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[15\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[15]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[15]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[15]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[15\]
17) instance \\acc_dsp_out_4_cZ\[16\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[16\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[16\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[16]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[16]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[16]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[16\]
18) instance \\acc_dsp_out_4_cZ\[17\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[17\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[17\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[17]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[17]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[17]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[17\]
19) instance \\acc_dsp_out_4_cZ\[18\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[18\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[18\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[18]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[18]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[18]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[18\]
20) instance \\acc_dsp_out_4_cZ\[19\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[19\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[19\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[19]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[19]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[19]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[19\]
21) instance \\acc_dsp_out_4_cZ\[20\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[20\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[20\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[20]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[20]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[20]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[20\]
22) instance \\acc_dsp_out_4_cZ\[21\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[21\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[21\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[21]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[21]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[21]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[21\]
23) instance \\acc_dsp_out_4_cZ\[22\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[22\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[22\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[22]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[22]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[22]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[22\]
24) instance \\acc_dsp_out_4_cZ\[23\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4 (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[23]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[23]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[23]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4
25) instance \\acc_dsp_out_4_cZ\[24\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[24\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[24]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[24]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]_RNO
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]
26) instance \\acc_dsp_out_4_cZ\[25\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[25\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[25\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[25]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[25]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[25]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[25\]
27) instance \\acc_dsp_out_4_cZ\[26\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[26\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[26\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[26]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[26]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[26]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[26\]
28) instance \\acc_dsp_out_4_cZ\[27\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[27\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[27\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[27]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[27]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[27]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[27\]
29) instance \\acc_dsp_out_4_cZ\[28\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[28\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[28\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[28]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[28]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[28]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[28\]
30) instance \\acc_dsp_out_4_cZ\[29\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[29\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[29\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[29]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[29]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[29]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[29\]
31) instance \\acc_dsp_out_4_cZ\[30\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[30\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[30\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[30]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[30]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[30]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[30\]
32) instance \\acc_dsp_out_4_cZ\[31\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[31\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[31\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[31]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[31]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[31]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[31\]
33) instance \\acc_dsp_out_4_cZ\[32\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[32\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[32\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[32]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[32]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[32]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[32\]
34) instance \\acc_dsp_out_4_cZ\[33\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[33\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[33\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[33]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[33]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[33]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[33\]
35) instance \\acc_dsp_out_4_cZ\[34\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[34\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[34\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[34]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[34]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[34]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[34\]
36) instance \\acc_dsp_out_4_cZ\[35\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[35\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[35\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[35]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[35]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[35]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[35\]
37) instance \\acc_dsp_out_4_cZ\[36\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[36\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[36\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[36]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[36]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[36]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[36\]
38) instance \\acc_dsp_out_4_cZ\[37\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[37\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[37\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[37]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[37]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[37]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[37\]
39) instance \\acc_dsp_out_4_cZ\[38\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[38\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[38\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[38]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[38]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[38]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[38\]
40) instance \\acc_dsp_out_4_cZ\[39\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[39\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[39\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[39]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[39]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[39]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[39\]
41) instance \\acc_dsp_out_4_cZ\[40\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[40\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[40\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[40]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[40]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[40]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[40\]
42) instance \\acc_dsp_out_4_cZ\[41\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[41\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[41\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[41]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[41]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[41]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[41\]
43) instance \\acc_dsp_out_4_cZ\[42\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[42\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[42\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[42]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[42]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[42]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[42\]
44) instance \\acc_dsp_out_4_cZ\[43\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[43\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[43\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[43]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[43]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[43]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[43\]
45) instance \\acc_dsp_out_4_cZ\[44\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[44\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[44\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[44]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[44]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[44]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[44\]
46) instance \\acc_dsp_out_4_cZ\[45\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[45\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[45\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[45]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[45]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[45]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[45\]
47) instance \\acc_dsp_out_4_cZ\[46\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[46\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[46\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[46]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[46]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[46]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[46\]
48) instance \\acc_dsp_out_4_cZ\[47\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[47\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[47\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[47]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[47]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[47]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[47\]
End of loops

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 234MB peak: 237MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 234MB peak: 237MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 235MB peak: 237MB)


Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:13s; Memory used current: 230MB peak: 237MB)

Warning: Found 48 combinational loops!
1) instance \\un2_acc_dsp_out\[47\:0\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net N_1 (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.N_1
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[0\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[0]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[0]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.N_1
2) instance \\acc_dsp_out_4_cZ\[1\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[1\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[1\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[1]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[1]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[1]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[1\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[1\]
3) instance \\acc_dsp_out_4_cZ\[2\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[2\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[2\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[2]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[2]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[2]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[2\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[2\]
4) instance \\acc_dsp_out_4_cZ\[3\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[3\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[3\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[3]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[3]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[3]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[3\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[3\]
5) instance \\acc_dsp_out_4_cZ\[4\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[4\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[4\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[4]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[4]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.acc_dsp_out_4_RNO[4]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]/I0
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[4\]
6) instance \\acc_dsp_out_4_cZ\[5\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[5\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[5\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[5]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[5]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[5]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[5\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[5\]
7) instance \\acc_dsp_out_4_cZ\[6\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[6\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[6\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[6]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[6]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[6]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[6\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[6\]
8) instance \\acc_dsp_out_4_cZ\[7\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[7\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[7\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[7]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[7]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[7]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[7\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[7\]
9) instance \\acc_dsp_out_4_cZ\[8\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[8\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[8\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[8]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[8]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[8]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[8\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[8\]
10) instance \\acc_dsp_out_4_cZ\[9\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[9\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[9\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[9]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[9]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[9]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[9\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[9\]
11) instance \\acc_dsp_out_4_cZ\[10\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[10\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[10\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[10]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[10]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[10]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[10\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[10\]
12) instance \\acc_dsp_out_4_cZ\[11\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[11\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[11\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[11]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[11]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[11]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[11\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[11\]
13) instance \\acc_dsp_out_4_cZ\[12\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[12\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[12\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[12]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[12]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[12]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[12\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[12\]
14) instance \\acc_dsp_out_4_cZ\[13\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[13\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[13\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[13]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[13]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[13]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[13\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[13\]
15) instance \\acc_dsp_out_4_cZ\[14\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[14\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[14\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[14]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[14]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[14]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[14\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[14\]
16) instance \\acc_dsp_out_4_cZ\[15\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[15\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[15\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[15]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[15]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[15]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[15\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[15\]
17) instance \\acc_dsp_out_4_cZ\[16\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[16\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[16\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[16]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[16]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[16]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[16\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[16\]
18) instance \\acc_dsp_out_4_cZ\[17\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[17\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[17\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[17]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[17]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[17]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[17\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[17\]
19) instance \\acc_dsp_out_4_cZ\[18\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[18\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[18\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[18]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[18]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[18]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[18\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[18\]
20) instance \\acc_dsp_out_4_cZ\[19\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[19\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[19\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[19]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[19]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[19]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[19\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[19\]
21) instance \\acc_dsp_out_4_cZ\[20\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[20\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[20\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[20]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[20]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[20]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[20\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[20\]
22) instance \\acc_dsp_out_4_cZ\[21\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[21\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[21\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[21]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[21]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[21]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[21\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[21\]
23) instance \\acc_dsp_out_4_cZ\[22\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[22\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[22\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[22]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[22]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[22]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[22\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[22\]
24) instance \\acc_dsp_out_4_cZ\[23\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4 (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[23]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[23]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[23]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[23\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[23\]_RNI8CN4
25) instance \\acc_dsp_out_4_cZ\[24\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[24\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[24]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[24]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]_RNO
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[24\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[24\]
26) instance \\acc_dsp_out_4_cZ\[25\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[25\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[25\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[25]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[25]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[25]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[25\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[25\]
27) instance \\acc_dsp_out_4_cZ\[26\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[26\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[26\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[26]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[26]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[26]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[26\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[26\]
28) instance \\acc_dsp_out_4_cZ\[27\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[27\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[27\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[27]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[27]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[27]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[27\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[27\]
29) instance \\acc_dsp_out_4_cZ\[28\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[28\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[28\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[28]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[28]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[28]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[28\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[28\]
30) instance \\acc_dsp_out_4_cZ\[29\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[29\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[29\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[29]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[29]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[29]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[29\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[29\]
31) instance \\acc_dsp_out_4_cZ\[30\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[30\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[30\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[30]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[30]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[30]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[30\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[30\]
32) instance \\acc_dsp_out_4_cZ\[31\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[31\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[31\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[31]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[31]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[31]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[31\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[31\]
33) instance \\acc_dsp_out_4_cZ\[32\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[32\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[32\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[32]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[32]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[32]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[32\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[32\]
34) instance \\acc_dsp_out_4_cZ\[33\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[33\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[33\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[33]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[33]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[33]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[33\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[33\]
35) instance \\acc_dsp_out_4_cZ\[34\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[34\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[34\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[34]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[34]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[34]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[34\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[34\]
36) instance \\acc_dsp_out_4_cZ\[35\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[35\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[35\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[35]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[35]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[35]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[35\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[35\]
37) instance \\acc_dsp_out_4_cZ\[36\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[36\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[36\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[36]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[36]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[36]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[36\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[36\]
38) instance \\acc_dsp_out_4_cZ\[37\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[37\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[37\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[37]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[37]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[37]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[37\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[37\]
39) instance \\acc_dsp_out_4_cZ\[38\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[38\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[38\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[38]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[38]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[38]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[38\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[38\]
40) instance \\acc_dsp_out_4_cZ\[39\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[39\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[39\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[39]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[39]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[39]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[39\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[39\]
41) instance \\acc_dsp_out_4_cZ\[40\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[40\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[40\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[40]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[40]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[40]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[40\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[40\]
42) instance \\acc_dsp_out_4_cZ\[41\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[41\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[41\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[41]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[41]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[41]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[41\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[41\]
43) instance \\acc_dsp_out_4_cZ\[42\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[42\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[42\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[42]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[42]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[42]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[42\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[42\]
44) instance \\acc_dsp_out_4_cZ\[43\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[43\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[43\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[43]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[43]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[43]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[43\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[43\]
45) instance \\acc_dsp_out_4_cZ\[44\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[44\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[44\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[44]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[44]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[44]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[44\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[44\]
46) instance \\acc_dsp_out_4_cZ\[45\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[45\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[45\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[45]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[45]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[45]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[45\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[45\]
47) instance \\acc_dsp_out_4_cZ\[46\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[46\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[46\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[46]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[46]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[46]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[46\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[46\]
48) instance \\acc_dsp_out_4_cZ\[47\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist)), output net Z\\acc_dsp_out_4_cZ\[47\] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top__Z1\ (netlist))
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[47\]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/B[47]
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\] (cell ALU54D)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]/DOUT[47]
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\un2_acc_dsp_out\[47\:0\]_DOUT[47]
    input  pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\]/I3
    instance   PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\] (cell LUT4)
    output pin PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[47\]/F
    net        PDM2PCM_Top.pdm2pcm.cic_cmp.Z\\acc_dsp_out_4_cZ\[47\]
End of loops
@W: MT246 :"c:\users\noa\desktop\myworkplace\gowin\project\pdm2pcm\refdesign\project\ref_design\src\pdm2pcm\pdm2pcm.v":18745:7:18745:22|Blackbox rROM is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\users\noa\desktop\myworkplace\gowin\project\pdm2pcm\refdesign\project\ref_design\src\pdm2pcm\pdm2pcm.v":177:6:177:13|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock Top|SYM_CLK with period 15.23ns. Please declare a user-defined clock on port SYM_CLK.
@W: MT420 |Found inferred clock _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock with period 4.44ns. Please declare a user-defined clock on net PDM2PCM_Top.pdm2pcm.iSysClk.sym_clk.


##### START OF TIMING REPORT #####[
# Timing report written on Fri Dec  6 15:51:52 2019
#


Top view:               Top
Requested Frequency:    65.6 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -2.492

                                                     Requested      Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                                       Frequency      Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Top|SYM_CLK                                          65.6 MHz       56.4 MHz      15.234        17.726        -2.492     inferred     Autoconstr_clkgroup_0
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     225.2 MHz      191.4 MHz     4.441         5.225         -0.784     inferred     Autoconstr_clkgroup_1
System                                               1152.2 MHz     979.4 MHz     0.868         1.021         -0.153     system       system_clkgroup      
===========================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                          Ending                                            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                            System                                            |  0.868       -0.153  |  No paths    -      |  No paths    -      |  No paths    -    
System                                            Top|SYM_CLK                                       |  15.234      -0.969  |  No paths    -      |  No paths    -      |  No paths    -    
System                                            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock  |  4.441       3.287   |  No paths    -      |  No paths    -      |  No paths    -    
Top|SYM_CLK                                       System                                            |  15.234      8.966   |  No paths    -      |  No paths    -      |  No paths    -    
Top|SYM_CLK                                       Top|SYM_CLK                                       |  15.234      -2.492  |  No paths    -      |  No paths    -      |  No paths    -    
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock  System                                            |  4.441       3.053   |  No paths    -      |  No paths    -      |  No paths    -    
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock  Top|SYM_CLK                                       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock  _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock  |  4.441       -0.784  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Top|SYM_CLK
====================================



Starting Points with Worst Slack
********************************

                                                      Starting                                              Arrival           
Instance                                              Reference       Type      Pin     Net                 Time        Slack 
                                                      Clock                                                                   
------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[1]     0.367       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[2\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[2]     0.367       -2.435
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_rd_d_Z\[0\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_rd_d[0]     0.367       -2.405
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[3\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[3]     0.367       -2.378
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_rd_d_Z\[1\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_rd_d[1]     0.367       -2.348
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[4\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[4]     0.367       -2.321
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_rd_d_Z\[2\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_rd_d[2]     0.367       -2.291
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[5\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[5]     0.367       -2.264
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_rd_d_Z\[3\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_rd_d[3]     0.367       -2.234
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[6\]     Top|SYM_CLK     DFFCE     Q       cnt_mem_wr_d[6]     0.367       -2.207
==============================================================================================================================


Ending Points with Worst Slack
******************************

                                                               Starting                                                         Required           
Instance                                                       Reference       Type        Pin       Net                        Time         Slack 
                                                               Clock                                                                               
---------------------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     Top|SYM_CLK     RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[0\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     Top|SYM_CLK     RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[1\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     Top|SYM_CLK     RAM16S4     DI[2]     Z\\un1_acc_out_cZ\[2\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     Top|SYM_CLK     RAM16S4     DI[3]     Z\\un1_acc_out_cZ\[3\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     Top|SYM_CLK     RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[4\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     Top|SYM_CLK     RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[5\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     Top|SYM_CLK     RAM16S4     DI[2]     Z\\un1_acc_out_cZ\[6\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     Top|SYM_CLK     RAM16S4     DI[3]     Z\\un1_acc_out_cZ\[7\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_2     Top|SYM_CLK     RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[8\]     15.173       -2.492
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_2     Top|SYM_CLK     RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[9\]     15.173       -2.492
===================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      17.665
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.492

    Number of logic level(s):                16
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            Top|SYM_CLK [rising] on pin CLK
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]                     DFFCE         Q            Out     0.367     0.367       -         
cnt_mem_wr_d[1]                                                       Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           I1           In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           COUT         Out     1.045     2.433       -         
un1_cnt_mem_wr_d_cry_0_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           CIN          In      -         2.433       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           COUT         Out     0.057     2.490       -         
un1_cnt_mem_wr_d_cry_1_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           CIN          In      -         2.490       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           COUT         Out     0.057     2.547       -         
un1_cnt_mem_wr_d_cry_2_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           CIN          In      -         2.547       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           COUT         Out     0.057     2.604       -         
un1_cnt_mem_wr_d_cry_3_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           CIN          In      -         2.604       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           COUT         Out     0.057     2.661       -         
un1_cnt_mem_wr_d_cry_4_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           CIN          In      -         2.661       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           COUT         Out     0.057     2.718       -         
un1_cnt_mem_wr_d_cry_5_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           CIN          In      -         2.718       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           COUT         Out     0.057     2.775       -         
un1_cnt_mem_wr_d_cry_6_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           CIN          In      -         2.775       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           COUT         Out     0.057     2.832       -         
un1_cnt_mem_wr_d_cry_7_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           CIN          In      -         2.832       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           COUT         Out     0.057     2.889       -         
un1_cnt_mem_wr_d_cry_8_0_COUT                                         Net           -            -       1.671     -           24        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I1           In      -         4.560       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.099     5.659       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[23]        In      -         6.741       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     7.579       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         8.600       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     9.226       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         10.247      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     11.085      -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         12.106      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     13.138      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         14.159      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     14.997      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         16.018      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     16.644      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         17.665      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 17.726 is 7.826(44.1%) logic and 9.900(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      17.665
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.492

    Number of logic level(s):                16
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            Top|SYM_CLK [rising] on pin CLK
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]                     DFFCE         Q            Out     0.367     0.367       -         
cnt_mem_wr_d[1]                                                       Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           I1           In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           COUT         Out     1.045     2.433       -         
un1_cnt_mem_wr_d_cry_0_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           CIN          In      -         2.433       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           COUT         Out     0.057     2.490       -         
un1_cnt_mem_wr_d_cry_1_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           CIN          In      -         2.490       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           COUT         Out     0.057     2.547       -         
un1_cnt_mem_wr_d_cry_2_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           CIN          In      -         2.547       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           COUT         Out     0.057     2.604       -         
un1_cnt_mem_wr_d_cry_3_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           CIN          In      -         2.604       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           COUT         Out     0.057     2.661       -         
un1_cnt_mem_wr_d_cry_4_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           CIN          In      -         2.661       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           COUT         Out     0.057     2.718       -         
un1_cnt_mem_wr_d_cry_5_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           CIN          In      -         2.718       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           COUT         Out     0.057     2.775       -         
un1_cnt_mem_wr_d_cry_6_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           CIN          In      -         2.775       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           COUT         Out     0.057     2.832       -         
un1_cnt_mem_wr_d_cry_7_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           CIN          In      -         2.832       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           COUT         Out     0.057     2.889       -         
un1_cnt_mem_wr_d_cry_8_0_COUT                                         Net           -            -       1.671     -           24        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I1           In      -         4.560       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.099     5.659       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[35]        In      -         6.741       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     7.579       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         8.600       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     9.226       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         10.247      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     11.085      -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         12.106      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     13.138      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         14.159      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     14.997      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         16.018      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     16.644      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         17.665      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 17.726 is 7.826(44.1%) logic and 9.900(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      17.665
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.492

    Number of logic level(s):                16
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            Top|SYM_CLK [rising] on pin CLK
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]                     DFFCE         Q            Out     0.367     0.367       -         
cnt_mem_wr_d[1]                                                       Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           I1           In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           COUT         Out     1.045     2.433       -         
un1_cnt_mem_wr_d_cry_0_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           CIN          In      -         2.433       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           COUT         Out     0.057     2.490       -         
un1_cnt_mem_wr_d_cry_1_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           CIN          In      -         2.490       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           COUT         Out     0.057     2.547       -         
un1_cnt_mem_wr_d_cry_2_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           CIN          In      -         2.547       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           COUT         Out     0.057     2.604       -         
un1_cnt_mem_wr_d_cry_3_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           CIN          In      -         2.604       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           COUT         Out     0.057     2.661       -         
un1_cnt_mem_wr_d_cry_4_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           CIN          In      -         2.661       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           COUT         Out     0.057     2.718       -         
un1_cnt_mem_wr_d_cry_5_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           CIN          In      -         2.718       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           COUT         Out     0.057     2.775       -         
un1_cnt_mem_wr_d_cry_6_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           CIN          In      -         2.775       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           COUT         Out     0.057     2.832       -         
un1_cnt_mem_wr_d_cry_7_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           CIN          In      -         2.832       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           COUT         Out     0.057     2.889       -         
un1_cnt_mem_wr_d_cry_8_0_COUT                                         Net           -            -       1.671     -           24        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I1           In      -         4.560       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.099     5.659       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[34]        In      -         6.741       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     7.579       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         8.600       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     9.226       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         10.247      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     11.085      -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         12.106      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     13.138      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         14.159      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     14.997      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         16.018      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     16.644      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         17.665      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 17.726 is 7.826(44.1%) logic and 9.900(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      17.665
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.492

    Number of logic level(s):                16
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            Top|SYM_CLK [rising] on pin CLK
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]                     DFFCE         Q            Out     0.367     0.367       -         
cnt_mem_wr_d[1]                                                       Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           I1           In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           COUT         Out     1.045     2.433       -         
un1_cnt_mem_wr_d_cry_0_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           CIN          In      -         2.433       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           COUT         Out     0.057     2.490       -         
un1_cnt_mem_wr_d_cry_1_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           CIN          In      -         2.490       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           COUT         Out     0.057     2.547       -         
un1_cnt_mem_wr_d_cry_2_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           CIN          In      -         2.547       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           COUT         Out     0.057     2.604       -         
un1_cnt_mem_wr_d_cry_3_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           CIN          In      -         2.604       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           COUT         Out     0.057     2.661       -         
un1_cnt_mem_wr_d_cry_4_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           CIN          In      -         2.661       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           COUT         Out     0.057     2.718       -         
un1_cnt_mem_wr_d_cry_5_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           CIN          In      -         2.718       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           COUT         Out     0.057     2.775       -         
un1_cnt_mem_wr_d_cry_6_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           CIN          In      -         2.775       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           COUT         Out     0.057     2.832       -         
un1_cnt_mem_wr_d_cry_7_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           CIN          In      -         2.832       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           COUT         Out     0.057     2.889       -         
un1_cnt_mem_wr_d_cry_8_0_COUT                                         Net           -            -       1.671     -           24        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I1           In      -         4.560       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.099     5.659       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[33]        In      -         6.741       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     7.579       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         8.600       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     9.226       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         10.247      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     11.085      -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         12.106      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     13.138      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         14.159      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     14.997      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         16.018      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     16.644      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         17.665      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 17.726 is 7.826(44.1%) logic and 9.900(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      17.665
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.492

    Number of logic level(s):                16
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            Top|SYM_CLK [rising] on pin CLK
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\cnt_mem_wr_d_Z\[1\]                     DFFCE         Q            Out     0.367     0.367       -         
cnt_mem_wr_d[1]                                                       Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           I1           In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_0_0                  ALU           COUT         Out     1.045     2.433       -         
un1_cnt_mem_wr_d_cry_0_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           CIN          In      -         2.433       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_1_0                  ALU           COUT         Out     0.057     2.490       -         
un1_cnt_mem_wr_d_cry_1_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           CIN          In      -         2.490       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_2_0                  ALU           COUT         Out     0.057     2.547       -         
un1_cnt_mem_wr_d_cry_2_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           CIN          In      -         2.547       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_3_0                  ALU           COUT         Out     0.057     2.604       -         
un1_cnt_mem_wr_d_cry_3_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           CIN          In      -         2.604       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_4_0                  ALU           COUT         Out     0.057     2.661       -         
un1_cnt_mem_wr_d_cry_4_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           CIN          In      -         2.661       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_5_0                  ALU           COUT         Out     0.057     2.718       -         
un1_cnt_mem_wr_d_cry_5_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           CIN          In      -         2.718       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_6_0                  ALU           COUT         Out     0.057     2.775       -         
un1_cnt_mem_wr_d_cry_6_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           CIN          In      -         2.775       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_7_0                  ALU           COUT         Out     0.057     2.832       -         
un1_cnt_mem_wr_d_cry_7_0_COUT                                         Net           -            -       0.000     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           CIN          In      -         2.832       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.un1_cnt_mem_wr_d_cry_8_0                  ALU           COUT         Out     0.057     2.889       -         
un1_cnt_mem_wr_d_cry_8_0_COUT                                         Net           -            -       1.671     -           24        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I1           In      -         4.560       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.099     5.659       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[32]        In      -         6.741       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     7.579       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         8.600       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     9.226       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         10.247      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     11.085      -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         12.106      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     13.138      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         14.159      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     14.997      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         16.018      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     16.644      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         17.665      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 17.726 is 7.826(44.1%) logic and 9.900(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                Arrival           
Instance                                             Reference                                            Type      Pin     Net              Time        Slack 
                                                     Clock                                                                                                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\]     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       cnt_div[1]       0.367       -0.784
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\]     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       cnt_div[0]       0.367       -0.656
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[2\]     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       cnt_div[2]       0.367       -0.507
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\]     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       cnt_div[3]       0.367       -0.311
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\]     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       cnt_div[4]       0.367       0.301 
PDM2PCM_Top.pdm2pcm.clk_div_PDM.clk_out              _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     Q       out_pdm_sclk     0.367       3.053 
===============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                      Starting                                                                                           Required           
Instance                                              Reference                                            Type      Pin     Net                         Time         Slack 
                                                      Clock                                                                                                                 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\]      _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     D       cnt_div_3[3]                4.308        -0.784
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\]      _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     D       cnt_div_3[4]                4.308        -0.784
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\]      _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     D       cnt_div_3[0]                4.308        -0.037
PDM2PCM_Top.pdm2pcm.clk_div_PDM.clk_out               _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     CE      clk_out_0_sqmuxa            4.308        0.368 
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\]      _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     D       un5_cnt_div_1_axbxc1_cZ     4.308        1.760 
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[2\]      _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     DFFCE     D       un5_cnt_div_1_axbxc2_cZ     4.308        1.760 
PDM2PCM_Top.pdm2pcm.clk_div_PDM.out_pdm_sclk_i_cZ     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     INV       I       out_pdm_sclk                4.441        3.053 
============================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.441
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.308

    - Propagation time:                      5.092
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.784

    Number of logic level(s):                2
    Starting point:                          PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\] / D
    The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                    Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\]        DFFCE         Q        Out     0.367     0.367       -         
cnt_div[1]                                              Net           -        -       1.082     -           14        
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          I1       In      -         1.449       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          F        Out     1.099     2.548       -         
cnt_div_3_rn_0[3]                                       Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     S0       In      -         3.569       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     O        Out     0.502     4.071       -         
cnt_div_3[3]                                            Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\]        DFFCE         D        In      -         5.092       -         
=======================================================================================================================
Total path delay (propagation time + setup) of 5.225 is 2.101(40.2%) logic and 3.124(59.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.441
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.308

    - Propagation time:                      5.092
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.784

    Number of logic level(s):                2
    Starting point:                          PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\] / D
    The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                    Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[1\]        DFFCE         Q        Out     0.367     0.367       -         
cnt_div[1]                                              Net           -        -       1.082     -           14        
PDM2PCM_Top.pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          I1       In      -         1.449       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          F        Out     1.099     2.548       -         
un5_cnt_div_1_ac0_5                                     Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_cZ\[4\]     MUX2_LUT6     S0       In      -         3.569       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_cZ\[4\]     MUX2_LUT6     O        Out     0.502     4.071       -         
cnt_div_3[4]                                            Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\]        DFFCE         D        In      -         5.092       -         
=======================================================================================================================
Total path delay (propagation time + setup) of 5.225 is 2.101(40.2%) logic and 3.124(59.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.441
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.308

    - Propagation time:                      4.964
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.656

    Number of logic level(s):                2
    Starting point:                          PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\] / D
    The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                    Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\]        DFFCE         Q        Out     0.367     0.367       -         
cnt_div[0]                                              Net           -        -       1.021     -           10        
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          I0       In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          F        Out     1.032     2.420       -         
cnt_div_3_rn_0[3]                                       Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     S0       In      -         3.441       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     O        Out     0.502     3.943       -         
cnt_div_3[3]                                            Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\]        DFFCE         D        In      -         4.964       -         
=======================================================================================================================
Total path delay (propagation time + setup) of 5.097 is 2.034(39.9%) logic and 3.063(60.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.441
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.308

    - Propagation time:                      4.964
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.656

    Number of logic level(s):                2
    Starting point:                          PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\] / D
    The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                    Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[0\]        DFFCE         Q        Out     0.367     0.367       -         
cnt_div[0]                                              Net           -        -       1.021     -           10        
PDM2PCM_Top.pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          I0       In      -         1.388       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          F        Out     1.032     2.420       -         
un5_cnt_div_1_ac0_5                                     Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_cZ\[4\]     MUX2_LUT6     S0       In      -         3.441       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_cZ\[4\]     MUX2_LUT6     O        Out     0.502     3.943       -         
cnt_div_3[4]                                            Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\]        DFFCE         D        In      -         4.964       -         
=======================================================================================================================
Total path delay (propagation time + setup) of 5.097 is 2.034(39.9%) logic and 3.063(60.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.441
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.308

    - Propagation time:                      4.815
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.507

    Number of logic level(s):                2
    Starting point:                          PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[2\] / Q
    Ending point:                            PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\] / D
    The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock [rising] on pin CLK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                    Type          Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[2\]        DFFCE         Q        Out     0.367     0.367       -         
cnt_div[2]                                              Net           -        -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          I2       In      -         1.449       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_rn\[3\]     LUT4          F        Out     0.822     2.271       -         
cnt_div_3_rn_0[3]                                       Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     S0       In      -         3.292       -         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_3_mb\[3\]     MUX2_LUT6     O        Out     0.502     3.794       -         
cnt_div_3[3]                                            Net           -        -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[3\]        DFFCE         D        In      -         4.815       -         
=======================================================================================================================
Total path delay (propagation time + setup) of 4.948 is 1.824(36.9%) logic and 3.124(63.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                             Starting                                           Arrival           
Instance                                                     Reference     Type     Pin        Net              Time        Slack 
                                                             Clock                                                                
----------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                           System        INV      O          rstn_i           0.000       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.rstn_i_cZ            System        INV      O          rstn_i           0.000       -0.153
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[23]     cmem_out[23]     0.000       3.167 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[0]      cmem_out[0]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[1]      cmem_out[1]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[2]      cmem_out[2]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[3]      cmem_out[3]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[4]      cmem_out[4]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[5]      cmem_out[5]      0.000       3.228 
PDM2PCM_Top.pdm2pcm.cic_cmp.cic_cmp_rom.mem_out_2_0_0_cZ     System        rROM     DO[6]      cmem_out[6]      0.000       3.228 
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                                               Starting                                                       Required           
Instance                                                       Reference     Type        Pin       Net                        Time         Slack 
                                                               Clock                                                                             
-------------------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     System        RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[0\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     System        RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[1\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     System        RAM16S4     DI[2]     Z\\un1_acc_out_cZ\[2\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_0     System        RAM16S4     DI[3]     Z\\un1_acc_out_cZ\[3\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     System        RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[4\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     System        RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[5\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     System        RAM16S4     DI[2]     Z\\un1_acc_out_cZ\[6\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_1     System        RAM16S4     DI[3]     Z\\un1_acc_out_cZ\[7\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_2     System        RAM16S4     DI[0]     Z\\un1_acc_out_cZ\[8\]     15.173       -0.969
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_2     System        RAM16S4     DI[1]     Z\\un1_acc_out_cZ\[9\]     15.173       -0.969
=================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      16.142
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.969

    Number of logic level(s):                8
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i / O
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                                    INV           O            Out     0.000     0.000       -         
rstn_i                                                                Net           -            -       1.265     -           1048      
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           RESETB       In      -         1.265       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           DO[7]        Out     0.818     2.083       -         
dmem_out[23]                                                          Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I0           In      -         3.104       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.032     4.136       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[23]        In      -         5.218       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     6.056       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         7.077       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     7.703       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         8.724       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     9.562       -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         10.583      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     11.615      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         12.636      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     13.474      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         14.495      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     15.121      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         16.142      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 16.203 is 6.709(41.4%) logic and 9.494(58.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      16.142
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.969

    Number of logic level(s):                8
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i / O
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                                    INV           O            Out     0.000     0.000       -         
rstn_i                                                                Net           -            -       1.265     -           1048      
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           RESETB       In      -         1.265       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           DO[7]        Out     0.818     2.083       -         
dmem_out[23]                                                          Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I0           In      -         3.104       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.032     4.136       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[35]        In      -         5.218       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     6.056       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         7.077       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     7.703       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         8.724       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     9.562       -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         10.583      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     11.615      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         12.636      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     13.474      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         14.495      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     15.121      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         16.142      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 16.203 is 6.709(41.4%) logic and 9.494(58.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      16.142
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.969

    Number of logic level(s):                8
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i / O
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                                    INV           O            Out     0.000     0.000       -         
rstn_i                                                                Net           -            -       1.265     -           1048      
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           RESETB       In      -         1.265       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           DO[7]        Out     0.818     2.083       -         
dmem_out[23]                                                          Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I0           In      -         3.104       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.032     4.136       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[34]        In      -         5.218       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     6.056       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         7.077       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     7.703       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         8.724       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     9.562       -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         10.583      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     11.615      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         12.636      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     13.474      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         14.495      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     15.121      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         16.142      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 16.203 is 6.709(41.4%) logic and 9.494(58.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      16.142
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.969

    Number of logic level(s):                8
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i / O
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                                    INV           O            Out     0.000     0.000       -         
rstn_i                                                                Net           -            -       1.265     -           1048      
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           RESETB       In      -         1.265       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           DO[7]        Out     0.818     2.083       -         
dmem_out[23]                                                          Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I0           In      -         3.104       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.032     4.136       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[33]        In      -         5.218       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     6.056       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         7.077       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     7.703       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         8.724       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     9.562       -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         10.583      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     11.615      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         12.636      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     13.474      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         14.495      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     15.121      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         16.142      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 16.203 is 6.709(41.4%) logic and 9.494(58.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      15.234
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         15.173

    - Propagation time:                      16.142
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.969

    Number of logic level(s):                8
    Starting point:                          PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i / O
    Ending point:                            PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11 / DI[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            Top|SYM_CLK [rising] on pin CLK

Instance / Net                                                                      Pin          Pin               Arrival     No. of    
Name                                                                  Type          Name         Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top.pdm2pcm.cic_cmp.rstn_i                                    INV           O            Out     0.000     0.000       -         
rstn_i                                                                Net           -            -       1.265     -           1048      
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           RESETB       In      -         1.265       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.dmem.bram_sdp_2                           SDP           DO[7]        Out     0.818     2.083       -         
dmem_out[23]                                                          Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          I0           In      -         3.104       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\shift2dsp_v\[23\]                       LUT3          F            Out     1.032     4.136       -         
shift2dsp_6[23]                                                       Net           -            -       1.082     -           13        
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     B[32]        In      -         5.218       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\dsp_out_2_preadd_mulonly_0\[47\:0\]     MULT36X36     DOUT[0]      Out     0.838     6.056       -         
dsp_out[0]                                                            Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          I3           In      -         7.077       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[0\]                   LUT4          F            Out     0.626     7.703       -         
Z\\acc_dsp_out_4_cZ\[0\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        B[0]         In      -         8.724       -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un2_acc_dsp_out\[47\:0\]                ALU54D        DOUT[4]      Out     0.838     9.562       -         
acc_dsp_out_4_RNO[4]                                                  Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          I0           In      -         10.583      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_dsp_out_4_cZ\[4\]                   LUT4          F            Out     1.032     11.615      -         
Z\\acc_dsp_out_4_cZ\[4\]                                              Net           -            -       1.021     -           3         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        A[4]         In      -         12.636      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un23_acc_out\[47\:0\]                   ALU54D        DOUT[47]     Out     0.838     13.474      -         
Z\\un23_acc_out\[47\:0\]_DOUT[47]                                     Net           -            -       1.021     -           1         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          I3           In      -         14.495      -         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\un1_acc_out_cZ\[47\]                    LUT4          F            Out     0.626     15.121      -         
Z\\un1_acc_out_cZ\[47\]                                               Net           -            -       1.021     -           2         
PDM2PCM_Top.pdm2pcm.cic_cmp.\\acc_out\.acc_out_acc_out_0_11           RAM16S4       DI[3]        In      -         16.142      -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 16.203 is 6.709(41.4%) logic and 9.494(58.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 234MB peak: 237MB)


Finished timing report (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 234MB peak: 237MB)

---------------------------------------
Resource Usage Report for Top 

Mapping to part: gw1n_9lqfp144-6
Cell usage:
ALU             324 uses
DFFC            29 uses
DFFCE           992 uses
DFFE            171 uses
DFFP            50 uses
DFFPE           16 uses
GSR             1 use
INV             8 uses
MUX2_LUT5       7 uses
MUX2_LUT6       2 uses
PLL             1 use
RAM16S4         92 uses
RAM16SDP4       45 uses
ROM             1 use
SDP             3 uses
rROM            1 use
LUT2            431 uses
LUT3            352 uses
LUT4            482 uses
MULT36X36      1 use
ALU54D         2 uses

I/O ports: 30
I/O primitives: 30
IBUF           3 uses
OBUF           27 uses

I/O Register bits:                  0
Register bits not including I/Os:   1258 of 6480 (19%)

RAM/ROM usage summary
Block Rams : 4 of 26 (15%)


Block Multipliers: 4 of 10 (40%)
Total load per clock:
   Top|SYM_CLK: 1401

@S |Mapping Summary:
Total  LUTs: 1265 (14%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 78MB peak: 237MB)

Process took 0h:00m:31s realtime, 0h:00m:29s cputime
# Fri Dec  6 15:52:08 2019

###########################################################]
