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#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\umr_capim.v":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1569428306
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\IDE\\ipcore\\PDM2PCM\\data\\pdm2pcm_wrap.v":1574750425
#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\define.v":1575252933
#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\parameter.v":1575252933
#CUR:"C:\\Users\\Noa\\Documents\\WXWork\\1688853129516911\\Cache\\File\\2019-11\\Gowin_V1.9.3Beta_36338_20191119\\IDE\\ipcore\\PDM2PCM\\data\\static_macro_define.v":1574750425
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#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\define.v":1575252933
#CUR:"C:\\Users\\Noa\\Desktop\\Myworkplace\\Program\\FPGAProgram\\Ref_design\\src\\pdm2pcm\\temp\\pdm2pcm\\./cic_comp_coeff.dat":1575252933
#numinternalfiles:5
#defaultlanguage:verilog
0			"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v" verilog
1		*	"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v" verilog
2		*	"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v" verilog
3		*	"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v" verilog
4			"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v" verilog
#Dependency Lists(Uses List)
0 1 2 3 4 0
1 2 3 0 1
2 1 3 0 2
3 1 2 0 3
4 1 0 2 3
#Dependency Lists(Users Of)
0 4 1 2 3
1 0 2 3 4
2 0 1 3 4
3 0 1 2 4
4 0
#Design Unit to File Association
package work work_C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v_unit 2
module work \~pdm2pcm.PDM2PCM_Top 4
module work PDM2PCM_Top 0
module work \~syn_signal.PDM2PCM_Top 4
module work \~delay.PDM2PCM_Top 4
module work \~Gowin_PLL.PDM2PCM_Top 4
module work \~clk_div_even.PDM2PCM_Top 4
module work \~edge_detect.PDM2PCM_Top 4
module work \~parallel2series.PDM2PCM_Top 4
module work \~cic_filter.PDM2PCM_Top 4
module work \~cic_compensation_filter.PDM2PCM_Top 4
module work \~cic_cmp_rom.PDM2PCM_Top 4
module work \~data_round.PDM2PCM_Top 4
module work \~cic_comb.PDM2PCM_Top 4
module work \~Gowin_SDP.PDM2PCM_Top 4
module work \~cic_integrator.PDM2PCM_Top 4
module work \~cic_down_sample.PDM2PCM_Top 4
module work \~cic_decimator.PDM2PCM_Top 4
