Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.vm
Physical Constraints File | E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.cst
Timing Constraint File | ---
GOWIN version | V1.9.3Beta
Part Number | GW1N-LV9LQ144C6/I5
Created Time | Mon Dec 16 17:06:24 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 6790
Numbers of Endpoints Analyzed | 5998
Numbers of Falling Endpoints | 0
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  |
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | Generated | 25.000 | 40.000 | 0.000 | 12.500 |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk |
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTP.default_gen_clk | Generated | 25.000 | 40.000 | 0.000 | 12.500 |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk |
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD.default_gen_clk | Generated | 50.000 | 20.000 | 0.000 | 25.000 |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk |
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD3.default_gen_clk | Generated | 75.000 | 13.333 | 0.000 | 37.500 |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk |
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | 40.000(MHz) | 253.291(MHz) | 3 | TOP

#### No timing paths to get frequency of PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk!

#### No timing paths to get frequency of PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of DEFAULT_CLK!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk | Setup | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKIN.default_clk | Hold | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 21.052 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 3.348
2 | 21.216 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 3.184
3 | 21.263 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CE | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 3.494
4 | 21.564 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 2.836
5 | 21.811 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 2.589
6 | 22.412 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 1.988
7 | 23.303 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 25.000 | 0.000 | 1.097

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.709 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.709
2 | 0.711 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.711
3 | 0.893 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.893
4 | 1.064 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.064
5 | 1.136 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.136
6 | 1.236 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/D | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.236
7 | 1.873 | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CE | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.888

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### Nothing to report!

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### Nothing to report!

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
2 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
3 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
4 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
5 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
6 | 10.727 | 11.977 | 1.250 | Low Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
7 | 10.785 | 12.035 | 1.250 | High Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
8 | 10.785 | 12.035 | 1.250 | High Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
9 | 10.785 | 12.035 | 1.250 | High Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
10 | 10.785 | 12.035 | 1.250 | High Pulse Width | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 21.052
Data Arrival Time | 5.259
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK
2.369 | 0.458 | tC2Q | RF | 10 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/Q
2.725 | 0.355 | tNET | FF | 1 | R21C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div13_3_x_cZ/I2
3.824 | 1.099 | tINS | FF | 1 | R21C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div13_3_x_cZ/F
4.160 | 0.336 | tNET | FF | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m22/I0
5.259 | 1.099 | tINS | FF | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m22/F
5.259 | 0.000 | tNET | FF | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
26.311 | -0.400 | tSu |  | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 2.198, 65.651%; route: 0.692, 20.660%; tC2Q: 0.458, 13.690%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path2

Path Summary:

Slack | 21.216
Data Arrival Time | 5.095
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK
2.369 | 0.458 | tC2Q | RF | 13 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/Q
3.210 | 0.841 | tNET | FF | 1 | R21C6[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_rn[3]/I2
4.242 | 1.032 | tINS | FF | 1 | R21C6[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_rn[3]/F
4.578 | 0.336 | tNET | FF | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb[3]/S0
5.080 | 0.502 | tINS | FF | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb[3]/O
5.095 | 0.015 | tNET | FF | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
26.311 | -0.400 | tSu |  | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 1.534, 48.172%; route: 1.192, 37.435%; tC2Q: 0.458, 14.393%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path3

Path Summary:

Slack | 21.263
Data Arrival Time | 5.405
Data Required Time | 26.668
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK
2.369 | 0.458 | tC2Q | RF | 14 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q
3.204 | 0.835 | tNET | FF | 1 | R22C6[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23_1_cZ/I0
4.026 | 0.822 | tINS | FF | 1 | R22C6[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23_1_cZ/F
4.032 | 0.005 | tNET | FF | 1 | R22C6[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23/I3
4.657 | 0.625 | tINS | FR | 1 | R22C6[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23/F
5.405 | 0.749 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
26.668 | -0.043 | tSu |  | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 1.447, 41.413%; route: 1.589, 45.470%; tC2Q: 0.458, 13.117%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path4

Path Summary:

Slack | 21.564
Data Arrival Time | 4.746
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK
2.369 | 0.458 | tC2Q | RR | 10 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q
2.794 | 0.425 | tNET | RR | 1 | R21C5[1][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_ac0_5_cZ/I0
3.893 | 1.099 | tINS | RF | 1 | R21C5[1][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_ac0_5_cZ/F
4.229 | 0.336 | tNET | FF | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_cZ[4]/S0
4.731 | 0.502 | tINS | FF | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_cZ[4]/O
4.746 | 0.015 | tNET | FF | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
26.311 | -0.400 | tSu |  | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 1.601, 56.462%; route: 0.776, 27.374%; tC2Q: 0.458, 16.164%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path5

Path Summary:

Slack | 21.811
Data Arrival Time | 4.500
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK
2.369 | 0.458 | tC2Q | RF | 10 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q
3.874 | 1.505 | tNET | FF | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc1_cZ_cZ/I0
4.500 | 0.626 | tINS | FF | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc1_cZ_cZ/F
4.500 | 0.000 | tNET | FF | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
26.311 | -0.400 | tSu |  | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 0.626, 24.180%; route: 1.505, 58.116%; tC2Q: 0.458, 17.704%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path6

Path Summary:

Slack | 22.412
Data Arrival Time | 3.899
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK
2.369 | 0.458 | tC2Q | RR | 14 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q
2.800 | 0.430 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc2_cZ_cZ/I1
3.899 | 1.099 | tINS | RF | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc2_cZ_cZ/F
3.899 | 0.000 | tNET | FF | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
26.311 | -0.400 | tSu |  | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 1.099, 55.292%; route: 0.430, 21.649%; tC2Q: 0.458, 23.059%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Path7

Path Summary:

Slack | 23.303
Data Arrival Time | 3.008
Data Required Time | 26.311
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
2.369 | 0.458 | tC2Q | RF | 4 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/Q
2.382 | 0.012 | tNET | FF | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/out_pdm_sclk_i_cZ/I0
3.008 | 0.626 | tINS | FF | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/out_pdm_sclk_i_cZ/F
3.008 | 0.000 | tNET | FF | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
25.000 | 25.000 |  |  |  |  | active clock edge time
25.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.911 | 1.911 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
26.711 | -0.200 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
26.311 | -0.400 | tSu |  | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 25.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%
Arrival Data Path Delay | cell: 0.626, 57.084%; route: 0.012, 1.121%; tC2Q: 0.458, 41.795%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.709
Data Arrival Time | 2.144
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
1.769 | 0.333 | tC2Q | RR | 4 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/Q
1.772 | 0.004 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/out_pdm_sclk_i_cZ/I0
2.144 | 0.372 | tINS | RF | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/out_pdm_sclk_i_cZ/F
2.144 | 0.000 | tNET | FF | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
1.436 | 0.000 | tHld |  | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path2

Path Summary:

Slack | 0.711
Data Arrival Time | 2.147
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK
1.769 | 0.333 | tC2Q | RR | 10 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/Q
1.775 | 0.006 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m22/I1
2.147 | 0.372 | tINS | RF | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m22/F
2.147 | 0.000 | tNET | FF | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]
1.436 | 0.000 | tHld |  | 1 | R21C5[0][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path3

Path Summary:

Slack | 0.893
Data Arrival Time | 2.328
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK
1.769 | 0.333 | tC2Q | RR | 13 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/Q
1.772 | 0.004 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc2_cZ_cZ/I2
2.328 | 0.556 | tINS | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc2_cZ_cZ/F
2.328 | 0.000 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]
1.436 | 0.000 | tHld |  | 1 | R22C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path4

Path Summary:

Slack | 1.064
Data Arrival Time | 2.500
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK
1.769 | 0.333 | tC2Q | RR | 14 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/Q
1.776 | 0.007 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc1_cZ_cZ/I1
2.500 | 0.724 | tINS | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/un5_cnt_div_1_axbxc1_cZ_cZ/F
2.500 | 0.000 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]
1.436 | 0.000 | tHld |  | 1 | R21C5[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.724, 68.018%; route: 0.007, 0.665%; tC2Q: 0.333, 31.316%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path5

Path Summary:

Slack | 1.136
Data Arrival Time | 2.571
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK
1.769 | 0.333 | tC2Q | RF | 12 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q
2.016 | 0.247 | tNET | FF | 1 | R21C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_1_0_cZ[4]/I2
2.401 | 0.385 | tINS | FR | 1 | R21C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_1_0_cZ[4]/F
2.401 | 0.000 | tNET | RR | 1 | R21C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_1_cZ[4]/I0
2.499 | 0.098 | tINS | RR | 1 | R21C5[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_1_cZ[4]/O
2.499 | 0.000 | tNET | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_cZ[4]/I1
2.565 | 0.066 | tINS | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_cZ[4]/O
2.571 | 0.006 | tNET | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]
1.436 | 0.000 | tHld |  | 1 | R21C5[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.549, 48.336%; route: 0.253, 22.316%; tC2Q: 0.333, 29.348%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path6

Path Summary:

Slack | 1.236
Data Arrival Time | 2.672
Data Required Time | 1.436
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK
1.769 | 0.333 | tC2Q | RR | 12 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q
1.776 | 0.007 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb_1_1_cZ[3]/I2
2.502 | 0.726 | tINS | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb_1_1_cZ[3]/F
2.502 | 0.000 | tNET | RR | 1 | R21C6[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb_1_cZ[3]/I1
2.600 | 0.098 | tINS | RR | 1 | R21C6[2][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb_1_cZ[3]/O
2.600 | 0.000 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb[3]/I1
2.666 | 0.066 | tINS | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_3_mb[3]/O
2.672 | 0.006 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
1.436 | 0.000 | tHld |  | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.890, 71.978%; route: 0.013, 1.064%; tC2Q: 0.333, 26.958%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Path7

Path Summary:

Slack | 1.873
Data Arrival Time | 3.324
Data Required Time | 1.451
From | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]
To | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
Launch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK
1.769 | 0.333 | tC2Q | RF | 12 | R21C6[2][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/Q
2.016 | 0.247 | tNET | FF | 1 | R22C6[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23_1_cZ/I2
2.388 | 0.372 | tINS | FF | 1 | R22C6[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23_1_cZ/F
2.393 | 0.004 | tNET | FF | 1 | R22C6[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23/I3
2.778 | 0.385 | tINS | FR | 1 | R22C6[0][B] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/m23/F
3.324 | 0.546 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 6 | PLL_L | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.436 | 1.436 | tNET | RR | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK
1.436 | 0.000 | tUnc |  |  |  | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out
1.451 | 0.015 | tHld |  | 1 | R22C5[1][A] | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay | cell: 0.757, 40.086%; route: 0.798, 42.263%; tC2Q: 0.333, 17.651%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.436, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

#### No recovery paths to report!

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

#### No removal paths to report!

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/clk_out/CLK

### MPW2

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[1]/CLK

### MPW3

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK

### MPW4

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK

### MPW5

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK

### MPW6

MPW Summary:

Slack: | 10.727
Actual Width: | 11.977
Required Width: | 1.250
Type: | Low Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
14.458 | 1.958 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
25.000 | 0.000 |  |  | active clock edge time
25.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
25.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
26.436 | 1.436 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK

### MPW7

MPW Summary:

Slack: | 10.785
Actual Width: | 12.035
Required Width: | 1.250
Type: | High Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
13.946 | 1.446 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[2]/CLK

### MPW8

MPW Summary:

Slack: | 10.785
Actual Width: | 12.035
Required Width: | 1.250
Type: | High Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
13.946 | 1.446 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[0]/CLK

### MPW9

MPW Summary:

Slack: | 10.785
Actual Width: | 12.035
Required Width: | 1.250
Type: | High Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
13.946 | 1.446 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[4]/CLK

### MPW10

MPW Summary:

Slack: | 10.785
Actual Width: | 12.035
Required Width: | 1.250
Type: | High Pulse Width
Clock: | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
Objects: | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
1.911 | 1.911 | tNET | RR | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
12.500 | 0.000 |  |  | active clock edge time
12.500 | 0.000 |  |  | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT.default_gen_clk
12.500 | 0.000 | tCL | FF | PDM2PCM_Top/pdm2pcm/iSysClk/pll_inst/CLKOUT
13.946 | 1.446 | tNET | FF | PDM2PCM_Top/pdm2pcm/clk_div_PDM/cnt_div_Z[3]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
14 | cnt_div[1] | 21.263 | 0.878
13 | cnt_div[2] | 21.216 | 0.841
12 | cnt_div[3] | 21.242 | 0.442
10 | cnt_div[4] | 21.052 | 0.835
10 | cnt_div[0] | 21.292 | 1.505
6 | sym_clk | 21.052 | 1.958
4 | out_pdm_sclk_c | 23.303 | 3.886
1 | cnt_div_3[0] | 21.052 | 0.000
1 | cnt_div_3_rn_0[3] | 21.216 | 0.336
1 | out_pdm_sclk_i | 23.303 | 0.000

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R18C14 | 0.806
R18C16 | 0.708
R21C29 | 0.694
R18C17 | 0.694
R18C13 | 0.681
R20C16 | 0.667
R19C13 | 0.653
R19C12 | 0.625
R18C15 | 0.625
R18C18 | 0.625

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---