#OPTIONS:"|-layerid|0|-orig_srs|E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\impl\\synthesize\\rev_1\\synwork\\Ref_design_comp.srs|-top|Top|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-I|E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\src\\data|-I|E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\src\\pdm2pcm\\temp\\pdm2pcm|-I|E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\impl\\synthesize\\|-I|C:\\Gowin\\1.9\\SynplifyPro\\lib|-sysv|-devicelib|C:\\Gowin\\1.9\\SynplifyPro\\lib\\generic\\gw1n.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\bin64\\c_ver.exe":1575393480
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\generic\\gw1n.v":1575572956
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\hypermods.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\umr_capim.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1575393232
#CUR:"E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\src\\pdm2pcm\\pdm2pcm.v":1575252981
#CUR:"E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\src\\Top.v":1575856832
#CUR:"E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\src\\data_rom.v":1572579510
#numinternalfiles:5
#defaultlanguage:verilog
0			"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v" verilog
1			"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v" verilog
2			"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\data_rom.v" verilog
#Dependency Lists(Uses List)
0 -1
1 0 2
2 -1
#Dependency Lists(Users Of)
0 1
1 -1
2 1
#Design Unit to File Association
module work \~syn_signal.PDM2PCM_Top_ 0
module work \~delay.PDM2PCM_Top__4s_2s 0
module work \~Gowin_PLL.PDM2PCM_Top_ 0
module work \~clk_div_even.PDM2PCM_Top_ 0
module work \~edge_detect.PDM2PCM_Top__1_4s 0
module work \~parallel2series.PDM2PCM_Top__1_4s_4s_1s_2s 0
module work \~cic_integrator.PDM2PCM_Top__4s_46s_46s_2 0
module work \~cic_integrator.PDM2PCM_Top__4s_46s_46s 0
module work \~cic_integrator.PDM2PCM_Top__4s_46s_46s_0 0
module work \~cic_down_sample.PDM2PCM_Top__4s_32s_46s_2s 0
module work \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s 0
module work \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_0 0
module work \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_1 0
module work \~data_round.PDM2PCM_Top__46s_24s_22s_23s_47s_0s 0
module work \~cic_decimator.PDM2PCM_Top__4s_64s_3s_1s_24s_24s_46s 0
module work \~cic_filter.PDM2PCM_Top__4s_64s_3s_1s_24s_24s 0
module work \~cic_cmp_rom.PDM2PCM_Top__96s_24s 0
module work \~Gowin_SDP.PDM2PCM_Top_ 0
module work \~delay.PDM2PCM_Top__6s_3s 0
module work \~delay.PDM2PCM_Top__2s_5s 0
module work \~delay.PDM2PCM_Top__6s_2s 0
module work \~delay.PDM2PCM_Top__1s_59s 0
module work \~data_round.PDM2PCM_Top__48s_24s_9s_23s_34s_15s 0
module work \~cic_compensation_filter.PDM2PCM_Top__Z1 0
module work \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s 0
module work PDM2PCM_Top 0
module work Data_ROM 2
module work Top 1
