@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v":1:0:1:8|Synthesizing module work_C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v_unit in library work.
@N: CG364 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":4:19:4:19|Synthesizing module PDM2PCM_Top in library work.
@N|Running in 64-bit mode
@N: NF107 :"c:\users\noa\documents\wxwork\1688853129516911\cache\file\2019-11\gowin_v1.9.3beta_36338_20191119\ide\ipcore\pdm2pcm\data\pdm2pcm_wrap.v":4:19:4:19|Selected library: work cell: PDM2PCM_Top view verilog as top level
@N: NF107 :"c:\users\noa\documents\wxwork\1688853129516911\cache\file\2019-11\gowin_v1.9.3beta_36338_20191119\ide\ipcore\pdm2pcm\data\pdm2pcm_wrap.v":4:19:4:19|Selected library: work cell: PDM2PCM_Top view verilog as top level

