# Mon Dec 16 17:04:24 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: C:\Gowin\1.9\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design_scck.rpt 
Printing clock  summary report in "E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB)



Clock Summary
******************

          Start                                                Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                Frequency     Period        Type         Group                     Load 
---------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                               100.0 MHz     10.000        system       system_clkgroup           0    
                                                                                                                                       
0 -       Top|SYM_CLK                                          35.2 MHz      28.407        inferred     Autoconstr_clkgroup_0     1399 
                                                                                                                                       
0 -       _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     417.6 MHz     2.395         inferred     Autoconstr_clkgroup_1     6    
=======================================================================================================================================



Clock Load Summary
***********************

                                                     Clock     Source                                               Clock Pin                                                Non-clock Pin     Non-clock Pin
Clock                                                Load      Pin                                                  Seq Example                                              Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                               0         -                                                    -                                                        -                 -            
                                                                                                                                                                                                            
Top|SYM_CLK                                          1399      SYM_CLK(port)                                        pdm_sclk_r1.C                                            -                 -            
                                                                                                                                                                                                            
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     6         PDM2PCM_Top.pdm2pcm.iSysClk.pll_inst.CLKOUT(PLL)     PDM2PCM_Top.pdm2pcm.clk_div_PDM.\\cnt_div_Z\[4\].CLK     -                 -            
============================================================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 1399 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 6 clock pin(s) of sequential element(s)
0 instances converted, 6 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       SYM_CLK             port                   1399       cnt_addr[11:0] 
=======================================================================================
=================================================== Gated/Generated Clocks ====================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation            
-------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_1       ENCRYPTED           PLL                    6                      ENCRYPTED           Black box on clock path
===============================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.sap.

Starting constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 230MB peak: 230MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 230MB peak: 230MB)


Finished constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 230MB peak: 230MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 151MB peak: 232MB)

Process took 0h:00m:06s realtime, 0h:00m:05s cputime
# Mon Dec 16 17:04:31 2019

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