<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\synlog\pdm2pcm_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>PDM2PCM_Top|clk</data>
<data>87.4 MHz</data>
<data>74.3 MHz</data>
<data>-2.018</data>
</row>
<row>
<data>_~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock</data>
<data>225.2 MHz</data>
<data>191.4 MHz</data>
<data>-0.784</data>
</row>
<row>
<data>System</data>
<data>225.5 MHz</data>
<data>191.6 MHz</data>
<data>-0.783</data>
</row>
</report_table>
