@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: MF794 |RAM in_data_r2_CR23[23:0] required 25 registers during mapping 
@N: MF794 |RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping 
@N: MF794 |RAM delay_cnt_tdm.dReg_CR5[5:0] required 6 registers during mapping 
@N: MF794 |RAM comb\[1\]\.genblk1\.cic_comb.mem[45:0] required 12 registers during mapping 
@N: MF794 |RAM intg\[1\]\.genblk1\.cic_intg.data_out_1[45:0] required 12 registers during mapping 
@N: MF794 |RAM in_data_r2_CR23[23:0] required 28 registers during mapping 
@N: MF794 |RAM acc_out_1[47:0] required 4 registers during mapping 
@N: MF794 |RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping 
@N: MF794 |RAM delay_cnt_tdm.dReg_CR5[5:0] required 14 registers during mapping 
@N: FX211 |Packed ROM mem_out_2_0[23:0] (7 input, 24 output) to Block SelectRAM 
@N: MF794 |RAM comb\[1\]\.genblk1\.cic_comb.mem[45:0] required 12 registers during mapping 
@N: MF794 |RAM intg\[1\]\.genblk1\.cic_intg.data_out_1[45:0] required 12 registers during mapping 
@N: MF794 |RAM in_data_r2_CR23[23:0] required 27 registers during mapping 
@N: MF794 |RAM acc_out_1[47:0] required 4 registers during mapping 
@N: MF794 |RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping 
@N: MF794 |RAM delay_cnt_tdm.dReg_CR5[5:0] required 14 registers during mapping 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
