
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1

# Written on Mon Dec  2 10:15:41 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                                              Requested     Requested     Clock        Clock                     Clock
Level     Clock                                              Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------------------------
0 -       PDM2PCM_Top|clk                                    149.3 MHz     6.699         inferred     Autoconstr_clkgroup_0     1931 
                                                                                                                                     
0 -       _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     325.7 MHz     3.071         inferred     Autoconstr_clkgroup_1     6    
=====================================================================================================================================


Clock Load Summary
******************

                                                   Clock     Source                                   Clock Pin                         Non-clock Pin     Non-clock Pin
Clock                                              Load      Pin                                      Seq Example                       Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
PDM2PCM_Top|clk                                    1931      clk(port)                                pdm2pcm.cic_cmp.sync_r0.C         -                 -            
                                                                                                                                                                       
_~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     6         pdm2pcm.iSysClk.pll_inst.CLKOUT(PLL)     pdm2pcm.clk_div_PDM.clk_out.C     -                 -            
=======================================================================================================================================================================
