Selecting top level module Top
@N: CG364 :"C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v":2377:7:2377:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~syn_signal.PDM2PCM_Top_  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__4s_2s  .......
Running optimization stage 1 on PLL .......
Running optimization stage 1 on \~Gowin_PLL.PDM2PCM_Top_  .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on \~clk_div_even.PDM2PCM_Top_  .......
Running optimization stage 1 on \~edge_detect.PDM2PCM_Top__1_4s  .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on \~parallel2series.PDM2PCM_Top__1_4s_4s_1s_2s  .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on RAM16SDP4 .......
Running optimization stage 1 on RAM16S4 .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_2  .......
Running optimization stage 1 on DFFE .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s  .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_0  .......
Running optimization stage 1 on \~cic_down_sample.PDM2PCM_Top__4s_32s_46s_2s  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_0  .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_1  .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top__46s_24s_22s_23s_47s_0s  .......
Running optimization stage 1 on \~cic_decimator.PDM2PCM_Top__4s_64s_3s_1s_24s_24s_46s  .......
Running optimization stage 1 on \~cic_filter.PDM2PCM_Top__4s_64s_3s_1s_24s_24s  .......
Running optimization stage 1 on ALU54D .......
Running optimization stage 1 on MULT36X36 .......
Running optimization stage 1 on rROM .......
Running optimization stage 1 on \~cic_cmp_rom.PDM2PCM_Top__96s_24s  .......
Running optimization stage 1 on SDP .......
Running optimization stage 1 on \~Gowin_SDP.PDM2PCM_Top_  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__6s_3s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__2s_5s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__6s_2s  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top__1s_59s  .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top__48s_24s_9s_23s_34s_15s  .......
Running optimization stage 1 on \~cic_compensation_filter.PDM2PCM_Top__Z1  .......
Running optimization stage 1 on \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s  .......
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v":26441:7:26441:17|Synthesizing module PDM2PCM_Top in library work.
Running optimization stage 1 on PDM2PCM_Top .......
@W: CL168 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v":26486:6:26486:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v":1920:7:1920:9|Synthesizing module ROM in library work.
Running optimization stage 1 on ROM .......
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\data_rom.v":8:7:8:14|Synthesizing module Data_ROM in library work.
@W: CS263 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\data_rom.v":23:8:23:15|Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on Data_ROM .......
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v":1:7:1:9|Synthesizing module Top in library work.
@N: CG179 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v":137:54:137:60|Removing redundant assignment.
Running optimization stage 1 on Top .......
Running optimization stage 2 on Top .......
Running optimization stage 2 on Data_ROM .......
Running optimization stage 2 on ROM .......
Running optimization stage 2 on PDM2PCM_Top .......
Running optimization stage 2 on \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s  .......
Running optimization stage 2 on \~cic_compensation_filter.PDM2PCM_Top__Z1  .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top__48s_24s_9s_23s_34s_15s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__1s_59s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__6s_2s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__2s_5s  .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__6s_3s  .......
Running optimization stage 2 on \~Gowin_SDP.PDM2PCM_Top_  .......
Running optimization stage 2 on SDP .......
Running optimization stage 2 on \~cic_cmp_rom.PDM2PCM_Top__96s_24s  .......
Running optimization stage 2 on rROM .......
Running optimization stage 2 on MULT36X36 .......
Running optimization stage 2 on ALU54D .......
Running optimization stage 2 on \~cic_filter.PDM2PCM_Top__4s_64s_3s_1s_24s_24s  .......
Running optimization stage 2 on \~cic_decimator.PDM2PCM_Top__4s_64s_3s_1s_24s_24s_46s  .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top__46s_24s_22s_23s_47s_0s  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_1  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s_0  .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top__4s_1s_46s_46s_2s  .......
Running optimization stage 2 on \~cic_down_sample.PDM2PCM_Top__4s_32s_46s_2s  .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_0  .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s  .......
Running optimization stage 2 on DFFE .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top__4s_46s_46s_2  .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on RAM16S4 .......
Running optimization stage 2 on RAM16SDP4 .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on \~parallel2series.PDM2PCM_Top__1_4s_4s_1s_2s  .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on \~edge_detect.PDM2PCM_Top__1_4s  .......
Running optimization stage 2 on \~clk_div_even.PDM2PCM_Top_  .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on \~Gowin_PLL.PDM2PCM_Top_  .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on \~delay.PDM2PCM_Top__4s_2s  .......
Running optimization stage 2 on \~syn_signal.PDM2PCM_Top_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\layer0.rt.csv

