<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synlog\Ref_design_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>Top|SYM_CLK</data>
<data>65.6 MHz</data>
<data>56.4 MHz</data>
<data>-2.492</data>
</row>
<row>
<data>_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock</data>
<data>225.2 MHz</data>
<data>191.4 MHz</data>
<data>-0.784</data>
</row>
<row>
<data>System</data>
<data>1152.2 MHz</data>
<data>979.4 MHz</data>
<data>-0.153</data>
</row>
</report_table>
