<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device>gw1n9-008</Device>
    <FileList>
        <File path="src/pdm2pcm/pdm2pcm.v" type="file.verilog" enable="1"/>
        <File path="src/Top.v" type="file.verilog" enable="1"/>
        <File path="src/Top.cst" type="file.cst" enable="1"/>
        <File path="src/Ref_design.gao" type="file.gao" enable="1"/>
        <File path="src/data_rom.v" type="file.verilog" enable="1"/>
    </FileList>
</Project>
