<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>Beta</Version>
    <Device id="GW1N-9" package="LQFP144" speed="6" partNumber="GW1N-LV9LQ144C6/I5"/>
    <FileList>
        <File type="verilog"  path="E:\IP_verify\1.9.3\IP官网发布案例\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v"/>
        <File type="verilog"  path="E:\IP_verify\1.9.3\IP官网发布案例\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v"/>
        <File type="verilog"  path="E:\IP_verify\1.9.3\IP官网发布案例\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\data_rom.v"/>
    </FileList>
    <OptionList>
        <Option type="top_module"  value="Top"/>
        <Option type="include_path"  value="E:/IP_verify/1.9.3/IP官网发布案例/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/src/data"/>
        <Option type="include_path"  value="E:/IP_verify/1.9.3/IP官网发布案例/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/src/pdm2pcm/temp/pdm2pcm"/>
        <Option type="output_file"  value="E:\IP_verify\1.9.3\IP官网发布案例\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\gwsynthesis\Ref_design.vg"/>
    </OptionList>
</Project>
