@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v":2377:7:2377:9|Synthesizing module GSR in library work.
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v":26441:7:26441:17|Synthesizing module PDM2PCM_Top in library work.
@N: CG364 :"C:\Gowin\1.9\SynplifyPro\lib\generic\gw1n.v":1920:7:1920:9|Synthesizing module ROM in library work.
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\data_rom.v":8:7:8:14|Synthesizing module Data_ROM in library work.
@N: CG364 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v":1:7:1:9|Synthesizing module Top in library work.
@N: CG179 :"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\src\Top.v":137:54:137:60|Removing redundant assignment.
@N|Running in 64-bit mode

