`

    #Build: Synplify Pro (R) P-2019.03G-Beta4, Build 231R, Aug  2 2019
    #install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    #OS: Windows 8 6.2
    #Hostname: GW-SW-063

    # Mon Dec  9 16:08:14 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 231R, Built Aug  2 2019 09:58:27

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 231R, Built Aug  2 2019 09:58:27

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_define.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(104) | Net capture_length_zero is not declared.
    @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_top.v" (library work)
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top
    Running optimization stage 1 on ao_mem_ctrl_1024s_42s_10s .......
    Running optimization stage 1 on ao_top .......
    Running optimization stage 2 on ao_top .......
    Extracted state machine for register module_state
    State machine has 6 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
    Running optimization stage 2 on ao_mem_ctrl_1024s_42s_10s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 98MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  9 16:08:15 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 231R, Built Aug  2 2019 09:58:27

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  9 16:08:16 2019

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  ao_0_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 19MB peak: 20MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  9 16:08:16 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 231R, Built Aug  2 2019 09:58:27

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  9 16:08:17 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Dec  9 16:08:18 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1429R, Built Aug 27 2019 09:36:45

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  ao_0_scck.rpt
    Printing clock  summary report in "E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

    Encoding state machine module_state[5:0] (in view: work.ao_top(verilog))
    original code -> new code
       0000 -> 000001
       0001 -> 000010
       0010 -> 000100
       0011 -> 001000
       0100 -> 010000
       0101 -> 100000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Clock Summary
    ******************

              Start                 Requested     Requested     Clock        Clock                     Clock
    Level     Clock                 Frequency     Period        Type         Group                     Load
    --------------------------------------------------------------------------------------------------------
    0 -       ao_top|control[0]     158.1 MHz     6.326         inferred     Autoconstr_clkgroup_1     228

    0 -       ao_top|clk_i          240.4 MHz     4.160         inferred     Autoconstr_clkgroup_0     64
    ========================================================================================================

    Clock Load Summary
    ***********************

                          Clock     Source               Clock Pin                         Non-clock Pin     Non-clock Pin
    Clock                 Load      Pin                  Seq Example                       Seq Example       Comb Example
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top|control[0]     228       control[0](port)     data_register[62:0].C             -                 -

    ao_top|clk_i          64        clk_i(port)          internal_reg_start_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    =============================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 251 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           port                   23         ENCRYPTED
    ClockId_0_1       ENCRYPTED           IO_port                228        ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 223MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Mon Dec  9 16:08:20 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Dec  9 16:08:21 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-Beta4
    Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1429R, Built Aug 27 2019 09:36:45

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 119MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 121MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 216MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB)

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB)

    Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -3.21ns		 229 /       202
       2		0h:00m:02s		    -3.21ns		 228 /       202
       3		0h:00m:02s		    -3.21ns		 228 /       202
       4		0h:00m:02s		    -3.21ns		 228 /       202
       5		0h:00m:02s		    -3.21ns		 228 /       202
       6		0h:00m:02s		    -3.21ns		 228 /       202
    Timing driven replication report
    Added 3 Registers via timing driven replication
    Added 2 LUTs via timing driven replication

       7		0h:00m:03s		    -2.89ns		 233 /       205
       8		0h:00m:03s		    -3.14ns		 235 /       205
       9		0h:00m:03s		    -2.79ns		 235 /       205
      10		0h:00m:03s		    -3.14ns		 235 /       205
      11		0h:00m:03s		    -2.79ns		 235 /       205
      12		0h:00m:03s		    -3.14ns		 235 /       205
      13		0h:00m:03s		    -2.79ns		 235 /       205
    Timing driven replication report
    Added 1 Registers via timing driven replication
    Added 2 LUTs via timing driven replication

      14		0h:00m:03s		    -2.77ns		 236 /       206
      15		0h:00m:03s		    -2.77ns		 237 /       206
      16		0h:00m:03s		    -2.77ns		 237 /       206
      17		0h:00m:03s		    -2.77ns		 237 /       206
      18		0h:00m:03s		    -2.77ns		 237 /       206

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 232MB)

    Writing Analyst data base E:\W-File\PDM2PCM\RefDesign\project\Ref_design\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 229MB peak: 232MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 229MB peak: 232MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 229MB peak: 232MB)

    Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 227MB peak: 232MB)

    @W:MT420 :  | Found inferred clock ao_top|clk_i with period 5.38ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top|control[0] with period 8.99ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Dec  9 16:08:27 2019
    #

    Top view:               ao_top
    Requested Frequency:    111.2 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.587

                          Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock        Frequency     Frequency     Period        Period        Slack      Type         Group
    ---------------------------------------------------------------------------------------------------------------------------
    ao_top|clk_i          185.9 MHz     158.0 MHz     5.378         6.328         -0.949     inferred     Autoconstr_clkgroup_0
    ao_top|control[0]     111.2 MHz     94.5 MHz      8.995         10.582        -1.587     inferred     Autoconstr_clkgroup_1
    System                100.0 MHz     146.9 MHz     10.000        6.807         3.193      system       system_clkgroup
    ===========================================================================================================================

    Clock Relationships
    *******************

    Clocks                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------
    Starting           Ending             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------
    System             ao_top|clk_i       |  5.378       3.193   |  No paths    -      |  No paths    -      |  No paths    -
    System             ao_top|control[0]  |  8.995       5.744   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top|clk_i       System             |  5.378       3.991   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top|clk_i       ao_top|clk_i       |  5.378       -0.949  |  5.378       3.858  |  No paths    -      |  2.689       1.168
    ao_top|clk_i       ao_top|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top|control[0]  System             |  8.995       7.607   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top|control[0]  ao_top|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top|control[0]  ao_top|control[0]  |  8.995       -1.587  |  No paths    -      |  No paths    -      |  No paths    -
    =============================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                         Arrival
    Instance                              Reference        Type      Pin     Net                           Time        Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    internal_reg_start_dly[0]             ao_top|clk_i     DFFC      Q       internal_reg_start_dly[0]     0.367       -0.949
    capture_start_sel                     ao_top|clk_i     DFFCE     Q       capture_start_sel             0.367       -0.882
    u_ao_mem_ctrl.capture_mem_addr[6]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[6]           0.367       -0.747
    internal_reg_start_dly[1]             ao_top|clk_i     DFFC      Q       internal_reg_start_dly[1]     0.367       -0.733
    u_ao_mem_ctrl.capture_mem_addr[3]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[3]           0.367       -0.680
    u_ao_mem_ctrl.capture_mem_addr[7]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[7]           0.367       -0.470
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[0]           0.367       0.037
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[1]           0.367       0.095
    u_ao_mem_ctrl.capture_mem_addr[2]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[2]           0.367       0.151
    u_ao_mem_ctrl.capture_mem_addr[4]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[4]           0.367       0.266
    =========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                      Required
    Instance                              Reference        Type      Pin     Net                        Time         Slack
                                          Clock
    -----------------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr          ao_top|clk_i     DFFCE     CE      un1_start_reg_0_mb_mb      5.245        -0.949
    u_ao_mem_ctrl.capture_mem_addr[0]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[0]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[1]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[1]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[2]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[2]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[3]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[3]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[4]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[4]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[5]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[5]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[6]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[6]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[7]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[7]     5.245        -0.747
    u_ao_mem_ctrl.capture_mem_addr[8]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[8]     5.245        -0.747
    =======================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.195
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.949

        Number of logic level(s):                3
        Starting point:                          internal_reg_start_dly[0] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    internal_reg_start_dly[0]               DFFC      Q        Out     0.367     0.367       -
    internal_reg_start_dly[0]               Net       -        -       1.021     -           4
    start_reg                               LUT3      I1       In      -         1.388       -
    start_reg                               LUT3      F        Out     1.099     2.487       -
    start_reg                               Net       -        -       1.021     -           3
    u_ao_mem_ctrl.un1_start_reg_0_mb_rn     LUT2      I1       In      -         3.508       -
    u_ao_mem_ctrl.un1_start_reg_0_mb_rn     LUT2      F        Out     1.099     4.607       -
    un1_start_reg_0_mb_rn_0                 Net       -        -       0.766     -           1
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb     LUT4      I2       In      -         5.373       -
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb     LUT4      F        Out     0.822     6.195       -
    un1_start_reg_0_mb_mb                   Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr            DFFCE     CE       In      -         6.195       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.328 is 3.520(55.6%) logic and 2.808(44.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.128
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.882

        Number of logic level(s):                3
        Starting point:                          capture_start_sel / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    capture_start_sel                       DFFCE     Q        Out     0.367     0.367       -
    capture_start_sel                       Net       -        -       1.021     -           4
    start_reg                               LUT3      I0       In      -         1.388       -
    start_reg                               LUT3      F        Out     1.032     2.420       -
    start_reg                               Net       -        -       1.021     -           3
    u_ao_mem_ctrl.un1_start_reg_0_mb_rn     LUT2      I1       In      -         3.441       -
    u_ao_mem_ctrl.un1_start_reg_0_mb_rn     LUT2      F        Out     1.099     4.540       -
    un1_start_reg_0_mb_rn_0                 Net       -        -       0.766     -           1
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb     LUT4      I2       In      -         5.306       -
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb     LUT4      F        Out     0.822     6.128       -
    un1_start_reg_0_mb_mb                   Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr            DFFCE     CE       In      -         6.128       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.261 is 3.453(55.2%) logic and 2.808(44.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      5.993
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.747

        Number of logic level(s):                3
        Starting point:                          u_ao_mem_ctrl.capture_mem_addr[6] / Q
        Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
        The start point is clocked by            ao_top|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                                           Pin      Pin               Arrival     No. of
    Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_addr[6]              DFFCE     Q        Out     0.367     0.367       -
    capture_mem_addr[6]                            Net       -        -       1.021     -           5
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      I1       In      -         1.388       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      F        Out     1.099     2.487       -
    un1_capture_mem_addr_7_N_2L1                   Net       -        -       0.766     -           1
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      I3       In      -         3.253       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      F        Out     0.626     3.879       -
    N_14_i_1                                       Net       -        -       1.082     -           12
    u_ao_mem_ctrl.N_14_i                           LUT4      I0       In      -         4.961       -
    u_ao_mem_ctrl.N_14_i                           LUT4      F        Out     1.032     5.993       -
    N_14_i                                         Net       -        -       0.000     -           1
    u_ao_mem_ctrl.mem_addr_inc_en                  DFFCE     CE       In      -         5.993       -
    ==========================================================================================================
    Total path delay (propagation time + setup) of 6.126 is 3.257(53.2%) logic and 2.869(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      5.993
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.747

        Number of logic level(s):                3
        Starting point:                          u_ao_mem_ctrl.capture_mem_addr[6] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
        The start point is clocked by            ao_top|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                                           Pin      Pin               Arrival     No. of
    Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_addr[6]              DFFCE     Q        Out     0.367     0.367       -
    capture_mem_addr[6]                            Net       -        -       1.021     -           5
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      I1       In      -         1.388       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      F        Out     1.099     2.487       -
    un1_capture_mem_addr_7_N_2L1                   Net       -        -       0.766     -           1
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      I3       In      -         3.253       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      F        Out     0.626     3.879       -
    N_14_i_1                                       Net       -        -       1.082     -           12
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb            LUT4      I0       In      -         4.961       -
    u_ao_mem_ctrl.un1_start_reg_0_mb_mb            LUT4      F        Out     1.032     5.993       -
    un1_start_reg_0_mb_mb                          Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_wr                   DFFCE     CE       In      -         5.993       -
    ==========================================================================================================
    Total path delay (propagation time + setup) of 6.126 is 3.257(53.2%) logic and 2.869(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      5.993
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.747

        Number of logic level(s):                3
        Starting point:                          u_ao_mem_ctrl.capture_mem_addr[6] / Q
        Ending point:                            u_ao_mem_ctrl.capture_mem_addr[9] / D
        The start point is clocked by            ao_top|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                                           Pin      Pin               Arrival     No. of
    Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_addr[6]              DFFCE     Q        Out     0.367     0.367       -
    capture_mem_addr[6]                            Net       -        -       1.021     -           5
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      I1       In      -         1.388       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3      F        Out     1.099     2.487       -
    un1_capture_mem_addr_7_N_2L1                   Net       -        -       0.766     -           1
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      I3       In      -         3.253       -
    u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4      F        Out     0.626     3.879       -
    N_14_i_1                                       Net       -        -       1.082     -           12
    u_ao_mem_ctrl.capture_mem_addr_lm_0[9]         LUT4      I0       In      -         4.961       -
    u_ao_mem_ctrl.capture_mem_addr_lm_0[9]         LUT4      F        Out     1.032     5.993       -
    capture_mem_addr_lm[9]                         Net       -        -       0.000     -           1
    u_ao_mem_ctrl.capture_mem_addr[9]              DFFCE     D        In      -         5.993       -
    ==========================================================================================================
    Total path delay (propagation time + setup) of 6.126 is 3.257(53.2%) logic and 2.869(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                 Arrival
    Instance                         Reference             Type      Pin     Net                              Time        Slack
                                     Clock
    ----------------------------------------------------------------------------------------------------------------------------
    module_state_fast[4]             ao_top|control[0]     DFFC      Q       module_state_fast[4]             0.367       -1.587
    module_state[3]                  ao_top|control[0]     DFFC      Q       module_state[3]                  0.367       -1.520
    internal_register_select[4]      ao_top|control[0]     DFFCE     Q       internal_register_select[4]      0.367       -1.272
    word_count[0]                    ao_top|control[0]     DFFCE     Q       word_count[0]                    0.367       -1.220
    internal_register_select[3]      ao_top|control[0]     DFFCE     Q       internal_register_select[3]      0.367       -1.205
    internal_register_select[15]     ao_top|control[0]     DFFCE     Q       internal_register_select[15]     0.367       -1.205
    word_count[1]                    ao_top|control[0]     DFFCE     Q       word_count[1]                    0.367       -1.163
    internal_register_select[6]      ao_top|control[0]     DFFCE     Q       internal_register_select[6]      0.367       -1.138
    word_count[2]                    ao_top|control[0]     DFFCE     Q       word_count[2]                    0.367       -1.106
    word_count[3]                    ao_top|control[0]     DFFCE     Q       word_count[3]                    0.367       -1.049
    ============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                               Starting                                                             Required
    Instance                   Reference             Type      Pin     Net                          Time         Slack
                               Clock
    -------------------------------------------------------------------------------------------------------------------
    data_out_shift_reg[0]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[0]      8.861        -1.587
    data_out_shift_reg[1]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[1]      8.861        -1.587
    data_out_shift_reg[3]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[3]      8.861        -1.587
    data_out_shift_reg[5]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[5]      8.861        -1.587
    data_out_shift_reg[7]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[7]      8.861        -1.587
    data_out_shift_reg[8]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[8]      8.861        -1.587
    data_out_shift_reg[9]      ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[9]      8.861        -1.587
    data_out_shift_reg[10]     ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[10]     8.861        -1.587
    data_out_shift_reg[11]     ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[11]     8.861        -1.587
    data_out_shift_reg[12]     ao_top|control[0]     DFFCE     D       data_out_shift_reg_4[12]     8.861        -1.587
    ===================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      8.995
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.861

        - Propagation time:                      10.449
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.587

        Number of logic level(s):                5
        Starting point:                          module_state_fast[4] / Q
        Ending point:                            data_out_shift_reg[1] / D
        The start point is clocked by            ao_top|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                       Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    module_state_fast[4]                       DFFC      Q        Out     0.367     0.367       -
    module_state_fast[4]                       Net       -        -       1.021     -           1
    N_139_i_0_o2                               LUT2      I1       In      -         1.388       -
    N_139_i_0_o2                               LUT2      F        Out     1.099     2.487       -
    N_61                                       Net       -        -       1.021     -           5
    out_reg_ld_en_d                            LUT4      I0       In      -         3.508       -
    out_reg_ld_en_d                            LUT4      F        Out     1.032     4.540       -
    out_reg_ld_en_d                            Net       -        -       1.082     -           16
    out_reg_ld_en                              LUT4      I2       In      -         5.622       -
    out_reg_ld_en                              LUT4      F        Out     0.822     6.444       -
    out_reg_ld_en                              Net       -        -       1.265     -           44
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      I3       In      -         7.709       -
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      F        Out     0.626     8.335       -
    N_426                                      Net       -        -       1.082     -           15
    data_out_shift_reg_4_m_0[1]                LUT4      I0       In      -         9.417       -
    data_out_shift_reg_4_m_0[1]                LUT4      F        Out     1.032     10.449      -
    data_out_shift_reg_4[1]                    Net       -        -       0.000     -           1
    data_out_shift_reg[1]                      DFFCE     D        In      -         10.449      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 10.582 is 5.111(48.3%) logic and 5.471(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      8.995
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.861

        - Propagation time:                      10.449
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.587

        Number of logic level(s):                5
        Starting point:                          module_state_fast[4] / Q
        Ending point:                            data_out_shift_reg[0] / D
        The start point is clocked by            ao_top|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                       Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    module_state_fast[4]                       DFFC      Q        Out     0.367     0.367       -
    module_state_fast[4]                       Net       -        -       1.021     -           1
    N_139_i_0_o2                               LUT2      I1       In      -         1.388       -
    N_139_i_0_o2                               LUT2      F        Out     1.099     2.487       -
    N_61                                       Net       -        -       1.021     -           5
    out_reg_ld_en_d                            LUT4      I0       In      -         3.508       -
    out_reg_ld_en_d                            LUT4      F        Out     1.032     4.540       -
    out_reg_ld_en_d                            Net       -        -       1.082     -           16
    out_reg_ld_en                              LUT4      I2       In      -         5.622       -
    out_reg_ld_en                              LUT4      F        Out     0.822     6.444       -
    out_reg_ld_en                              Net       -        -       1.265     -           44
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      I3       In      -         7.709       -
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      F        Out     0.626     8.335       -
    N_426                                      Net       -        -       1.082     -           15
    data_out_shift_reg_4_m_0_0[0]              LUT4      I0       In      -         9.417       -
    data_out_shift_reg_4_m_0_0[0]              LUT4      F        Out     1.032     10.449      -
    data_out_shift_reg_4[0]                    Net       -        -       0.000     -           1
    data_out_shift_reg[0]                      DFFCE     D        In      -         10.449      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 10.582 is 5.111(48.3%) logic and 5.471(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      8.995
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.861

        - Propagation time:                      10.449
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.587

        Number of logic level(s):                5
        Starting point:                          module_state_fast[4] / Q
        Ending point:                            data_out_shift_reg[3] / D
        The start point is clocked by            ao_top|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                       Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    module_state_fast[4]                       DFFC      Q        Out     0.367     0.367       -
    module_state_fast[4]                       Net       -        -       1.021     -           1
    N_139_i_0_o2                               LUT2      I1       In      -         1.388       -
    N_139_i_0_o2                               LUT2      F        Out     1.099     2.487       -
    N_61                                       Net       -        -       1.021     -           5
    out_reg_ld_en_d                            LUT4      I0       In      -         3.508       -
    out_reg_ld_en_d                            LUT4      F        Out     1.032     4.540       -
    out_reg_ld_en_d                            Net       -        -       1.082     -           16
    out_reg_ld_en                              LUT4      I2       In      -         5.622       -
    out_reg_ld_en                              LUT4      F        Out     0.822     6.444       -
    out_reg_ld_en                              Net       -        -       1.265     -           44
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      I3       In      -         7.709       -
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      F        Out     0.626     8.335       -
    N_426                                      Net       -        -       1.082     -           15
    data_out_shift_reg_4_m_0[3]                LUT4      I0       In      -         9.417       -
    data_out_shift_reg_4_m_0[3]                LUT4      F        Out     1.032     10.449      -
    data_out_shift_reg_4[3]                    Net       -        -       0.000     -           1
    data_out_shift_reg[3]                      DFFCE     D        In      -         10.449      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 10.582 is 5.111(48.3%) logic and 5.471(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      8.995
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.861

        - Propagation time:                      10.449
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.587

        Number of logic level(s):                5
        Starting point:                          module_state_fast[4] / Q
        Ending point:                            data_out_shift_reg[5] / D
        The start point is clocked by            ao_top|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                       Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    module_state_fast[4]                       DFFC      Q        Out     0.367     0.367       -
    module_state_fast[4]                       Net       -        -       1.021     -           1
    N_139_i_0_o2                               LUT2      I1       In      -         1.388       -
    N_139_i_0_o2                               LUT2      F        Out     1.099     2.487       -
    N_61                                       Net       -        -       1.021     -           5
    out_reg_ld_en_d                            LUT4      I0       In      -         3.508       -
    out_reg_ld_en_d                            LUT4      F        Out     1.032     4.540       -
    out_reg_ld_en_d                            Net       -        -       1.082     -           16
    out_reg_ld_en                              LUT4      I2       In      -         5.622       -
    out_reg_ld_en                              LUT4      F        Out     0.822     6.444       -
    out_reg_ld_en                              Net       -        -       1.265     -           44
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      I3       In      -         7.709       -
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      F        Out     0.626     8.335       -
    N_426                                      Net       -        -       1.082     -           15
    data_out_shift_reg_4_m_0[5]                LUT4      I0       In      -         9.417       -
    data_out_shift_reg_4_m_0[5]                LUT4      F        Out     1.032     10.449      -
    data_out_shift_reg_4[5]                    Net       -        -       0.000     -           1
    data_out_shift_reg[5]                      DFFCE     D        In      -         10.449      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 10.582 is 5.111(48.3%) logic and 5.471(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      8.995
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.861

        - Propagation time:                      10.449
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.587

        Number of logic level(s):                5
        Starting point:                          module_state_fast[4] / Q
        Ending point:                            data_out_shift_reg[7] / D
        The start point is clocked by            ao_top|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                       Type      Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    module_state_fast[4]                       DFFC      Q        Out     0.367     0.367       -
    module_state_fast[4]                       Net       -        -       1.021     -           1
    N_139_i_0_o2                               LUT2      I1       In      -         1.388       -
    N_139_i_0_o2                               LUT2      F        Out     1.099     2.487       -
    N_61                                       Net       -        -       1.021     -           5
    out_reg_ld_en_d                            LUT4      I0       In      -         3.508       -
    out_reg_ld_en_d                            LUT4      F        Out     1.032     4.540       -
    out_reg_ld_en_d                            Net       -        -       1.082     -           16
    out_reg_ld_en                              LUT4      I2       In      -         5.622       -
    out_reg_ld_en                              LUT4      F        Out     0.822     6.444       -
    out_reg_ld_en                              Net       -        -       1.265     -           44
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      I3       In      -         7.709       -
    data_out_shift_reg_4_m_0_a4_3_i_o2[15]     LUT4      F        Out     0.626     8.335       -
    N_426                                      Net       -        -       1.082     -           15
    data_out_shift_reg_4_m_0[7]                LUT4      I0       In      -         9.417       -
    data_out_shift_reg_4_m_0[7]                LUT4      F        Out     1.032     10.449      -
    data_out_shift_reg_4[7]                    Net       -        -       0.000     -           1
    data_out_shift_reg[7]                      DFFCE     D        In      -         10.449      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 10.582 is 5.111(48.3%) logic and 5.471(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                       Starting                                           Arrival
    Instance                           Reference     Type     Pin     Net                 Time        Slack
                                       Clock
    -------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_i     System        INV      O       capture_end         0.000       3.193
    module_state_i[0]                  System        INV      O       address_counter     0.000       5.744
    =======================================================================================================

    Ending Points with Worst Slack
    ******************************

                                  Starting                                                          Required
    Instance                      Reference     Type      Pin     Net                               Time         Slack
                                  Clock
    ------------------------------------------------------------------------------------------------------------------
    capture_start_sel             System        DFFCE     CE      internal_reg_start_dly_2_i[0]     5.245        3.193
    internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]       5.245        3.193
    capture_end_dly               System        DFFP      D       capture_end                       5.245        4.224
    address_counter[9]            System        DFFCE     D       address_counter_s[9]              8.861        5.744
    address_counter[8]            System        DFFCE     D       address_counter_s[8]              8.861        5.801
    address_counter[7]            System        DFFCE     D       address_counter_s[7]              8.861        5.857
    address_counter[6]            System        DFFCE     D       address_counter_s[6]              8.861        5.915
    address_counter[5]            System        DFFCE     D       address_counter_s[5]              8.861        5.971
    address_counter[4]            System        DFFCE     D       address_counter_s[4]              8.861        6.029
    address_counter[3]            System        DFFCE     D       address_counter_s[3]              8.861        6.085
    ==================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.378
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      2.053
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 3.193

        Number of logic level(s):                1
        Starting point:                          u_ao_mem_ctrl.capture_mem_wr_i / O
        Ending point:                            internal_reg_start_dly[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

    Instance / Net                              Pin      Pin               Arrival     No. of
    Name                               Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_i     INV      O        Out     0.000     0.000       -
    capture_end                        Net      -        -       1.021     -           4
    internal_reg_start_dly_2[0]        LUT3     I0       In      -         1.021       -
    internal_reg_start_dly_2[0]        LUT3     F        Out     1.032     2.053       -
    internal_reg_start_dly_2[0]        Net      -        -       0.000     -           1
    internal_reg_start_dly[0]          DFFC     D        In      -         2.053       -
    =============================================================================================
    Total path delay (propagation time + setup) of 2.186 is 1.165(53.3%) logic and 1.021(46.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 228MB peak: 232MB)

    Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 228MB peak: 232MB)

    ---------------------------------------
    Resource Usage Report for ao_top

    Mapping to part: gw1n_9lqfp144-6
    Cell usage:
    ALU             42 uses
    DFFC            13 uses
    DFFCE           187 uses
    DFFNP           2 uses
    DFFP            4 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       2 uses
    MUX2_LUT6       1 use
    SDPX9           3 uses
    LUT2            35 uses
    LUT3            36 uses
    LUT4            135 uses

    I/O ports: 53
    I/O primitives: 53
    IBUF           51 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   206 of 6480 (3%)

    RAM/ROM usage summary
    Block Rams : 3 of 26 (11%)

    Total load per clock:
       ao_top|clk_i: 1
       ao_top|control[0]: 187

    @S |Mapping Summary:
    Total  LUTs: 206 (2%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 76MB peak: 232MB)

    Process took 0h:00m:06s realtime, 0h:00m:06s cputime
    # Mon Dec  9 16:08:28 2019

    ###########################################################]

`