`

    #Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
    #install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    #OS: Windows 8 6.2
    #Hostname: DESKTOP-8MH08IC

    # Mon Dec  2 10:15:34 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\generic\gw1n.v" (library work)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v" (library work)
    @I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v" (library work)
    @I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v" (library work)
    @I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v" (library work)
    @I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v" (library work)
    @W:CS141 : pdm2pcm_top.v(1890) | Unrecognized synthesis directive name. Verify the correct directive name.
    @W:CS141 : pdm2pcm_top.v(2054) | Unrecognized synthesis directive name. Verify the correct directive name.
    @W:CS141 : pdm2pcm_top.v(2212) | Unrecognized synthesis directive title. Verify the correct directive name.
    @W:CS141 : pdm2pcm_top.v(2279) | Unrecognized synthesis directive title. Verify the correct directive name.
    Verilog syntax check successful!
    @N:CG364 : parameter.v(1) | Synthesizing module work_C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v_unit in library work.
    Selecting top level module PDM2PCM_Top
    Running optimization stage 1 on \~syn_signal.PDM2PCM_Top  .......
    Running optimization stage 1 on \~delay.PDM2PCM_Top _4s_2s .......
    Running optimization stage 1 on PLL .......
    Running optimization stage 1 on \~Gowin_PLL.PDM2PCM_Top  .......
    Running optimization stage 1 on \~clk_div_even.PDM2PCM_Top  .......
    Running optimization stage 1 on \~edge_detect.PDM2PCM_Top _1_4s .......
    Running optimization stage 1 on \~parallel2series.PDM2PCM_Top _1_4s_4s_1s_2s .......
    Running optimization stage 1 on \~cic_down_sample.PDM2PCM_Top _4s_32s_46s_2s .......
    Running optimization stage 1 on \~data_round.PDM2PCM_Top _46s_24s_22s_23s_47s_0s .......
    Running optimization stage 1 on \~data_round.PDM2PCM_Top _46s_46s_0s_45s_47s_0s .......
    Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top _4s_46s_46s .......
    Running optimization stage 1 on \~cic_comb.PDM2PCM_Top _4s_1s_46s_46s_2s .......
    Running optimization stage 1 on \~cic_decimator.PDM2PCM_Top _4s_64s_3s_1s_24s_24s_46s .......
    Running optimization stage 1 on \~cic_filter.PDM2PCM_Top _4s_64s_3s_1s_24s_24s .......
    Opening data file ./cic_comp_coeff.dat from directory C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\.
    Running optimization stage 1 on \~cic_cmp_rom.PDM2PCM_Top _96s_24s .......
    Running optimization stage 1 on SDP .......
    Running optimization stage 1 on \~Gowin_SDP.PDM2PCM_Top  .......
    Running optimization stage 1 on \~delay.PDM2PCM_Top _6s_3s .......
    Running optimization stage 1 on \~delay.PDM2PCM_Top _2s_5s .......
    Running optimization stage 1 on \~delay.PDM2PCM_Top _6s_2s .......
    Running optimization stage 1 on \~delay.PDM2PCM_Top _1s_59s .......
    Running optimization stage 1 on \~data_round.PDM2PCM_Top _48s_24s_9s_23s_34s_15s .......
    Running optimization stage 1 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
    Running optimization stage 1 on \~pdm2pcm.PDM2PCM_Top _96s_64s_3s_1s_4s_1_24s_24s_24s_4s .......
    @N:CG364 : pdm2pcm_wrap.v(4) | Synthesizing module PDM2PCM_Top in library work.
    Running optimization stage 1 on PDM2PCM_Top .......
    Running optimization stage 2 on PDM2PCM_Top .......
    Running optimization stage 2 on \~pdm2pcm.PDM2PCM_Top _96s_64s_3s_1s_4s_1_24s_24s_24s_4s .......
    Running optimization stage 2 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
    Running optimization stage 2 on \~data_round.PDM2PCM_Top _48s_24s_9s_23s_34s_15s .......
    Running optimization stage 2 on \~delay.PDM2PCM_Top _1s_59s .......
    Running optimization stage 2 on \~delay.PDM2PCM_Top _6s_2s .......
    Running optimization stage 2 on \~delay.PDM2PCM_Top _2s_5s .......
    Running optimization stage 2 on \~delay.PDM2PCM_Top _6s_3s .......
    Running optimization stage 2 on \~Gowin_SDP.PDM2PCM_Top  .......
    Running optimization stage 2 on SDP .......
    Running optimization stage 2 on \~cic_cmp_rom.PDM2PCM_Top _96s_24s .......
    Running optimization stage 2 on \~cic_filter.PDM2PCM_Top _4s_64s_3s_1s_24s_24s .......
    Running optimization stage 2 on \~cic_comb.PDM2PCM_Top _4s_1s_46s_46s_2s .......
    Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top _4s_46s_46s .......
    Running optimization stage 2 on \~data_round.PDM2PCM_Top _46s_46s_0s_45s_47s_0s .......
    Running optimization stage 2 on \~cic_decimator.PDM2PCM_Top _4s_64s_3s_1s_24s_24s_46s .......
    Running optimization stage 2 on \~data_round.PDM2PCM_Top _46s_24s_22s_23s_47s_0s .......
    Running optimization stage 2 on \~cic_down_sample.PDM2PCM_Top _4s_32s_46s_2s .......
    Running optimization stage 2 on \~parallel2series.PDM2PCM_Top _1_4s_4s_1s_2s .......
    Running optimization stage 2 on \~edge_detect.PDM2PCM_Top _1_4s .......
    Running optimization stage 2 on \~clk_div_even.PDM2PCM_Top  .......
    Running optimization stage 2 on \~Gowin_PLL.PDM2PCM_Top  .......
    Running optimization stage 2 on PLL .......
    Running optimization stage 2 on \~delay.PDM2PCM_Top _4s_2s .......
    Running optimization stage 2 on \~syn_signal.PDM2PCM_Top  .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 97MB peak: 118MB)

    Process took 0h:00m:04s realtime, 0h:00m:04s cputime

    Process completed successfully.
    # Mon Dec  2 10:15:39 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

    @N: :  | Running in 64-bit mode
    @N:NF107 : pdm2pcm_wrap.v(4) | Selected library: work cell: PDM2PCM_Top view verilog as top level
    @N:NF107 : pdm2pcm_wrap.v(4) | Selected library: work cell: PDM2PCM_Top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  2 10:15:39 2019

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  pdm2pcm_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 18MB peak: 19MB)

    Process took 0h:00m:04s realtime, 0h:00m:04s cputime

    Process completed successfully.
    # Mon Dec  2 10:15:39 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

    @N: :  | Running in 64-bit mode
    @N:NF107 : pdm2pcm_wrap.v(4) | Selected library: work cell: PDM2PCM_Top view verilog as top level
    @N:NF107 : pdm2pcm_wrap.v(4) | Selected library: work cell: PDM2PCM_Top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Dec  2 10:15:41 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Dec  2 10:15:41 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  pdm2pcm_scck.rpt
    Printing clock  summary report in "C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\pdm2pcm_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 225MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 225MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Clock Summary
    ******************

              Start                                              Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                              Frequency     Period        Type         Group                     Load
    -------------------------------------------------------------------------------------------------------------------------------------
    0 -       PDM2PCM_Top|clk                                    149.3 MHz     6.699         inferred     Autoconstr_clkgroup_0     1931

    0 -       _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     325.7 MHz     3.071         inferred     Autoconstr_clkgroup_1     6
    =====================================================================================================================================

    Clock Load Summary
    ***********************

                                                       Clock     Source                                   Clock Pin                         Non-clock Pin     Non-clock Pin
    Clock                                              Load      Pin                                      Seq Example                       Seq Example       Comb Example
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    PDM2PCM_Top|clk                                    1931      clk(port)                                pdm2pcm.cic_cmp.sync_r0.C         -                 -

    _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     6         pdm2pcm.iSysClk.pll_inst.CLKOUT(PLL)     pdm2pcm.clk_div_PDM.clk_out.C     -                 -
    =======================================================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 1403 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 6 clock pin(s) of sequential element(s)
    0 instances converted, 6 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       clk                 port                   1403       ENCRYPTED
    =======================================================================================
    =================================================== Gated/Generated Clocks ====================================================
    Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    -------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_1       ENCRYPTED           PLL                    6                      ENCRYPTED           Black box on clock path
    ===============================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\pdm2pcm.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 228MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Mon Dec  2 10:15:43 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Dec  2 10:15:43 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G
    Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
    OS: Windows 6.2

    Hostname: DESKTOP-8MH08IC

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 121MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 217MB peak: 217MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)

    @N:MF794 :  | RAM in_data_r2_CR23[23:0] required 25 registers during mapping
    @N:MF794 :  | RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping
    @N:MF794 :  | RAM delay_cnt_tdm.dReg_CR5[5:0] required 6 registers during mapping
    @N:MF794 :  | RAM comb\[1\]\.genblk1\.cic_comb.mem[45:0] required 12 registers during mapping
    @N:MF794 :  | RAM intg\[1\]\.genblk1\.cic_intg.data_out_1[45:0] required 12 registers during mapping
    @N:MF794 :  | RAM in_data_r2_CR23[23:0] required 28 registers during mapping
    @N:MF794 :  | RAM acc_out_1[47:0] required 4 registers during mapping
    @N:MF794 :  | RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping
    @N:MF794 :  | RAM delay_cnt_tdm.dReg_CR5[5:0] required 14 registers during mapping

    Starting factoring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 245MB peak: 245MB)

    Finished factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 245MB peak: 245MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 251MB peak: 251MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 258MB peak: 258MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 258MB peak: 259MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 258MB peak: 259MB)

    @N:FX211 :  | Packed ROM mem_out_2_0[23:0] (7 input, 24 output) to Block SelectRAM
    @N:MF794 :  | RAM comb\[1\]\.genblk1\.cic_comb.mem[45:0] required 12 registers during mapping
    @N:MF794 :  | RAM intg\[1\]\.genblk1\.cic_intg.data_out_1[45:0] required 12 registers during mapping
    @N:MF794 :  | RAM in_data_r2_CR23[23:0] required 27 registers during mapping
    @N:MF794 :  | RAM acc_out_1[47:0] required 4 registers during mapping
    @N:MF794 :  | RAM delay_cnt_chn_rd_dx2.dReg_CR1[1:0] required 4 registers during mapping
    @N:MF794 :  | RAM delay_cnt_tdm.dReg_CR5[5:0] required 14 registers during mapping

    Finished preparing to map (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 259MB peak: 259MB)

    Finished technology mapping (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 262MB peak: 262MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:16s		    -4.00ns		1237 /      1211
       2		0h:00m:16s		    -4.00ns		1234 /      1211
       3		0h:00m:16s		    -4.00ns		1234 /      1211

       4		0h:00m:16s		    -4.00ns		1234 /      1211
       5		0h:00m:19s		    -4.00ns		1235 /      1211

       6		0h:00m:22s		    -4.00ns		1236 /      1211

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 262MB peak: 262MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port
    @W: :  | Converting bidirection inout port to output port. Because it's a pure output port
    @W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port

    Finished restoring hierarchy (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:28s; Memory used current: 262MB peak: 262MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 168MB peak: 263MB)

    Writing Analyst data base C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\synwork\pdm2pcm_m.srm
    Warning: Found 48 combinational loops!
    1) instance un2_acc_dsp_out[47:0] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net un2_acc_dsp_out_DOUT[0] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[0]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[0]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[0] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[0]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[0]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[0]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[0]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[0]
    2) instance acc_dsp_out_4[1] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[1] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[1]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[1]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[1]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[1]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[1]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[1] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[1]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[1]
    3) instance acc_dsp_out_4[2] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[2] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[2]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[2]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[2]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[2]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[2]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[2] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[2]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[2]
    4) instance acc_dsp_out_4[3] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[3] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[3]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[3]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[3]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[3]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[3]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[3] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[3]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[3]
    5) instance acc_dsp_out_4[4] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[4] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[4]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[4]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[4]
        net        pdm2pcm.cic_cmp.acc_dsp_out_4_RNO[4]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[4]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[4] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[4]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[4]
    6) instance acc_dsp_out_4[5] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[5] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[5]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[5]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[5]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[5]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[5]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[5] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[5]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[5]
    7) instance acc_dsp_out_4[6] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[6] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[6]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[6]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[6]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[6]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[6]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[6] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[6]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[6]
    8) instance acc_dsp_out_4[7] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[7] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[7]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[7]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[7]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[7]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[7]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[7] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[7]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[7]
    9) instance acc_dsp_out_4[8] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[8] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[8]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[8]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[8]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[8]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[8]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[8] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[8]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[8]
    10) instance acc_dsp_out_4[9] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[9] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[9]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[9]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[9]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[9]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[9]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[9] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[9]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[9]
    11) instance acc_dsp_out_4[10] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[10] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[10]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[10]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[10]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[10]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[10]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[10] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[10]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[10]
    12) instance acc_dsp_out_4[11] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[11] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[11]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[11]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[11]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[11]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[11]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[11] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[11]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[11]
    13) instance acc_dsp_out_4[12] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[12] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[12]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[12]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[12]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[12]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[12]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[12] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[12]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[12]
    14) instance acc_dsp_out_4[13] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[13] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[13]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[13]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[13]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[13]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[13]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[13] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[13]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[13]
    15) instance acc_dsp_out_4[14] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[14] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[14]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[14]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[14]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[14]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[14]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[14] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[14]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[14]
    16) instance acc_dsp_out_4[15] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[15] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[15]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[15]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[15]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[15]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[15]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[15] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[15]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[15]
    17) instance acc_dsp_out_4[16] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[16] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[16]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[16]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[16]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[16]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[16]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[16] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[16]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[16]
    18) instance acc_dsp_out_4[17] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[17] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[17]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[17]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[17]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[17]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[17]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[17] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[17]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[17]
    19) instance acc_dsp_out_4[18] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[18] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[18]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[18]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[18]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[18]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[18]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[18] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[18]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[18]
    20) instance acc_dsp_out_4[19] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[19] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[19]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[19]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[19]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[19]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[19]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[19] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[19]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[19]
    21) instance acc_dsp_out_4[20] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[20] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[20]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[20]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[20]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[20]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[20]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[20] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[20]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[20]
    22) instance acc_dsp_out_4[21] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[21] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[21]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[21]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[21]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[21]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[21]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[21] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[21]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[21]
    23) instance acc_dsp_out_4[22] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[22] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[22]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[22]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[22]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[22]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[22]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[22] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[22]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[22]
    24) instance acc_dsp_out_4[23] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[23] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[23]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[23]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[23]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[23]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[23]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[23] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[23]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[23]
    25) instance acc_dsp_out_4[24] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[24] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[24]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[24]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[24]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[24]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[24]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[24] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[24]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[24]
    26) instance acc_dsp_out_4[25] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[25] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[25]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[25]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[25]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[25]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[25]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[25] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[25]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[25]
    27) instance acc_dsp_out_4[26] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[26] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[26]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[26]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[26]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[26]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[26]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[26] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[26]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[26]
    28) instance acc_dsp_out_4[27] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[27] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[27]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[27]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[27]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[27]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[27]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[27] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[27]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[27]
    29) instance acc_dsp_out_4[28] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[28] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[28]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[28]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[28]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[28]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[28]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[28] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[28]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[28]
    30) instance acc_dsp_out_4[29] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[29] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[29]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[29]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[29]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[29]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[29]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[29] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[29]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[29]
    31) instance acc_dsp_out_4[30] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[30] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[30]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[30]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[30]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[30]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[30]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[30] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[30]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[30]
    32) instance acc_dsp_out_4[31] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[31] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[31]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[31]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[31]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[31]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[31]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[31] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[31]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[31]
    33) instance acc_dsp_out_4[32] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[32] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[32]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[32]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[32]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[32]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[32]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[32] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[32]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[32]
    34) instance acc_dsp_out_4[33] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[33] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[33]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[33]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[33]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[33]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[33]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[33] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[33]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[33]
    35) instance acc_dsp_out_4[34] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[34] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[34]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[34]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[34]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[34]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[34]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[34] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[34]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[34]
    36) instance acc_dsp_out_4[35] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[35] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[35]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[35]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[35]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[35]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[35]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[35] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[35]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[35]
    37) instance acc_dsp_out_4[36] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[36] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[36]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[36]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[36]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[36]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[36]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[36] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[36]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[36]
    38) instance acc_dsp_out_4[37] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[37] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[37]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[37]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[37]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[37]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[37]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[37] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[37]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[37]
    39) instance acc_dsp_out_4[38] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[38] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[38]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[38]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[38]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[38]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[38]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[38] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[38]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[38]
    40) instance acc_dsp_out_4[39] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[39] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[39]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[39]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[39]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[39]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[39]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[39] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[39]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[39]
    41) instance acc_dsp_out_4[40] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[40] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[40]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[40]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[40]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[40]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[40]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[40] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[40]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[40]
    42) instance acc_dsp_out_4[41] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[41] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[41]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[41]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[41]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[41]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[41]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[41] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[41]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[41]
    43) instance acc_dsp_out_4[42] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[42] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[42]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[42]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[42]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[42]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[42]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[42] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[42]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[42]
    44) instance acc_dsp_out_4[43] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[43] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[43]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[43]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[43]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[43]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[43]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[43] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[43]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[43]
    45) instance acc_dsp_out_4[44] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[44] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[44]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[44]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[44]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[44]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[44]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[44] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[44]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[44]
    46) instance acc_dsp_out_4[45] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[45] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[45]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[45]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[45]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[45]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[45]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[45] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[45]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[45]
    47) instance acc_dsp_out_4[46] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[46] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[46]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[46]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[46]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[46]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[46]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[46] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[46]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[46]
    48) instance acc_dsp_out_4[47] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[47] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[47]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[47]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[47]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[47]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[47]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[47] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[47]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[47]
    End of loops

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 243MB peak: 263MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:30s; Memory used current: 244MB peak: 263MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:31s; Memory used current: 244MB peak: 263MB)

    Start final timing analysis (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:31s; Memory used current: 240MB peak: 263MB)

    Warning: Found 48 combinational loops!
    1) instance un2_acc_dsp_out[47:0] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net un2_acc_dsp_out_DOUT[0] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[0]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[0]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[0] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[0]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[0]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[0]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[0]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[0]
    2) instance acc_dsp_out_4[1] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[1] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[1]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[1]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[1]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[1]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[1]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[1] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[1]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[1]
    3) instance acc_dsp_out_4[2] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[2] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[2]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[2]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[2]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[2]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[2]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[2] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[2]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[2]
    4) instance acc_dsp_out_4[3] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[3] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[3]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[3]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[3]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[3]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[3]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[3] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[3]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[3]
    5) instance acc_dsp_out_4[4] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[4] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[4]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[4]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[4]
        net        pdm2pcm.cic_cmp.acc_dsp_out_4_RNO[4]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[4]/I0
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[4] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[4]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[4]
    6) instance acc_dsp_out_4[5] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[5] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[5]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[5]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[5]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[5]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[5]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[5] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[5]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[5]
    7) instance acc_dsp_out_4[6] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[6] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[6]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[6]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[6]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[6]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[6]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[6] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[6]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[6]
    8) instance acc_dsp_out_4[7] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[7] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[7]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[7]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[7]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[7]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[7]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[7] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[7]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[7]
    9) instance acc_dsp_out_4[8] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[8] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[8]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[8]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[8]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[8]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[8]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[8] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[8]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[8]
    10) instance acc_dsp_out_4[9] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[9] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[9]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[9]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[9]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[9]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[9]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[9] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[9]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[9]
    11) instance acc_dsp_out_4[10] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[10] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[10]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[10]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[10]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[10]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[10]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[10] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[10]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[10]
    12) instance acc_dsp_out_4[11] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[11] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[11]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[11]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[11]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[11]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[11]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[11] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[11]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[11]
    13) instance acc_dsp_out_4[12] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[12] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[12]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[12]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[12]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[12]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[12]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[12] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[12]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[12]
    14) instance acc_dsp_out_4[13] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[13] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[13]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[13]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[13]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[13]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[13]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[13] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[13]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[13]
    15) instance acc_dsp_out_4[14] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[14] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[14]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[14]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[14]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[14]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[14]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[14] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[14]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[14]
    16) instance acc_dsp_out_4[15] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[15] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[15]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[15]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[15]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[15]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[15]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[15] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[15]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[15]
    17) instance acc_dsp_out_4[16] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[16] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[16]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[16]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[16]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[16]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[16]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[16] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[16]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[16]
    18) instance acc_dsp_out_4[17] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[17] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[17]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[17]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[17]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[17]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[17]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[17] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[17]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[17]
    19) instance acc_dsp_out_4[18] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[18] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[18]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[18]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[18]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[18]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[18]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[18] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[18]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[18]
    20) instance acc_dsp_out_4[19] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[19] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[19]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[19]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[19]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[19]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[19]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[19] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[19]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[19]
    21) instance acc_dsp_out_4[20] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[20] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[20]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[20]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[20]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[20]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[20]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[20] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[20]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[20]
    22) instance acc_dsp_out_4[21] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[21] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[21]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[21]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[21]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[21]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[21]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[21] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[21]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[21]
    23) instance acc_dsp_out_4[22] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[22] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[22]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[22]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[22]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[22]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[22]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[22] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[22]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[22]
    24) instance acc_dsp_out_4[23] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[23] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[23]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[23]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[23]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[23]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[23]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[23] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[23]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[23]
    25) instance acc_dsp_out_4[24] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[24] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[24]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[24]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[24]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[24]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[24]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[24] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[24]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[24]
    26) instance acc_dsp_out_4[25] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[25] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[25]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[25]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[25]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[25]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[25]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[25] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[25]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[25]
    27) instance acc_dsp_out_4[26] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[26] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[26]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[26]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[26]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[26]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[26]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[26] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[26]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[26]
    28) instance acc_dsp_out_4[27] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[27] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[27]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[27]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[27]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[27]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[27]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[27] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[27]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[27]
    29) instance acc_dsp_out_4[28] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[28] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[28]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[28]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[28]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[28]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[28]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[28] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[28]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[28]
    30) instance acc_dsp_out_4[29] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[29] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[29]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[29]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[29]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[29]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[29]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[29] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[29]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[29]
    31) instance acc_dsp_out_4[30] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[30] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[30]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[30]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[30]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[30]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[30]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[30] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[30]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[30]
    32) instance acc_dsp_out_4[31] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[31] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[31]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[31]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[31]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[31]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[31]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[31] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[31]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[31]
    33) instance acc_dsp_out_4[32] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[32] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[32]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[32]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[32]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[32]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[32]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[32] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[32]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[32]
    34) instance acc_dsp_out_4[33] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[33] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[33]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[33]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[33]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[33]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[33]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[33] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[33]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[33]
    35) instance acc_dsp_out_4[34] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[34] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[34]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[34]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[34]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[34]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[34]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[34] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[34]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[34]
    36) instance acc_dsp_out_4[35] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[35] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[35]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[35]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[35]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[35]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[35]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[35] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[35]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[35]
    37) instance acc_dsp_out_4[36] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[36] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[36]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[36]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[36]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[36]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[36]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[36] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[36]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[36]
    38) instance acc_dsp_out_4[37] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[37] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[37]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[37]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[37]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[37]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[37]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[37] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[37]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[37]
    39) instance acc_dsp_out_4[38] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[38] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[38]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[38]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[38]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[38]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[38]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[38] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[38]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[38]
    40) instance acc_dsp_out_4[39] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[39] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[39]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[39]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[39]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[39]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[39]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[39] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[39]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[39]
    41) instance acc_dsp_out_4[40] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[40] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[40]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[40]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[40]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[40]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[40]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[40] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[40]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[40]
    42) instance acc_dsp_out_4[41] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[41] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[41]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[41]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[41]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[41]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[41]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[41] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[41]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[41]
    43) instance acc_dsp_out_4[42] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[42] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[42]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[42]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[42]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[42]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[42]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[42] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[42]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[42]
    44) instance acc_dsp_out_4[43] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[43] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[43]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[43]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[43]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[43]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[43]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[43] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[43]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[43]
    45) instance acc_dsp_out_4[44] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[44] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[44]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[44]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[44]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[44]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[44]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[44] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[44]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[44]
    46) instance acc_dsp_out_4[45] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[45] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[45]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[45]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[45]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[45]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[45]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[45] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[45]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[45]
    47) instance acc_dsp_out_4[46] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[46] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[46]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[46]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[46]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[46]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[46]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[46] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[46]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[46]
    48) instance acc_dsp_out_4[47] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist)), output net acc_dsp_out_4[47] (in view: work.\\\~cic_compensation_filter\.PDM2PCM_Top\ _Z1(netlist))
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[47]
        input  pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/B[47]
        instance   pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0] (cell ALU54D)
        output pin pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]/DOUT[47]
        net        pdm2pcm.cic_cmp.un2_acc_dsp_out_DOUT[47]
        input  pin pdm2pcm.cic_cmp.acc_dsp_out_4[47]/I3
        instance   pdm2pcm.cic_cmp.acc_dsp_out_4[47] (cell LUT4)
        output pin pdm2pcm.cic_cmp.acc_dsp_out_4[47]/F
        net        pdm2pcm.cic_cmp.acc_dsp_out_4[47]
    End of loops
    @W:MT246 : pdm2pcm_top.v(994) | Blackbox MULT36X36 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : pdm2pcm_top.v(2232) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock PDM2PCM_Top|clk with period 11.44ns. Please declare a user-defined clock on port clk.
    @W:MT420 :  | Found inferred clock _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock with period 4.44ns. Please declare a user-defined clock on net pdm2pcm.iSysClk.sym_clk.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Dec  2 10:16:16 2019
    #

    Top view:               PDM2PCM_Top
    Requested Frequency:    87.4 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -2.018

                                                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                     Frequency     Frequency     Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    PDM2PCM_Top|clk                                    87.4 MHz      74.3 MHz      11.438        13.457        -2.018     inferred     Autoconstr_clkgroup_0
    _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     225.2 MHz     191.4 MHz     4.441         5.225         -0.784     inferred     Autoconstr_clkgroup_1
    System                                             225.5 MHz     191.6 MHz     4.435         5.218         -0.783     system       system_clkgroup
    ========================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                          System                                          |  4.435       -0.783  |  No paths    -      |  No paths    -      |  No paths    -
    System                                          PDM2PCM_Top|clk                                 |  11.438      1.291   |  No paths    -      |  No paths    -      |  No paths    -
    System                                          _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock  |  4.441       3.287   |  No paths    -      |  No paths    -      |  No paths    -
    PDM2PCM_Top|clk                                 System                                          |  11.438      4.697   |  No paths    -      |  No paths    -      |  No paths    -
    PDM2PCM_Top|clk                                 PDM2PCM_Top|clk                                 |  11.438      -2.018  |  No paths    -      |  No paths    -      |  No paths    -
    _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock  System                                          |  4.441       3.053   |  No paths    -      |  No paths    -      |  No paths    -
    _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock  _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock  |  4.441       -0.784  |  No paths    -      |  No paths    -      |  No paths    -
    =======================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: PDM2PCM_Top|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                 Starting                                                 Arrival
    Instance                                                                     Reference           Type      Pin     Net                Time        Slack
                                                                                 Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.cnt_mem_wr[4]                                                PDM2PCM_Top|clk     DFFP      Q       cnt_mem_wr[4]      0.367       -2.018
    pdm2pcm.cic_cmp.cnt_mem_wr[3]                                                PDM2PCM_Top|clk     DFFP      Q       cnt_mem_wr[3]      0.367       -1.951
    pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][4]                                 PDM2PCM_Top|clk     DFFCE     Q       cnt_tdm_dx2[4]     0.367       -1.913
    pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][2]                                 PDM2PCM_Top|clk     DFFCE     Q       cnt_tdm_dx2[2]     0.367       -1.845
    pdm2pcm.cic_filter.cic_decimator.comb\[1\]\.genblk1\.cic_comb.cnt_chn[1]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[1]         0.367       -1.798
    pdm2pcm.cic_filter.cic_decimator.comb\[0\]\.genblk1\.cic_comb.cnt_chn[1]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[1]         0.367       -1.798
    pdm2pcm.cic_filter.cic_decimator.comb\[2\]\.genblk1\.cic_comb.cnt_chn[1]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[1]         0.367       -1.798
    pdm2pcm.cic_filter.cic_decimator.comb\[2\]\.genblk1\.cic_comb.cnt_chn[0]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[0]         0.367       -1.731
    pdm2pcm.cic_filter.cic_decimator.comb\[1\]\.genblk1\.cic_comb.cnt_chn[0]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[0]         0.367       -1.731
    pdm2pcm.cic_filter.cic_decimator.comb\[0\]\.genblk1\.cic_comb.cnt_chn[0]     PDM2PCM_Top|clk     DFFP      Q       cnt_chn[0]         0.367       -1.731
    ========================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                    Starting                                                      Required
    Instance                                        Reference           Type        Pin       Net                 Time         Slack
                                                    Clock
    ---------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.cnt_mem_rd[8]                   PDM2PCM_Top|clk     DFFC        D         cnt_mem_rd_5[8]     11.305       -2.018
    pdm2pcm.cic_cmp.cnt_mem_rd[7]                   PDM2PCM_Top|clk     DFFC        D         cnt_mem_rd_5[7]     11.305       -1.962
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_0     PDM2PCM_Top|clk     RAM16S4     DI[0]     un1_acc_out[0]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_0     PDM2PCM_Top|clk     RAM16S4     DI[1]     un1_acc_out[1]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_0     PDM2PCM_Top|clk     RAM16S4     DI[2]     un1_acc_out[2]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_0     PDM2PCM_Top|clk     RAM16S4     DI[3]     un1_acc_out[3]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_1     PDM2PCM_Top|clk     RAM16S4     DI[0]     un1_acc_out[4]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_1     PDM2PCM_Top|clk     RAM16S4     DI[1]     un1_acc_out[5]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_1     PDM2PCM_Top|clk     RAM16S4     DI[2]     un1_acc_out[6]      11.377       -1.913
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_1     PDM2PCM_Top|clk     RAM16S4     DI[3]     un1_acc_out[7]      11.377       -1.913
    =================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      11.438
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         11.305

        - Propagation time:                      13.324
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -2.018

        Number of logic level(s):                14
        Starting point:                          pdm2pcm.cic_cmp.cnt_mem_wr[4] / Q
        Ending point:                            pdm2pcm.cic_cmp.cnt_mem_rd[8] / D
        The start point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK
        The end   point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                         Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.cnt_mem_wr[4]                DFFP     Q        Out     0.367     0.367       -
    cnt_mem_wr[4]                                Net      -        -       1.021     -           8
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     I1       In      -         1.388       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     F        Out     1.099     2.487       -
    cnt_mem_rd19_2                               Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     I0       In      -         3.508       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     F        Out     1.032     4.540       -
    cnt_mem_rd19_2_0                             Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     I1       In      -         5.561       -
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     F        Out     1.099     6.660       -
    cnt_mem_rd19                                 Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     I1       In      -         7.681       -
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     F        Out     1.099     8.780       -
    cnt_mem_rd_2_sqmuxa                          Net      -        -       1.472     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      CIN      In      -         10.252      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      COUT     Out     0.057     10.309      -
    un1_cnt_mem_rd_7_cry_0                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      CIN      In      -         10.309      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      COUT     Out     0.057     10.366      -
    un1_cnt_mem_rd_7_cry_1                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      CIN      In      -         10.366      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      COUT     Out     0.057     10.423      -
    un1_cnt_mem_rd_7_cry_2                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      CIN      In      -         10.423      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      COUT     Out     0.057     10.480      -
    un1_cnt_mem_rd_7_cry_3                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      CIN      In      -         10.480      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      COUT     Out     0.057     10.537      -
    un1_cnt_mem_rd_7_cry_4                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      CIN      In      -         10.537      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      COUT     Out     0.057     10.594      -
    un1_cnt_mem_rd_7_cry_5                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      CIN      In      -         10.594      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      COUT     Out     0.057     10.651      -
    un1_cnt_mem_rd_7_cry_6                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      CIN      In      -         10.651      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      COUT     Out     0.057     10.708      -
    un1_cnt_mem_rd_7_cry_7                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_s_8_0       ALU      CIN      In      -         10.708      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_s_8_0       ALU      SUM      Out     0.563     11.271      -
    un1_cnt_mem_rd_7_s_8_0_SUM                   Net      -        -       1.021     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd_5[8]              LUT2     I0       In      -         12.292      -
    pdm2pcm.cic_cmp.cnt_mem_rd_5[8]              LUT2     F        Out     1.032     13.324      -
    cnt_mem_rd_5[8]                              Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd[8]                DFFC     D        In      -         13.324      -
    =======================================================================================================
    Total path delay (propagation time + setup) of 13.457 is 6.880(51.1%) logic and 6.577(48.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      11.438
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         11.305

        - Propagation time:                      13.267
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.961

        Number of logic level(s):                13
        Starting point:                          pdm2pcm.cic_cmp.cnt_mem_wr[4] / Q
        Ending point:                            pdm2pcm.cic_cmp.cnt_mem_rd[7] / D
        The start point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK
        The end   point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                         Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.cnt_mem_wr[4]                DFFP     Q        Out     0.367     0.367       -
    cnt_mem_wr[4]                                Net      -        -       1.021     -           8
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     I1       In      -         1.388       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     F        Out     1.099     2.487       -
    cnt_mem_rd19_2                               Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     I0       In      -         3.508       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     F        Out     1.032     4.540       -
    cnt_mem_rd19_2_0                             Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     I1       In      -         5.561       -
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     F        Out     1.099     6.660       -
    cnt_mem_rd19                                 Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     I1       In      -         7.681       -
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     F        Out     1.099     8.780       -
    cnt_mem_rd_2_sqmuxa                          Net      -        -       1.472     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      CIN      In      -         10.252      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      COUT     Out     0.057     10.309      -
    un1_cnt_mem_rd_7_cry_0                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      CIN      In      -         10.309      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      COUT     Out     0.057     10.366      -
    un1_cnt_mem_rd_7_cry_1                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      CIN      In      -         10.366      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      COUT     Out     0.057     10.423      -
    un1_cnt_mem_rd_7_cry_2                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      CIN      In      -         10.423      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      COUT     Out     0.057     10.480      -
    un1_cnt_mem_rd_7_cry_3                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      CIN      In      -         10.480      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      COUT     Out     0.057     10.537      -
    un1_cnt_mem_rd_7_cry_4                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      CIN      In      -         10.537      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      COUT     Out     0.057     10.594      -
    un1_cnt_mem_rd_7_cry_5                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      CIN      In      -         10.594      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      COUT     Out     0.057     10.651      -
    un1_cnt_mem_rd_7_cry_6                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      CIN      In      -         10.651      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      SUM      Out     0.563     11.214      -
    un1_cnt_mem_rd_7_cry_7_0_SUM                 Net      -        -       1.021     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd_5_iv[7]           LUT4     I0       In      -         12.235      -
    pdm2pcm.cic_cmp.cnt_mem_rd_5_iv[7]           LUT4     F        Out     1.032     13.267      -
    cnt_mem_rd_5[7]                              Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd[7]                DFFC     D        In      -         13.267      -
    =======================================================================================================
    Total path delay (propagation time + setup) of 13.400 is 6.823(50.9%) logic and 6.577(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      11.438
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         11.305

        - Propagation time:                      13.257
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.951

        Number of logic level(s):                14
        Starting point:                          pdm2pcm.cic_cmp.cnt_mem_wr[3] / Q
        Ending point:                            pdm2pcm.cic_cmp.cnt_mem_rd[8] / D
        The start point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK
        The end   point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                         Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.cnt_mem_wr[3]                DFFP     Q        Out     0.367     0.367       -
    cnt_mem_wr[3]                                Net      -        -       1.021     -           8
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     I0       In      -         1.388       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2               LUT2     F        Out     1.032     2.420       -
    cnt_mem_rd19_2                               Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     I0       In      -         3.441       -
    pdm2pcm.cic_cmp.cnt_mem_rd19_2_0             LUT4     F        Out     1.032     4.473       -
    cnt_mem_rd19_2_0                             Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     I1       In      -         5.494       -
    pdm2pcm.cic_cmp.cnt_mem_rd19                 LUT2     F        Out     1.099     6.593       -
    cnt_mem_rd19                                 Net      -        -       1.021     -           2
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     I1       In      -         7.614       -
    pdm2pcm.cic_cmp.cnt_mem_rd_2_sqmuxa          LUT4     F        Out     1.099     8.713       -
    cnt_mem_rd_2_sqmuxa                          Net      -        -       1.472     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      CIN      In      -         10.185      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_0_0     ALU      COUT     Out     0.057     10.242      -
    un1_cnt_mem_rd_7_cry_0                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      CIN      In      -         10.242      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_1_0     ALU      COUT     Out     0.057     10.299      -
    un1_cnt_mem_rd_7_cry_1                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      CIN      In      -         10.299      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_2_0     ALU      COUT     Out     0.057     10.356      -
    un1_cnt_mem_rd_7_cry_2                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      CIN      In      -         10.356      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_3_0     ALU      COUT     Out     0.057     10.413      -
    un1_cnt_mem_rd_7_cry_3                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      CIN      In      -         10.413      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_4_0     ALU      COUT     Out     0.057     10.470      -
    un1_cnt_mem_rd_7_cry_4                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      CIN      In      -         10.470      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_5_0     ALU      COUT     Out     0.057     10.527      -
    un1_cnt_mem_rd_7_cry_5                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      CIN      In      -         10.527      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_6_0     ALU      COUT     Out     0.057     10.584      -
    un1_cnt_mem_rd_7_cry_6                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      CIN      In      -         10.584      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_cry_7_0     ALU      COUT     Out     0.057     10.641      -
    un1_cnt_mem_rd_7_cry_7                       Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_s_8_0       ALU      CIN      In      -         10.641      -
    pdm2pcm.cic_cmp.un1_cnt_mem_rd_7_s_8_0       ALU      SUM      Out     0.563     11.204      -
    un1_cnt_mem_rd_7_s_8_0_SUM                   Net      -        -       1.021     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd_5[8]              LUT2     I0       In      -         12.225      -
    pdm2pcm.cic_cmp.cnt_mem_rd_5[8]              LUT2     F        Out     1.032     13.257      -
    cnt_mem_rd_5[8]                              Net      -        -       0.000     -           1
    pdm2pcm.cic_cmp.cnt_mem_rd[8]                DFFC     D        In      -         13.257      -
    =======================================================================================================
    Total path delay (propagation time + setup) of 13.390 is 6.813(50.9%) logic and 6.577(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      11.438
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         11.377

        - Propagation time:                      13.290
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.913

        Number of logic level(s):                6
        Starting point:                          pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][4] / Q
        Ending point:                            pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_11 / DI[3]
        The start point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK
        The end   point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK

    Instance / Net                                               Pin          Pin               Arrival     No. of
    Name                                             Type        Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][4]     DFFCE       Q            Out     0.367     0.367       -
    cnt_tdm_dx2[4]                                   Net         -            -       1.021     -           2
    pdm2pcm.cic_cmp.acc_dsp_out7_2                   LUT2        I1           In      -         1.388       -
    pdm2pcm.cic_cmp.acc_dsp_out7_2                   LUT2        F            Out     1.099     2.487       -
    acc_dsp_out7_2                                   Net         -            -       1.265     -           49
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        I1           In      -         3.752       -
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        F            Out     1.099     4.851       -
    acc_dsp_out_4[0]                                 Net         -            -       1.021     -           3
    pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]            ALU54D      B[0]         In      -         5.872       -
    pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]            ALU54D      DOUT[4]      Out     0.838     6.710       -
    acc_dsp_out_4_RNO[4]                             Net         -            -       1.021     -           1
    pdm2pcm.cic_cmp.acc_dsp_out_4[4]                 LUT4        I0           In      -         7.731       -
    pdm2pcm.cic_cmp.acc_dsp_out_4[4]                 LUT4        F            Out     1.032     8.763       -
    acc_dsp_out_4[4]                                 Net         -            -       1.021     -           3
    pdm2pcm.cic_cmp.un23_acc_out[47:0]               ALU54D      A[4]         In      -         9.784       -
    pdm2pcm.cic_cmp.un23_acc_out[47:0]               ALU54D      DOUT[47]     Out     0.838     10.622      -
    un23_acc_out_DOUT[47]                            Net         -            -       1.021     -           1
    pdm2pcm.cic_cmp.un1_acc_out[47]                  LUT4        I3           In      -         11.643      -
    pdm2pcm.cic_cmp.un1_acc_out[47]                  LUT4        F            Out     0.626     12.269      -
    un1_acc_out[47]                                  Net         -            -       1.021     -           2
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_11     RAM16S4     DI[3]        In      -         13.290      -
    ==================================================================================================================
    Total path delay (propagation time + setup) of 13.351 is 5.960(44.6%) logic and 7.391(55.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      11.438
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         11.377

        - Propagation time:                      13.290
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.913

        Number of logic level(s):                6
        Starting point:                          pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][4] / Q
        Ending point:                            pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_11 / DI[3]
        The start point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK
        The end   point is clocked by            PDM2PCM_Top|clk [rising] on pin CLK

    Instance / Net                                               Pin          Pin               Arrival     No. of
    Name                                             Type        Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.delay_cnt_tdm_d.dReg\[1\][4]     DFFCE       Q            Out     0.367     0.367       -
    cnt_tdm_dx2[4]                                   Net         -            -       1.021     -           2
    pdm2pcm.cic_cmp.acc_dsp_out7_2                   LUT2        I1           In      -         1.388       -
    pdm2pcm.cic_cmp.acc_dsp_out7_2                   LUT2        F            Out     1.099     2.487       -
    acc_dsp_out7_2                                   Net         -            -       1.265     -           49
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        I1           In      -         3.752       -
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        F            Out     1.099     4.851       -
    acc_dsp_out_4[0]                                 Net         -            -       1.021     -           3
    pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]            ALU54D      B[0]         In      -         5.872       -
    pdm2pcm.cic_cmp.un2_acc_dsp_out[47:0]            ALU54D      DOUT[0]      Out     0.838     6.710       -
    un2_acc_dsp_out_DOUT[0]                          Net         -            -       1.021     -           1
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        I0           In      -         7.731       -
    pdm2pcm.cic_cmp.acc_dsp_out_4[0]                 LUT4        F            Out     1.032     8.763       -
    acc_dsp_out_4[0]                                 Net         -            -       1.021     -           3
    pdm2pcm.cic_cmp.un23_acc_out[47:0]               ALU54D      A[0]         In      -         9.784       -
    pdm2pcm.cic_cmp.un23_acc_out[47:0]               ALU54D      DOUT[47]     Out     0.838     10.622      -
    un23_acc_out_DOUT[47]                            Net         -            -       1.021     -           1
    pdm2pcm.cic_cmp.un1_acc_out[47]                  LUT4        I3           In      -         11.643      -
    pdm2pcm.cic_cmp.un1_acc_out[47]                  LUT4        F            Out     0.626     12.269      -
    un1_acc_out[47]                                  Net         -            -       1.021     -           2
    pdm2pcm.cic_cmp.acc_out.acc_out_acc_out_0_11     RAM16S4     DI[3]        In      -         13.290      -
    ==================================================================================================================
    Total path delay (propagation time + setup) of 13.351 is 5.960(44.6%) logic and 7.391(55.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                       Starting                                                                              Arrival
    Instance                           Reference                                          Type      Pin     Net              Time        Slack
                                       Clock
    -------------------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[1]     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       cnt_div[1]       0.367       -0.784
    pdm2pcm.clk_div_PDM.cnt_div[0]     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       cnt_div[0]       0.367       -0.656
    pdm2pcm.clk_div_PDM.cnt_div[2]     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       cnt_div[2]       0.367       -0.507
    pdm2pcm.clk_div_PDM.cnt_div[3]     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       cnt_div[3]       0.367       -0.311
    pdm2pcm.clk_div_PDM.cnt_div[4]     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       cnt_div[4]       0.367       0.301
    pdm2pcm.clk_div_PDM.clk_out        _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     Q       out_pdm_sclk     0.367       3.053
    ===========================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                           Starting                                                                                      Required
    Instance                               Reference                                          Type      Pin     Net                      Time         Slack
                                           Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[3]         _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     D       cnt_div_3[3]             4.308        -0.784
    pdm2pcm.clk_div_PDM.cnt_div[4]         _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     D       cnt_div_3[4]             4.308        -0.784
    pdm2pcm.clk_div_PDM.cnt_div[0]         _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     D       cnt_div_3[0]             4.308        -0.037
    pdm2pcm.clk_div_PDM.clk_out            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     CE      clk_out_0_sqmuxa         4.308        0.368
    pdm2pcm.clk_div_PDM.cnt_div[1]         _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     D       un5_cnt_div_1_axbxc1     4.308        1.760
    pdm2pcm.clk_div_PDM.cnt_div[2]         _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     DFFCE     D       un5_cnt_div_1_axbxc2     4.308        1.760
    pdm2pcm.clk_div_PDM.out_pdm_sclk_i     _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock     INV       I       out_pdm_sclk             4.441        3.053
    ========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.441
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.092
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.784

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.clk_div_PDM.cnt_div[1] / Q
        Ending point:                            pdm2pcm.clk_div_PDM.cnt_div[3] / D
        The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                    Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[1]          DFFCE         Q        Out     0.367     0.367       -
    cnt_div[1]                              Net           -        -       1.082     -           14
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          I1       In      -         1.449       -
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          F        Out     1.099     2.548       -
    cnt_div_3_rn_0[3]                       Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     S0       In      -         3.569       -
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     O        Out     0.502     4.071       -
    cnt_div_3[3]                            Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div[3]          DFFCE         D        In      -         5.092       -
    =======================================================================================================
    Total path delay (propagation time + setup) of 5.225 is 2.101(40.2%) logic and 3.124(59.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.441
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      5.092
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.784

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.clk_div_PDM.cnt_div[1] / Q
        Ending point:                            pdm2pcm.clk_div_PDM.cnt_div[4] / D
        The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                            Pin      Pin               Arrival     No. of
    Name                                        Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[1]              DFFCE         Q        Out     0.367     0.367       -
    cnt_div[1]                                  Net           -        -       1.082     -           14
    pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          I1       In      -         1.449       -
    pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          F        Out     1.099     2.548       -
    un5_cnt_div_1_c4                            Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div_3[4]            MUX2_LUT6     S0       In      -         3.569       -
    pdm2pcm.clk_div_PDM.cnt_div_3[4]            MUX2_LUT6     O        Out     0.502     4.071       -
    cnt_div_3[4]                                Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div[4]              DFFCE         D        In      -         5.092       -
    ===========================================================================================================
    Total path delay (propagation time + setup) of 5.225 is 2.101(40.2%) logic and 3.124(59.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.441
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      4.964
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.656

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.clk_div_PDM.cnt_div[0] / Q
        Ending point:                            pdm2pcm.clk_div_PDM.cnt_div[3] / D
        The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                    Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[0]          DFFCE         Q        Out     0.367     0.367       -
    cnt_div[0]                              Net           -        -       1.021     -           10
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          I0       In      -         1.388       -
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          F        Out     1.032     2.420       -
    cnt_div_3_rn_0[3]                       Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     S0       In      -         3.441       -
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     O        Out     0.502     3.943       -
    cnt_div_3[3]                            Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div[3]          DFFCE         D        In      -         4.964       -
    =======================================================================================================
    Total path delay (propagation time + setup) of 5.097 is 2.034(39.9%) logic and 3.063(60.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.441
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      4.964
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.656

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.clk_div_PDM.cnt_div[0] / Q
        Ending point:                            pdm2pcm.clk_div_PDM.cnt_div[4] / D
        The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                            Pin      Pin               Arrival     No. of
    Name                                        Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[0]              DFFCE         Q        Out     0.367     0.367       -
    cnt_div[0]                                  Net           -        -       1.021     -           10
    pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          I0       In      -         1.388       -
    pdm2pcm.clk_div_PDM.un5_cnt_div_1_ac0_5     LUT4          F        Out     1.032     2.420       -
    un5_cnt_div_1_c4                            Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div_3[4]            MUX2_LUT6     S0       In      -         3.441       -
    pdm2pcm.clk_div_PDM.cnt_div_3[4]            MUX2_LUT6     O        Out     0.502     3.943       -
    cnt_div_3[4]                                Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div[4]              DFFCE         D        In      -         4.964       -
    ===========================================================================================================
    Total path delay (propagation time + setup) of 5.097 is 2.034(39.9%) logic and 3.063(60.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.441
        - Setup time:                            0.133
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.308

        - Propagation time:                      4.815
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.507

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.clk_div_PDM.cnt_div[2] / Q
        Ending point:                            pdm2pcm.clk_div_PDM.cnt_div[3] / D
        The start point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~Gowin_PLL_PDM2PCM_Top_|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                        Pin      Pin               Arrival     No. of
    Name                                    Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------
    pdm2pcm.clk_div_PDM.cnt_div[2]          DFFCE         Q        Out     0.367     0.367       -
    cnt_div[2]                              Net           -        -       1.082     -           13
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          I2       In      -         1.449       -
    pdm2pcm.clk_div_PDM.cnt_div_3_rn[3]     LUT4          F        Out     0.822     2.271       -
    cnt_div_3_rn_0[3]                       Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     S0       In      -         3.292       -
    pdm2pcm.clk_div_PDM.cnt_div_3_mb[3]     MUX2_LUT6     O        Out     0.502     3.794       -
    cnt_div_3[3]                            Net           -        -       1.021     -           1
    pdm2pcm.clk_div_PDM.cnt_div[3]          DFFCE         D        In      -         4.815       -
    =======================================================================================================
    Total path delay (propagation time + setup) of 4.948 is 1.824(36.9%) logic and 3.124(63.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                         Starting                                               Arrival
    Instance                                             Reference     Type          Pin         Net            Time        Slack
                                                         Clock
    ------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               System        INV           O           rstn_i         0.000       -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[0]     dsp_out[0]     0.000       1.291
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[0]     dsp_out[0]     0.000       1.291
    pdm2pcm.cic_cmp.cic_cmp_rom.rstn_i                   System        INV           O           rstn_i         0.000       1.514
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[1]     dsp_out[1]     0.000       2.938
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[1]     dsp_out[1]     0.000       2.938
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[2]     dsp_out[2]     0.000       2.938
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[2]     dsp_out[2]     0.000       2.938
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[3]     dsp_out[3]     0.000       2.938
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     DOUT[3]     dsp_out[3]     0.000       2.938
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                         Starting                                                   Required
    Instance                                             Reference     Type          Pin        Net                 Time         Slack
                                                         Clock
    -----------------------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      System        SDP           RESETB     rstn_i              0.482        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[23]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[23]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[24]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[24]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[25]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[25]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[26]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[26]      shift2dsp_6[23]     4.435        -0.783
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     System        MULT36X36     B[27]      shift2dsp_6[23]     4.435        -0.783
    ===================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.435
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.435

        - Propagation time:                      5.218
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.783

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.cic_cmp.rstn_i / O
        Ending point:                            pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0] / B[23]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                     Pin        Pin               Arrival     No. of
    Name                                                 Type          Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               INV           O          Out     0.000     0.000       -
    rstn_i                                               Net           -          -       1.265     -           1048
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           RESETB     In      -         1.265       -
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           DO[7]      Out     0.818     2.083       -
    dmem_out[23]                                         Net           -          -       1.021     -           1
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          I0         In      -         3.104       -
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          F          Out     1.032     4.136       -
    shift2dsp_6[23]                                      Net           -          -       1.082     -           13
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     MULT36X36     B[23]      In      -         5.218       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 5.218 is 1.850(35.5%) logic and 3.368(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.435
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.435

        - Propagation time:                      5.218
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.783

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.cic_cmp.rstn_i / O
        Ending point:                            pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0] / B[35]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                     Pin        Pin               Arrival     No. of
    Name                                                 Type          Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               INV           O          Out     0.000     0.000       -
    rstn_i                                               Net           -          -       1.265     -           1048
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           RESETB     In      -         1.265       -
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           DO[7]      Out     0.818     2.083       -
    dmem_out[23]                                         Net           -          -       1.021     -           1
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          I0         In      -         3.104       -
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          F          Out     1.032     4.136       -
    shift2dsp_6[23]                                      Net           -          -       1.082     -           13
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     MULT36X36     B[35]      In      -         5.218       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 5.218 is 1.850(35.5%) logic and 3.368(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.435
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.435

        - Propagation time:                      5.218
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.783

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.cic_cmp.rstn_i / O
        Ending point:                            pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0] / B[34]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                     Pin        Pin               Arrival     No. of
    Name                                                 Type          Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               INV           O          Out     0.000     0.000       -
    rstn_i                                               Net           -          -       1.265     -           1048
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           RESETB     In      -         1.265       -
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           DO[7]      Out     0.818     2.083       -
    dmem_out[23]                                         Net           -          -       1.021     -           1
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          I0         In      -         3.104       -
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          F          Out     1.032     4.136       -
    shift2dsp_6[23]                                      Net           -          -       1.082     -           13
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     MULT36X36     B[34]      In      -         5.218       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 5.218 is 1.850(35.5%) logic and 3.368(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.435
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.435

        - Propagation time:                      5.218
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.783

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.cic_cmp.rstn_i / O
        Ending point:                            pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0] / B[33]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                     Pin        Pin               Arrival     No. of
    Name                                                 Type          Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               INV           O          Out     0.000     0.000       -
    rstn_i                                               Net           -          -       1.265     -           1048
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           RESETB     In      -         1.265       -
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           DO[7]      Out     0.818     2.083       -
    dmem_out[23]                                         Net           -          -       1.021     -           1
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          I0         In      -         3.104       -
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          F          Out     1.032     4.136       -
    shift2dsp_6[23]                                      Net           -          -       1.082     -           13
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     MULT36X36     B[33]      In      -         5.218       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 5.218 is 1.850(35.5%) logic and 3.368(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.435
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.435

        - Propagation time:                      5.218
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.783

        Number of logic level(s):                2
        Starting point:                          pdm2pcm.cic_cmp.rstn_i / O
        Ending point:                            pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0] / B[32]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                     Pin        Pin               Arrival     No. of
    Name                                                 Type          Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    pdm2pcm.cic_cmp.rstn_i                               INV           O          Out     0.000     0.000       -
    rstn_i                                               Net           -          -       1.265     -           1048
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           RESETB     In      -         1.265       -
    pdm2pcm.cic_cmp.dmem.bram_sdp_2                      SDP           DO[7]      Out     0.818     2.083       -
    dmem_out[23]                                         Net           -          -       1.021     -           1
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          I0         In      -         3.104       -
    pdm2pcm.cic_cmp.shift2dsp_v[23]                      LUT3          F          Out     1.032     4.136       -
    shift2dsp_6[23]                                      Net           -          -       1.082     -           13
    pdm2pcm.cic_cmp.dsp_out_2_preadd_mulonly_0[47:0]     MULT36X36     B[32]      In      -         5.218       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 5.218 is 1.850(35.5%) logic and 3.368(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:35s; CPU Time elapsed 0h:00m:34s; Memory used current: 242MB peak: 263MB)

    Finished timing report (Real Time elapsed 0h:00m:35s; CPU Time elapsed 0h:00m:34s; Memory used current: 242MB peak: 263MB)

    ---------------------------------------
    Resource Usage Report for PDM2PCM_Top

    Mapping to part: gw1n_9lqfp144-6
    Cell usage:
    ALU             312 uses
    DFFC            27 uses
    DFFCE           970 uses
    DFFE            171 uses
    DFFP            38 uses
    DFFPE           4 uses
    GSR             1 use
    INV             7 uses
    MUX2_LUT5       7 uses
    MUX2_LUT6       2 uses
    PLL             1 use
    RAM16S4         92 uses
    RAM16SDP4       45 uses
    SDP             3 uses
    rROM            1 use
    LUT2            427 uses
    LUT3            337 uses
    LUT4            468 uses
    MULT36X36      1 use
    ALU54D         2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   1210 of 6480 (18%)

    RAM/ROM usage summary
    Block Rams : 4 of 26 (15%)

    Block Multipliers: 4 of 10 (40%)
    Total load per clock:
       PDM2PCM_Top|clk: 1352

    @S |Mapping Summary:
    Total  LUTs: 1232 (14%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:35s; CPU Time elapsed 0h:00m:34s; Memory used current: 86MB peak: 263MB)

    Process took 0h:00m:35s realtime, 0h:00m:34s cputime
    # Mon Dec  2 10:16:19 2019

    ###########################################################]

`