
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v" (library work)
@I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\define.v" (library work)
@I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v" (library work)
@I:"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\static_macro_define.v" (library work)
@I::"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v" (library work)
@W: CS141 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v":1890:8:1890:11|Unrecognized synthesis directive name. Verify the correct directive name.
@W: CS141 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v":2054:8:2054:11|Unrecognized synthesis directive name. Verify the correct directive name.
@W: CS141 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v":2212:7:2212:11|Unrecognized synthesis directive title. Verify the correct directive name.
@W: CS141 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_top.v":2279:7:2279:11|Unrecognized synthesis directive title. Verify the correct directive name.
Verilog syntax check successful!
@N: CG364 :"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\parameter.v":1:0:1:8|Synthesizing module work_C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v_unit in library work.
Selecting top level module PDM2PCM_Top
Running optimization stage 1 on \~syn_signal.PDM2PCM_Top  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top _4s_2s .......
Running optimization stage 1 on PLL .......
Running optimization stage 1 on \~Gowin_PLL.PDM2PCM_Top  .......
Running optimization stage 1 on \~clk_div_even.PDM2PCM_Top  .......
Running optimization stage 1 on \~edge_detect.PDM2PCM_Top _1_4s .......
Running optimization stage 1 on \~parallel2series.PDM2PCM_Top _1_4s_4s_1s_2s .......
Running optimization stage 1 on \~cic_down_sample.PDM2PCM_Top _4s_32s_46s_2s .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top _46s_24s_22s_23s_47s_0s .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top _46s_46s_0s_45s_47s_0s .......
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top _4s_46s_46s .......
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top _4s_1s_46s_46s_2s .......
Running optimization stage 1 on \~cic_decimator.PDM2PCM_Top _4s_64s_3s_1s_24s_24s_46s .......
Running optimization stage 1 on \~cic_filter.PDM2PCM_Top _4s_64s_3s_1s_24s_24s .......
Opening data file ./cic_comp_coeff.dat from directory C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\.
Running optimization stage 1 on \~cic_cmp_rom.PDM2PCM_Top _96s_24s .......
Running optimization stage 1 on SDP .......
Running optimization stage 1 on \~Gowin_SDP.PDM2PCM_Top  .......
Running optimization stage 1 on \~delay.PDM2PCM_Top _6s_3s .......
Running optimization stage 1 on \~delay.PDM2PCM_Top _2s_5s .......
Running optimization stage 1 on \~delay.PDM2PCM_Top _6s_2s .......
Running optimization stage 1 on \~delay.PDM2PCM_Top _1s_59s .......
Running optimization stage 1 on \~data_round.PDM2PCM_Top _48s_24s_9s_23s_34s_15s .......
Running optimization stage 1 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
Running optimization stage 1 on \~pdm2pcm.PDM2PCM_Top _96s_64s_3s_1s_4s_1_24s_24s_24s_4s .......
@N: CG364 :"C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v":4:19:4:19|Synthesizing module PDM2PCM_Top in library work.
Running optimization stage 1 on PDM2PCM_Top .......
Running optimization stage 2 on PDM2PCM_Top .......
Running optimization stage 2 on \~pdm2pcm.PDM2PCM_Top _96s_64s_3s_1s_4s_1_24s_24s_24s_4s .......
Running optimization stage 2 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top _48s_24s_9s_23s_34s_15s .......
Running optimization stage 2 on \~delay.PDM2PCM_Top _1s_59s .......
Running optimization stage 2 on \~delay.PDM2PCM_Top _6s_2s .......
Running optimization stage 2 on \~delay.PDM2PCM_Top _2s_5s .......
Running optimization stage 2 on \~delay.PDM2PCM_Top _6s_3s .......
Running optimization stage 2 on \~Gowin_SDP.PDM2PCM_Top  .......
Running optimization stage 2 on SDP .......
Running optimization stage 2 on \~cic_cmp_rom.PDM2PCM_Top _96s_24s .......
Running optimization stage 2 on \~cic_filter.PDM2PCM_Top _4s_64s_3s_1s_24s_24s .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top _4s_1s_46s_46s_2s .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top _4s_46s_46s .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top _46s_46s_0s_45s_47s_0s .......
Running optimization stage 2 on \~cic_decimator.PDM2PCM_Top _4s_64s_3s_1s_24s_24s_46s .......
Running optimization stage 2 on \~data_round.PDM2PCM_Top _46s_24s_22s_23s_47s_0s .......
Running optimization stage 2 on \~cic_down_sample.PDM2PCM_Top _4s_32s_46s_2s .......
Running optimization stage 2 on \~parallel2series.PDM2PCM_Top _1_4s_4s_1s_2s .......
Running optimization stage 2 on \~edge_detect.PDM2PCM_Top _1_4s .......
Running optimization stage 2 on \~clk_div_even.PDM2PCM_Top  .......
Running optimization stage 2 on \~Gowin_PLL.PDM2PCM_Top  .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on \~delay.PDM2PCM_Top _4s_2s .......
Running optimization stage 2 on \~syn_signal.PDM2PCM_Top  .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 97MB peak: 118MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime

Process completed successfully.
# Mon Dec  2 10:15:39 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: C:\Users\Noa\Documents\WXWork\1688853129516911\Cache\File\2019-11\Gowin_V1.9.3Beta_36338_20191119\SynplifyPro
OS: Windows 6.2

Hostname: DESKTOP-8MH08IC

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: NF107 :"c:\users\noa\documents\wxwork\1688853129516911\cache\file\2019-11\gowin_v1.9.3beta_36338_20191119\ide\ipcore\pdm2pcm\data\pdm2pcm_wrap.v":4:19:4:19|Selected library: work cell: PDM2PCM_Top view verilog as top level
@N: NF107 :"c:\users\noa\documents\wxwork\1688853129516911\cache\file\2019-11\gowin_v1.9.3beta_36338_20191119\ide\ipcore\pdm2pcm\data\pdm2pcm_wrap.v":4:19:4:19|Selected library: work cell: PDM2PCM_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Dec  2 10:15:39 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\synwork\pdm2pcm_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime

Process completed successfully.
# Mon Dec  2 10:15:39 2019

###########################################################]
