#--  Synopsys, Inc.
#--  Version P-2019.03G-1-Beta1
#--  Project file E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\scratchproject.prs

#project files
add_file -verilog "E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/src/pdm2pcm/pdm2pcm.v"
add_file -verilog "E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/src/Top.v"
add_file -verilog "E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/src/data_rom.v"



#implementation: "rev_1"
impl -add E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1 -type fpga
set_option -include_path {E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/src/data;E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/src/pdm2pcm/temp/pdm2pcm}

#device options
set_option -technology GOWIN-GW1N
set_option -part GW1N_9
set_option -package LQFP144
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "Top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW1N
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "E:/IP_verify/1.9.3/IP_web/Gowin_PDM2PCM_RefDesign/PDM2PCM_RefDesign/project/impl/synthesize/rev_1/Ref_design.vm"
impl -active "rev_1"
