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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: C:\Gowin\1.9\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-032

Implementation : rev_1

# Written on Mon Dec 16 17:04:31 2019

##### DESIGN INFO #######################################################

Top View:                "Top"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                             Ending                                               |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                               System                                               |     10.000           |     No paths         |     No paths         |     No paths                         
System                                               Top|SYM_CLK                                          |     28.407           |     No paths         |     No paths         |     No paths                         
System                                               _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     |     2.395            |     No paths         |     No paths         |     No paths                         
Top|SYM_CLK                                          System                                               |     28.407           |     No paths         |     No paths         |     No paths                         
Top|SYM_CLK                                          Top|SYM_CLK                                          |     28.407           |     No paths         |     No paths         |     No paths                         
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     System                                               |     2.395            |     No paths         |     No paths         |     No paths                         
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     Top|SYM_CLK                                          |     Diff grp         |     No paths         |     No paths         |     No paths                         
_~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock     |     2.395            |     No paths         |     No paths         |     No paths                         
=====================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:KEY1
p:SW1
p:out_pcm_data[0]
p:out_pcm_data[1]
p:out_pcm_data[2]
p:out_pcm_data[3]
p:out_pcm_data[4]
p:out_pcm_data[5]
p:out_pcm_data[6]
p:out_pcm_data[7]
p:out_pcm_data[8]
p:out_pcm_data[9]
p:out_pcm_data[10]
p:out_pcm_data[11]
p:out_pcm_data[12]
p:out_pcm_data[13]
p:out_pcm_data[14]
p:out_pcm_data[15]
p:out_pcm_data[16]
p:out_pcm_data[17]
p:out_pcm_data[18]
p:out_pcm_data[19]
p:out_pcm_data[20]
p:out_pcm_data[21]
p:out_pcm_data[22]
p:out_pcm_data[23]
p:out_pcm_sync
p:out_pcm_valid
p:out_pdm_sclk


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
