#OPTIONS:"|-modgen|-top|ALU54D|-I|C:\\Gowin\\1.9\\SynplifyPro\\lib|-devicelib|C:\\Gowin\\1.9\\SynplifyPro\\lib\\xilinx\\unisim.v|-encrypt|-pro|-sysv|-dw|-primux|-ram|-fixsmult|-tri_compatible|-autosm|-fid2|-sharing|on|-ll|2000|-params|E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\impl\\synthesize\\rev_1\\syntmp\\ALU54D.param"
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\bin64\\c_ver.exe":1575393480
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\hypermods.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\umr_capim.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1575393232
#CUR:"C:\\Gowin\\1.9\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1575393232
#CUR:"E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\impl\\synthesize\\rev_1\\syntmp\\ALU54D.v":1575400124
#CUR:"E:\\IP_verify\\1.9.3\\IP_web\\Gowin_PDM2PCM_RefDesign\\PDM2PCM_RefDesign\\project\\impl\\synthesize\\rev_1\\syntmp\\ALU54D.param":1576487114
#numinternalfiles:4
#defaultlanguage:verilog
0			"E:\IP_verify\1.9.3\IP_web\Gowin_PDM2PCM_RefDesign\PDM2PCM_RefDesign\project\impl\synthesize\rev_1\syntmp\ALU54D.v" verilog
#Dependency Lists(Uses List)
0 -1
#Dependency Lists(Users Of)
0 -1
#Design Unit to File Association
module work MULTADDALU18X18 0
module work ALU54D 0
module work PADD18 0
module work PADD9 0
