@N: CD630 :"C:\Users\Noa\Desktop\Myworkplace\Program\FPGAProgram\Ref_design\src\pdm2pcm\temp\pdm2pcm\rev_1\syntmp\gentmp4998a13772":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a13772":696:7:696:11|Synthesizing work.smult.cell_level.
@W: CD638 :"syng0a13772":751:8:751:13|Signal result is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"syng0a13772":523:7:523:15|Synthesizing work.smallmult.arch1.
@N: CD630 :"syng0a13772":319:7:319:16|Synthesizing work.addertree2.arch1.
@N: CD630 :"syng0a13772":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a13772":58:10:58:16|Synthesizing work.pipebuf.syn_black_box.
Post processing for work.pipebuf.syn_black_box
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a13772":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a13772":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a13772":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
@N: CD630 :"syng0a13772":163:7:163:11|Synthesizing work.floor.arch1.
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
@N: CD630 :"syng0a13772":81:7:81:12|Synthesizing work.addreg.arch1.
Post processing for work.addreg.arch1
Running optimization stage 1 on addreg .......
Post processing for work.floor.arch1
Running optimization stage 1 on floor .......
Post processing for work.addertree2.arch1
Running optimization stage 1 on adderTree2 .......
@N: CD630 :"syng0a13772":17:7:17:19|Synthesizing work.firstproducts.arch1.
@W: CD638 :"syng0a13772":32:10:32:14|Signal a_aux is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"syng0a13772":33:10:33:14|Signal b_aux is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.firstproducts.arch1
Running optimization stage 1 on FirstProducts .......
Post processing for work.smallmult.arch1
Running optimization stage 1 on smallMult .......
Post processing for work.smult.cell_level
Running optimization stage 1 on SMULT .......
Post processing for work.top.gen
Running optimization stage 1 on top .......
Running optimization stage 2 on FirstProducts .......
Running optimization stage 2 on addreg_48_24_1_24_1 .......
Running optimization stage 2 on addreg_46_24_2_24_1 .......
Running optimization stage 2 on addreg_44_24_3_24_1 .......
Running optimization stage 2 on addreg_42_24_4_24_1 .......
Running optimization stage 2 on addreg_40_24_5_24_1 .......
Running optimization stage 2 on addreg_38_24_6_24_1 .......
Running optimization stage 2 on addreg_36_24_7_24_1 .......
Running optimization stage 2 on addreg_34_24_8_24_1 .......
Running optimization stage 2 on addreg_32_24_9_24_1 .......
Running optimization stage 2 on addreg_30_24_10_24_1 .......
Running optimization stage 2 on addreg_28_24_11_24_1 .......
Running optimization stage 2 on addreg_26_24_12_24_1 .......
Running optimization stage 2 on floor_1200_600_24_24_1 .......
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 1173 to 1151 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 1122 to 1100 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 1071 to 1051 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 1020 to 1000 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 969 to 951 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 918 to 900 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 867 to 851 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 816 to 800 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 765 to 751 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 714 to 700 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 663 to 651 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 612 to 600 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 561 to 551 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 510 to 500 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 459 to 451 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 408 to 400 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 357 to 351 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 306 to 300 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 255 to 251 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 204 to 200 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 153 to 151 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 102 to 100 of input(1199 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 51 of input(1199 downto 0) is unused 
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 0 of input(1199 downto 0) is unused 
Running optimization stage 2 on addreg_47_24_1_12_2 .......
Running optimization stage 2 on addreg_43_24_2_12_2 .......
Running optimization stage 2 on addreg_39_24_3_12_2 .......
Running optimization stage 2 on addreg_35_24_4_12_2 .......
Running optimization stage 2 on addreg_31_24_5_12_2 .......
Running optimization stage 2 on addreg_27_24_6_12_2 .......
Running optimization stage 2 on floor_600_300_12_24_2 .......
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 572 to 551 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 520 to 500 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 468 to 451 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 416 to 400 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 364 to 351 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 312 to 300 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 260 to 251 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 208 to 200 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 156 to 151 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 104 to 100 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 52 to 51 of input(599 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 0 of input(599 downto 0) is unused 
Running optimization stage 2 on addreg_45_24_1_6_3 .......
Running optimization stage 2 on addreg_37_24_2_6_3 .......
Running optimization stage 2 on addreg_29_24_3_6_3 .......
Running optimization stage 2 on floor_300_150_6_24_3 .......
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 270 to 251 of input(299 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 216 to 200 of input(299 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 162 to 151 of input(299 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 108 to 100 of input(299 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 54 to 51 of input(299 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 0 of input(299 downto 0) is unused 
Running optimization stage 2 on addreg_41_24_1_3_4 .......
Running optimization stage 2 on floor_150_100_3_24_4 .......
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 58 to 51 of input(149 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 0 of input(149 downto 0) is unused 
Running optimization stage 2 on addreg_33_24_1_2_5 .......
Running optimization stage 2 on floor_100_50_2_24_5 .......
@W: CL246 :"syng0a13772":172:4:172:8|Input port bits 66 to 51 of input(99 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"syng0a13772":172:4:172:8|Input port bit 0 of input(99 downto 0) is unused 
Running optimization stage 2 on adderTree2 .......
Running optimization stage 2 on smallMult .......
Running optimization stage 2 on SMULT .......
Running optimization stage 2 on top .......
