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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-Beta4
Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-063

Implementation : rev_1

# Written on Mon Dec  9 16:08:18 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                 Requested     Requested     Clock        Clock                     Clock
Level     Clock                 Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------
0 -       ao_top|control[0]     158.1 MHz     6.326         inferred     Autoconstr_clkgroup_1     228  
                                                                                                        
0 -       ao_top|clk_i          240.4 MHz     4.160         inferred     Autoconstr_clkgroup_0     64   
========================================================================================================


Clock Load Summary
******************

                      Clock     Source               Clock Pin                         Non-clock Pin     Non-clock Pin       
Clock                 Load      Pin                  Seq Example                       Seq Example       Comb Example        
-----------------------------------------------------------------------------------------------------------------------------
ao_top|control[0]     228       control[0](port)     data_register[62:0].C             -                 -                   
                                                                                                                             
ao_top|clk_i          64        clk_i(port)          internal_reg_start_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
=============================================================================================================================
