@W: MT246 :"e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\src\pdm2pcm\pdm2pcm.v":18745:7:18745:22|Blackbox rROM is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\src\pdm2pcm\pdm2pcm.v":177:6:177:13|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock Top|SYM_CLK with period 15.23ns. Please declare a user-defined clock on port SYM_CLK.
@W: MT420 |Found inferred clock _~Gowin_PLL_PDM2PCM_Top__|sym_clk_inferred_clock with period 4.44ns. Please declare a user-defined clock on net PDM2PCM_Top.pdm2pcm.iSysClk.sym_clk.
