//
// Written by Synplify Pro 
// Product Version "P-2019.03G-1-Beta1"
// Program "Synplify Pro", Mapper "mapgw2019q1p1, Build 007R"
// Mon Dec 16 17:05:17 2019
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\c:\gowin\1.9\synplifypro\lib\generic\gw1n.v "
// file 1 "\c:\gowin\1.9\synplifypro\lib\vlog\hypermods.v "
// file 2 "\c:\gowin\1.9\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\c:\gowin\1.9\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\c:\gowin\1.9\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\src\pdm2pcm\pdm2pcm.v "
// file 6 "\e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\src\top.v "
// file 7 "\e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\src\data_rom.v "
// file 8 "\c:\gowin\1.9\synplifypro\lib\nlconst.dat "
// file 9 "\e:\ip_verify\1.9.3\ip_web\gowin_pdm2pcm_refdesign\pdm2pcm_refdesign\project\impl\synthesize\rev_1\syntmp\alu54d.v "

`timescale 100 ps/100 ps
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
`pragma protect key_block
FjMcgK/7HthahkfZezyav91MoDuAYwUKxV5VOMPrt1QXMLgOb5OHQgKNY8n2k7arx4Rjq7+G61RX
SxLKkYp2Ra6kR5WmxrVSF9lrDE1yU0fdXkFJZV9CczO4Fyb5g6FRGTiUHhZI4TIXW2tPlGYg2P8H
az23US9PTrQNEoU3mo4EwyniUSA7H4Pq65GCP4aIP4zsI10lNye5MnrMNi8VpANxZ4Z5mVvoKSYD
RE/Girr+c7Oc9vQ81dBkcG6d1G44ka2/KNch0BWG+5J+OnUit5rS8bdAXA2U+0gJZQXf77O2TOgc
d2xjOyL1Lftd5ihpUQ1I+mCehyrSEciqhETpMw==

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GoWin"
`pragma protect key_keyname="GoWin001"
`pragma protect key_method="rsa"
`pragma protect key_block
NVURKuHRxQ30zxQQ88vGUJuq8g7PzmsmD8ZRNBQhEmcLJzi+EtbUYlFv04IuiWtg9bDUpcyzJMe/
1r8sl0WLAaI0Un5UhnPde2Yn6fDiDVq8dzo6FvLkVHlfTuZrXhNyYsqE3Cf+WVqQWWOuiPbfDbvb
/uZpgktQLUM0YW+IE4Js9HSKVDNAzgZ0O/aRNIDbLQ016ONvKvWTWf5NXfals6uVb3kcBSUEO+SX
CtnIP70GEMPJHH1rSjW7to5B3SZEaiYxuq2c0vmbZSAPUcEb0v77/rGw/Pc/O5wJrw28b9vZv/vb
u0UhHfZBpPf7lNqoH1RNelUW0iI4DqvIbQFk2g==

`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=574912)
`pragma protect data_block
[encoded data, 766536 characters]
HqA5u8z9jxFf3A==
`pragma protect end_protected
module PDM2PCM_Top (
  out_pcm_data_c,
  in_pdm_data,
  pdm_valid_d_0,
  out_pcm_sync_c,
  out_pcm_valid_c,
  out_pdm_sclk_c,
  SW1_c,
  un1_KEY1_1,
  SYM_CLK_c
)
;
output [23:0] out_pcm_data_c /* synthesis syn_tristate = 1 */ ;
input [3:0] in_pdm_data ;
input pdm_valid_d_0 ;
output out_pcm_sync_c ;
output out_pcm_valid_c ;
output out_pdm_sclk_c ;
input SW1_c ;
input un1_KEY1_1 ;
input SYM_CLK_c ;
wire pdm_valid_d_0 ;
wire out_pcm_sync_c ;
wire out_pcm_valid_c ;
wire out_pdm_sclk_c ;
wire SW1_c ;
wire un1_KEY1_1 ;
wire SYM_CLK_c ;
wire VCC ;
wire GND ;
// @5:26475
  \~pdm2pcm.PDM2PCM_Top__96s_64s_3s_1s_4s_1_24s_24s_24s_4s_  pdm2pcm (
	.clk(SYM_CLK_c),
	.rstn(un1_KEY1_1),
	.ce(SW1_c),
	.out_pdm_sclk(out_pdm_sclk_c),
	.in_pdm_valid(pdm_valid_d_0),
	.in_pdm_data(in_pdm_data[3:0]),
	.out_pcm_valid(out_pcm_valid_c),
	.out_pcm_sync(out_pcm_sync_c),
	.out_pcm_data(out_pcm_data_c[23:0])
);
// @5:26471
  GSR GSR_INST (
	.GSRI(VCC)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* PDM2PCM_Top */

module Data_ROM (
  drom_addr,
  KEY1_c_i,
  onboard_en,
  SYM_CLK_c,
  drom_out
)
;
input [13:0] drom_addr ;
input KEY1_c_i ;
input onboard_en ;
input SYM_CLK_c ;
output drom_out ;
wire KEY1_c_i ;
wire onboard_en ;
wire SYM_CLK_c ;
wire drom_out ;
wire [31:1] bram_rom_0_DO;
wire GND ;
wire VCC ;
// @7:22
  ROM bram_rom_0 (
	.DO({bram_rom_0_DO[31:1], drom_out}),
	.AD(drom_addr[13:0]),
	.CLK(SYM_CLK_c),
	.OCE(onboard_en),
	.CE(onboard_en),
	.RESET(KEY1_c_i),
	.BLKSEL({GND, GND, GND}),
	.WRE(GND)
);
defparam bram_rom_0.READ_MODE=1'b0;
defparam bram_rom_0.BIT_WIDTH=1;
defparam bram_rom_0.BLK_SEL=3'b000;
defparam bram_rom_0.RESET_MODE="SYNC";
defparam bram_rom_0.INIT_RAM_00=256'hBB6B6EB6DDB6BAEBB5ADADAB66CEAADAB5AD6BB5B6EEB7D6FAEF6EBBB576B559;
defparam bram_rom_0.INIT_RAM_01=256'hCEAAA655318CA51A4AA64D4CD666D6B6B5CF5B5D9D76ADB56D6AD6B59CEB56DA;
defparam bram_rom_0.INIT_RAM_02=256'h99665AAAB335A5B2B34D4D553334ACCAD5596D6B6B6EEB6FB7776F76EDD75D6A;
defparam bram_rom_0.INIT_RAM_03=256'hD2AA4A2A288A14505148528A8A5529A54D4D2CCAC9A9952A99315528D29952AA;
defparam bram_rom_0.INIT_RAM_04=256'hA6CD5AAB6AD56B95B2D669AAB32D2D4D959B55AD9DB5DAF5EB7AEEDADDAD66CC;
defparam bram_rom_0.INIT_RAM_05=256'h2A45249121124212244852492A525554B32CB4B5354D534CAA9994CCAA669669;
defparam bram_rom_0.INIT_RAM_06=256'h14A9254A5495295152928C52294522949494A995333959B36AE6ADAB55A99A65;
defparam bram_rom_0.INIT_RAM_07=256'h554CA44A85052412224490A48A89519498CA8CA9514A8C922944A22A22914549;
defparam bram_rom_0.INIT_RAM_08=256'h5ADBADD6EBAEDAED6E75B36D5AD59B5AB5756D6DBB6BBBD6F776DEDBADD5B36A;
defparam bram_rom_0.INIT_RAM_09=256'hD669AA54CA92A4AA4AA634D5359B35D6AEBADB5B75AEADB3ABAAD6B56CEADAD7;
defparam bram_rom_0.INIT_RAM_0A=256'h666965B2ACD659ACB3354D54CD3332ACD555B36B6AF6DBB776FB6F76EDBAED5C;
defparam bram_rom_0.INIT_RAM_0B=256'h52A9894A429222489144A15252552996534B4CB2C9A693525549A4A552694CAA;
defparam bram_rom_0.INIT_RAM_0C=256'hAAAB6AAB67556B65AD359AAAB2D2CD35956CB6AD6DB5D776BBBAF5BB5DAD5ACB;
defparam bram_rom_0.INIT_RAM_0D=256'hCA29250522221214424492492A4A9554B2CB3335354D4D332A99934B2A66956A;
defparam bram_rom_0.INIT_RAM_0E=256'h24C4A94A8AA5293252929154452914A294552995334D96AD6ADAB36D55A69A64;
defparam bram_rom_0.INIT_RAM_0F=256'hA552A28A8490A222222890A48A4A5254954995252A92525191249429249228A9;
defparam bram_rom_0.INIT_RAM_10=256'h575CF5D6DDB5BB6D6DB5AD6D57556B5AB56DAD6DBB6B7DBB6EFAEDBD76ADD555;
defparam bram_rom_0.INIT_RAM_11=256'h5669A6652A92952A4AA554D4D56AD6B5CEB75AEBAD75B5B56CEB55D56B9ADABB;
defparam bram_rom_0.INIT_RAM_12=256'h6665A69B2B5599ACACD54D53354B2B2B5555AD6AED6ED7D776FAFAEF5ED75B6B;
defparam bram_rom_0.INIT_RAM_13=256'hB4A95229485212889144928A4A9526964D34CCAB3269554C553292A952694ACA;
defparam bram_rom_0.INIT_RAM_14=256'h9AB559AD9AB66B56B2D56AAAACCCCD355672B6756DB5BB75DBBAEEBB5DAB6ACC;
defparam bram_rom_0.INIT_RAM_15=256'hC9462490A2212221444492492952955332B33333554D34D32AA5554B26A665A6;
defparam bram_rom_0.INIT_RAM_16=256'h2515294A529926328A5491524A24A46494552964CD4D96AD96EAAD6D556AA5A4;
defparam bram_rom_0.INIT_RAM_17=256'h955292A22511121242448924524A5252A54A54A64952928A49289429425248A9;
defparam bram_rom_0.INIT_RAM_18=256'h56ED5ED5EDAED76B76AD6DAD5AB69B56D56E5DADD6DED7B7776EEEDB75CEAD5A;
defparam bram_rom_0.INIT_RAM_19=256'h55A99A95299498A95299552D556ABAB5B5DAD76BABB5B5ADAD5B36D56B6AD9DB;
defparam bram_rom_0.INIT_RAM_1A=256'hA659A66ACCD566AB2CD5354D4CCCCCB2D356AD5D5D6EBBBB76FAF76EEED75B5D;
defparam bram_rom_0.INIT_RAM_1B=256'h34A9514944914244A14492515462AA98D533334AAAA6554A954A54A652693326;
defparam bram_rom_0.INIT_RAM_1C=256'hAAB559756AB5AB56AB55A5ACACCCB4D5566CB673ADAEBB75D7DB5DDAEDAB6AB3;
defparam bram_rom_0.INIT_RAM_1D=256'h49454849212411281248922A2A31A552CCCAD2D4D3554D2CACA555349A9A65A5;
defparam bram_rom_0.INIT_RAM_1E=256'h95252949926926324C5491523129149454A31A93533565CD6ABAB5AB36672955;
defparam bram_rom_0.INIT_RAM_1F=256'hA53494542510A1412444512292514A92994994A92A52925189289250A2A12948;
defparam bram_rom_0.INIT_RAM_20=256'h5B5BADB75BB6D76B75AEAB755AB5AAEAADADAB75BADED7AFB76EF5BBB5B9AD59;
defparam bram_rom_0.INIT_RAM_21=256'hE5A69A592A8AA52652A553355596DAB5B5D7575D7575AEAD755AD6D56B5B5AB7;
defparam bram_rom_0.INIT_RAM_22=256'h9A596AA6AD555AAACD3355354CCCB32D2D599DAB5B76BBD6FAF7776F5DDAEB6A;
defparam bram_rom_0.INIT_RAM_23=256'h34A6324A24541444A1288A924A94AA9555332D32AA9A5549A54994A592955326;
defparam bram_rom_0.INIT_RAM_24=256'hAACB66B35B366ADAAAE59A9ACCCB335555AB35B56D75DB6EDBB75EDB6B6BAAB3;
defparam bram_rom_0.INIT_RAM_25=256'h4945288A1121422222451229512A9952CB332CCD54D4D4D31AA955331A9A5996;
defparam bram_rom_0.INIT_RAM_26=256'hA525294954A4AA318C54544951252494549529554CD595B3AAD676AAD969AA55;
defparam bram_rom_0.INIT_RAM_27=256'h165292924889212412844A244A8A4A92A52A93262A8A54524545214922924544;
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* Data_ROM */

module Top (
  SYM_CLK,
  SW1,
  KEY1,
  out_pdm_sclk,
  out_pcm_sync,
  out_pcm_valid,
  out_pcm_data
)
;
input SYM_CLK ;
input SW1 ;
input KEY1 ;
output out_pdm_sclk ;
output out_pcm_sync ;
output out_pcm_valid ;
output [23:0] out_pcm_data ;
wire SYM_CLK ;
wire SW1 ;
wire KEY1 ;
wire out_pdm_sclk ;
wire out_pcm_sync ;
wire out_pcm_valid ;
wire [6:0] pdm_valid_d;
wire [3:0] in_pdm_data;
wire [13:0] drom_addr;
wire [11:0] cnt_addr;
wire [1:0] cnt_chn_d1;
wire [1:0] cnt_chn_d0;
wire [1:0] cnt_chn;
wire [11:0] cnt_addr_4;
wire [1:1] SUM;
wire [23:0] out_pcm_data_c;
wire [3:0] in_pdm_datace;
wire un1_KEY1_1 ;
wire drom_out ;
wire onboard_en ;
wire GND ;
wire restart ;
wire pdm_sclk_r1 ;
wire VCC ;
wire pdm_sclk_r0 ;
wire restart9 ;
wire pstart_dxn ;
wire pdm_sclk_posedge ;
wire pstart_dxn_0_sqmuxa ;
wire restart5 ;
wire cnt_addr_1_sqmuxa ;
wire cnt_addr13 ;
wire SYM_CLK_c ;
wire SW1_c ;
wire KEY1_c ;
wire out_pdm_sclk_c ;
wire out_pcm_sync_c ;
wire out_pcm_valid_c ;
wire un1_cnt_addr_11_cry_0_0_SUM ;
wire un1_cnt_addr_11_cry_1_0_SUM ;
wire un1_cnt_addr_11_cry_2_0_SUM ;
wire un1_cnt_addr_11_cry_3_0_SUM ;
wire un1_cnt_addr_11_cry_4_0_SUM ;
wire un1_cnt_addr_11_cry_5_0_SUM ;
wire un1_cnt_addr_11_cry_6_0_SUM ;
wire un1_cnt_addr_11_cry_7_0_SUM ;
wire un1_cnt_addr_11_cry_8_0_SUM ;
wire un1_cnt_addr_11_cry_9_0_SUM ;
wire un1_cnt_addr_11_cry_10_0_SUM ;
wire un1_cnt_addr_11_s_11_0_SUM ;
wire un1_cnt_addr_11_cry_0 ;
wire un1_cnt_addr_11_cry_1 ;
wire un1_cnt_addr_11_cry_2 ;
wire un1_cnt_addr_11_cry_3 ;
wire un1_cnt_addr_11_cry_4 ;
wire un1_cnt_addr_11_cry_5 ;
wire un1_cnt_addr_11_cry_6 ;
wire un1_cnt_addr_11_cry_7 ;
wire un1_cnt_addr_11_cry_8 ;
wire un1_cnt_addr_11_cry_9 ;
wire un1_cnt_addr_11_cry_10 ;
wire KEY1_c_i ;
wire N_36_i ;
wire restart5_6 ;
wire restart5_7 ;
wire restart5_8 ;
wire restart5_9 ;
wire pstart_dxn_0_sqmuxa_7 ;
wire pstart_dxn_0_sqmuxa_8 ;
wire cnt_addr13_6 ;
wire cnt_addr13_7 ;
wire cnt_addr13_8 ;
wire pstart_dxn_0_sqmuxa_1 ;
wire un1_cnt_addr_11_s_11_0_COUT ;
// @6:120
  INV KEY1_c_i_cZ (
	.I(KEY1_c),
	.O(KEY1_c_i)
);
// @6:121
  LUT3 \cnt_addr_4_cZ[11]  (
	.I0(un1_cnt_addr_11_s_11_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[11])
);
defparam \cnt_addr_4_cZ[11] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[0]  (
	.I0(un1_cnt_addr_11_cry_0_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[0])
);
defparam \cnt_addr_4_cZ[0] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[1]  (
	.I0(un1_cnt_addr_11_cry_1_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[1])
);
defparam \cnt_addr_4_cZ[1] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[2]  (
	.I0(un1_cnt_addr_11_cry_2_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[2])
);
defparam \cnt_addr_4_cZ[2] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[3]  (
	.I0(un1_cnt_addr_11_cry_3_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[3])
);
defparam \cnt_addr_4_cZ[3] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[4]  (
	.I0(un1_cnt_addr_11_cry_4_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[4])
);
defparam \cnt_addr_4_cZ[4] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[5]  (
	.I0(un1_cnt_addr_11_cry_5_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[5])
);
defparam \cnt_addr_4_cZ[5] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[6]  (
	.I0(un1_cnt_addr_11_cry_6_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[6])
);
defparam \cnt_addr_4_cZ[6] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[7]  (
	.I0(un1_cnt_addr_11_cry_7_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[7])
);
defparam \cnt_addr_4_cZ[7] .INIT=8'h2A;
// @6:121
  LUT3 \cnt_addr_4_cZ[8]  (
	.I0(un1_cnt_addr_11_cry_8_0_SUM),
	.I1(cnt_addr13),
	.I2(onboard_en),
	.F(cnt_addr_4[8])
);
defparam \cnt_addr_4_cZ[8] .INIT=8'h2A;
// @6:131
  LUT4 N_36_i_cZ (
	.I0(cnt_chn[0]),
	.I1(cnt_chn[1]),
	.I2(onboard_en),
	.I3(pdm_sclk_posedge),
	.F(N_36_i)
);
defparam N_36_i_cZ.INIT=16'h5ADA;
// @6:138
  LUT4 \SUM_cZ[1]  (
	.I0(cnt_chn[0]),
	.I1(cnt_chn[1]),
	.I2(onboard_en),
	.I3(pdm_sclk_posedge),
	.F(SUM[1])
);
defparam \SUM_cZ[1] .INIT=16'h6CEC;
// @6:125
  LUT3 cnt_addr_1_sqmuxa_cZ (
	.I0(cnt_addr13),
	.I1(onboard_en),
	.I2(pdm_sclk_posedge),
	.F(cnt_addr_1_sqmuxa)
);
defparam cnt_addr_1_sqmuxa_cZ.INIT=8'h40;
// @6:125
  LUT4 cnt_addr13_cZ (
	.I0(cnt_addr13_6),
	.I1(cnt_addr13_7),
	.I2(cnt_addr13_8),
	.I3(pdm_sclk_posedge),
	.F(cnt_addr13)
);
defparam cnt_addr13_cZ.INIT=16'h8000;
// @6:113
  LUT4 restart5_cZ (
	.I0(restart5_6),
	.I1(restart5_7),
	.I2(restart5_8),
	.I3(restart5_9),
	.F(restart5)
);
defparam restart5_cZ.INIT=16'h8000;
// @6:175
  LUT3 \in_pdm_datace_cZ[3]  (
	.I0(cnt_chn_d1[0]),
	.I1(cnt_chn_d1[1]),
	.I2(onboard_en),
	.F(in_pdm_datace[3])
);
defparam \in_pdm_datace_cZ[3] .INIT=8'h80;
// @6:175
  LUT3 \in_pdm_datace_cZ[2]  (
	.I0(cnt_chn_d1[0]),
	.I1(cnt_chn_d1[1]),
	.I2(onboard_en),
	.F(in_pdm_datace[2])
);
defparam \in_pdm_datace_cZ[2] .INIT=8'h40;
// @6:175
  LUT3 \in_pdm_datace_cZ[1]  (
	.I0(cnt_chn_d1[0]),
	.I1(cnt_chn_d1[1]),
	.I2(onboard_en),
	.F(in_pdm_datace[1])
);
defparam \in_pdm_datace_cZ[1] .INIT=8'h20;
// @6:175
  LUT3 \in_pdm_datace_cZ[0]  (
	.I0(cnt_chn_d1[0]),
	.I1(cnt_chn_d1[1]),
	.I2(onboard_en),
	.F(in_pdm_datace[0])
);
defparam \in_pdm_datace_cZ[0] .INIT=8'h10;
// @6:113
  LUT4 restart5_7_cZ (
	.I0(drom_addr[3]),
	.I1(drom_addr[6]),
	.I2(drom_addr[10]),
	.I3(drom_addr[13]),
	.F(restart5_7)
);
defparam restart5_7_cZ.INIT=16'h0001;
// @6:113
  LUT4 restart5_8_cZ (
	.I0(drom_addr[1]),
	.I1(drom_addr[4]),
	.I2(drom_addr[5]),
	.I3(drom_addr[7]),
	.F(restart5_8)
);
defparam restart5_8_cZ.INIT=16'h0001;
// @6:113
  LUT4 restart5_9_cZ (
	.I0(drom_addr[8]),
	.I1(drom_addr[9]),
	.I2(drom_addr[11]),
	.I3(drom_addr[12]),
	.F(restart5_9)
);
defparam restart5_9_cZ.INIT=16'h0001;
// @6:106
  LUT4 pstart_dxn_0_sqmuxa_7_cZ (
	.I0(cnt_addr[3]),
	.I1(cnt_addr[4]),
	.I2(cnt_addr[5]),
	.I3(cnt_addr[11]),
	.F(pstart_dxn_0_sqmuxa_7)
);
defparam pstart_dxn_0_sqmuxa_7_cZ.INIT=16'h0001;
// @6:106
  LUT4 pstart_dxn_0_sqmuxa_8_cZ (
	.I0(cnt_addr[1]),
	.I1(cnt_addr[2]),
	.I2(cnt_addr[7]),
	.I3(cnt_addr[10]),
	.F(pstart_dxn_0_sqmuxa_8)
);
defparam pstart_dxn_0_sqmuxa_8_cZ.INIT=16'h0001;
// @6:125
  LUT4 cnt_addr13_6_cZ (
	.I0(cnt_addr[0]),
	.I1(cnt_addr[1]),
	.I2(cnt_addr[2]),
	.I3(cnt_addr[3]),
	.F(cnt_addr13_6)
);
defparam cnt_addr13_6_cZ.INIT=16'h8000;
// @6:125
  LUT4 cnt_addr13_7_cZ (
	.I0(cnt_addr[4]),
	.I1(cnt_addr[5]),
	.I2(cnt_addr[6]),
	.I3(cnt_addr[7]),
	.F(cnt_addr13_7)
);
defparam cnt_addr13_7_cZ.INIT=16'h8000;
// @6:125
  LUT4 cnt_addr13_8_cZ (
	.I0(cnt_addr[8]),
	.I1(cnt_addr[9]),
	.I2(cnt_addr[10]),
	.I3(cnt_addr[11]),
	.F(cnt_addr13_8)
);
defparam cnt_addr13_8_cZ.INIT=16'h0200;
// @6:112
  LUT2 restart9_cZ (
	.I0(onboard_en),
	.I1(pstart_dxn),
	.F(restart9)
);
defparam restart9_cZ.INIT=4'h8;
// @6:59
  LUT2 un1_KEY1_1_cZ (
	.I0(KEY1_c),
	.I1(restart),
	.F(un1_KEY1_1)
);
defparam un1_KEY1_1_cZ.INIT=4'h2;
// @6:98
  LUT2 pdm_sclk_posedge_cZ (
	.I0(pdm_sclk_r0),
	.I1(pdm_sclk_r1),
	.F(pdm_sclk_posedge)
);
defparam pdm_sclk_posedge_cZ.INIT=4'h2;
// @6:113
  LUT2 restart5_6_cZ (
	.I0(drom_addr[0]),
	.I1(drom_addr[2]),
	.F(restart5_6)
);
defparam restart5_6_cZ.INIT=4'h1;
// @6:106
  LUT4 pstart_dxn_0_sqmuxa_1_cZ (
	.I0(SW1_c),
	.I1(cnt_addr[0]),
	.I2(cnt_addr[6]),
	.I3(cnt_addr[8]),
	.F(pstart_dxn_0_sqmuxa_1)
);
defparam pstart_dxn_0_sqmuxa_1_cZ.INIT=16'h0008;
// @6:106
  LUT4 pstart_dxn_0_sqmuxa_cZ (
	.I0(cnt_addr[9]),
	.I1(pstart_dxn_0_sqmuxa_1),
	.I2(pstart_dxn_0_sqmuxa_7),
	.I3(pstart_dxn_0_sqmuxa_8),
	.F(pstart_dxn_0_sqmuxa)
);
defparam pstart_dxn_0_sqmuxa_cZ.INIT=16'h4000;
// @6:120
  DFFP \cnt_addr_Z[8]  (
	.Q(cnt_addr[8]),
	.D(cnt_addr_4[8]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[7]  (
	.Q(cnt_addr[7]),
	.D(cnt_addr_4[7]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[6]  (
	.Q(cnt_addr[6]),
	.D(cnt_addr_4[6]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[5]  (
	.Q(cnt_addr[5]),
	.D(cnt_addr_4[5]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[4]  (
	.Q(cnt_addr[4]),
	.D(cnt_addr_4[4]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[3]  (
	.Q(cnt_addr[3]),
	.D(cnt_addr_4[3]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[2]  (
	.Q(cnt_addr[2]),
	.D(cnt_addr_4[2]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[1]  (
	.Q(cnt_addr[1]),
	.D(cnt_addr_4[1]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[0]  (
	.Q(cnt_addr[0]),
	.D(cnt_addr_4[0]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:131
  DFFP \cnt_chn_Z[1]  (
	.Q(cnt_chn[1]),
	.D(SUM[1]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:131
  DFFP \cnt_chn_Z[0]  (
	.Q(cnt_chn[0]),
	.D(N_36_i),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFP \cnt_addr_Z[11]  (
	.Q(cnt_addr[11]),
	.D(cnt_addr_4[11]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i)
);
// @6:120
  DFFC \cnt_addr_Z[10]  (
	.Q(cnt_addr[10]),
	.D(un1_cnt_addr_11_cry_10_0_SUM),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i)
);
// @6:120
  DFFC \cnt_addr_Z[9]  (
	.Q(cnt_addr[9]),
	.D(un1_cnt_addr_11_cry_9_0_SUM),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i)
);
// @6:88
  DFFCE pdm_sclk_r1_Z (
	.Q(pdm_sclk_r1),
	.D(pdm_sclk_r0),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:164
  DFFCE \cnt_chn_d1_Z[1]  (
	.Q(cnt_chn_d1[1]),
	.D(cnt_chn_d0[1]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:164
  DFFCE \cnt_chn_d1_Z[0]  (
	.Q(cnt_chn_d1[0]),
	.D(cnt_chn_d0[0]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:80
  DFFCE onboard_en_Z (
	.Q(onboard_en),
	.D(VCC),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(SW1_c)
);
// @6:88
  DFFCE pdm_sclk_r0_Z (
	.Q(pdm_sclk_r0),
	.D(out_pdm_sclk_c),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[13]  (
	.Q(drom_addr[13]),
	.D(cnt_addr[11]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFCE \drom_addr_Z[12]  (
	.Q(drom_addr[12]),
	.D(cnt_addr[10]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFCE \drom_addr_Z[11]  (
	.Q(drom_addr[11]),
	.D(cnt_addr[9]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[10]  (
	.Q(drom_addr[10]),
	.D(cnt_addr[8]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[9]  (
	.Q(drom_addr[9]),
	.D(cnt_addr[7]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[8]  (
	.Q(drom_addr[8]),
	.D(cnt_addr[6]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[7]  (
	.Q(drom_addr[7]),
	.D(cnt_addr[5]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[6]  (
	.Q(drom_addr[6]),
	.D(cnt_addr[4]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[5]  (
	.Q(drom_addr[5]),
	.D(cnt_addr[3]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[4]  (
	.Q(drom_addr[4]),
	.D(cnt_addr[2]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[3]  (
	.Q(drom_addr[3]),
	.D(cnt_addr[1]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[2]  (
	.Q(drom_addr[2]),
	.D(cnt_addr[0]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[1]  (
	.Q(drom_addr[1]),
	.D(cnt_chn[1]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:143
  DFFPE \drom_addr_Z[0]  (
	.Q(drom_addr[0]),
	.D(cnt_chn[0]),
	.CLK(SYM_CLK_c),
	.PRESET(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[6]  (
	.Q(pdm_valid_d[6]),
	.D(pdm_valid_d[5]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[5]  (
	.Q(pdm_valid_d[5]),
	.D(pdm_valid_d[4]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[4]  (
	.Q(pdm_valid_d[4]),
	.D(pdm_valid_d[3]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[3]  (
	.Q(pdm_valid_d[3]),
	.D(pdm_valid_d[2]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[2]  (
	.Q(pdm_valid_d[2]),
	.D(pdm_valid_d[1]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[1]  (
	.Q(pdm_valid_d[1]),
	.D(pdm_valid_d[0]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:183
  DFFCE \pdm_valid_d_Z[0]  (
	.Q(pdm_valid_d[0]),
	.D(pdm_sclk_posedge),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:101
  DFFCE pstart_dxn_Z (
	.Q(pstart_dxn),
	.D(VCC),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(pstart_dxn_0_sqmuxa)
);
// @6:110
  DFFCE restart_Z (
	.Q(restart),
	.D(restart5),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(restart9)
);
// @6:175
  DFFCE \in_pdm_data_Z[3]  (
	.Q(in_pdm_data[3]),
	.D(drom_out),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(in_pdm_datace[3])
);
// @6:175
  DFFCE \in_pdm_data_Z[2]  (
	.Q(in_pdm_data[2]),
	.D(drom_out),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(in_pdm_datace[2])
);
// @6:175
  DFFCE \in_pdm_data_Z[1]  (
	.Q(in_pdm_data[1]),
	.D(drom_out),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(in_pdm_datace[1])
);
// @6:175
  DFFCE \in_pdm_data_Z[0]  (
	.Q(in_pdm_data[0]),
	.D(drom_out),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(in_pdm_datace[0])
);
// @6:164
  DFFCE \cnt_chn_d0_Z[1]  (
	.Q(cnt_chn_d0[1]),
	.D(cnt_chn[1]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:164
  DFFCE \cnt_chn_d0_Z[0]  (
	.Q(cnt_chn_d0[0]),
	.D(cnt_chn[0]),
	.CLK(SYM_CLK_c),
	.CLEAR(KEY1_c_i),
	.CE(onboard_en)
);
// @6:2
  IBUF SYM_CLK_ibuf (
	.O(SYM_CLK_c),
	.I(SYM_CLK)
);
// @6:3
  IBUF SW1_ibuf (
	.O(SW1_c),
	.I(SW1)
);
// @6:4
  IBUF KEY1_ibuf (
	.O(KEY1_c),
	.I(KEY1)
);
// @6:5
  OBUF out_pdm_sclk_obuf (
	.O(out_pdm_sclk),
	.I(out_pdm_sclk_c)
);
// @6:6
  OBUF out_pcm_sync_obuf (
	.O(out_pcm_sync),
	.I(out_pcm_sync_c)
);
// @6:7
  OBUF out_pcm_valid_obuf (
	.O(out_pcm_valid),
	.I(out_pcm_valid_c)
);
// @6:8
  OBUF \out_pcm_data_obuf[0]  (
	.O(out_pcm_data[0]),
	.I(out_pcm_data_c[0])
);
// @6:8
  OBUF \out_pcm_data_obuf[1]  (
	.O(out_pcm_data[1]),
	.I(out_pcm_data_c[1])
);
// @6:8
  OBUF \out_pcm_data_obuf[2]  (
	.O(out_pcm_data[2]),
	.I(out_pcm_data_c[2])
);
// @6:8
  OBUF \out_pcm_data_obuf[3]  (
	.O(out_pcm_data[3]),
	.I(out_pcm_data_c[3])
);
// @6:8
  OBUF \out_pcm_data_obuf[4]  (
	.O(out_pcm_data[4]),
	.I(out_pcm_data_c[4])
);
// @6:8
  OBUF \out_pcm_data_obuf[5]  (
	.O(out_pcm_data[5]),
	.I(out_pcm_data_c[5])
);
// @6:8
  OBUF \out_pcm_data_obuf[6]  (
	.O(out_pcm_data[6]),
	.I(out_pcm_data_c[6])
);
// @6:8
  OBUF \out_pcm_data_obuf[7]  (
	.O(out_pcm_data[7]),
	.I(out_pcm_data_c[7])
);
// @6:8
  OBUF \out_pcm_data_obuf[8]  (
	.O(out_pcm_data[8]),
	.I(out_pcm_data_c[8])
);
// @6:8
  OBUF \out_pcm_data_obuf[9]  (
	.O(out_pcm_data[9]),
	.I(out_pcm_data_c[9])
);
// @6:8
  OBUF \out_pcm_data_obuf[10]  (
	.O(out_pcm_data[10]),
	.I(out_pcm_data_c[10])
);
// @6:8
  OBUF \out_pcm_data_obuf[11]  (
	.O(out_pcm_data[11]),
	.I(out_pcm_data_c[11])
);
// @6:8
  OBUF \out_pcm_data_obuf[12]  (
	.O(out_pcm_data[12]),
	.I(out_pcm_data_c[12])
);
// @6:8
  OBUF \out_pcm_data_obuf[13]  (
	.O(out_pcm_data[13]),
	.I(out_pcm_data_c[13])
);
// @6:8
  OBUF \out_pcm_data_obuf[14]  (
	.O(out_pcm_data[14]),
	.I(out_pcm_data_c[14])
);
// @6:8
  OBUF \out_pcm_data_obuf[15]  (
	.O(out_pcm_data[15]),
	.I(out_pcm_data_c[15])
);
// @6:8
  OBUF \out_pcm_data_obuf[16]  (
	.O(out_pcm_data[16]),
	.I(out_pcm_data_c[16])
);
// @6:8
  OBUF \out_pcm_data_obuf[17]  (
	.O(out_pcm_data[17]),
	.I(out_pcm_data_c[17])
);
// @6:8
  OBUF \out_pcm_data_obuf[18]  (
	.O(out_pcm_data[18]),
	.I(out_pcm_data_c[18])
);
// @6:8
  OBUF \out_pcm_data_obuf[19]  (
	.O(out_pcm_data[19]),
	.I(out_pcm_data_c[19])
);
// @6:8
  OBUF \out_pcm_data_obuf[20]  (
	.O(out_pcm_data[20]),
	.I(out_pcm_data_c[20])
);
// @6:8
  OBUF \out_pcm_data_obuf[21]  (
	.O(out_pcm_data[21]),
	.I(out_pcm_data_c[21])
);
// @6:8
  OBUF \out_pcm_data_obuf[22]  (
	.O(out_pcm_data[22]),
	.I(out_pcm_data_c[22])
);
// @6:8
  OBUF \out_pcm_data_obuf[23]  (
	.O(out_pcm_data[23]),
	.I(out_pcm_data_c[23])
);
// @6:126
  ALU un1_cnt_addr_11_s_11_0 (
	.CIN(un1_cnt_addr_11_cry_10),
	.I0(cnt_addr[11]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_s_11_0_COUT),
	.SUM(un1_cnt_addr_11_s_11_0_SUM)
);
defparam un1_cnt_addr_11_s_11_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_10_0 (
	.CIN(un1_cnt_addr_11_cry_9),
	.I0(cnt_addr[10]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_10),
	.SUM(un1_cnt_addr_11_cry_10_0_SUM)
);
defparam un1_cnt_addr_11_cry_10_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_9_0 (
	.CIN(un1_cnt_addr_11_cry_8),
	.I0(cnt_addr[9]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_9),
	.SUM(un1_cnt_addr_11_cry_9_0_SUM)
);
defparam un1_cnt_addr_11_cry_9_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_8_0 (
	.CIN(un1_cnt_addr_11_cry_7),
	.I0(cnt_addr[8]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_8),
	.SUM(un1_cnt_addr_11_cry_8_0_SUM)
);
defparam un1_cnt_addr_11_cry_8_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_7_0 (
	.CIN(un1_cnt_addr_11_cry_6),
	.I0(cnt_addr[7]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_7),
	.SUM(un1_cnt_addr_11_cry_7_0_SUM)
);
defparam un1_cnt_addr_11_cry_7_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_6_0 (
	.CIN(un1_cnt_addr_11_cry_5),
	.I0(cnt_addr[6]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_6),
	.SUM(un1_cnt_addr_11_cry_6_0_SUM)
);
defparam un1_cnt_addr_11_cry_6_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_5_0 (
	.CIN(un1_cnt_addr_11_cry_4),
	.I0(cnt_addr[5]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_5),
	.SUM(un1_cnt_addr_11_cry_5_0_SUM)
);
defparam un1_cnt_addr_11_cry_5_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_4_0 (
	.CIN(un1_cnt_addr_11_cry_3),
	.I0(cnt_addr[4]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_4),
	.SUM(un1_cnt_addr_11_cry_4_0_SUM)
);
defparam un1_cnt_addr_11_cry_4_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_3_0 (
	.CIN(un1_cnt_addr_11_cry_2),
	.I0(cnt_addr[3]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_3),
	.SUM(un1_cnt_addr_11_cry_3_0_SUM)
);
defparam un1_cnt_addr_11_cry_3_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_2_0 (
	.CIN(un1_cnt_addr_11_cry_1),
	.I0(cnt_addr[2]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_2),
	.SUM(un1_cnt_addr_11_cry_2_0_SUM)
);
defparam un1_cnt_addr_11_cry_2_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_1_0 (
	.CIN(un1_cnt_addr_11_cry_0),
	.I0(cnt_addr[1]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_1),
	.SUM(un1_cnt_addr_11_cry_1_0_SUM)
);
defparam un1_cnt_addr_11_cry_1_0.ALU_MODE=0;
// @6:126
  ALU un1_cnt_addr_11_cry_0_0 (
	.CIN(cnt_addr_1_sqmuxa),
	.I0(cnt_addr[0]),
	.I1(GND),
	.I3(GND),
	.COUT(un1_cnt_addr_11_cry_0),
	.SUM(un1_cnt_addr_11_cry_0_0_SUM)
);
defparam un1_cnt_addr_11_cry_0_0.ALU_MODE=0;
// @6:57
  PDM2PCM_Top PDM2PCM_Top (
	.out_pcm_data_c(out_pcm_data_c[23:0]),
	.in_pdm_data(in_pdm_data[3:0]),
	.pdm_valid_d_0(pdm_valid_d[6]),
	.out_pcm_sync_c(out_pcm_sync_c),
	.out_pcm_valid_c(out_pcm_valid_c),
	.out_pdm_sclk_c(out_pdm_sclk_c),
	.SW1_c(SW1_c),
	.un1_KEY1_1(un1_KEY1_1),
	.SYM_CLK_c(SYM_CLK_c)
);
// @6:153
  Data_ROM data_rom (
	.drom_addr(drom_addr[13:0]),
	.KEY1_c_i(KEY1_c_i),
	.onboard_en(onboard_en),
	.SYM_CLK_c(SYM_CLK_c),
	.drom_out(drom_out)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* Top */

