Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\myWork\IP\releaseVerify\V1.9.7.02\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\Top.v E:\myWork\IP\releaseVerify\V1.9.7.02\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\clk_div_even.v E:\myWork\IP\releaseVerify\V1.9.7.02\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\data_prom.v E:\myWork\IP\releaseVerify\V1.9.7.02\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm.v
GowinSynthesis Constraints File	---
GowinSynthesis Version	GowinSynthesis V1.9.7.02Beta
Part Number	GW1N-LV9LQ144C6/I5
Device	GW1N-9
Created Time	Wed Mar 03 17:11:40 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	Top
Synthesis Process	Running parser: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 1s, Peak memory usage = 143.727MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 143.727MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 143.727MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 143.727MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 143.727MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 143.727MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 143.727MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 143.727MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 143.727MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 143.727MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 143.727MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 148.410MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 148.410MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 148.410MB
Total Time and Memory Usage	CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 148.410MB

Resource

Resource Usage Summary

I/O Port	21
I/O Buf	21
IBUF	3
OBUF	18
Register	2574
DFFE	1
DFFP	11
DFFPE	72
DFFC	2
DFFCE	2488
LUT	1683
LUT2	143
LUT3	784
LUT4	756
ALU	1008
ALU	1008
SSRAM	14
RAM16S4	10
RAM16SDP4	4
INV	7
INV	7
DSP	2
MULT18X18	2
BSRAM	3
SDPX9B	2
pROM	1

Resource Utilization Summary

Logic	2782(1690 LUTs, 1008 ALUs, 14 SSRAMs) / 8640	32%
Register	2574 / 6843	38%
--Register as Latch	0 / 6843	0%
--Register as FF	2574 / 6843	38%
BSRAM	3 / 26	12%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
SYM_CLK	Base	10.000	100.0	0.000	5.000			SYM_CLK_ibuf/I

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	SYM_CLK	100.0(MHz)	111.7(MHz)	8	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	1.050
Data Arrival Time	9.895
Data Required Time	10.945
From	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0
Launch Clk	SYM_CLK[R]
Latch Clk	SYM_CLK[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				SYM_CLK
0.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
0.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
1.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.803	0.458	tC2Q	RF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
2.283	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
3.382	1.099	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/F
3.862	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
4.011	0.149	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/O
4.491	0.480	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/I0
5.449	0.958	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
5.449	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
5.506	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
5.506	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
5.563	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
5.563	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
5.620	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
5.620	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
5.677	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
5.677	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
5.734	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
5.734	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
5.791	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
5.791	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
5.848	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
5.848	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
5.905	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
5.905	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
5.962	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
5.962	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
6.019	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
6.019	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
6.076	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
6.076	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
6.133	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
6.133	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
6.190	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
6.190	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
6.247	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
6.247	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
6.304	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
6.304	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
6.361	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
6.361	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
6.418	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
6.418	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
6.475	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
6.475	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
6.532	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
6.532	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
6.589	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
6.589	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
6.646	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
6.646	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
6.703	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
6.703	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
6.760	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
6.760	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
6.817	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
6.817	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
6.874	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
6.874	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
6.931	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
6.931	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
6.988	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
6.988	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
7.045	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
7.045	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
7.102	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
7.102	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
7.159	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
7.159	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
7.216	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
7.216	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
7.273	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
7.273	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
7.836	0.563	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
8.316	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
9.415	1.099	tINS	FF	4	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/F
9.895	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				SYM_CLK
10.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
10.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
11.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0/CLK
10.945	-0.400	tSu		1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 5.692, 66.570%; route: 2.400, 28.069%; tC2Q: 0.458, 5.360%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:

Slack	1.050
Data Arrival Time	9.895
Data Required Time	10.945
From	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0
Launch Clk	SYM_CLK[R]
Latch Clk	SYM_CLK[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				SYM_CLK
0.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
0.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
1.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.803	0.458	tC2Q	RF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
2.283	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
3.382	1.099	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/F
3.862	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
4.011	0.149	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/O
4.491	0.480	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/I0
5.449	0.958	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
5.449	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
5.506	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
5.506	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
5.563	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
5.563	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
5.620	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
5.620	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
5.677	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
5.677	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
5.734	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
5.734	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
5.791	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
5.791	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
5.848	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
5.848	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
5.905	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
5.905	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
5.962	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
5.962	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
6.019	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
6.019	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
6.076	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
6.076	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
6.133	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
6.133	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
6.190	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
6.190	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
6.247	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
6.247	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
6.304	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
6.304	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
6.361	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
6.361	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
6.418	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
6.418	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
6.475	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
6.475	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
6.532	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
6.532	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
6.589	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
6.589	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
6.646	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
6.646	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
6.703	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
6.703	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
6.760	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
6.760	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
6.817	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
6.817	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
6.874	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
6.874	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
6.931	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
6.931	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
6.988	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
6.988	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
7.045	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
7.045	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
7.102	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
7.102	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
7.159	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
7.159	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
7.216	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
7.216	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
7.273	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
7.273	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
7.836	0.563	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
8.316	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
9.415	1.099	tINS	FF	4	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/F
9.895	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				SYM_CLK
10.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
10.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
11.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0/CLK
10.945	-0.400	tSu		1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 5.692, 66.570%; route: 2.400, 28.069%; tC2Q: 0.458, 5.360%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:

Slack	1.050
Data Arrival Time	9.895
Data Required Time	10.945
From	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0
Launch Clk	SYM_CLK[R]
Latch Clk	SYM_CLK[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				SYM_CLK
0.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
0.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
1.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.803	0.458	tC2Q	RF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
2.283	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
3.382	1.099	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/F
3.862	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
4.011	0.149	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/O
4.491	0.480	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/I0
5.449	0.958	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
5.449	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
5.506	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
5.506	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
5.563	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
5.563	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
5.620	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
5.620	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
5.677	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
5.677	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
5.734	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
5.734	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
5.791	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
5.791	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
5.848	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
5.848	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
5.905	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
5.905	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
5.962	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
5.962	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
6.019	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
6.019	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
6.076	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
6.076	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
6.133	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
6.133	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
6.190	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
6.190	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
6.247	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
6.247	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
6.304	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
6.304	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
6.361	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
6.361	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
6.418	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
6.418	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
6.475	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
6.475	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
6.532	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
6.532	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
6.589	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
6.589	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
6.646	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
6.646	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
6.703	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
6.703	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
6.760	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
6.760	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
6.817	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
6.817	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
6.874	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
6.874	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
6.931	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
6.931	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
6.988	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
6.988	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
7.045	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
7.045	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
7.102	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
7.102	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
7.159	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
7.159	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
7.216	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
7.216	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
7.273	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
7.273	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
7.836	0.563	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
8.316	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
9.415	1.099	tINS	FF	4	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/F
9.895	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				SYM_CLK
10.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
10.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
11.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0/CLK
10.945	-0.400	tSu		1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 5.692, 66.570%; route: 2.400, 28.069%; tC2Q: 0.458, 5.360%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:

Slack	1.050
Data Arrival Time	9.895
Data Required Time	10.945
From	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0
Launch Clk	SYM_CLK[R]
Latch Clk	SYM_CLK[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				SYM_CLK
0.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
0.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
1.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.803	0.458	tC2Q	RF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
2.283	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
3.382	1.099	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s6/F
3.862	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
4.011	0.149	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1379_s5/O
4.491	0.480	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/I0
5.449	0.958	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
5.449	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
5.506	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
5.506	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
5.563	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
5.563	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
5.620	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
5.620	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
5.677	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
5.677	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
5.734	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
5.734	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
5.791	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
5.791	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
5.848	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
5.848	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
5.905	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
5.905	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
5.962	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
5.962	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
6.019	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
6.019	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
6.076	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
6.076	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
6.133	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
6.133	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
6.190	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
6.190	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
6.247	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
6.247	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
6.304	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
6.304	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
6.361	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
6.361	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
6.418	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
6.418	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
6.475	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
6.475	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
6.532	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
6.532	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
6.589	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
6.589	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
6.646	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
6.646	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
6.703	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
6.703	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
6.760	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
6.760	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
6.817	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
6.817	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
6.874	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
6.874	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
6.931	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
6.931	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
6.988	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
6.988	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
7.045	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
7.045	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
7.102	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
7.102	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
7.159	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
7.159	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
7.216	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
7.216	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
7.273	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
7.273	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
7.836	0.563	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
8.316	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
9.415	1.099	tINS	FF	4	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/n1716_s2/F
9.895	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				SYM_CLK
10.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
10.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
11.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0/CLK
10.945	-0.400	tSu		1	u_PDM2PCM_Top/u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 5.692, 66.570%; route: 2.400, 28.069%; tC2Q: 0.458, 5.360%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:

Slack	1.050
Data Arrival Time	9.895
Data Required Time	10.945
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0
Launch Clk	SYM_CLK[R]
Latch Clk	SYM_CLK[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				SYM_CLK
0.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
0.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
1.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0/CLK
1.803	0.458	tC2Q	RF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0/Q
2.283	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1379_s6/I1
3.382	1.099	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1379_s6/F
3.862	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1379_s5/I0
4.011	0.149	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1379_s5/O
4.491	0.480	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1416_s/I0
5.449	0.958	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1416_s/COUT
5.449	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1415_s/CIN
5.506	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1415_s/COUT
5.506	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1414_s/CIN
5.563	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1414_s/COUT
5.563	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1413_s/CIN
5.620	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1413_s/COUT
5.620	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1412_s/CIN
5.677	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1412_s/COUT
5.677	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1411_s/CIN
5.734	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1411_s/COUT
5.734	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1410_s/CIN
5.791	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1410_s/COUT
5.791	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1409_s/CIN
5.848	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1409_s/COUT
5.848	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1408_s/CIN
5.905	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1408_s/COUT
5.905	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1407_s/CIN
5.962	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1407_s/COUT
5.962	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1406_s/CIN
6.019	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1406_s/COUT
6.019	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1405_s/CIN
6.076	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1405_s/COUT
6.076	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1404_s/CIN
6.133	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1404_s/COUT
6.133	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1403_s/CIN
6.190	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1403_s/COUT
6.190	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1402_s/CIN
6.247	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1402_s/COUT
6.247	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1401_s/CIN
6.304	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1401_s/COUT
6.304	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1400_s/CIN
6.361	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1400_s/COUT
6.361	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1399_s/CIN
6.418	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1399_s/COUT
6.418	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1398_s/CIN
6.475	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1398_s/COUT
6.475	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1397_s/CIN
6.532	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1397_s/COUT
6.532	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1396_s/CIN
6.589	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1396_s/COUT
6.589	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1395_s/CIN
6.646	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1395_s/COUT
6.646	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1394_s/CIN
6.703	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1394_s/COUT
6.703	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1393_s/CIN
6.760	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1393_s/COUT
6.760	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1392_s/CIN
6.817	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1392_s/COUT
6.817	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1391_s/CIN
6.874	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1391_s/COUT
6.874	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1390_s/CIN
6.931	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1390_s/COUT
6.931	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1389_s/CIN
6.988	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1389_s/COUT
6.988	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1388_s/CIN
7.045	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1388_s/COUT
7.045	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1387_s/CIN
7.102	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1387_s/COUT
7.102	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1386_s/CIN
7.159	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1386_s/COUT
7.159	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1385_s/CIN
7.216	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1385_s/COUT
7.216	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1384_s/CIN
7.273	0.057	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1384_s/COUT
7.273	0.000	tNET	FF	2	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1383_s/CIN
7.836	0.563	tINS	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1383_s/SUM
8.316	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1716_s2/I1
9.415	1.099	tINS	FF	4	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/n1716_s2/F
9.895	0.480	tNET	FF	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				SYM_CLK
10.000	0.000	tCL	RR	1	SYM_CLK_ibuf/I
10.982	0.982	tINS	RR	2595	SYM_CLK_ibuf/O
11.345	0.363	tNET	RR	1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0/CLK
10.945	-0.400	tSu		1	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 5.692, 66.570%; route: 2.400, 28.069%; tC2Q: 0.458, 5.360%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%