Project Settings
Project Name Ref_design Device Name rev_1: GOWIN-GW1N : GW1N_9
Implementation Name rev_1 Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 40 67 0 - 00m:11s - 9/7/2020
7:15:18 AM
(premap)Complete 12 1 0 0m:16s 0m:16s 239MB 9/7/2020
7:15:37 AM
(fpga_mapper)Canceled 1906 133 0 01m:16s 01m:22s 265MB 9/7/2020
7:17:00 AM

Area Summary
I/O ports (io_port) 30 Non I/O Register bits (non_io_reg) 270 (4%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 0 (26) Block Multipliers (dsp_used) 0 (10)
LUTs (total_luts) 271 (3%)

Timing Summary
Clock NameReq FreqEst FreqSlack
Gowin_PLL|clkout_inferred_clock108.0 MHz91.8 MHz-1.634
System100.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 1 / 0