Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.02Beta1_GowinSynthesis-only\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v
C:\Gowin\Gowin_V1.9.7.02Beta1_GowinSynthesis-only\IDE\ipcore\PDM2PCM\data\pdm2pcm.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta1
Created Time Mon Feb 08 09:30:19 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: PDM2PCM_Top
Part Number: GW2A-LV18PG256C8/I7
Device: GW2A-18

Resource

Resource Usage Summary

I/O Port 26
I/O Buf 26
    IBUF 8
    OBUF 18
Register 2556
    DFFE 1
    DFFP 10
    DFFPE 62
    DFFC 2
    DFFCE 2481
LUT 1659
    LUT2 138
    LUT3 777
    LUT4 744
ALU 1008
    ALU 1008
SSRAM 14
    RAM16S4 10
    RAM16SDP4 4
INV 6
    INV 6
DSP 2
    MULT18X18 2
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Logic 2757(1665 LUTs, 1008 ALUs, 14 SSRAMs) / 20736 13%
Register 2556 / 16173 16%
  --Register as Latch 0 / 16173 0%
  --Register as FF 2556 / 16173 16%
BSRAM 2 / 46 4%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 206.4(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.155
Data Arrival Time 5.638
Data Required Time 10.793
From u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.094 0.232 tC2Q RF 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
1.331 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
1.886 0.555 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/F
2.123 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
2.226 0.103 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/O
2.463 0.237 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1416_s/I0
3.012 0.549 tINS FR 1 u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
3.012 0 tNET RR 2 u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
3.047 0.035 tINS RF 1 u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
3.047 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
3.082 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
3.082 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
3.118 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
3.118 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
3.153 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
3.153 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
3.188 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
3.188 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
3.223 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
3.223 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
3.258 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
3.258 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
3.294 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
3.294 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
3.329 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
3.329 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
3.364 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
3.364 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
3.399 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
3.399 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
3.434 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
3.434 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
3.470 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
3.470 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
3.505 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
3.505 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
3.540 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
3.540 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
3.575 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
3.575 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
3.610 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
3.610 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
3.646 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
3.646 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
3.681 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
3.681 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
3.716 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
3.716 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
3.751 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
3.751 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
3.786 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
3.786 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
3.822 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
3.822 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
3.857 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
3.857 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
3.892 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
3.892 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
3.927 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
3.927 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
3.962 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
3.962 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
3.998 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
3.998 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
4.033 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
4.033 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
4.068 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
4.068 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
4.103 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
4.103 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
4.138 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
4.138 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
4.608 0.47 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
4.845 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
5.400 0.555 tINS FF 4 u_pdm2pcm/u1_cic_cmp/n1716_s2/F
5.637 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[3]_33_s0/CLK

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.358, 70.327%; route: 1.185, 24.815%; tC2Q: 0.232, 4.858%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 5.155
Data Arrival Time 5.638
Data Required Time 10.793
From u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.094 0.232 tC2Q RF 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
1.331 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
1.886 0.555 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/F
2.123 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
2.226 0.103 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/O
2.463 0.237 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1416_s/I0
3.012 0.549 tINS FR 1 u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
3.012 0 tNET RR 2 u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
3.047 0.035 tINS RF 1 u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
3.047 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
3.082 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
3.082 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
3.118 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
3.118 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
3.153 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
3.153 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
3.188 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
3.188 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
3.223 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
3.223 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
3.258 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
3.258 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
3.294 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
3.294 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
3.329 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
3.329 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
3.364 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
3.364 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
3.399 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
3.399 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
3.434 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
3.434 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
3.470 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
3.470 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
3.505 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
3.505 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
3.540 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
3.540 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
3.575 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
3.575 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
3.610 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
3.610 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
3.646 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
3.646 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
3.681 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
3.681 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
3.716 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
3.716 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
3.751 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
3.751 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
3.786 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
3.786 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
3.822 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
3.822 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
3.857 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
3.857 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
3.892 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
3.892 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
3.927 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
3.927 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
3.962 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
3.962 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
3.998 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
3.998 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
4.033 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
4.033 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
4.068 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
4.068 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
4.103 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
4.103 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
4.138 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
4.138 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
4.608 0.47 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
4.845 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
5.400 0.555 tINS FF 4 u_pdm2pcm/u1_cic_cmp/n1716_s2/F
5.637 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[2]_33_s0/CLK

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 6.717, 72.078%; route: 2.370, 25.432%; tC2Q: 0.232, 2.490%
Required Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%

Path 3

Path Summary:
Slack 5.155
Data Arrival Time 5.638
Data Required Time 10.793
From u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.094 0.232 tC2Q RF 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
1.331 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
1.886 0.555 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/F
2.123 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
2.226 0.103 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/O
2.463 0.237 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1416_s/I0
3.012 0.549 tINS FR 1 u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
3.012 0 tNET RR 2 u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
3.047 0.035 tINS RF 1 u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
3.047 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
3.082 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
3.082 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
3.118 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
3.118 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
3.153 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
3.153 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
3.188 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
3.188 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
3.223 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
3.223 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
3.258 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
3.258 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
3.294 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
3.294 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
3.329 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
3.329 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
3.364 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
3.364 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
3.399 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
3.399 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
3.434 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
3.434 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
3.470 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
3.470 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
3.505 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
3.505 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
3.540 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
3.540 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
3.575 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
3.575 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
3.610 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
3.610 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
3.646 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
3.646 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
3.681 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
3.681 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
3.716 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
3.716 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
3.751 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
3.751 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
3.786 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
3.786 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
3.822 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
3.822 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
3.857 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
3.857 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
3.892 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
3.892 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
3.927 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
3.927 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
3.962 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
3.962 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
3.998 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
3.998 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
4.033 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
4.033 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
4.068 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
4.068 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
4.103 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
4.103 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
4.138 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
4.138 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
4.608 0.47 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
4.845 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
5.400 0.555 tINS FF 4 u_pdm2pcm/u1_cic_cmp/n1716_s2/F
5.637 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_33_s0/CLK

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 10.075, 72.681%; route: 3.555, 25.645%; tC2Q: 0.232, 1.674%
Required Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%

Path 4

Path Summary:
Slack 5.155
Data Arrival Time 5.638
Data Required Time 10.793
From u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0
To u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/CLK
1.094 0.232 tC2Q RF 1 u_pdm2pcm/u1_cic_cmp/acc_out[1]_0_s0/Q
1.331 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/I1
1.886 0.555 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s6/F
2.123 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/I0
2.226 0.103 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1379_s5/O
2.463 0.237 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1416_s/I0
3.012 0.549 tINS FR 1 u_pdm2pcm/u1_cic_cmp/n1416_s/COUT
3.012 0 tNET RR 2 u_pdm2pcm/u1_cic_cmp/n1415_s/CIN
3.047 0.035 tINS RF 1 u_pdm2pcm/u1_cic_cmp/n1415_s/COUT
3.047 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1414_s/CIN
3.082 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1414_s/COUT
3.082 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1413_s/CIN
3.118 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1413_s/COUT
3.118 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1412_s/CIN
3.153 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1412_s/COUT
3.153 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1411_s/CIN
3.188 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1411_s/COUT
3.188 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1410_s/CIN
3.223 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1410_s/COUT
3.223 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1409_s/CIN
3.258 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1409_s/COUT
3.258 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1408_s/CIN
3.294 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1408_s/COUT
3.294 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1407_s/CIN
3.329 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1407_s/COUT
3.329 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1406_s/CIN
3.364 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1406_s/COUT
3.364 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1405_s/CIN
3.399 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1405_s/COUT
3.399 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1404_s/CIN
3.434 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1404_s/COUT
3.434 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1403_s/CIN
3.470 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1403_s/COUT
3.470 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1402_s/CIN
3.505 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1402_s/COUT
3.505 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1401_s/CIN
3.540 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1401_s/COUT
3.540 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1400_s/CIN
3.575 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1400_s/COUT
3.575 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1399_s/CIN
3.610 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1399_s/COUT
3.610 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1398_s/CIN
3.646 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1398_s/COUT
3.646 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1397_s/CIN
3.681 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1397_s/COUT
3.681 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1396_s/CIN
3.716 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1396_s/COUT
3.716 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1395_s/CIN
3.751 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1395_s/COUT
3.751 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1394_s/CIN
3.786 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1394_s/COUT
3.786 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1393_s/CIN
3.822 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1393_s/COUT
3.822 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1392_s/CIN
3.857 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1392_s/COUT
3.857 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1391_s/CIN
3.892 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1391_s/COUT
3.892 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1390_s/CIN
3.927 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1390_s/COUT
3.927 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1389_s/CIN
3.962 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1389_s/COUT
3.962 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1388_s/CIN
3.998 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1388_s/COUT
3.998 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1387_s/CIN
4.033 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1387_s/COUT
4.033 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1386_s/CIN
4.068 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1386_s/COUT
4.068 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1385_s/CIN
4.103 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1385_s/COUT
4.103 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1384_s/CIN
4.138 0.035 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1384_s/COUT
4.138 0 tNET FF 2 u_pdm2pcm/u1_cic_cmp/n1383_s/CIN
4.608 0.47 tINS FF 1 u_pdm2pcm/u1_cic_cmp/n1383_s/SUM
4.845 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/n1716_s2/I1
5.400 0.555 tINS FF 4 u_pdm2pcm/u1_cic_cmp/n1716_s2/F
5.637 0.237 tNET FF 1 u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u1_cic_cmp/acc_out[0]_33_s0/CLK

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 13.434, 72.987%; route: 4.740, 25.753%; tC2Q: 0.232, 1.260%
Required Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%

Path 5

Path Summary:
Slack 5.155
Data Arrival Time 5.638
Data Required Time 10.793
From u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0
To u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0
Launch Clk clk[R]
Latch Clk clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0/CLK
1.094 0.232 tC2Q RF 1 u_pdm2pcm/u0_cic_cmp/acc_out[1]_0_s0/Q
1.331 0.237 tNET FF 1 u_pdm2pcm/u0_cic_cmp/n1379_s6/I1
1.886 0.555 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1379_s6/F
2.123 0.237 tNET FF 1 u_pdm2pcm/u0_cic_cmp/n1379_s5/I0
2.226 0.103 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1379_s5/O
2.463 0.237 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1416_s/I0
3.012 0.549 tINS FR 1 u_pdm2pcm/u0_cic_cmp/n1416_s/COUT
3.012 0 tNET RR 2 u_pdm2pcm/u0_cic_cmp/n1415_s/CIN
3.047 0.035 tINS RF 1 u_pdm2pcm/u0_cic_cmp/n1415_s/COUT
3.047 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1414_s/CIN
3.082 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1414_s/COUT
3.082 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1413_s/CIN
3.118 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1413_s/COUT
3.118 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1412_s/CIN
3.153 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1412_s/COUT
3.153 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1411_s/CIN
3.188 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1411_s/COUT
3.188 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1410_s/CIN
3.223 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1410_s/COUT
3.223 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1409_s/CIN
3.258 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1409_s/COUT
3.258 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1408_s/CIN
3.294 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1408_s/COUT
3.294 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1407_s/CIN
3.329 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1407_s/COUT
3.329 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1406_s/CIN
3.364 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1406_s/COUT
3.364 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1405_s/CIN
3.399 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1405_s/COUT
3.399 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1404_s/CIN
3.434 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1404_s/COUT
3.434 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1403_s/CIN
3.470 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1403_s/COUT
3.470 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1402_s/CIN
3.505 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1402_s/COUT
3.505 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1401_s/CIN
3.540 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1401_s/COUT
3.540 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1400_s/CIN
3.575 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1400_s/COUT
3.575 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1399_s/CIN
3.610 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1399_s/COUT
3.610 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1398_s/CIN
3.646 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1398_s/COUT
3.646 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1397_s/CIN
3.681 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1397_s/COUT
3.681 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1396_s/CIN
3.716 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1396_s/COUT
3.716 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1395_s/CIN
3.751 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1395_s/COUT
3.751 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1394_s/CIN
3.786 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1394_s/COUT
3.786 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1393_s/CIN
3.822 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1393_s/COUT
3.822 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1392_s/CIN
3.857 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1392_s/COUT
3.857 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1391_s/CIN
3.892 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1391_s/COUT
3.892 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1390_s/CIN
3.927 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1390_s/COUT
3.927 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1389_s/CIN
3.962 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1389_s/COUT
3.962 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1388_s/CIN
3.998 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1388_s/COUT
3.998 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1387_s/CIN
4.033 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1387_s/COUT
4.033 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1386_s/CIN
4.068 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1386_s/COUT
4.068 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1385_s/CIN
4.103 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1385_s/COUT
4.103 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1384_s/CIN
4.138 0.035 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1384_s/COUT
4.138 0 tNET FF 2 u_pdm2pcm/u0_cic_cmp/n1383_s/CIN
4.608 0.47 tINS FF 1 u_pdm2pcm/u0_cic_cmp/n1383_s/SUM
4.845 0.237 tNET FF 1 u_pdm2pcm/u0_cic_cmp/n1716_s2/I1
5.400 0.555 tINS FF 4 u_pdm2pcm/u0_cic_cmp/n1716_s2/F
5.637 0.237 tNET FF 1 u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 2576 clk_ibuf/O
0.862 0.18 tNET RR 1 u_pdm2pcm/u0_cic_cmp/acc_out[3]_33_s0/CLK

Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 16.792, 73.171%; route: 5.925, 25.818%; tC2Q: 0.232, 1.011%
Required Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%

Synthesis completed successfully!
Process took 0h:0m:5s realtime, 0h:0m:5s cputime
Memory peak: 69.9MB