#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
#install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: NOA-PC

# Mon Sep  7 07:15:07 2020

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: NOA-PC

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: NOA-PC

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\Top.v" (library work)
@I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\data_rom.v" (library work)
@I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm_top.v" (library work)
@I:"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm_top.v":"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\define\define.vh" (library work)
@I:"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm_top.v":"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\define\static_macro_define.v" (library work)
@I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm_wrap.v" (library work)
@I:"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\pdm2pcm\pdm2pcm_wrap.v":"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\define\parameter.vh" (library work)
Verilog syntax check successful!
@N:CG364 : parameter.vh(6) | Synthesizing module work_C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\Top.v_unit in library work.
Selecting top level module Top
@N:CG364 : pdm2pcm_top.v(1819) | Synthesizing module \~syn_signal.PDM2PCM_Top  in library work.

	EDGE_MODE=2'b01
	DATA_WIDTH=32'b00000000000000000000000000001000
   Generated name = \~syn_signal.PDM2PCM_Top _1_8s
Running optimization stage 1 on \~syn_signal.PDM2PCM_Top _1_8s .......
@W:CL169 : pdm2pcm_top.v(1879) | Pruning unused register data_r3[7:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : pdm2pcm_top.v(1649) | Synthesizing module \~clk_div_even.PDM2PCM_Top  in library work.

	N=32'b00000000000000000000000000011001
   Generated name = \~clk_div_even.PDM2PCM_Top _25s
@N:CG179 : pdm2pcm_top.v(1682) | Removing redundant assignment.
Running optimization stage 1 on \~clk_div_even.PDM2PCM_Top _25s .......
@N:CG364 : pdm2pcm_top.v(1705) | Synthesizing module \~parallel2series.PDM2PCM_Top  in library work.

	EDGE_MODE=2'b01
	NUM_CHN=32'b00000000000000000000000000001000
	I_DATA_WIDTH=32'b00000000000000000000000010010000
	O_DATA_WIDTH=32'b00000000000000000000000000010010
	NUM_CYCLE=32'b00000000000000000000000000000010
   Generated name = \~parallel2series.PDM2PCM_Top _1_8s_144s_18s_2s
Running optimization stage 1 on \~parallel2series.PDM2PCM_Top _1_8s_144s_18s_2s .......
@N:CG364 : pdm2pcm_top.v(202) | Synthesizing module \~cic_cmp_rom.PDM2PCM_Top  in library work.

	MEM_DEPTH=32'b00000000000000000000000001100000
	DATA_WIDTH=32'b00000000000000000000000000010010
   Generated name = \~cic_cmp_rom.PDM2PCM_Top _96s_18s
Opening data file cic_comp_coeff_bin.dat from directory C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\src\data
@W:CG532 : pdm2pcm_top.v(241) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
Running optimization stage 1 on \~cic_cmp_rom.PDM2PCM_Top _96s_18s .......
@N:CG364 : gw1n.v(1691) | Synthesizing module SDPX9B in library work.
Running optimization stage 1 on SDPX9B .......
@N:CG364 : pdm2pcm_top.v(486) | Synthesizing module \~cic_compensation_filter.PDM2PCM_Top  in library work.

	N=32'b00000000000000000000000000000011
	R=32'b00000000000000000000000001000000
	M=32'b00000000000000000000000000000001
	TAP_SIZES=32'b00000000000000000000000001100000
	NUM_CHN=32'b00000000000000000000000000001000
	COEFF_WIDTH=32'b00000000000000000000000000010010
	I_DATA_WIDTH=32'b00000000000000000000000000010010
	O_DATA_WIDTH=32'b00000000000000000000000000100000
	FACTOR=32'b00000000000000000000000000000010
	NUM_MUL=32'b00000000000000000000000000000001
	NUM_TDM=32'b00000000000000000000000000110000
	TAPS_SIZE=32'b00000000000000000000000001100000
	LATENCY=32'b00000000000000000000000000111011
	MEM_DEPTH=32'b00000000000000000000001100000000
	NORMAL_GAIN=32'b00000000000000000000000000001111
   Generated name = \~cic_compensation_filter.PDM2PCM_Top _Z1
@W:CG390 : pdm2pcm_top.v(799) | Repeat multiplier in concatenation evaluates to 0
@W:CG390 : pdm2pcm_top.v(801) | Repeat multiplier in concatenation evaluates to 0
@N:CG179 : pdm2pcm_top.v(656) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(680) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(702) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(724) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(958) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(1032) | Removing redundant assignment.
@N:CG179 : pdm2pcm_top.v(1051) | Removing redundant assignment.
@W:CS263 : pdm2pcm_top.v(800) | Port-width mismatch for port DI. The port definition is 36 bits, but the actual port connection bit width is 18. Adjust either the definition or the instantiation of this port.
@W:CS263 : pdm2pcm_top.v(789) | Port-width mismatch for port DO. The port definition is 36 bits, but the actual port connection bit width is 18. Adjust either the definition or the instantiation of this port.
@W:CG133 : pdm2pcm_top.v(590) | Object out_sync_r is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
@W:CL271 : pdm2pcm_top.v(1047) | Pruning unused bits 62 to 60 of dout_r[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : pdm2pcm_top.v(1047) | Pruning unused bits 28 to 0 of dout_r[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : pdm2pcm_top.v(1028) | Pruning unused bits 62 to 60 of fir_dout[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : pdm2pcm_top.v(1028) | Pruning unused bits 28 to 0 of fir_dout[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL265 : pdm2pcm_top.v(842) | Removing unused bit 0 of cnt_mem_wr_d[9:0]. Either assign all bits or reduce the width of the signal.
@N:CG364 : pdm2pcm_top.v(17) | Synthesizing module \~pdm2pcm.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	DIV_N=32'b00000000000000000000000000011001
	TAP_SIZES=32'b00000000000000000000000001100000
	R=32'b00000000000000000000000001000000
	N=32'b00000000000000000000000000000011
	M=32'b00000000000000000000000000000001
	EDGE_MODE=2'b01
	DATA_WIDTH=32'b00000000000000000000000000100000
	COEFF_WIDTH=32'b00000000000000000000000000010010
	CIC_DATA_WIDTH=32'b00000000000000000000000000010010
   Generated name = \~pdm2pcm.PDM2PCM_Top _8s_25s_96s_64s_3s_1s_1_32s_18s_18s
@N:CG364 : pdm2pcm_top.v(1491) | Synthesizing module \~cic_integrator.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	I_DATA_WIDTH=32'b00000000000000000000000000000010
	O_DATA_WIDTH=32'b00000000000000000000000000010010
   Generated name = \~cic_integrator.PDM2PCM_Top _8s_2s_18s
@W:CG133 : pdm2pcm_top.v(1518) | Object data_valid is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top _8s_2s_18s .......
@N:CG364 : pdm2pcm_top.v(1491) | Synthesizing module \~cic_integrator.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	I_DATA_WIDTH=32'b00000000000000000000000000010010
	O_DATA_WIDTH=32'b00000000000000000000000000101100
   Generated name = \~cic_integrator.PDM2PCM_Top _8s_18s_44s
@W:CG133 : pdm2pcm_top.v(1518) | Object data_valid is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top _8s_18s_44s .......
@N:CG364 : pdm2pcm_top.v(1491) | Synthesizing module \~cic_integrator.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	I_DATA_WIDTH=32'b00000000000000000000000000101100
	O_DATA_WIDTH=32'b00000000000000000000000000101100
   Generated name = \~cic_integrator.PDM2PCM_Top _8s_44s_44s
@W:CG390 : pdm2pcm_top.v(1549) | Repeat multiplier in concatenation evaluates to 0
@W:CG133 : pdm2pcm_top.v(1518) | Object data_valid is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~cic_integrator.PDM2PCM_Top _8s_44s_44s .......
@N:CG364 : pdm2pcm_top.v(1316) | Synthesizing module \~cic_down_sample.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	R=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000000101100
	LATENCY=32'b00000000000000000000000000000010
   Generated name = \~cic_down_sample.PDM2PCM_Top _8s_32s_44s_2s
Running optimization stage 1 on \~cic_down_sample.PDM2PCM_Top _8s_32s_44s_2s .......
@N:CG364 : pdm2pcm_top.v(285) | Synthesizing module \~cic_comb.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	M=32'b00000000000000000000000000000001
	I_DATA_WIDTH=32'b00000000000000000000000000101100
	O_DATA_WIDTH=32'b00000000000000000000000000101100
	LATANCE=32'b00000000000000000000000000000010
   Generated name = \~cic_comb.PDM2PCM_Top _8s_1s_44s_44s_2s
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top _8s_1s_44s_44s_2s .......
@W:CL169 : pdm2pcm_top.v(330) | Pruning unused register data_reg1[43:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : pdm2pcm_top.v(285) | Synthesizing module \~cic_comb.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	M=32'b00000000000000000000000000000001
	I_DATA_WIDTH=32'b00000000000000000000000000101100
	O_DATA_WIDTH=32'b00000000000000000000000000010010
	LATANCE=32'b00000000000000000000000000000010
   Generated name = \~cic_comb.PDM2PCM_Top _8s_1s_44s_18s_2s
Running optimization stage 1 on \~cic_comb.PDM2PCM_Top _8s_1s_44s_18s_2s .......
@W:CL169 : pdm2pcm_top.v(330) | Pruning unused register data_reg1[43:0]. Make sure that there are no unused intermediate registers.
@W:CL271 : pdm2pcm_top.v(342) | Pruning unused bits 43 to 18 of data_out[43:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : pdm2pcm_top.v(1105) | Synthesizing module \~cic_decimator.PDM2PCM_Top  in library work.

	NUM_CHN=32'b00000000000000000000000000001000
	R=32'b00000000000000000000000001000000
	N=32'b00000000000000000000000000000011
	M=32'b00000000000000000000000000000001
	O_DATA_WIDTH=32'b00000000000000000000000000010010
	I_DATA_WIDTH=32'b00000000000000000000000000011011
	DATA_WIDTH=32'b00000000000000000000000000101100
   Generated name = \~cic_decimator.PDM2PCM_Top _8s_64s_3s_1s_18s_27s_44s
Running optimization stage 1 on \~cic_decimator.PDM2PCM_Top _8s_64s_3s_1s_18s_27s_44s .......
Running optimization stage 1 on \~pdm2pcm.PDM2PCM_Top _8s_25s_96s_64s_3s_1s_1_32s_18s_18s .......
@N:CG364 : pdm2pcm_wrap.v(4) | Synthesizing module PDM2PCM_Top in library work.
Running optimization stage 1 on PDM2PCM_Top .......
@N:CG364 : gw1n.v(999) | Synthesizing module ROM in library work.
Running optimization stage 1 on ROM .......
@N:CG364 : data_rom.v(8) | Synthesizing module Data_ROM in library work.
@W:CS263 : data_rom.v(23) | Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on Data_ROM .......
@N:CG364 : Top.v(13) | Synthesizing module Top in library work.
@N:CG179 : Top.v(122) | Removing redundant assignment.
Running optimization stage 1 on Top .......
Running optimization stage 2 on Top .......
Running optimization stage 2 on Data_ROM .......
Running optimization stage 2 on ROM .......
Running optimization stage 2 on PDM2PCM_Top .......
Running optimization stage 2 on \~cic_decimator.PDM2PCM_Top _8s_64s_3s_1s_18s_27s_44s .......
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top _8s_1s_44s_18s_2s .......
@W:CL246 : pdm2pcm_top.v(295) | Input port bits 43 to 18 of in_data[43:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on \~cic_comb.PDM2PCM_Top _8s_1s_44s_44s_2s .......
Running optimization stage 2 on \~cic_down_sample.PDM2PCM_Top _8s_32s_44s_2s .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top _8s_44s_44s .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top _8s_18s_44s .......
Running optimization stage 2 on \~cic_integrator.PDM2PCM_Top _8s_2s_18s .......
Running optimization stage 2 on \~pdm2pcm.PDM2PCM_Top _8s_25s_96s_64s_3s_1s_1_32s_18s_18s .......
Running optimization stage 2 on \~cic_compensation_filter.PDM2PCM_Top _Z1 .......
@N:CL134 : pdm2pcm_top.v(996) | Found RAM acc_out, depth=8, width=64
@N:CL135 : pdm2pcm_top.v(911) | Found sequential shift cnt_chn_rd_dx2 with address depth of 5 words and data bit width of 3.
@N:CL135 : pdm2pcm_top.v(872) | Found sequential shift cnt_tdm_d with address depth of 3 words and data bit width of 6.
@N:CL135 : pdm2pcm_top.v(623) | Found sequential shift in_data_r2 with address depth of 3 words and data bit width of 18.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : pdm2pcm_top.v(889) | Pruning register bits 13 to 0 of dsp_out[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(963) | Optimizing register bit acc_dsp_out[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : pdm2pcm_top.v(963) | Pruning register bits 13 to 0 of acc_dsp_out[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : pdm2pcm_top.v(996) | Pruning register bits 13 to 0 of acc_out[63:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL134 : pdm2pcm_top.v(996) | Found RAM acc_out, depth=8, width=31
@N:CL134 : pdm2pcm_top.v(996) | Found RAM acc_out, depth=8, width=1
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : pdm2pcm_top.v(889) | Optimizing register bit dsp_out[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : pdm2pcm_top.v(889) | Pruning register bits 27 to 14 of dsp_out[63:14]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on SDPX9B .......
Running optimization stage 2 on \~cic_cmp_rom.PDM2PCM_Top _96s_18s .......
Running optimization stage 2 on \~parallel2series.PDM2PCM_Top _1_8s_144s_18s_2s .......
Running optimization stage 2 on \~clk_div_even.PDM2PCM_Top _25s .......
Running optimization stage 2 on \~syn_signal.PDM2PCM_Top _1_8s .......
@N:CL135 : pdm2pcm_top.v(1855) | Found sequential shift signal_r3 with address depth of 3 words and data bit width of 1.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 103MB peak: 145MB)

Process took 0h:00m:10s realtime, 0h:00m:09s cputime

Process completed successfully.
# Mon Sep  7 07:15:18 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: NOA-PC

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep  7 07:15:18 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  Ref_design_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:09s; Memory used current: 22MB peak: 22MB)

Process took 0h:00m:11s realtime, 0h:00m:09s cputime

Process completed successfully.
# Mon Sep  7 07:15:18 2020

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: NOA-PC

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
File C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\impl\synthesize\rev_1\synwork\Ref_design_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep  7 07:15:20 2020

###########################################################]


# Mon Sep  7 07:15:20 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: C:\Gowin\Gowin_V1.9.6.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: NOA-PC

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  Ref_design_scck.rpt
See clock summary report "C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 130MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 131MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)

@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_4(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : pdm2pcm_top.v(355) | Removing sequential instance out_valid (in view: work.\\\~cic_comb\.PDM2PCM_Top\ _8s_1s_44s_18s_2s_6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.

Starting clock optimization phase (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 234MB peak: 234MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 234MB peak: 234MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 234MB peak: 234MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB)



Clock Summary
******************

          Start           Requested     Requested     Clock        Clock                     Clock
Level     Clock           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------
0 -       Top|SYM_CLK     134.4 MHz     7.443         inferred     Autoconstr_clkgroup_0     4402 
==================================================================================================



Clock Load Summary
***********************

                Clock     Source            Clock Pin        Non-clock Pin     Non-clock Pin
Clock           Load      Pin               Seq Example      Seq Example       Comb Example 
--------------------------------------------------------------------------------------------
Top|SYM_CLK     4402      SYM_CLK(port)     onboard_en.C     -                 -            
============================================================================================

@W:MT529 : pdm2pcm_top.v(1855) | Found inferred clock Top|SYM_CLK which controls 4402 sequential elements including u_pdm2pcm.pdm2pcm.u_syn_signal.signal_r3_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 4299 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       SYM_CLK             port                   4299       cnt_addr[10:0] 
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\Gowin_PDM2PCM_RefDesign\Gowin_PDM2PCM_RefDesign\project\impl\synthesize\rev_1\Ref_design.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 235MB peak: 235MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 235MB peak: 235MB)


Finished constraint checker (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 238MB peak: 238MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 157MB peak: 239MB)

Process took 0h:00m:16s realtime, 0h:00m:16s cputime
# Mon Sep  7 07:15:37 2020

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