Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\PID_Controller3p3z\data\controller_3p3z.v
C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\PID_Controller3p3z\data\controller_3p3z_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2A-LV55PG484C9/I8
Device GW2A-55
Created Time Wed Jul 06 10:14:52 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PID_Controller_3p3z_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.266s, Peak memory usage = 47.578MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 47.578MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 47.578MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 47.578MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 47.578MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 47.578MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 47.578MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 47.578MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.578MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 47.578MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 47.578MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 47.578MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.993s, Peak memory usage = 60.813MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 60.813MB
Generate output files:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 60.813MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.813MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 188
I/O Buf 188
    IBUF 168
    OBUF 20
Register 1183
    DFFP 2
    DFFPE 3
    DFFC 207
    DFFCE 971
LUT 722
    LUT2 10
    LUT3 401
    LUT4 311
ALU 70
    ALU 70
INV 1
    INV 1
DSP 1
    MULTADDALU18X18 1

Resource Utilization Summary

Resource Usage Utilization
Logic 793(723 LUTs, 70 ALUs) / 54720 1%
Register 1183 / 41997 3%
  --Register as Latch 0 / 41997 0%
  --Register as FF 1183 / 41997 3%
BSRAM 0 / 140 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 346.3(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.112
Data Arrival Time 3.599
Data Required Time 10.712
From controller_3p3z_inst/acc_out_8_s1
To controller_3p3z_inst/u_data_o_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.587 0.587 tINS RR 1184 clk_ibuf/O
0.742 0.155 tNET RR 1 controller_3p3z_inst/acc_out_8_s1/CLK
0.942 0.200 tC2Q RF 4 controller_3p3z_inst/acc_out_8_s1/Q
1.146 0.204 tNET FF 2 controller_3p3z_inst/n1387_s32/I1
1.638 0.491 tINS FR 1 controller_3p3z_inst/n1387_s32/COUT
1.638 0.000 tNET RR 2 controller_3p3z_inst/n1387_s33/CIN
1.668 0.030 tINS RF 1 controller_3p3z_inst/n1387_s33/COUT
1.668 0.000 tNET FF 2 controller_3p3z_inst/n1387_s34/CIN
1.698 0.030 tINS FF 1 controller_3p3z_inst/n1387_s34/COUT
1.698 0.000 tNET FF 2 controller_3p3z_inst/n1387_s35/CIN
1.729 0.030 tINS FF 1 controller_3p3z_inst/n1387_s35/COUT
1.729 0.000 tNET FF 2 controller_3p3z_inst/n1387_s36/CIN
1.759 0.030 tINS FF 1 controller_3p3z_inst/n1387_s36/COUT
1.759 0.000 tNET FF 2 controller_3p3z_inst/n1387_s37/CIN
1.789 0.030 tINS FF 1 controller_3p3z_inst/n1387_s37/COUT
1.789 0.000 tNET FF 2 controller_3p3z_inst/n1387_s38/CIN
1.820 0.030 tINS FF 1 controller_3p3z_inst/n1387_s38/COUT
1.820 0.000 tNET FF 2 controller_3p3z_inst/n1387_s39/CIN
1.850 0.030 tINS FF 1 controller_3p3z_inst/n1387_s39/COUT
1.850 0.000 tNET FF 2 controller_3p3z_inst/n1387_s40/CIN
1.880 0.030 tINS FF 1 controller_3p3z_inst/n1387_s40/COUT
1.880 0.000 tNET FF 2 controller_3p3z_inst/n1387_s41/CIN
1.911 0.030 tINS FF 1 controller_3p3z_inst/n1387_s41/COUT
1.911 0.000 tNET FF 2 controller_3p3z_inst/n1387_s42/CIN
1.941 0.030 tINS FF 1 controller_3p3z_inst/n1387_s42/COUT
1.941 0.000 tNET FF 2 controller_3p3z_inst/n1387_s43/CIN
1.971 0.030 tINS FF 1 controller_3p3z_inst/n1387_s43/COUT
1.971 0.000 tNET FF 2 controller_3p3z_inst/n1387_s44/CIN
2.002 0.030 tINS FF 1 controller_3p3z_inst/n1387_s44/COUT
2.002 0.000 tNET FF 2 controller_3p3z_inst/n1387_s45/CIN
2.032 0.030 tINS FF 1 controller_3p3z_inst/n1387_s45/COUT
2.032 0.000 tNET FF 2 controller_3p3z_inst/n1387_s46/CIN
2.063 0.030 tINS FF 30 controller_3p3z_inst/n1387_s46/COUT
2.267 0.204 tNET FF 1 controller_3p3z_inst/n1419_s1/I1
2.745 0.478 tINS FF 1 controller_3p3z_inst/n1419_s1/F
2.950 0.204 tNET FF 1 controller_3p3z_inst/n1419_s0/I0
3.395 0.446 tINS FF 1 controller_3p3z_inst/n1419_s0/F
3.599 0.204 tNET FF 1 controller_3p3z_inst/u_data_o_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.587 0.587 tINS RR 1184 clk_ibuf/O
10.742 0.155 tNET RR 1 controller_3p3z_inst/u_data_o_0_s0/CLK
10.712 -0.030 tSu 1 controller_3p3z_inst/u_data_o_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%
Arrival Data Path Delay: cell: 1.840, 64.402%; route: 0.817, 28.599%; tC2Q: 0.200, 6.999%
Required Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%

Path 2

Path Summary:
Slack 7.112
Data Arrival Time 3.599
Data Required Time 10.712
From controller_3p3z_inst/acc_out_8_s1
To controller_3p3z_inst/u_data_o_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.587 0.587 tINS RR 1184 clk_ibuf/O
0.742 0.155 tNET RR 1 controller_3p3z_inst/acc_out_8_s1/CLK
0.942 0.200 tC2Q RF 4 controller_3p3z_inst/acc_out_8_s1/Q
1.146 0.204 tNET FF 2 controller_3p3z_inst/n1387_s32/I1
1.638 0.491 tINS FR 1 controller_3p3z_inst/n1387_s32/COUT
1.638 0.000 tNET RR 2 controller_3p3z_inst/n1387_s33/CIN
1.668 0.030 tINS RF 1 controller_3p3z_inst/n1387_s33/COUT
1.668 0.000 tNET FF 2 controller_3p3z_inst/n1387_s34/CIN
1.698 0.030 tINS FF 1 controller_3p3z_inst/n1387_s34/COUT
1.698 0.000 tNET FF 2 controller_3p3z_inst/n1387_s35/CIN
1.729 0.030 tINS FF 1 controller_3p3z_inst/n1387_s35/COUT
1.729 0.000 tNET FF 2 controller_3p3z_inst/n1387_s36/CIN
1.759 0.030 tINS FF 1 controller_3p3z_inst/n1387_s36/COUT
1.759 0.000 tNET FF 2 controller_3p3z_inst/n1387_s37/CIN
1.789 0.030 tINS FF 1 controller_3p3z_inst/n1387_s37/COUT
1.789 0.000 tNET FF 2 controller_3p3z_inst/n1387_s38/CIN
1.820 0.030 tINS FF 1 controller_3p3z_inst/n1387_s38/COUT
1.820 0.000 tNET FF 2 controller_3p3z_inst/n1387_s39/CIN
1.850 0.030 tINS FF 1 controller_3p3z_inst/n1387_s39/COUT
1.850 0.000 tNET FF 2 controller_3p3z_inst/n1387_s40/CIN
1.880 0.030 tINS FF 1 controller_3p3z_inst/n1387_s40/COUT
1.880 0.000 tNET FF 2 controller_3p3z_inst/n1387_s41/CIN
1.911 0.030 tINS FF 1 controller_3p3z_inst/n1387_s41/COUT
1.911 0.000 tNET FF 2 controller_3p3z_inst/n1387_s42/CIN
1.941 0.030 tINS FF 1 controller_3p3z_inst/n1387_s42/COUT
1.941 0.000 tNET FF 2 controller_3p3z_inst/n1387_s43/CIN
1.971 0.030 tINS FF 1 controller_3p3z_inst/n1387_s43/COUT
1.971 0.000 tNET FF 2 controller_3p3z_inst/n1387_s44/CIN
2.002 0.030 tINS FF 1 controller_3p3z_inst/n1387_s44/COUT
2.002 0.000 tNET FF 2 controller_3p3z_inst/n1387_s45/CIN
2.032 0.030 tINS FF 1 controller_3p3z_inst/n1387_s45/COUT
2.032 0.000 tNET FF 2 controller_3p3z_inst/n1387_s46/CIN
2.063 0.030 tINS FF 30 controller_3p3z_inst/n1387_s46/COUT
2.267 0.204 tNET FF 1 controller_3p3z_inst/n1418_s1/I1
2.745 0.478 tINS FF 1 controller_3p3z_inst/n1418_s1/F
2.950 0.204 tNET FF 1 controller_3p3z_inst/n1418_s0/I0
3.395 0.446 tINS FF 1 controller_3p3z_inst/n1418_s0/F
3.599 0.204 tNET FF 1 controller_3p3z_inst/u_data_o_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.587 0.587 tINS RR 1184 clk_ibuf/O
10.742 0.155 tNET RR 1 controller_3p3z_inst/u_data_o_1_s0/CLK
10.712 -0.030 tSu 1 controller_3p3z_inst/u_data_o_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%
Arrival Data Path Delay: cell: 1.840, 64.402%; route: 0.817, 28.599%; tC2Q: 0.200, 6.999%
Required Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%

Path 3

Path Summary:
Slack 7.112
Data Arrival Time 3.599
Data Required Time 10.712
From controller_3p3z_inst/acc_out_8_s1
To controller_3p3z_inst/u_data_o_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.587 0.587 tINS RR 1184 clk_ibuf/O
0.742 0.155 tNET RR 1 controller_3p3z_inst/acc_out_8_s1/CLK
0.942 0.200 tC2Q RF 4 controller_3p3z_inst/acc_out_8_s1/Q
1.146 0.204 tNET FF 2 controller_3p3z_inst/n1387_s32/I1
1.638 0.491 tINS FR 1 controller_3p3z_inst/n1387_s32/COUT
1.638 0.000 tNET RR 2 controller_3p3z_inst/n1387_s33/CIN
1.668 0.030 tINS RF 1 controller_3p3z_inst/n1387_s33/COUT
1.668 0.000 tNET FF 2 controller_3p3z_inst/n1387_s34/CIN
1.698 0.030 tINS FF 1 controller_3p3z_inst/n1387_s34/COUT
1.698 0.000 tNET FF 2 controller_3p3z_inst/n1387_s35/CIN
1.729 0.030 tINS FF 1 controller_3p3z_inst/n1387_s35/COUT
1.729 0.000 tNET FF 2 controller_3p3z_inst/n1387_s36/CIN
1.759 0.030 tINS FF 1 controller_3p3z_inst/n1387_s36/COUT
1.759 0.000 tNET FF 2 controller_3p3z_inst/n1387_s37/CIN
1.789 0.030 tINS FF 1 controller_3p3z_inst/n1387_s37/COUT
1.789 0.000 tNET FF 2 controller_3p3z_inst/n1387_s38/CIN
1.820 0.030 tINS FF 1 controller_3p3z_inst/n1387_s38/COUT
1.820 0.000 tNET FF 2 controller_3p3z_inst/n1387_s39/CIN
1.850 0.030 tINS FF 1 controller_3p3z_inst/n1387_s39/COUT
1.850 0.000 tNET FF 2 controller_3p3z_inst/n1387_s40/CIN
1.880 0.030 tINS FF 1 controller_3p3z_inst/n1387_s40/COUT
1.880 0.000 tNET FF 2 controller_3p3z_inst/n1387_s41/CIN
1.911 0.030 tINS FF 1 controller_3p3z_inst/n1387_s41/COUT
1.911 0.000 tNET FF 2 controller_3p3z_inst/n1387_s42/CIN
1.941 0.030 tINS FF 1 controller_3p3z_inst/n1387_s42/COUT
1.941 0.000 tNET FF 2 controller_3p3z_inst/n1387_s43/CIN
1.971 0.030 tINS FF 1 controller_3p3z_inst/n1387_s43/COUT
1.971 0.000 tNET FF 2 controller_3p3z_inst/n1387_s44/CIN
2.002 0.030 tINS FF 1 controller_3p3z_inst/n1387_s44/COUT
2.002 0.000 tNET FF 2 controller_3p3z_inst/n1387_s45/CIN
2.032 0.030 tINS FF 1 controller_3p3z_inst/n1387_s45/COUT
2.032 0.000 tNET FF 2 controller_3p3z_inst/n1387_s46/CIN
2.063 0.030 tINS FF 30 controller_3p3z_inst/n1387_s46/COUT
2.267 0.204 tNET FF 1 controller_3p3z_inst/n1417_s1/I1
2.745 0.478 tINS FF 1 controller_3p3z_inst/n1417_s1/F
2.950 0.204 tNET FF 1 controller_3p3z_inst/n1417_s0/I0
3.395 0.446 tINS FF 1 controller_3p3z_inst/n1417_s0/F
3.599 0.204 tNET FF 1 controller_3p3z_inst/u_data_o_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.587 0.587 tINS RR 1184 clk_ibuf/O
10.742 0.155 tNET RR 1 controller_3p3z_inst/u_data_o_2_s0/CLK
10.712 -0.030 tSu 1 controller_3p3z_inst/u_data_o_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%
Arrival Data Path Delay: cell: 1.840, 64.402%; route: 0.817, 28.599%; tC2Q: 0.200, 6.999%
Required Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%

Path 4

Path Summary:
Slack 7.112
Data Arrival Time 3.599
Data Required Time 10.712
From controller_3p3z_inst/acc_out_8_s1
To controller_3p3z_inst/u_data_o_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.587 0.587 tINS RR 1184 clk_ibuf/O
0.742 0.155 tNET RR 1 controller_3p3z_inst/acc_out_8_s1/CLK
0.942 0.200 tC2Q RF 4 controller_3p3z_inst/acc_out_8_s1/Q
1.146 0.204 tNET FF 2 controller_3p3z_inst/n1387_s32/I1
1.638 0.491 tINS FR 1 controller_3p3z_inst/n1387_s32/COUT
1.638 0.000 tNET RR 2 controller_3p3z_inst/n1387_s33/CIN
1.668 0.030 tINS RF 1 controller_3p3z_inst/n1387_s33/COUT
1.668 0.000 tNET FF 2 controller_3p3z_inst/n1387_s34/CIN
1.698 0.030 tINS FF 1 controller_3p3z_inst/n1387_s34/COUT
1.698 0.000 tNET FF 2 controller_3p3z_inst/n1387_s35/CIN
1.729 0.030 tINS FF 1 controller_3p3z_inst/n1387_s35/COUT
1.729 0.000 tNET FF 2 controller_3p3z_inst/n1387_s36/CIN
1.759 0.030 tINS FF 1 controller_3p3z_inst/n1387_s36/COUT
1.759 0.000 tNET FF 2 controller_3p3z_inst/n1387_s37/CIN
1.789 0.030 tINS FF 1 controller_3p3z_inst/n1387_s37/COUT
1.789 0.000 tNET FF 2 controller_3p3z_inst/n1387_s38/CIN
1.820 0.030 tINS FF 1 controller_3p3z_inst/n1387_s38/COUT
1.820 0.000 tNET FF 2 controller_3p3z_inst/n1387_s39/CIN
1.850 0.030 tINS FF 1 controller_3p3z_inst/n1387_s39/COUT
1.850 0.000 tNET FF 2 controller_3p3z_inst/n1387_s40/CIN
1.880 0.030 tINS FF 1 controller_3p3z_inst/n1387_s40/COUT
1.880 0.000 tNET FF 2 controller_3p3z_inst/n1387_s41/CIN
1.911 0.030 tINS FF 1 controller_3p3z_inst/n1387_s41/COUT
1.911 0.000 tNET FF 2 controller_3p3z_inst/n1387_s42/CIN
1.941 0.030 tINS FF 1 controller_3p3z_inst/n1387_s42/COUT
1.941 0.000 tNET FF 2 controller_3p3z_inst/n1387_s43/CIN
1.971 0.030 tINS FF 1 controller_3p3z_inst/n1387_s43/COUT
1.971 0.000 tNET FF 2 controller_3p3z_inst/n1387_s44/CIN
2.002 0.030 tINS FF 1 controller_3p3z_inst/n1387_s44/COUT
2.002 0.000 tNET FF 2 controller_3p3z_inst/n1387_s45/CIN
2.032 0.030 tINS FF 1 controller_3p3z_inst/n1387_s45/COUT
2.032 0.000 tNET FF 2 controller_3p3z_inst/n1387_s46/CIN
2.063 0.030 tINS FF 30 controller_3p3z_inst/n1387_s46/COUT
2.267 0.204 tNET FF 1 controller_3p3z_inst/n1416_s1/I1
2.745 0.478 tINS FF 1 controller_3p3z_inst/n1416_s1/F
2.950 0.204 tNET FF 1 controller_3p3z_inst/n1416_s0/I0
3.395 0.446 tINS FF 1 controller_3p3z_inst/n1416_s0/F
3.599 0.204 tNET FF 1 controller_3p3z_inst/u_data_o_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.587 0.587 tINS RR 1184 clk_ibuf/O
10.742 0.155 tNET RR 1 controller_3p3z_inst/u_data_o_3_s0/CLK
10.712 -0.030 tSu 1 controller_3p3z_inst/u_data_o_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%
Arrival Data Path Delay: cell: 1.840, 64.402%; route: 0.817, 28.599%; tC2Q: 0.200, 6.999%
Required Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%

Path 5

Path Summary:
Slack 7.112
Data Arrival Time 3.599
Data Required Time 10.712
From controller_3p3z_inst/acc_out_8_s1
To controller_3p3z_inst/u_data_o_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.587 0.587 tINS RR 1184 clk_ibuf/O
0.742 0.155 tNET RR 1 controller_3p3z_inst/acc_out_8_s1/CLK
0.942 0.200 tC2Q RF 4 controller_3p3z_inst/acc_out_8_s1/Q
1.146 0.204 tNET FF 2 controller_3p3z_inst/n1387_s32/I1
1.638 0.491 tINS FR 1 controller_3p3z_inst/n1387_s32/COUT
1.638 0.000 tNET RR 2 controller_3p3z_inst/n1387_s33/CIN
1.668 0.030 tINS RF 1 controller_3p3z_inst/n1387_s33/COUT
1.668 0.000 tNET FF 2 controller_3p3z_inst/n1387_s34/CIN
1.698 0.030 tINS FF 1 controller_3p3z_inst/n1387_s34/COUT
1.698 0.000 tNET FF 2 controller_3p3z_inst/n1387_s35/CIN
1.729 0.030 tINS FF 1 controller_3p3z_inst/n1387_s35/COUT
1.729 0.000 tNET FF 2 controller_3p3z_inst/n1387_s36/CIN
1.759 0.030 tINS FF 1 controller_3p3z_inst/n1387_s36/COUT
1.759 0.000 tNET FF 2 controller_3p3z_inst/n1387_s37/CIN
1.789 0.030 tINS FF 1 controller_3p3z_inst/n1387_s37/COUT
1.789 0.000 tNET FF 2 controller_3p3z_inst/n1387_s38/CIN
1.820 0.030 tINS FF 1 controller_3p3z_inst/n1387_s38/COUT
1.820 0.000 tNET FF 2 controller_3p3z_inst/n1387_s39/CIN
1.850 0.030 tINS FF 1 controller_3p3z_inst/n1387_s39/COUT
1.850 0.000 tNET FF 2 controller_3p3z_inst/n1387_s40/CIN
1.880 0.030 tINS FF 1 controller_3p3z_inst/n1387_s40/COUT
1.880 0.000 tNET FF 2 controller_3p3z_inst/n1387_s41/CIN
1.911 0.030 tINS FF 1 controller_3p3z_inst/n1387_s41/COUT
1.911 0.000 tNET FF 2 controller_3p3z_inst/n1387_s42/CIN
1.941 0.030 tINS FF 1 controller_3p3z_inst/n1387_s42/COUT
1.941 0.000 tNET FF 2 controller_3p3z_inst/n1387_s43/CIN
1.971 0.030 tINS FF 1 controller_3p3z_inst/n1387_s43/COUT
1.971 0.000 tNET FF 2 controller_3p3z_inst/n1387_s44/CIN
2.002 0.030 tINS FF 1 controller_3p3z_inst/n1387_s44/COUT
2.002 0.000 tNET FF 2 controller_3p3z_inst/n1387_s45/CIN
2.032 0.030 tINS FF 1 controller_3p3z_inst/n1387_s45/COUT
2.032 0.000 tNET FF 2 controller_3p3z_inst/n1387_s46/CIN
2.063 0.030 tINS FF 30 controller_3p3z_inst/n1387_s46/COUT
2.267 0.204 tNET FF 1 controller_3p3z_inst/n1415_s1/I1
2.745 0.478 tINS FF 1 controller_3p3z_inst/n1415_s1/F
2.950 0.204 tNET FF 1 controller_3p3z_inst/n1415_s0/I0
3.395 0.446 tINS FF 1 controller_3p3z_inst/n1415_s0/F
3.599 0.204 tNET FF 1 controller_3p3z_inst/u_data_o_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.587 0.587 tINS RR 1184 clk_ibuf/O
10.742 0.155 tNET RR 1 controller_3p3z_inst/u_data_o_4_s0/CLK
10.712 -0.030 tSu 1 controller_3p3z_inst/u_data_o_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%
Arrival Data Path Delay: cell: 1.840, 64.402%; route: 0.817, 28.599%; tC2Q: 0.200, 6.999%
Required Clock Path Delay: cell: 0.587, 79.092%; route: 0.155, 20.908%