Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\impl\gwsynthesis\pid_controller_3p3z.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\src\pid_controller_3p3z.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\src\pid_controller_3p3z.sdc
Version V1.9.8.07
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jul 06 11:01:06 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 5953
Numbers of Endpoints Analyzed 6659
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 20.000 50.000 0.000 10.000 clk
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 195.710(MHz) 3 TOP
2 tck_pad_i 20.000(MHz) 132.162(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 14.890 controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_1_s1/D clk:[R] clk:[R] 20.000 0.000 5.075
2 14.914 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE clk:[R] clk:[R] 20.000 0.000 5.051
3 15.065 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_1_s0/CE clk:[R] clk:[R] 20.000 0.000 4.900
4 15.080 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D clk:[R] clk:[R] 20.000 0.000 4.885
5 15.080 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D clk:[R] clk:[R] 20.000 0.000 4.885
6 15.097 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s0/CE clk:[R] clk:[R] 20.000 0.000 4.868
7 15.322 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_7_s0/D clk:[R] clk:[R] 20.000 0.000 4.643
8 15.339 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_0_s0/D clk:[R] clk:[R] 20.000 0.000 4.626
9 15.339 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_14_s0/D clk:[R] clk:[R] 20.000 0.000 4.626
10 15.372 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_3_s0/D clk:[R] clk:[R] 20.000 0.000 4.593
11 15.379 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_15_s0/D clk:[R] clk:[R] 20.000 0.000 4.586
12 15.414 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_14_s0/D clk:[R] clk:[R] 20.000 0.000 4.551
13 15.450 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_13_s0/D clk:[R] clk:[R] 20.000 0.000 4.515
14 15.485 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0/D clk:[R] clk:[R] 20.000 0.000 4.480
15 15.486 controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_un23_din_11_s1/D clk:[R] clk:[R] 20.000 0.000 4.479
16 15.499 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D clk:[R] clk:[R] 20.000 0.000 4.466
17 15.499 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D clk:[R] clk:[R] 20.000 0.000 4.466
18 15.514 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_5_s0/D clk:[R] clk:[R] 20.000 0.000 4.451
19 15.517 controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_2_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/mem[4]_4_s0/CE clk:[R] clk:[R] 20.000 0.000 4.448
20 15.520 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_11_s0/D clk:[R] clk:[R] 20.000 0.000 4.445
21 15.532 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_8_s0/D clk:[R] clk:[R] 20.000 0.000 4.433
22 15.540 controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_5_s1/D clk:[R] clk:[R] 20.000 0.000 4.425
23 15.555 input_gen_inst/data_cycle_1_s0/Q controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_10_s0/D clk:[R] clk:[R] 20.000 0.000 4.410
24 15.563 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_11_s0/D clk:[R] clk:[R] 20.000 0.000 4.402
25 15.564 controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_4_s0/D clk:[R] clk:[R] 20.000 0.000 4.401

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
2 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
3 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
4 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
5 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
6 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
7 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
8 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
9 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
10 0.190 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA clk:[R] clk:[R] 0.000 0.000 0.202
11 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_148_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[9] clk:[R] clk:[R] 0.000 0.000 0.462
12 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[16] clk:[R] clk:[R] 0.000 0.000 0.462
13 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[14] clk:[R] clk:[R] 0.000 0.000 0.474
14 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5] clk:[R] clk:[R] 0.000 0.000 0.474
15 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] clk:[R] clk:[R] 0.000 0.000 0.474
16 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] clk:[R] clk:[R] 0.000 0.000 0.474
17 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_166_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[9] clk:[R] clk:[R] 0.000 0.000 0.596
18 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[8] clk:[R] clk:[R] 0.000 0.000 0.596
19 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_164_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[7] clk:[R] clk:[R] 0.000 0.000 0.596
20 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[17] clk:[R] clk:[R] 0.000 0.000 0.596
21 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_132_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[11] clk:[R] clk:[R] 0.000 0.000 0.596
22 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6] clk:[R] clk:[R] 0.000 0.000 0.596
23 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[6] clk:[R] clk:[R] 0.000 0.000 0.596
24 0.347 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] clk:[R] clk:[R] 0.000 0.000 0.596
25 0.351 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3] clk:[R] clk:[R] 0.000 0.000 0.600

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 8.751 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.191
2 8.751 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.191
3 8.819 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.123
4 8.819 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.123
5 8.819 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.123
6 8.819 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.123
7 8.877 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 1.065
8 8.976 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR clk:[F] clk:[R] 10.000 0.023 0.966
9 8.976 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.966
10 8.976 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.966
11 8.976 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.966
12 8.976 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.966
13 8.994 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.948
14 8.994 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.948
15 8.994 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.948
16 8.994 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.948
17 8.995 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.947
18 8.999 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.943
19 8.999 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.943
20 9.012 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.930
21 9.012 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.930
22 9.012 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR clk:[F] clk:[R] 10.000 0.023 0.930
23 9.033 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.909
24 9.033 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.909
25 9.033 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] 10.000 0.023 0.909

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.339 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.338
2 10.461 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.460
3 10.461 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk:[F] clk:[R] -10.000 0.012 0.460
4 10.461 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.460
5 10.466 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.465
6 10.466 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.465
7 10.466 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET clk:[F] clk:[R] -10.000 0.012 0.465
8 10.473 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.472
9 10.479 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.477
10 10.479 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.477
11 10.482 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.480
12 10.482 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.480
13 10.482 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.480
14 10.482 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.480
15 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
16 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
17 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
18 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
19 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
20 10.485 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR clk:[F] clk:[R] -10.000 0.012 0.483
21 10.593 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.592
22 10.593 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.592
23 10.593 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.592
24 10.593 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.592
25 10.593 gw_gao_inst_0/u_la0_top/rst_ao_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk:[F] clk:[R] -10.000 0.012 0.592

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
2 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
3 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/start_reg_s0
4 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
5 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_174_s0
6 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_142_s0
7 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_78_s0
8 8.911 9.911 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_104_s0
9 8.911 9.911 1.000 Low Pulse Width clk controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0
10 8.911 9.911 1.000 Low Pulse Width clk controller_3p3z_inst/controller_3p3z_inst_0/spram_En12/mem[5]_6_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 14.890
Data Arrival Time 6.000
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0
To controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_1_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/CLK
1.158 0.232 tC2Q RF 44 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q
1.863 0.706 tNET FF 1 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/I2
2.418 0.555 tINS FF 48 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/F
4.245 1.827 tNET FF 1 R42C20[3][A] controller_3p3z_inst/controller_3p3z_inst_0/n795_s0/I2
4.698 0.453 tINS FF 2 R42C20[3][A] controller_3p3z_inst/controller_3p3z_inst_0/n795_s0/F
6.000 1.302 tNET FF 1 R39C15[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R39C15[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_1_s1/CLK
20.891 -0.035 tSu 1 R39C15[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.008, 19.864%; route: 3.835, 75.565%; tC2Q: 0.232, 4.572%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack 14.914
Data Arrival Time 5.976
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.158 0.232 tC2Q RF 16 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
2.145 0.987 tNET FF 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/I2
2.715 0.570 tINS FR 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/F
2.716 0.001 tNET RR 1 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I2
3.271 0.555 tINS RF 2 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F
3.961 0.690 tNET FF 1 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1
4.414 0.453 tINS FF 10 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F
5.262 0.848 tNET FF 1 R20C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
5.832 0.570 tINS FR 1 R20C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
5.977 0.144 tNET RR 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
20.891 -0.035 tSu 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.148, 42.529%; route: 2.671, 52.878%; tC2Q: 0.232, 4.593%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack 15.065
Data Arrival Time 5.826
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.980 0.822 tNET FF 1 R26C18[3][B] input_gen_inst/data_valid_i_s2/I1
2.433 0.453 tINS FF 27 R26C18[3][B] input_gen_inst/data_valid_i_s2/F
3.926 1.493 tNET FF 1 R38C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s3/I1
4.481 0.555 tINS FF 2 R38C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s3/F
4.732 0.252 tNET FF 1 R36C17[3][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s2/I0
5.281 0.549 tINS FR 2 R36C17[3][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s2/F
5.826 0.545 tNET RR 1 R35C21[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R35C21[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_1_s0/CLK
20.891 -0.035 tSu 1 R35C21[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.557, 31.774%; route: 3.111, 63.492%; tC2Q: 0.232, 4.734%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack 15.080
Data Arrival Time 5.811
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.158 0.232 tC2Q RF 16 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
2.145 0.987 tNET FF 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/I2
2.715 0.570 tINS FR 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/F
2.716 0.001 tNET RR 1 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I2
3.271 0.555 tINS RF 2 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F
3.961 0.690 tNET FF 1 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1
4.414 0.453 tINS FF 10 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F
5.262 0.848 tNET FF 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1082_s1/I2
5.811 0.549 tINS FR 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1082_s1/F
5.811 0.000 tNET RR 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.891 -0.035 tSu 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.127, 43.537%; route: 2.526, 51.714%; tC2Q: 0.232, 4.749%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack 15.080
Data Arrival Time 5.811
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.158 0.232 tC2Q RF 16 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
2.145 0.987 tNET FF 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/I2
2.715 0.570 tINS FR 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/F
2.716 0.001 tNET RR 1 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I2
3.271 0.555 tINS RF 2 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F
3.961 0.690 tNET FF 1 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1
4.414 0.453 tINS FF 10 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F
5.262 0.848 tNET FF 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1080_s1/I3
5.811 0.549 tINS FR 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1080_s1/F
5.811 0.000 tNET RR 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.891 -0.035 tSu 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.127, 43.537%; route: 2.526, 51.714%; tC2Q: 0.232, 4.749%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack 15.097
Data Arrival Time 5.794
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.980 0.822 tNET FF 1 R26C18[3][B] input_gen_inst/data_valid_i_s2/I1
2.433 0.453 tINS FF 27 R26C18[3][B] input_gen_inst/data_valid_i_s2/F
3.926 1.493 tNET FF 1 R38C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s3/I1
4.481 0.555 tINS FF 2 R38C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s3/F
4.732 0.252 tNET FF 1 R36C17[3][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s2/I0
5.281 0.549 tINS FR 2 R36C17[3][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s2/F
5.794 0.513 tNET RR 1 R36C21[1][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R36C21[1][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s0/CLK
20.891 -0.035 tSu 1 R36C21[1][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_chn_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.557, 31.983%; route: 3.079, 63.252%; tC2Q: 0.232, 4.766%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack 15.322
Data Arrival Time 5.569
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/CLK
1.158 0.232 tC2Q RF 4 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q
2.409 1.252 tNET FF 2 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/I1
2.780 0.371 tINS FF 1 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/COUT
2.780 0.000 tNET FF 2 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/CIN
2.816 0.035 tINS FF 1 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/COUT
2.816 0.000 tNET FF 2 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/CIN
2.851 0.035 tINS FF 1 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/COUT
2.851 0.000 tNET FF 2 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/CIN
2.886 0.035 tINS FF 1 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/COUT
2.886 0.000 tNET FF 2 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/CIN
2.921 0.035 tINS FF 1 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/COUT
2.921 0.000 tNET FF 2 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/CIN
2.956 0.035 tINS FF 30 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/COUT
4.277 1.321 tNET FF 1 R44C14[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1412_s2/I2
4.826 0.549 tINS FR 1 R44C14[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1412_s2/F
4.999 0.172 tNET RR 1 R44C15[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1412_s0/I1
5.569 0.570 tINS RR 1 R44C15[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1412_s0/F
5.569 0.000 tNET RR 1 R44C15[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R44C15[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_7_s0/CLK
20.891 -0.035 tSu 1 R44C15[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.666, 35.881%; route: 2.745, 59.122%; tC2Q: 0.232, 4.997%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack 15.339
Data Arrival Time 5.552
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/CLK
1.158 0.232 tC2Q RF 4 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q
2.093 0.936 tNET FF 2 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/I0
2.642 0.549 tINS FR 1 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/COUT
2.642 0.000 tNET RR 2 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/CIN
2.678 0.035 tINS RF 1 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/COUT
2.678 0.000 tNET FF 2 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/CIN
2.713 0.035 tINS FF 1 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/COUT
2.713 0.000 tNET FF 2 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/CIN
2.748 0.035 tINS FF 1 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/COUT
2.748 0.000 tNET FF 2 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/CIN
2.783 0.035 tINS FF 1 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/COUT
2.783 0.000 tNET FF 2 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/CIN
2.818 0.035 tINS FF 1 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/COUT
2.818 0.000 tNET FF 2 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/CIN
2.854 0.035 tINS FF 1 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/COUT
2.854 0.000 tNET FF 2 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/CIN
2.889 0.035 tINS FF 1 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/COUT
2.889 0.000 tNET FF 2 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/CIN
2.924 0.035 tINS FF 1 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/COUT
2.924 0.000 tNET FF 2 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/CIN
2.959 0.035 tINS FF 1 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/COUT
2.959 0.000 tNET FF 2 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/CIN
2.994 0.035 tINS FF 1 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/COUT
2.994 0.000 tNET FF 2 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/CIN
3.030 0.035 tINS FF 1 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/COUT
3.030 0.000 tNET FF 2 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/CIN
3.065 0.035 tINS FF 1 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/COUT
3.065 0.000 tNET FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/CIN
3.100 0.035 tINS FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/COUT
3.745 0.645 tNET FF 1 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/I2
4.300 0.555 tINS FF 15 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/F
4.982 0.682 tNET FF 1 R42C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1419_s0/I3
5.552 0.570 tINS FR 1 R42C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1419_s0/F
5.552 0.000 tNET RR 1 R42C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R42C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_0_s0/CLK
20.891 -0.035 tSu 1 R42C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.132, 46.077%; route: 2.263, 48.908%; tC2Q: 0.232, 5.015%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack 15.339
Data Arrival Time 5.552
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/CLK
1.158 0.232 tC2Q RF 4 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q
2.093 0.936 tNET FF 2 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/I0
2.642 0.549 tINS FR 1 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/COUT
2.642 0.000 tNET RR 2 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/CIN
2.678 0.035 tINS RF 1 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/COUT
2.678 0.000 tNET FF 2 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/CIN
2.713 0.035 tINS FF 1 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/COUT
2.713 0.000 tNET FF 2 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/CIN
2.748 0.035 tINS FF 1 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/COUT
2.748 0.000 tNET FF 2 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/CIN
2.783 0.035 tINS FF 1 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/COUT
2.783 0.000 tNET FF 2 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/CIN
2.818 0.035 tINS FF 1 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/COUT
2.818 0.000 tNET FF 2 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/CIN
2.854 0.035 tINS FF 1 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/COUT
2.854 0.000 tNET FF 2 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/CIN
2.889 0.035 tINS FF 1 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/COUT
2.889 0.000 tNET FF 2 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/CIN
2.924 0.035 tINS FF 1 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/COUT
2.924 0.000 tNET FF 2 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/CIN
2.959 0.035 tINS FF 1 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/COUT
2.959 0.000 tNET FF 2 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/CIN
2.994 0.035 tINS FF 1 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/COUT
2.994 0.000 tNET FF 2 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/CIN
3.030 0.035 tINS FF 1 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/COUT
3.030 0.000 tNET FF 2 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/CIN
3.065 0.035 tINS FF 1 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/COUT
3.065 0.000 tNET FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/CIN
3.100 0.035 tINS FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/COUT
3.745 0.645 tNET FF 1 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/I2
4.300 0.555 tINS FF 15 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/F
4.982 0.682 tNET FF 1 R41C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s0/I3
5.552 0.570 tINS FR 1 R41C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s0/F
5.552 0.000 tNET RR 1 R41C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R41C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_14_s0/CLK
20.891 -0.035 tSu 1 R41C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.132, 46.077%; route: 2.263, 48.908%; tC2Q: 0.232, 5.015%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack 15.372
Data Arrival Time 5.519
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/CLK
1.158 0.232 tC2Q RF 4 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q
2.409 1.252 tNET FF 2 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/I1
2.780 0.371 tINS FF 1 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/COUT
2.780 0.000 tNET FF 2 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/CIN
2.816 0.035 tINS FF 1 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/COUT
2.816 0.000 tNET FF 2 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/CIN
2.851 0.035 tINS FF 1 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/COUT
2.851 0.000 tNET FF 2 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/CIN
2.886 0.035 tINS FF 1 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/COUT
2.886 0.000 tNET FF 2 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/CIN
2.921 0.035 tINS FF 1 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/COUT
2.921 0.000 tNET FF 2 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/CIN
2.956 0.035 tINS FF 30 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/COUT
4.227 1.271 tNET FF 1 R44C14[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1416_s2/I2
4.776 0.549 tINS FR 1 R44C14[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1416_s2/F
4.949 0.172 tNET RR 1 R43C14[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1416_s0/I1
5.519 0.570 tINS RR 1 R43C14[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1416_s0/F
5.519 0.000 tNET RR 1 R43C14[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R43C14[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_3_s0/CLK
20.891 -0.035 tSu 1 R43C14[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.666, 36.274%; route: 2.695, 58.675%; tC2Q: 0.232, 5.051%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack 15.379
Data Arrival Time 5.512
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
4.901 0.035 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/COUT
4.901 0.000 tNET FF 2 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/CIN
4.936 0.035 tINS FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/COUT
4.936 0.000 tNET FF 2 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/CIN
4.971 0.035 tINS FF 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/COUT
4.971 0.000 tNET FF 2 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/CIN
5.006 0.035 tINS FF 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/COUT
5.006 0.000 tNET FF 2 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n395_s/CIN
5.042 0.035 tINS FF 1 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n395_s/COUT
5.042 0.000 tNET FF 2 R34C20[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n394_s/CIN
5.512 0.470 tINS FF 1 R34C20[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n394_s/SUM
5.512 0.000 tNET FF 1 R34C20[1][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C20[1][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_15_s0/CLK
20.891 -0.035 tSu 1 R34C20[1][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.198, 47.935%; route: 2.156, 47.006%; tC2Q: 0.232, 5.059%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack 15.414
Data Arrival Time 5.476
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
4.901 0.035 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/COUT
4.901 0.000 tNET FF 2 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/CIN
4.936 0.035 tINS FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/COUT
4.936 0.000 tNET FF 2 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/CIN
4.971 0.035 tINS FF 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/COUT
4.971 0.000 tNET FF 2 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/CIN
5.006 0.035 tINS FF 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/COUT
5.006 0.000 tNET FF 2 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n395_s/CIN
5.476 0.470 tINS FF 1 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n395_s/SUM
5.476 0.000 tNET FF 1 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_14_s0/CLK
20.891 -0.035 tSu 1 R34C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.163, 47.532%; route: 2.156, 47.370%; tC2Q: 0.232, 5.098%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack 15.450
Data Arrival Time 5.441
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
4.901 0.035 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/COUT
4.901 0.000 tNET FF 2 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/CIN
4.936 0.035 tINS FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/COUT
4.936 0.000 tNET FF 2 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/CIN
4.971 0.035 tINS FF 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/COUT
4.971 0.000 tNET FF 2 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/CIN
5.441 0.470 tINS FF 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n396_s/SUM
5.441 0.000 tNET FF 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_13_s0/CLK
20.891 -0.035 tSu 1 R34C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.128, 47.123%; route: 2.156, 47.739%; tC2Q: 0.232, 5.138%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack 15.485
Data Arrival Time 5.406
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
4.901 0.035 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/COUT
4.901 0.000 tNET FF 2 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/CIN
4.936 0.035 tINS FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/COUT
4.936 0.000 tNET FF 2 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/CIN
5.406 0.470 tINS FF 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n397_s/SUM
5.406 0.000 tNET FF 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0/CLK
20.891 -0.035 tSu 1 R34C20[0][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.093, 46.707%; route: 2.156, 48.114%; tC2Q: 0.232, 5.178%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack 15.486
Data Arrival Time 5.405
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_un23_din_11_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/CLK
1.158 0.232 tC2Q RF 44 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q
1.863 0.706 tNET FF 1 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/I2
2.418 0.555 tINS FF 48 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/F
4.003 1.584 tNET FF 1 R40C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n785_s0/I2
4.374 0.371 tINS FF 2 R40C20[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n785_s0/F
5.405 1.031 tNET FF 1 R45C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_un23_din_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R45C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_un23_din_11_s1/CLK
20.891 -0.035 tSu 1 R45C20[1][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_un23_din_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 0.926, 20.674%; route: 3.321, 74.146%; tC2Q: 0.232, 5.180%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack 15.499
Data Arrival Time 5.391
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.158 0.232 tC2Q RF 16 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
2.145 0.987 tNET FF 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/I2
2.715 0.570 tINS FR 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/F
2.716 0.001 tNET RR 1 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I2
3.271 0.555 tINS RF 2 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F
3.961 0.690 tNET FF 1 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1
4.414 0.453 tINS FF 10 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F
4.842 0.428 tNET FF 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1078_s1/I3
5.391 0.549 tINS FR 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1078_s1/F
5.391 0.000 tNET RR 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
20.891 -0.035 tSu 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.127, 47.632%; route: 2.107, 47.173%; tC2Q: 0.232, 5.195%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack 15.499
Data Arrival Time 5.391
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.158 0.232 tC2Q RF 16 R18C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
2.145 0.987 tNET FF 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/I2
2.715 0.570 tINS FR 1 R12C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s12/F
2.716 0.001 tNET RR 1 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I2
3.271 0.555 tINS RF 2 R12C21[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F
3.961 0.690 tNET FF 1 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1
4.414 0.453 tINS FF 10 R18C22[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F
4.842 0.428 tNET FF 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1077_s1/I3
5.391 0.549 tINS FR 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1077_s1/F
5.391 0.000 tNET RR 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.891 -0.035 tSu 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.127, 47.632%; route: 2.107, 47.173%; tC2Q: 0.232, 5.195%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack 15.514
Data Arrival Time 5.376
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/CLK
1.158 0.232 tC2Q RF 4 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q
2.093 0.936 tNET FF 2 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/I0
2.642 0.549 tINS FR 1 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/COUT
2.642 0.000 tNET RR 2 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/CIN
2.678 0.035 tINS RF 1 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/COUT
2.678 0.000 tNET FF 2 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/CIN
2.713 0.035 tINS FF 1 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/COUT
2.713 0.000 tNET FF 2 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/CIN
2.748 0.035 tINS FF 1 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/COUT
2.748 0.000 tNET FF 2 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/CIN
2.783 0.035 tINS FF 1 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/COUT
2.783 0.000 tNET FF 2 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/CIN
2.818 0.035 tINS FF 1 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/COUT
2.818 0.000 tNET FF 2 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/CIN
2.854 0.035 tINS FF 1 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/COUT
2.854 0.000 tNET FF 2 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/CIN
2.889 0.035 tINS FF 1 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/COUT
2.889 0.000 tNET FF 2 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/CIN
2.924 0.035 tINS FF 1 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/COUT
2.924 0.000 tNET FF 2 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/CIN
2.959 0.035 tINS FF 1 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/COUT
2.959 0.000 tNET FF 2 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/CIN
2.994 0.035 tINS FF 1 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/COUT
2.994 0.000 tNET FF 2 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/CIN
3.030 0.035 tINS FF 1 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/COUT
3.030 0.000 tNET FF 2 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/CIN
3.065 0.035 tINS FF 1 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/COUT
3.065 0.000 tNET FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/CIN
3.100 0.035 tINS FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/COUT
3.745 0.645 tNET FF 1 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/I2
4.300 0.555 tINS FF 15 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/F
4.827 0.528 tNET FF 1 R44C13[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1414_s0/I3
5.376 0.549 tINS FR 1 R44C13[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1414_s0/F
5.376 0.000 tNET RR 1 R44C13[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R44C13[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_5_s0/CLK
20.891 -0.035 tSu 1 R44C13[1][B] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.111, 47.423%; route: 2.108, 47.364%; tC2Q: 0.232, 5.213%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack 15.517
Data Arrival Time 5.373
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_2_s0
To controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/mem[4]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R43C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_2_s0/CLK
1.158 0.232 tC2Q RF 45 R43C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_2_s0/Q
2.148 0.990 tNET FF 1 R30C19[3][A] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/n532_s1/I0
2.703 0.555 tINS FF 12 R30C19[3][A] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/n532_s1/F
3.855 1.153 tNET FF 1 R41C23[3][A] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/n595_s0/I3
4.404 0.549 tINS FR 16 R41C23[3][A] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/n595_s0/F
5.373 0.969 tNET RR 1 R43C20[2][B] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/mem[4]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R43C20[2][B] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/mem[4]_4_s0/CLK
20.891 -0.035 tSu 1 R43C20[2][B] controller_3p3z_inst/controller_3p3z_inst_0/spram_Un23/mem[4]_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.104, 24.822%; route: 3.112, 69.962%; tC2Q: 0.232, 5.216%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack 15.520
Data Arrival Time 5.371
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
4.901 0.035 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/COUT
4.901 0.000 tNET FF 2 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/CIN
5.371 0.470 tINS FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n398_s/SUM
5.371 0.000 tNET FF 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_11_s0/CLK
20.891 -0.035 tSu 1 R34C19[2][B] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.057, 46.285%; route: 2.156, 48.495%; tC2Q: 0.232, 5.219%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack 15.532
Data Arrival Time 5.359
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/CLK
1.158 0.232 tC2Q RF 4 R39C13[2][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_9_s1/Q
2.093 0.936 tNET FF 2 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/I0
2.642 0.549 tINS FR 1 R44C16[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s33/COUT
2.642 0.000 tNET RR 2 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/CIN
2.678 0.035 tINS RF 1 R44C16[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s34/COUT
2.678 0.000 tNET FF 2 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/CIN
2.713 0.035 tINS FF 1 R44C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s35/COUT
2.713 0.000 tNET FF 2 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/CIN
2.748 0.035 tINS FF 1 R44C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s36/COUT
2.748 0.000 tNET FF 2 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/CIN
2.783 0.035 tINS FF 1 R44C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s37/COUT
2.783 0.000 tNET FF 2 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/CIN
2.818 0.035 tINS FF 1 R44C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s38/COUT
2.818 0.000 tNET FF 2 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/CIN
2.854 0.035 tINS FF 1 R44C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s39/COUT
2.854 0.000 tNET FF 2 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/CIN
2.889 0.035 tINS FF 1 R44C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s40/COUT
2.889 0.000 tNET FF 2 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/CIN
2.924 0.035 tINS FF 1 R44C17[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s41/COUT
2.924 0.000 tNET FF 2 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/CIN
2.959 0.035 tINS FF 1 R44C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s42/COUT
2.959 0.000 tNET FF 2 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/CIN
2.994 0.035 tINS FF 1 R44C17[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s43/COUT
2.994 0.000 tNET FF 2 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/CIN
3.030 0.035 tINS FF 1 R44C18[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s44/COUT
3.030 0.000 tNET FF 2 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/CIN
3.065 0.035 tINS FF 1 R44C18[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s45/COUT
3.065 0.000 tNET FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/CIN
3.100 0.035 tINS FF 2 R44C18[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1386_s46/COUT
3.745 0.645 tNET FF 1 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/I2
4.300 0.555 tINS FF 15 R44C17[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1405_s3/F
4.988 0.688 tNET FF 1 R43C14[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1411_s0/I3
5.359 0.371 tINS FF 1 R43C14[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1411_s0/F
5.359 0.000 tNET FF 1 R43C14[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R43C14[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_8_s0/CLK
20.891 -0.035 tSu 1 R43C14[1][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.933, 43.597%; route: 2.268, 51.169%; tC2Q: 0.232, 5.234%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack 15.540
Data Arrival Time 5.351
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0
To controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_5_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/CLK
1.158 0.232 tC2Q RF 44 R38C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/cnt_mult_0_s0/Q
1.863 0.706 tNET FF 1 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/I2
2.418 0.555 tINS FF 48 R41C18[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1621_s4/F
3.997 1.578 tNET FF 1 R40C21[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n791_s0/I2
4.368 0.371 tINS FF 2 R40C21[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n791_s0/F
5.351 0.983 tNET FF 1 R39C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R39C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_5_s1/CLK
20.891 -0.035 tSu 1 R39C14[2][A] controller_3p3z_inst/controller_3p3z_inst_0/mult_a1_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 0.926, 20.928%; route: 3.267, 73.829%; tC2Q: 0.232, 5.243%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack 15.555
Data Arrival Time 5.336
Data Required Time 20.891
From input_gen_inst/data_cycle_1_s0
To controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R26C23[0][A] input_gen_inst/data_cycle_1_s0/CLK
1.158 0.232 tC2Q RF 40 R26C23[0][A] input_gen_inst/data_cycle_1_s0/Q
1.985 0.828 tNET FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/I2
2.438 0.453 tINS FF 1 R26C19[0][B] input_gen_inst/data_fdb_i_Z_3_s0/F
2.835 0.397 tNET FF 1 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/I3
3.352 0.517 tINS FF 2 R26C17[3][A] input_gen_inst/data_fdb_i_Z_3_s/F
4.283 0.931 tNET FF 2 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/I1
4.654 0.371 tINS FF 1 R34C18[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n406_s/COUT
4.654 0.000 tNET FF 2 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/CIN
4.690 0.035 tINS FF 1 R34C18[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n405_s/COUT
4.690 0.000 tNET FF 2 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/CIN
4.725 0.035 tINS FF 1 R34C18[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n404_s/COUT
4.725 0.000 tNET FF 2 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/CIN
4.760 0.035 tINS FF 1 R34C19[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n403_s/COUT
4.760 0.000 tNET FF 2 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/CIN
4.795 0.035 tINS FF 1 R34C19[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n402_s/COUT
4.795 0.000 tNET FF 2 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/CIN
4.830 0.035 tINS FF 1 R34C19[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n401_s/COUT
4.830 0.000 tNET FF 2 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/CIN
4.866 0.035 tINS FF 1 R34C19[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n400_s/COUT
4.866 0.000 tNET FF 2 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/CIN
5.336 0.470 tINS FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n399_s/SUM
5.336 0.000 tNET FF 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_10_s0/CLK
20.891 -0.035 tSu 1 R34C19[2][A] controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 2.022, 45.857%; route: 2.156, 48.883%; tC2Q: 0.232, 5.261%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack 15.563
Data Arrival Time 5.328
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/CLK
1.158 0.232 tC2Q RF 4 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q
2.409 1.252 tNET FF 2 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/I1
2.780 0.371 tINS FF 1 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/COUT
2.780 0.000 tNET FF 2 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/CIN
2.816 0.035 tINS FF 1 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/COUT
2.816 0.000 tNET FF 2 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/CIN
2.851 0.035 tINS FF 1 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/COUT
2.851 0.000 tNET FF 2 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/CIN
2.886 0.035 tINS FF 1 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/COUT
2.886 0.000 tNET FF 2 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/CIN
2.921 0.035 tINS FF 1 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/COUT
2.921 0.000 tNET FF 2 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/CIN
2.956 0.035 tINS FF 30 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/COUT
4.037 1.080 tNET FF 1 R43C16[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1408_s2/I2
4.586 0.549 tINS FR 1 R43C16[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1408_s2/F
4.758 0.172 tNET RR 1 R43C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1408_s0/I1
5.328 0.570 tINS RR 1 R43C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1408_s0/F
5.328 0.000 tNET RR 1 R43C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R43C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_11_s0/CLK
20.891 -0.035 tSu 1 R43C17[2][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.666, 37.842%; route: 2.504, 56.888%; tC2Q: 0.232, 5.270%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack 15.564
Data Arrival Time 5.327
Data Required Time 20.891
From controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1
To controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
0.926 0.243 tNET RR 1 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/CLK
1.158 0.232 tC2Q RF 4 R40C15[1][B] controller_3p3z_inst/controller_3p3z_inst_0/acc_out_17_s1/Q
2.409 1.252 tNET FF 2 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/I1
2.780 0.371 tINS FF 1 R43C16[1][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s41/COUT
2.780 0.000 tNET FF 2 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/CIN
2.816 0.035 tINS FF 1 R43C16[2][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s42/COUT
2.816 0.000 tNET FF 2 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/CIN
2.851 0.035 tINS FF 1 R43C16[2][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s43/COUT
2.851 0.000 tNET FF 2 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/CIN
2.886 0.035 tINS FF 1 R43C17[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s44/COUT
2.886 0.000 tNET FF 2 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/CIN
2.921 0.035 tINS FF 1 R43C17[0][B] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s45/COUT
2.921 0.000 tNET FF 2 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/CIN
2.956 0.035 tINS FF 30 R43C17[1][A] controller_3p3z_inst/controller_3p3z_inst_0/n1387_s46/COUT
4.227 1.271 tNET FF 1 R44C14[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1415_s2/I2
4.776 0.549 tINS FR 1 R44C14[3][B] controller_3p3z_inst/controller_3p3z_inst_0/n1415_s2/F
4.778 0.001 tNET RR 1 R44C14[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1415_s0/I1
5.327 0.549 tINS RR 1 R44C14[0][A] controller_3p3z_inst/controller_3p3z_inst_0/n1415_s0/F
5.327 0.000 tNET RR 1 R44C14[0][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R44C14[0][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_4_s0/CLK
20.891 -0.035 tSu 1 R44C14[0][A] controller_3p3z_inst/controller_3p3z_inst_0/u_data_o_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay cell: 1.645, 37.381%; route: 2.524, 57.347%; tC2Q: 0.232, 5.272%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA
0.872 0.012 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R10[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
0.872 0.012 tHld 1 BSRAM_R10[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.872 0.012 tHld 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872 0.012 tHld 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack 0.190
Data Arrival Time 1.062
Data Required Time 0.872
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062 0.202 tC2Q RR 17 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062 0.000 tNET RR 1 BSRAM_R28[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872 0.012 tHld 1 BSRAM_R28[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 0.213
Data Arrival Time 1.322
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_148_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R11C19[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_148_s0/CLK
1.062 0.202 tC2Q RR 1 R11C19[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_148_s0/Q
1.322 0.260 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 0.213
Data Arrival Time 1.322
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R11C10[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/CLK
1.062 0.202 tC2Q RR 1 R11C10[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q
1.322 0.260 tNET RR 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[2] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack 0.225
Data Arrival Time 1.334
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C13[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/CLK
1.062 0.202 tC2Q RR 1 R18C13[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/Q
1.334 0.272 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack 0.225
Data Arrival Time 1.334
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C12[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/CLK
1.062 0.202 tC2Q RR 1 R18C12[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q
1.334 0.272 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 0.225
Data Arrival Time 1.334
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R11C10[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK
1.062 0.202 tC2Q RR 1 R11C10[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q
1.334 0.272 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 0.225
Data Arrival Time 1.334
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C11[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/CLK
1.062 0.202 tC2Q RR 1 R18C11[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q
1.334 0.272 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_166_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C18[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_166_s0/CLK
1.062 0.202 tC2Q RR 1 R18C18[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_166_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C18[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/CLK
1.062 0.202 tC2Q RR 1 R18C18[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_165_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_164_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C18[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_164_s0/CLK
1.062 0.202 tC2Q RR 1 R18C18[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_164_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C14[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/CLK
1.062 0.202 tC2Q RR 1 R20C14[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[17]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_132_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C17[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_132_s0/CLK
1.062 0.202 tC2Q RR 1 R22C17[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_132_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R24C21[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/CLK
1.062 0.202 tC2Q RR 1 R24C21[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_127_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C14[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/CLK
1.062 0.202 tC2Q RR 1 R22C14[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 0.347
Data Arrival Time 1.456
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R18C9[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK
1.062 0.202 tC2Q RR 1 R18C9[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q
1.456 0.394 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[3] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 0.351
Data Arrival Time 1.460
Data Required Time 1.109
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R24C19[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/CLK
1.062 0.202 tC2Q RR 1 R24C19[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q
1.460 0.398 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.109 0.249 tHld 1 BSRAM_R28[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 8.751
Data Arrival Time 12.140
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.140 0.959 tNET FF 1 R18C25[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C25[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
20.891 -0.035 tSu 1 R18C25[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.959, 80.522%; tC2Q: 0.232, 19.478%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack 8.751
Data Arrival Time 12.140
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.140 0.959 tNET FF 1 R18C25[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C25[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
20.891 -0.035 tSu 1 R18C25[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.959, 80.522%; tC2Q: 0.232, 19.478%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack 8.819
Data Arrival Time 12.072
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.072 0.891 tNET FF 1 R11C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
20.891 -0.035 tSu 1 R11C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.891, 79.336%; tC2Q: 0.232, 20.664%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack 8.819
Data Arrival Time 12.072
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.072 0.891 tNET FF 1 R11C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
20.891 -0.035 tSu 1 R11C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.891, 79.336%; tC2Q: 0.232, 20.664%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack 8.819
Data Arrival Time 12.072
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.072 0.891 tNET FF 1 R11C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
20.891 -0.035 tSu 1 R11C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.891, 79.336%; tC2Q: 0.232, 20.664%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack 8.819
Data Arrival Time 12.072
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.072 0.891 tNET FF 1 R11C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
20.891 -0.035 tSu 1 R11C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.891, 79.336%; tC2Q: 0.232, 20.664%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack 8.877
Data Arrival Time 12.014
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.014 0.833 tNET FF 1 R16C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R16C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
20.891 -0.035 tSu 1 R16C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.833, 78.222%; tC2Q: 0.232, 21.778%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack 8.976
Data Arrival Time 11.914
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.914 0.734 tNET FF 1 R20C24[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C24[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
20.891 -0.035 tSu 1 R20C24[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.734, 75.971%; tC2Q: 0.232, 24.029%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack 8.976
Data Arrival Time 11.914
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.914 0.734 tNET FF 1 R20C24[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C24[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
20.891 -0.035 tSu 1 R20C24[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.734, 75.971%; tC2Q: 0.232, 24.029%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack 8.976
Data Arrival Time 11.914
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.914 0.734 tNET FF 1 R20C24[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C24[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
20.891 -0.035 tSu 1 R20C24[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.734, 75.971%; tC2Q: 0.232, 24.029%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack 8.976
Data Arrival Time 11.914
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.914 0.734 tNET FF 1 R20C24[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C24[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
20.891 -0.035 tSu 1 R20C24[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.734, 75.971%; tC2Q: 0.232, 24.029%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack 8.976
Data Arrival Time 11.914
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.914 0.734 tNET FF 1 R20C24[1][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R20C24[1][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
20.891 -0.035 tSu 1 R20C24[1][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.734, 75.971%; tC2Q: 0.232, 24.029%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack 8.994
Data Arrival Time 11.897
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.897 0.716 tNET FF 1 R17C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
20.891 -0.035 tSu 1 R17C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.716, 75.536%; tC2Q: 0.232, 24.464%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack 8.994
Data Arrival Time 11.897
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.897 0.716 tNET FF 1 R17C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
20.891 -0.035 tSu 1 R17C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.716, 75.536%; tC2Q: 0.232, 24.464%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack 8.994
Data Arrival Time 11.897
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.897 0.716 tNET FF 1 R17C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
20.891 -0.035 tSu 1 R17C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.716, 75.536%; tC2Q: 0.232, 24.464%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack 8.994
Data Arrival Time 11.897
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.897 0.716 tNET FF 1 R17C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
20.891 -0.035 tSu 1 R17C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.716, 75.536%; tC2Q: 0.232, 24.464%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack 8.995
Data Arrival Time 11.896
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.896 0.715 tNET FF 1 R18C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
20.891 -0.035 tSu 1 R18C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.715, 75.500%; tC2Q: 0.232, 24.500%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack 8.999
Data Arrival Time 11.891
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.891 0.711 tNET FF 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
20.891 -0.035 tSu 1 R18C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.711, 75.387%; tC2Q: 0.232, 24.613%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack 8.999
Data Arrival Time 11.891
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.891 0.711 tNET FF 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.891 -0.035 tSu 1 R18C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.711, 75.387%; tC2Q: 0.232, 24.613%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack 9.012
Data Arrival Time 11.878
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.878 0.698 tNET FF 1 R11C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
20.891 -0.035 tSu 1 R11C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.698, 75.041%; tC2Q: 0.232, 24.959%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack 9.012
Data Arrival Time 11.878
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.878 0.698 tNET FF 1 R11C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
20.891 -0.035 tSu 1 R11C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.698, 75.041%; tC2Q: 0.232, 24.959%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack 9.012
Data Arrival Time 11.878
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.878 0.698 tNET FF 1 R11C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R11C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
20.891 -0.035 tSu 1 R11C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.698, 75.041%; tC2Q: 0.232, 24.959%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack 9.033
Data Arrival Time 11.858
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.858 0.677 tNET FF 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
20.891 -0.035 tSu 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.677, 74.484%; tC2Q: 0.232, 25.516%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack 9.033
Data Arrival Time 11.858
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.858 0.677 tNET FF 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
20.891 -0.035 tSu 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.677, 74.484%; tC2Q: 0.232, 25.516%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack 9.033
Data Arrival Time 11.858
Data Required Time 20.891
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.688 0.688 tINS FF 1753 IOT27[A] clk_ibuf/O
10.949 0.261 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181 0.232 tC2Q FF 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.858 0.677 tNET FF 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
20.683 0.683 tINS RR 1753 IOT27[A] clk_ibuf/O
20.926 0.243 tNET RR 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
20.891 -0.035 tSu 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.023
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.677, 74.484%; tC2Q: 0.232, 25.516%
Required Clock Path Delay cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.339
Data Arrival Time 11.210
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.210 0.136 tNET RR 1 R21C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.871 0.011 tHld 1 R21C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.136, 40.192%; tC2Q: 0.202, 59.808%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack 10.461
Data Arrival Time 11.332
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.332 0.258 tNET RR 1 R20C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
0.871 0.011 tHld 1 R20C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack 10.461
Data Arrival Time 11.332
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.332 0.258 tNET RR 1 R23C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R23C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.871 0.011 tHld 1 R23C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack 10.461
Data Arrival Time 11.332
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.332 0.258 tNET RR 1 R23C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R23C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871 0.011 tHld 1 R23C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack 10.466
Data Arrival Time 11.337
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.337 0.263 tNET RR 1 R22C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.871 0.011 tHld 1 R22C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.263, 56.533%; tC2Q: 0.202, 43.467%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 10.466
Data Arrival Time 11.337
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.337 0.263 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
0.871 0.011 tHld 1 R21C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.263, 56.533%; tC2Q: 0.202, 43.467%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 10.466
Data Arrival Time 11.337
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.337 0.263 tNET RR 1 R22C22[0][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C22[0][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
0.871 0.011 tHld 1 R22C22[0][B] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.263, 56.533%; tC2Q: 0.202, 43.467%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack 10.473
Data Arrival Time 11.344
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.344 0.270 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871 0.011 tHld 1 R22C24[2][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack 10.479
Data Arrival Time 11.349
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.349 0.275 tNET RR 1 R22C23[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C23[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871 0.011 tHld 1 R22C23[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.275, 57.691%; tC2Q: 0.202, 42.309%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack 10.479
Data Arrival Time 11.349
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.349 0.275 tNET RR 1 R22C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R22C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871 0.011 tHld 1 R22C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.275, 57.691%; tC2Q: 0.202, 42.309%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 10.482
Data Arrival Time 11.352
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.352 0.278 tNET RR 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871 0.011 tHld 1 R20C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.278, 57.956%; tC2Q: 0.202, 42.044%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 10.482
Data Arrival Time 11.352
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.352 0.278 tNET RR 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.871 0.011 tHld 1 R20C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.278, 57.956%; tC2Q: 0.202, 42.044%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack 10.482
Data Arrival Time 11.352
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.352 0.278 tNET RR 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871 0.011 tHld 1 R20C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.278, 57.956%; tC2Q: 0.202, 42.044%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack 10.482
Data Arrival Time 11.352
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.352 0.278 tNET RR 1 R20C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R20C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871 0.011 tHld 1 R20C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.278, 57.956%; tC2Q: 0.202, 42.044%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871 0.011 tHld 1 R21C24[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871 0.011 tHld 1 R21C24[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871 0.011 tHld 1 R21C24[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871 0.011 tHld 1 R21C24[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.871 0.011 tHld 1 R21C24[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack 10.485
Data Arrival Time 11.355
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.355 0.281 tNET RR 1 R21C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R21C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.871 0.011 tHld 1 R21C24[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.281, 58.217%; tC2Q: 0.202, 41.783%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 10.593
Data Arrival Time 11.464
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.464 0.390 tNET RR 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871 0.011 tHld 1 R17C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 10.593
Data Arrival Time 11.464
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.464 0.390 tNET RR 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871 0.011 tHld 1 R17C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 10.593
Data Arrival Time 11.464
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.464 0.390 tNET RR 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871 0.011 tHld 1 R17C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 10.593
Data Arrival Time 11.464
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.464 0.390 tNET RR 1 R17C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R17C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871 0.011 tHld 1 R17C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 10.593
Data Arrival Time 11.464
Data Required Time 0.871
From gw_gao_inst_0/u_la0_top/rst_ao_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF 1 IOT27[A] clk_ibuf/I
10.677 0.678 tINS FF 1753 IOT27[A] clk_ibuf/O
10.872 0.195 tNET FF 1 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074 0.202 tC2Q FR 55 R21C22[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.464 0.390 tNET RR 1 R17C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
0.675 0.675 tINS RR 1753 IOT27[A] clk_ibuf/O
0.860 0.184 tNET RR 1 R17C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871 0.011 tHld 1 R17C22[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK

MPW2

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK

MPW3

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/start_reg_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/start_reg_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/start_reg_s0/CLK

MPW4

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK

MPW5

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_174_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_174_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_174_s0/CLK

MPW6

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_142_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_142_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_142_s0/CLK

MPW7

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_78_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_78_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_78_s0/CLK

MPW8

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_104_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_104_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_104_s0/CLK

MPW9

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR controller_3p3z_inst/controller_3p3z_inst_0/ram_en0_din_12_s0/CLK

MPW10

MPW Summary:

Slack: 8.911
Actual Width: 9.911
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: controller_3p3z_inst/controller_3p3z_inst_0/spram_En12/mem[5]_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
10.688 0.688 tINS FF clk_ibuf/O
10.949 0.261 tNET FF controller_3p3z_inst/controller_3p3z_inst_0/spram_En12/mem[5]_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR clk_ibuf/I
20.676 0.675 tINS RR clk_ibuf/O
20.860 0.184 tNET RR controller_3p3z_inst/controller_3p3z_inst_0/spram_En12/mem[5]_6_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1753 clk_d 8.751 0.261
659 control0[0] 23.072 0.912
256 ram_a1_addrb[0] 15.869 2.328
209 n20_3 42.434 2.032
188 data_out_shift_reg_185_7 42.434 2.141
173 n1444_5 43.261 1.583
157 n1444_4 42.711 2.258
133 param_valid_i 17.659 2.074
128 n336_3 16.510 1.951
128 ram_a1_addrb[1] 16.576 2.695

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R34C19 91.67%
R11C20 90.28%
R29C20 90.28%
R34C18 90.28%
R11C14 88.89%
R36C22 88.89%
R40C15 88.89%
R29C21 88.89%
R11C18 87.50%
R29C12 87.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk}] -group [get_clocks {tck_pad_i}]