Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_verify\1.9.8.09\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign(1)\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign\project\src\gowin_rpll\gowin_rpll.v
E:\IP_verify\1.9.8.09\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign(1)\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign\project\src\psram_memory_interface_hs_v2\psram_memory_interface_hs_v2.v
E:\IP_verify\1.9.8.09\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign(1)\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign\project\src\psram_syn_top.v
E:\IP_verify\1.9.8.09\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign(1)\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign\project\src\psram_test.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.8.09\IDE\data\ipcores\gw_jtag.v
E:\IP_verify\1.9.8.09\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign(1)\Gowin_PSRAM_Memory_Interface_HS_V2.0_refDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09
Part Number GW2AR-LV18EQ144PC8/I7
Device GW2AR-18C
Created Time Fri Oct 28 15:00:49 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module psram_syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.791s, Peak memory usage = 347.145MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 347.145MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 347.145MB
    Optimizing Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 347.145MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 347.145MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 347.145MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 347.145MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 347.145MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 347.145MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 347.145MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 347.145MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 347.145MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 347.145MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 347.145MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 347.145MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 8
Embedded Port 26
I/O Buf 32
    IBUF 5
    OBUF 7
    IOBUF 18
    ELVDS_OBUF 2
Register 1443
    DFF 203
    DFFP 5
    DFFPE 39
    DFFC 451
    DFFCE 739
    DFFNP 2
    DFFNC 4
LUT 1658
    LUT2 299
    LUT3 515
    LUT4 844
MUX 1
    MUX16 1
ALU 98
    ALU 98
INV 9
    INV 9
IOLOGIC 54
    IDES4 16
    OSER4 22
    IODELAY 16
BSRAM 8
    SDPX9B 8
CLOCK 4
    CLKDIV 1
    DHCEN 2
    rPLL 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1773(1675 LUTs, 98 ALUs) / 20736 9%
Register 1443 / 15990 9%
  --Register as Latch 0 / 15990 0%
  --Register as FF 1443 / 15990 9%
BSRAM 8 / 46 17%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
your_instance_name/rpll_inst/CLKOUT.default_gen_clk Generated 8.333 120.0 0.000 4.167 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 8.333 120.0 2.083 6.250 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Generated 33.333 30.0 0.000 16.667 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 25.000 40.0 0.000 12.500 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3
u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 16.667 60.0 0.000 8.333 your_instance_name/rpll_inst/CLKOUT your_instance_name/rpll_inst/CLKOUT.default_gen_clk u_psram_top/u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk 30.0(MHz) 278.1(MHz) 5 TOP
2 u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk 60.0(MHz) 224.0(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.550
Data Arrival Time 1.662
Data Required Time 5.212
From u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_top/u_psram_top/u_dqce_clk_x2
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.013 1.013 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.193 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.425 0.232 tC2Q RF 7 u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0/Q
1.662 0.237 tNET FF 1 u_psram_top/u_psram_top/u_dqce_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
4.167 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
5.196 1.029 tCL FF 1 your_instance_name/rpll_inst/CLKOUT
5.433 0.237 tNET FF 3 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKIN
5.398 -0.035 tUnc u_psram_top/u_psram_top/u_dqce_clk_x2
5.212 -0.186 tSu 1 u_psram_top/u_psram_top/u_dqce_clk_x2
Path Statistics:
Clock Skew: 0.073
Setup Relationship: 4.167
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 5.631
Data Arrival Time 1.662
Data Required Time 7.293
From u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_top/u_psram_top/u_dqce_clk_x2p
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUTP.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.013 1.013 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.193 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.425 0.232 tC2Q RF 7 u_psram_top/u_psram_top/u_psram_sync/cs_memsync_4_s0/Q
1.662 0.237 tNET FF 1 u_psram_top/u_psram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk
7.277 1.027 tCL FF 1 your_instance_name/rpll_inst/CLKOUTP
7.514 0.237 tNET FF 3 u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKIN
7.479 -0.035 tUnc u_psram_top/u_psram_top/u_dqce_clk_x2p
7.293 -0.186 tSu 1 u_psram_top/u_psram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.071
Setup Relationship: 6.250
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 9.050
Data Arrival Time 0.819
Data Required Time 9.870
From u_psram_top/u_psram_top/u_psram_init/calib_1_s0
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1086 u_psram_top/u_psram_top/clkdiv/CLKOUT
0.350 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/CLK
0.582 0.232 tC2Q RF 11 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/Q
0.819 0.237 tNET FF 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.363 1.029 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.543 0.180 tNET RR 3 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKIN
9.725 0.182 tINS RR 38 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKOUT
9.905 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
9.870 -0.035 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
9.870 0.000 tSu 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Path Statistics:
Clock Skew: 1.221
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack 9.050
Data Arrival Time 0.819
Data Required Time 9.870
From u_psram_top/u_psram_top/u_psram_init/calib_1_s0
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1086 u_psram_top/u_psram_top/clkdiv/CLKOUT
0.350 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/CLK
0.582 0.232 tC2Q RF 11 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/Q
0.819 0.237 tNET FF 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.363 1.029 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.543 0.180 tNET RR 3 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKIN
9.725 0.182 tINS RR 38 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKOUT
9.905 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
9.870 -0.035 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
9.870 0.000 tSu 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Path Statistics:
Clock Skew: 1.221
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 9.050
Data Arrival Time 0.819
Data Required Time 9.870
From u_psram_top/u_psram_top/u_psram_init/calib_1_s0
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1086 u_psram_top/u_psram_top/clkdiv/CLKOUT
0.350 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/CLK
0.582 0.232 tC2Q RF 11 u_psram_top/u_psram_top/u_psram_init/calib_1_s0/Q
0.819 0.237 tNET FF 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.363 1.029 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.543 0.180 tNET RR 3 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKIN
9.725 0.182 tINS RR 38 u_psram_top/u_psram_top/u_dqce_clk_x2/CLKOUT
9.905 0.180 tNET RR 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
9.870 -0.035 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
9.870 0.000 tSu 1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Path Statistics:
Clock Skew: 1.221
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%