Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Mon Aug 21 10:04:38 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 86.977MB
Running netlist conversion:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 86.977MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.689s, Peak memory usage = 86.977MB
    Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 86.977MB
    Optimizing Phase 2: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.956s, Peak memory usage = 86.977MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.361s, Peak memory usage = 86.977MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 86.977MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 86.977MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 86.977MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 86.977MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.237s, Peak memory usage = 86.977MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.431s, Peak memory usage = 86.977MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 33s, Peak memory usage = 96.535MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.829s, Peak memory usage = 96.535MB
Generate output files:
    CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.842s, Peak memory usage = 109.246MB
Total Time and Memory Usage CPU time = 0h 0m 38s, Elapsed time = 0h 0m 39s, Peak memory usage = 109.246MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 269
I/O Buf 267
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 34
Register 4217
    DFFSE 127
    DFFRE 2667
    DFFPE 17
    DFFCE 1406
LUT 6484
    LUT2 516
    LUT3 1945
    LUT4 4023
ALU 630
    ALU 630
SSRAM 24
    RAM16SDP4 24
INV 55
    INV 55
DSP
    MULT27X36 2
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 7313(6539 LUT, 630 ALU, 24 RAM16) / 23040 32%
Register 4217 / 23685 18%
  --Register as Latch 0 / 23685 0%
  --Register as FF 4217 / 23685 18%
BSRAM 32 / 56 58%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_in Base 10.000 100.0 0.000 5.000 clk_in_ibuf/I
jtag_TCK Base 10.000 100.0 0.000 5.000 jtag_TCK_ibuf/I
n37_6 Base 10.000 100.0 0.000 5.000 n37_s2/O
u_dm/u_s_jtag_dtm/n637_6 Base 10.000 100.0 0.000 5.000 u_dm/u_s_jtag_dtm/n637_s2/O
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.0 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.0(MHz) 85.0(MHz) 17 TOP
2 jtag_TCK 100.0(MHz) 305.1(MHz) 5 TOP
3 n37_6 100.0(MHz) 1643.7(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.762
Data Arrival Time 12.267
Data Required Time 10.505
From core/mem_addr_26_s0
To core/decoded_csr_0_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4104 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_26_s0/CLK
1.230 0.367 tC2Q RR 3 core/mem_addr_26_s0/Q
1.410 0.180 tNET RR 1 itcm_valid_s3/I0
1.915 0.505 tINS RR 8 itcm_valid_s3/F
2.095 0.180 tNET RR 1 itcm_valid_s4/I3
2.347 0.252 tINS RR 5 itcm_valid_s4/F
2.527 0.180 tNET RR 1 u_dm/wr_cleardebint_ena_s7/I0
3.032 0.505 tINS RR 5 u_dm/wr_cleardebint_ena_s7/F
3.212 0.180 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
3.717 0.505 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
3.897 0.180 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.149 0.252 tINS RR 70 u_dm/ram_addr_2_s2/F
4.329 0.180 tNET RR 1 u_dm/ram_addr_0_s0/I2
4.772 0.443 tINS RR 103 u_dm/ram_addr_0_s0/F
4.952 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/I2
5.395 0.443 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/F
5.575 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/I0
5.706 0.131 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/O
5.886 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s/I0
5.968 0.083 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_17_s/O
6.148 0.180 tNET RR 1 mem_rdata_17_s4/I0
6.654 0.505 tINS RR 1 mem_rdata_17_s4/F
6.834 0.180 tNET RR 1 mem_rdata_17_s3/I1
7.329 0.496 tINS RR 1 mem_rdata_17_s3/F
7.509 0.180 tNET RR 1 mem_rdata_17_s1/I0
8.014 0.505 tINS RR 2 mem_rdata_17_s1/F
8.194 0.180 tNET RR 1 core/mem_rdata_latched_1_s3/I1
8.690 0.496 tINS RR 6 core/mem_rdata_latched_1_s3/F
8.870 0.180 tNET RR 1 core/mem_rdata_latched_1_s1/I1
9.366 0.496 tINS RR 32 core/mem_rdata_latched_1_s1/F
9.546 0.180 tNET RR 1 core/n5306_s2/I0
10.051 0.505 tINS RR 4 core/n5306_s2/F
10.231 0.180 tNET RR 1 core/n5306_s4/I0
10.736 0.505 tINS RR 7 core/n5306_s4/F
10.916 0.180 tNET RR 1 core/n5306_s0/I1
11.412 0.496 tINS RR 69 core/n5306_s0/F
11.592 0.180 tNET RR 1 core/n5711_s1/I1
12.087 0.496 tINS RR 13 core/n5711_s1/F
12.267 0.180 tNET RR 1 core/decoded_csr_0_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4104 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_csr_0_s0/CLK
10.505 -0.358 tSu 1 core/decoded_csr_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.618, 66.793%; route: 3.420, 29.987%; tC2Q: 0.367, 3.220%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -1.762
Data Arrival Time 12.267
Data Required Time 10.505
From core/mem_addr_26_s0
To core/decoded_csr_1_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4104 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_26_s0/CLK
1.230 0.367 tC2Q RR 3 core/mem_addr_26_s0/Q
1.410 0.180 tNET RR 1 itcm_valid_s3/I0
1.915 0.505 tINS RR 8 itcm_valid_s3/F
2.095 0.180 tNET RR 1 itcm_valid_s4/I3
2.347 0.252 tINS RR 5 itcm_valid_s4/F
2.527 0.180 tNET RR 1 u_dm/wr_cleardebint_ena_s7/I0
3.032 0.505 tINS RR 5 u_dm/wr_cleardebint_ena_s7/F
3.212 0.180 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
3.717 0.505 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
3.897 0.180 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.149 0.252 tINS RR 70 u_dm/ram_addr_2_s2/F
4.329 0.180 tNET RR 1 u_dm/ram_addr_0_s0/I2
4.772 0.443 tINS RR 103 u_dm/ram_addr_0_s0/F
4.952 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/I2
5.395 0.443 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/F
5.575 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/I0
5.706 0.131 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/O
5.886 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s/I0
5.968 0.083 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_17_s/O
6.148 0.180 tNET RR 1 mem_rdata_17_s4/I0
6.654 0.505 tINS RR 1 mem_rdata_17_s4/F
6.834 0.180 tNET RR 1 mem_rdata_17_s3/I1
7.329 0.496 tINS RR 1 mem_rdata_17_s3/F
7.509 0.180 tNET RR 1 mem_rdata_17_s1/I0
8.014 0.505 tINS RR 2 mem_rdata_17_s1/F
8.194 0.180 tNET RR 1 core/mem_rdata_latched_1_s3/I1
8.690 0.496 tINS RR 6 core/mem_rdata_latched_1_s3/F
8.870 0.180 tNET RR 1 core/mem_rdata_latched_1_s1/I1
9.366 0.496 tINS RR 32 core/mem_rdata_latched_1_s1/F
9.546 0.180 tNET RR 1 core/n5306_s2/I0
10.051 0.505 tINS RR 4 core/n5306_s2/F
10.231 0.180 tNET RR 1 core/n5306_s4/I0
10.736 0.505 tINS RR 7 core/n5306_s4/F
10.916 0.180 tNET RR 1 core/n5306_s0/I1
11.412 0.496 tINS RR 69 core/n5306_s0/F
11.592 0.180 tNET RR 1 core/n5711_s1/I1
12.087 0.496 tINS RR 13 core/n5711_s1/F
12.267 0.180 tNET RR 1 core/decoded_csr_1_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4104 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_csr_1_s0/CLK
10.505 -0.358 tSu 1 core/decoded_csr_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.618, 66.793%; route: 3.420, 29.987%; tC2Q: 0.367, 3.220%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -1.762
Data Arrival Time 12.267
Data Required Time 10.505
From core/mem_addr_26_s0
To core/decoded_csr_2_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4104 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_26_s0/CLK
1.230 0.367 tC2Q RR 3 core/mem_addr_26_s0/Q
1.410 0.180 tNET RR 1 itcm_valid_s3/I0
1.915 0.505 tINS RR 8 itcm_valid_s3/F
2.095 0.180 tNET RR 1 itcm_valid_s4/I3
2.347 0.252 tINS RR 5 itcm_valid_s4/F
2.527 0.180 tNET RR 1 u_dm/wr_cleardebint_ena_s7/I0
3.032 0.505 tINS RR 5 u_dm/wr_cleardebint_ena_s7/F
3.212 0.180 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
3.717 0.505 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
3.897 0.180 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.149 0.252 tINS RR 70 u_dm/ram_addr_2_s2/F
4.329 0.180 tNET RR 1 u_dm/ram_addr_0_s0/I2
4.772 0.443 tINS RR 103 u_dm/ram_addr_0_s0/F
4.952 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/I2
5.395 0.443 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/F
5.575 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/I0
5.706 0.131 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/O
5.886 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s/I0
5.968 0.083 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_17_s/O
6.148 0.180 tNET RR 1 mem_rdata_17_s4/I0
6.654 0.505 tINS RR 1 mem_rdata_17_s4/F
6.834 0.180 tNET RR 1 mem_rdata_17_s3/I1
7.329 0.496 tINS RR 1 mem_rdata_17_s3/F
7.509 0.180 tNET RR 1 mem_rdata_17_s1/I0
8.014 0.505 tINS RR 2 mem_rdata_17_s1/F
8.194 0.180 tNET RR 1 core/mem_rdata_latched_1_s3/I1
8.690 0.496 tINS RR 6 core/mem_rdata_latched_1_s3/F
8.870 0.180 tNET RR 1 core/mem_rdata_latched_1_s1/I1
9.366 0.496 tINS RR 32 core/mem_rdata_latched_1_s1/F
9.546 0.180 tNET RR 1 core/n5306_s2/I0
10.051 0.505 tINS RR 4 core/n5306_s2/F
10.231 0.180 tNET RR 1 core/n5306_s4/I0
10.736 0.505 tINS RR 7 core/n5306_s4/F
10.916 0.180 tNET RR 1 core/n5306_s0/I1
11.412 0.496 tINS RR 69 core/n5306_s0/F
11.592 0.180 tNET RR 1 core/n5711_s1/I1
12.087 0.496 tINS RR 13 core/n5711_s1/F
12.267 0.180 tNET RR 1 core/decoded_csr_2_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4104 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_csr_2_s0/CLK
10.505 -0.358 tSu 1 core/decoded_csr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.618, 66.793%; route: 3.420, 29.987%; tC2Q: 0.367, 3.220%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -1.762
Data Arrival Time 12.267
Data Required Time 10.505
From core/mem_addr_26_s0
To core/decoded_csr_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4104 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_26_s0/CLK
1.230 0.367 tC2Q RR 3 core/mem_addr_26_s0/Q
1.410 0.180 tNET RR 1 itcm_valid_s3/I0
1.915 0.505 tINS RR 8 itcm_valid_s3/F
2.095 0.180 tNET RR 1 itcm_valid_s4/I3
2.347 0.252 tINS RR 5 itcm_valid_s4/F
2.527 0.180 tNET RR 1 u_dm/wr_cleardebint_ena_s7/I0
3.032 0.505 tINS RR 5 u_dm/wr_cleardebint_ena_s7/F
3.212 0.180 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
3.717 0.505 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
3.897 0.180 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.149 0.252 tINS RR 70 u_dm/ram_addr_2_s2/F
4.329 0.180 tNET RR 1 u_dm/ram_addr_0_s0/I2
4.772 0.443 tINS RR 103 u_dm/ram_addr_0_s0/F
4.952 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/I2
5.395 0.443 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/F
5.575 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/I0
5.706 0.131 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/O
5.886 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s/I0
5.968 0.083 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_17_s/O
6.148 0.180 tNET RR 1 mem_rdata_17_s4/I0
6.654 0.505 tINS RR 1 mem_rdata_17_s4/F
6.834 0.180 tNET RR 1 mem_rdata_17_s3/I1
7.329 0.496 tINS RR 1 mem_rdata_17_s3/F
7.509 0.180 tNET RR 1 mem_rdata_17_s1/I0
8.014 0.505 tINS RR 2 mem_rdata_17_s1/F
8.194 0.180 tNET RR 1 core/mem_rdata_latched_1_s3/I1
8.690 0.496 tINS RR 6 core/mem_rdata_latched_1_s3/F
8.870 0.180 tNET RR 1 core/mem_rdata_latched_1_s1/I1
9.366 0.496 tINS RR 32 core/mem_rdata_latched_1_s1/F
9.546 0.180 tNET RR 1 core/n5306_s2/I0
10.051 0.505 tINS RR 4 core/n5306_s2/F
10.231 0.180 tNET RR 1 core/n5306_s4/I0
10.736 0.505 tINS RR 7 core/n5306_s4/F
10.916 0.180 tNET RR 1 core/n5306_s0/I1
11.412 0.496 tINS RR 69 core/n5306_s0/F
11.592 0.180 tNET RR 1 core/n5711_s1/I1
12.087 0.496 tINS RR 13 core/n5711_s1/F
12.267 0.180 tNET RR 1 core/decoded_csr_3_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4104 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_csr_3_s0/CLK
10.505 -0.358 tSu 1 core/decoded_csr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.618, 66.793%; route: 3.420, 29.987%; tC2Q: 0.367, 3.220%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -1.762
Data Arrival Time 12.267
Data Required Time 10.505
From core/mem_addr_26_s0
To core/decoded_csr_4_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4104 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_26_s0/CLK
1.230 0.367 tC2Q RR 3 core/mem_addr_26_s0/Q
1.410 0.180 tNET RR 1 itcm_valid_s3/I0
1.915 0.505 tINS RR 8 itcm_valid_s3/F
2.095 0.180 tNET RR 1 itcm_valid_s4/I3
2.347 0.252 tINS RR 5 itcm_valid_s4/F
2.527 0.180 tNET RR 1 u_dm/wr_cleardebint_ena_s7/I0
3.032 0.505 tINS RR 5 u_dm/wr_cleardebint_ena_s7/F
3.212 0.180 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
3.717 0.505 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
3.897 0.180 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.149 0.252 tINS RR 70 u_dm/ram_addr_2_s2/F
4.329 0.180 tNET RR 1 u_dm/ram_addr_0_s0/I2
4.772 0.443 tINS RR 103 u_dm/ram_addr_0_s0/F
4.952 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/I2
5.395 0.443 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s2/F
5.575 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/I0
5.706 0.131 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s0/O
5.886 0.180 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_17_s/I0
5.968 0.083 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_17_s/O
6.148 0.180 tNET RR 1 mem_rdata_17_s4/I0
6.654 0.505 tINS RR 1 mem_rdata_17_s4/F
6.834 0.180 tNET RR 1 mem_rdata_17_s3/I1
7.329 0.496 tINS RR 1 mem_rdata_17_s3/F
7.509 0.180 tNET RR 1 mem_rdata_17_s1/I0
8.014 0.505 tINS RR 2 mem_rdata_17_s1/F
8.194 0.180 tNET RR 1 core/mem_rdata_latched_1_s3/I1
8.690 0.496 tINS RR 6 core/mem_rdata_latched_1_s3/F
8.870 0.180 tNET RR 1 core/mem_rdata_latched_1_s1/I1
9.366 0.496 tINS RR 32 core/mem_rdata_latched_1_s1/F
9.546 0.180 tNET RR 1 core/n5306_s2/I0
10.051 0.505 tINS RR 4 core/n5306_s2/F
10.231 0.180 tNET RR 1 core/n5306_s4/I0
10.736 0.505 tINS RR 7 core/n5306_s4/F
10.916 0.180 tNET RR 1 core/n5306_s0/I1
11.412 0.496 tINS RR 69 core/n5306_s0/F
11.592 0.180 tNET RR 1 core/n5711_s1/I1
12.087 0.496 tINS RR 13 core/n5711_s1/F
12.267 0.180 tNET RR 1 core/decoded_csr_4_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4104 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_csr_4_s0/CLK
10.505 -0.358 tSu 1 core/decoded_csr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 7.618, 66.793%; route: 3.420, 29.987%; tC2Q: 0.367, 3.220%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%