Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Sun Aug 20 16:37:42 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_PicoRV32_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 87.496MB Running netlist conversion: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 87.496MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.679s, Peak memory usage = 87.496MB Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.261s, Peak memory usage = 87.496MB Optimizing Phase 2: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.95s, Peak memory usage = 87.496MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.306s, Peak memory usage = 87.496MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 87.496MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 87.496MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 87.496MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 87.496MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.261s, Peak memory usage = 87.496MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.444s, Peak memory usage = 87.496MB Tech-Mapping Phase 3: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 33s, Peak memory usage = 96.961MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.841s, Peak memory usage = 96.961MB Generate output files: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 1s, Peak memory usage = 115.066MB |
Total Time and Memory Usage | CPU time = 0h 0m 38s, Elapsed time = 0h 0m 40s, Peak memory usage = 115.066MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 269 |
I/O Buf | 267 |
    IBUF | 84 |
    OBUF | 147 |
    TBUF | 2 |
    IOBUF | 34 |
Register | 4225 |
    DFFSE | 127 |
    DFFRE | 2675 |
    DFFPE | 17 |
    DFFCE | 1406 |
LUT | 6565 |
    LUT2 | 560 |
    LUT3 | 2114 |
    LUT4 | 3891 |
ALU | 629 |
    ALU | 629 |
SSRAM | 24 |
    RAM16SDP4 | 24 |
INV | 54 |
    INV | 54 |
DSP | |
    MULT27X36 | 2 |
BSRAM | 128 |
    SDPB | 128 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 7392(6619 LUT, 629 ALU, 24 RAM16) / 138240 | 6% |
Register | 4225 / 139140 | 4% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 4225 / 139140 | 4% |
BSRAM | 128 / 340 | 38% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_in_ibuf/I | ||
jtag_TCK | Base | 10.000 | 100.0 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
n37_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | n37_s2/O | ||
u_dm/u_s_jtag_dtm/n637_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_dm/u_s_jtag_dtm/n637_s2/O | ||
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_in | 100.0(MHz) | 86.1(MHz) | 18 | TOP |
2 | jtag_TCK | 100.0(MHz) | 278.2(MHz) | 6 | TOP |
3 | n37_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -1.611 |
Data Arrival Time | 12.413 |
Data Required Time | 10.801 |
From | core/mem_addr_26_s0 |
To | core/mem_rdata_q_24_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.915 | 0.505 | tINS | RR | 11 | itcm_valid_s3/F |
2.095 | 0.180 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.347 | 0.252 | tINS | RR | 7 | itcm_valid_s4/F |
2.527 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.032 | 0.505 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.212 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
3.655 | 0.443 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
3.835 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
4.087 | 0.252 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
4.267 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
4.710 | 0.443 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
4.890 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_8_s2/I2 |
5.332 | 0.443 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_8_s2/F |
5.512 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_8_s0/I0 |
5.643 | 0.131 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_8_s0/O |
5.823 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_8_s/I0 |
5.906 | 0.083 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_8_s/O |
6.086 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s10/I3 |
6.338 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_24_s10/F |
6.518 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s6/I3 |
6.770 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_24_s6/F |
6.950 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s4/I0 |
7.455 | 0.505 | tINS | RR | 1 | core/mem_rdata_latched_24_s4/F |
7.635 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s11/I0 |
8.140 | 0.505 | tINS | RR | 4 | core/mem_rdata_latched_24_s11/F |
8.320 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s2/I0 |
8.826 | 0.505 | tINS | RR | 1 | core/mem_rdata_latched_24_s2/F |
9.006 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_24_s0/I1 |
9.501 | 0.496 | tINS | RR | 6 | core/mem_rdata_latched_24_s0/F |
9.681 | 0.180 | tNET | RR | 1 | core/n2210_s12/I0 |
10.186 | 0.505 | tINS | RR | 2 | core/n2210_s12/F |
10.366 | 0.180 | tNET | RR | 1 | core/n2210_s5/I1 |
10.862 | 0.496 | tINS | RR | 1 | core/n2210_s5/F |
11.042 | 0.180 | tNET | RR | 1 | core/n2210_s1/I0 |
11.547 | 0.505 | tINS | RR | 1 | core/n2210_s1/F |
11.727 | 0.180 | tNET | RR | 1 | core/n2210_s0/I0 |
12.233 | 0.505 | tINS | RR | 1 | core/n2210_s0/F |
12.413 | 0.180 | tNET | RR | 1 | core/mem_rdata_q_24_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/mem_rdata_q_24_s0/CLK |
10.801 | -0.061 | tSu | 1 | core/mem_rdata_q_24_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 7.583, 65.652%; route: 3.600, 31.169%; tC2Q: 0.367, 3.179% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | -1.496 |
Data Arrival Time | 12.297 |
Data Required Time | 10.801 |
From | core/mem_addr_26_s0 |
To | core/decoded_rs1_0_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.915 | 0.505 | tINS | RR | 11 | itcm_valid_s3/F |
2.095 | 0.180 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.347 | 0.252 | tINS | RR | 7 | itcm_valid_s4/F |
2.527 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.032 | 0.505 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.212 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
3.655 | 0.443 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
3.835 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
4.087 | 0.252 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
4.267 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
4.710 | 0.443 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
4.890 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/I2 |
5.332 | 0.443 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/F |
5.512 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/I0 |
5.643 | 0.131 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/O |
5.823 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/I0 |
5.906 | 0.083 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/O |
6.086 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s14/I3 |
6.338 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s14/F |
6.518 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s7/I3 |
6.770 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s7/F |
6.950 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s3/I0 |
7.455 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s3/F |
7.635 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s1/I0 |
8.140 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s1/F |
8.320 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_4_s3/I0 |
8.826 | 0.505 | tINS | RR | 8 | core/mem_rdata_latched_4_s3/F |
9.006 | 0.180 | tNET | RR | 1 | core/n5766_s6/I2 |
9.448 | 0.443 | tINS | RR | 2 | core/n5766_s6/F |
9.628 | 0.180 | tNET | RR | 1 | core/n5766_s3/I2 |
10.071 | 0.443 | tINS | RR | 10 | core/n5766_s3/F |
10.251 | 0.180 | tNET | RR | 1 | core/n5712_s9/I0 |
10.756 | 0.505 | tINS | RR | 3 | core/n5712_s9/F |
10.936 | 0.180 | tNET | RR | 1 | core/n5713_s1/I1 |
11.432 | 0.496 | tINS | RR | 3 | core/n5713_s1/F |
11.612 | 0.180 | tNET | RR | 1 | core/n5716_s0/I0 |
12.117 | 0.505 | tINS | RR | 1 | core/n5716_s0/F |
12.297 | 0.180 | tNET | RR | 1 | core/decoded_rs1_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/decoded_rs1_0_s0/CLK |
10.801 | -0.061 | tSu | 1 | core/decoded_rs1_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 7.468, 65.306%; route: 3.600, 31.483%; tC2Q: 0.367, 3.211% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | -1.496 |
Data Arrival Time | 12.297 |
Data Required Time | 10.801 |
From | core/mem_addr_26_s0 |
To | core/decoded_rs1_2_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.915 | 0.505 | tINS | RR | 11 | itcm_valid_s3/F |
2.095 | 0.180 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.347 | 0.252 | tINS | RR | 7 | itcm_valid_s4/F |
2.527 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.032 | 0.505 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.212 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
3.655 | 0.443 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
3.835 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
4.087 | 0.252 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
4.267 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
4.710 | 0.443 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
4.890 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/I2 |
5.332 | 0.443 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/F |
5.512 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/I0 |
5.643 | 0.131 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/O |
5.823 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/I0 |
5.906 | 0.083 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/O |
6.086 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s14/I3 |
6.338 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s14/F |
6.518 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s7/I3 |
6.770 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s7/F |
6.950 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s3/I0 |
7.455 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s3/F |
7.635 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s1/I0 |
8.140 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s1/F |
8.320 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_4_s3/I0 |
8.826 | 0.505 | tINS | RR | 8 | core/mem_rdata_latched_4_s3/F |
9.006 | 0.180 | tNET | RR | 1 | core/n5766_s6/I2 |
9.448 | 0.443 | tINS | RR | 2 | core/n5766_s6/F |
9.628 | 0.180 | tNET | RR | 1 | core/n5766_s3/I2 |
10.071 | 0.443 | tINS | RR | 10 | core/n5766_s3/F |
10.251 | 0.180 | tNET | RR | 1 | core/n5712_s9/I0 |
10.756 | 0.505 | tINS | RR | 3 | core/n5712_s9/F |
10.936 | 0.180 | tNET | RR | 1 | core/n5713_s1/I1 |
11.432 | 0.496 | tINS | RR | 3 | core/n5713_s1/F |
11.612 | 0.180 | tNET | RR | 1 | core/n5714_s0/I0 |
12.117 | 0.505 | tINS | RR | 1 | core/n5714_s0/F |
12.297 | 0.180 | tNET | RR | 1 | core/decoded_rs1_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/decoded_rs1_2_s0/CLK |
10.801 | -0.061 | tSu | 1 | core/decoded_rs1_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 7.468, 65.306%; route: 3.600, 31.483%; tC2Q: 0.367, 3.211% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | -1.496 |
Data Arrival Time | 12.297 |
Data Required Time | 10.801 |
From | core/mem_addr_26_s0 |
To | core/decoded_rs1_3_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.915 | 0.505 | tINS | RR | 11 | itcm_valid_s3/F |
2.095 | 0.180 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.347 | 0.252 | tINS | RR | 7 | itcm_valid_s4/F |
2.527 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.032 | 0.505 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.212 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
3.655 | 0.443 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
3.835 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
4.087 | 0.252 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
4.267 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
4.710 | 0.443 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
4.890 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/I2 |
5.332 | 0.443 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/F |
5.512 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/I0 |
5.643 | 0.131 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/O |
5.823 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/I0 |
5.906 | 0.083 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/O |
6.086 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s14/I3 |
6.338 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s14/F |
6.518 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s7/I3 |
6.770 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s7/F |
6.950 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s3/I0 |
7.455 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s3/F |
7.635 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s1/I0 |
8.140 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s1/F |
8.320 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_4_s3/I0 |
8.826 | 0.505 | tINS | RR | 8 | core/mem_rdata_latched_4_s3/F |
9.006 | 0.180 | tNET | RR | 1 | core/n5766_s6/I2 |
9.448 | 0.443 | tINS | RR | 2 | core/n5766_s6/F |
9.628 | 0.180 | tNET | RR | 1 | core/n5766_s3/I2 |
10.071 | 0.443 | tINS | RR | 10 | core/n5766_s3/F |
10.251 | 0.180 | tNET | RR | 1 | core/n5712_s9/I0 |
10.756 | 0.505 | tINS | RR | 3 | core/n5712_s9/F |
10.936 | 0.180 | tNET | RR | 1 | core/n5713_s1/I1 |
11.432 | 0.496 | tINS | RR | 3 | core/n5713_s1/F |
11.612 | 0.180 | tNET | RR | 1 | core/n5713_s0/I0 |
12.117 | 0.505 | tINS | RR | 1 | core/n5713_s0/F |
12.297 | 0.180 | tNET | RR | 1 | core/decoded_rs1_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/decoded_rs1_3_s0/CLK |
10.801 | -0.061 | tSu | 1 | core/decoded_rs1_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 7.468, 65.306%; route: 3.600, 31.483%; tC2Q: 0.367, 3.211% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | -1.496 |
Data Arrival Time | 12.297 |
Data Required Time | 10.801 |
From | core/mem_addr_26_s0 |
To | core/mem_rdata_q_29_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.915 | 0.505 | tINS | RR | 11 | itcm_valid_s3/F |
2.095 | 0.180 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.347 | 0.252 | tINS | RR | 7 | itcm_valid_s4/F |
2.527 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.032 | 0.505 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.212 | 0.180 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
3.655 | 0.443 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
3.835 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
4.087 | 0.252 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
4.267 | 0.180 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
4.710 | 0.443 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
4.890 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/I2 |
5.332 | 0.443 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s2/F |
5.512 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/I0 |
5.643 | 0.131 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s0/O |
5.823 | 0.180 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/I0 |
5.906 | 0.083 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_4_s/O |
6.086 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s14/I3 |
6.338 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s14/F |
6.518 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s7/I3 |
6.770 | 0.252 | tINS | RR | 1 | core/mem_rdata_latched_20_s7/F |
6.950 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s3/I0 |
7.455 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s3/F |
7.635 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_20_s1/I0 |
8.140 | 0.505 | tINS | RR | 2 | core/mem_rdata_latched_20_s1/F |
8.320 | 0.180 | tNET | RR | 1 | core/mem_rdata_latched_4_s3/I0 |
8.826 | 0.505 | tINS | RR | 8 | core/mem_rdata_latched_4_s3/F |
9.006 | 0.180 | tNET | RR | 1 | core/n5766_s6/I2 |
9.448 | 0.443 | tINS | RR | 2 | core/n5766_s6/F |
9.628 | 0.180 | tNET | RR | 1 | core/n5766_s3/I2 |
10.071 | 0.443 | tINS | RR | 10 | core/n5766_s3/F |
10.251 | 0.180 | tNET | RR | 1 | core/n2203_s4/I0 |
10.756 | 0.505 | tINS | RR | 1 | core/n2203_s4/F |
10.936 | 0.180 | tNET | RR | 1 | core/n2203_s2/I0 |
11.442 | 0.505 | tINS | RR | 3 | core/n2203_s2/F |
11.622 | 0.180 | tNET | RR | 1 | core/n2205_s0/I1 |
12.117 | 0.496 | tINS | RR | 1 | core/n2205_s0/F |
12.297 | 0.180 | tNET | RR | 1 | core/mem_rdata_q_29_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4304 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/mem_rdata_q_29_s0/CLK |
10.801 | -0.061 | tSu | 1 | core/mem_rdata_q_29_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 18 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 7.468, 65.306%; route: 3.600, 31.483%; tC2Q: 0.367, 3.211% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |