Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Sun Aug 20 16:12:35 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 82.363MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 82.363MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.677s, Peak memory usage = 82.363MB
    Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.255s, Peak memory usage = 82.363MB
    Optimizing Phase 2: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.943s, Peak memory usage = 82.363MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 82.363MB
    Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 82.363MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 82.363MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 82.363MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 82.363MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.231s, Peak memory usage = 82.363MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.42s, Peak memory usage = 82.363MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 33s, Peak memory usage = 95.012MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.826s, Peak memory usage = 95.012MB
Generate output files:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 1s, Peak memory usage = 105.691MB
Total Time and Memory Usage CPU time = 0h 0m 38s, Elapsed time = 0h 0m 39s, Peak memory usage = 105.691MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 269
I/O Buf 267
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 34
Register 4179
    DFF 242
    DFFE 1842
    DFFS 22
    DFFSE 105
    DFFR 170
    DFFRE 679
    DFFP 6
    DFFPE 11
    DFFC 161
    DFFCE 941
LUT 6461
    LUT2 446
    LUT3 2021
    LUT4 3994
ALU 591
    ALU 591
SSRAM 24
    RAM16SDP4 24
INV 53
    INV 53
DSP
    MULT36X36 1
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 7249(6514 LUT, 591 ALU, 24 RAM16) / 20736 35%
Register 4179 / 16173 26%
  --Register as Latch 0 / 16173 0%
  --Register as FF 4179 / 16173 26%
BSRAM 32 / 46 70%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_in Base 10.000 100.0 0.000 5.000 clk_in_ibuf/I
jtag_TCK Base 10.000 100.0 0.000 5.000 jtag_TCK_ibuf/I
n37_6 Base 10.000 100.0 0.000 5.000 n37_s2/O
u_dm/u_s_jtag_dtm/n637_6 Base 10.000 100.0 0.000 5.000 u_dm/u_s_jtag_dtm/n637_s2/O
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.0 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.0(MHz) 76.8(MHz) 17 TOP
2 jtag_TCK 100.0(MHz) 247.6(MHz) 6 TOP
3 n37_6 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -3.018
Data Arrival Time 13.846
Data Required Time 10.828
From core/mem_addr_27_s0
To core/mem_rdata_q_15_s1
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4065 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_27_s0/CLK
1.095 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.332 0.237 tNET FF 1 itcm_valid_s2/I1
1.887 0.555 tINS FF 5 itcm_valid_s2/F
2.124 0.237 tNET FF 1 itcm_valid_s3/I3
2.495 0.371 tINS FF 4 itcm_valid_s3/F
2.732 0.237 tNET FF 1 u_dm/wr_cleardebint_ena_s7/I0
3.249 0.517 tINS FF 5 u_dm/wr_cleardebint_ena_s7/F
3.486 0.237 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.003 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.240 0.237 tNET FF 1 u_dm/ram_addr_2_s2/I3
4.610 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
4.847 0.237 tNET FF 1 u_dm/ram_addr_0_s0/I2
5.300 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
5.537 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_7_s2/I2
5.990 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_7_s2/F
6.227 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_7_s0/I0
6.331 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_7_s0/O
6.568 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_7_s/I0
6.671 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_7_s/O
6.908 0.237 tNET FF 1 core/mem_rdata_latched_23_s6/I0
7.425 0.517 tINS FF 1 core/mem_rdata_latched_23_s6/F
7.662 0.237 tNET FF 1 core/mem_rdata_latched_23_s3/I0
8.179 0.517 tINS FF 2 core/mem_rdata_latched_23_s3/F
8.416 0.237 tNET FF 1 core/n2227_s8/I0
8.933 0.517 tINS FF 2 core/n2227_s8/F
9.170 0.237 tNET FF 1 core/n2227_s4/I1
9.725 0.555 tINS FF 1 core/n2227_s4/F
9.962 0.237 tNET FF 1 core/n2227_s9/I0
10.479 0.517 tINS FF 12 core/n2227_s9/F
10.716 0.237 tNET FF 1 core/n5772_s6/I0
11.233 0.517 tINS FF 13 core/n5772_s6/F
11.470 0.237 tNET FF 1 core/n5772_s4/I1
12.025 0.555 tINS FF 6 core/n5772_s4/F
12.262 0.237 tNET FF 1 core/n1860_s2/I1
12.817 0.555 tINS FF 2 core/n1860_s2/F
13.054 0.237 tNET FF 1 core/n1864_s8/I1
13.609 0.555 tINS FF 1 core/n1864_s8/F
13.846 0.237 tNET FF 1 core/mem_rdata_q_15_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4065 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/mem_rdata_q_15_s1/CLK
10.828 -0.035 tSu 1 core/mem_rdata_q_15_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.248, 63.529%; route: 4.503, 34.684%; tC2Q: 0.232, 1.787%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -3.018
Data Arrival Time 13.846
Data Required Time 10.828
From core/mem_addr_27_s0
To core/decoded_rd_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4065 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_27_s0/CLK
1.095 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.332 0.237 tNET FF 1 itcm_valid_s2/I1
1.887 0.555 tINS FF 5 itcm_valid_s2/F
2.124 0.237 tNET FF 1 itcm_valid_s3/I3
2.495 0.371 tINS FF 4 itcm_valid_s3/F
2.732 0.237 tNET FF 1 u_dm/wr_cleardebint_ena_s7/I0
3.249 0.517 tINS FF 5 u_dm/wr_cleardebint_ena_s7/F
3.486 0.237 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.003 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.240 0.237 tNET FF 1 u_dm/ram_addr_2_s2/I3
4.610 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
4.847 0.237 tNET FF 1 u_dm/ram_addr_0_s0/I2
5.300 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
5.537 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2
5.990 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F
6.227 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0
6.331 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O
6.568 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0
6.671 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_1_s/O
6.908 0.237 tNET FF 1 core/mem_rdata_latched_1_s9/I0
7.425 0.517 tINS FF 1 core/mem_rdata_latched_1_s9/F
7.662 0.237 tNET FF 1 core/mem_rdata_latched_1_s7/I1
8.217 0.555 tINS FF 1 core/mem_rdata_latched_1_s7/F
8.454 0.237 tNET FF 1 core/mem_rdata_latched_1_s4/I0
8.971 0.517 tINS FF 3 core/mem_rdata_latched_1_s4/F
9.208 0.237 tNET FF 1 core/mem_rdata_latched_1_s3/I0
9.725 0.517 tINS FF 1 core/mem_rdata_latched_1_s3/F
9.962 0.237 tNET FF 1 core/mem_rdata_latched_1_s1/I1
10.517 0.555 tINS FF 35 core/mem_rdata_latched_1_s1/F
10.754 0.237 tNET FF 1 core/n5772_s7/I0
11.271 0.517 tINS FF 2 core/n5772_s7/F
11.508 0.237 tNET FF 1 core/n5706_s3/I1
12.063 0.555 tINS FF 1 core/n5706_s3/F
12.300 0.237 tNET FF 1 core/n5706_s1/I1
12.855 0.555 tINS FF 2 core/n5706_s1/F
13.092 0.237 tNET FF 1 core/n5707_s0/I0
13.609 0.517 tINS FF 1 core/n5707_s0/F
13.846 0.237 tNET FF 1 core/decoded_rd_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4065 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_rd_3_s0/CLK
10.828 -0.035 tSu 1 core/decoded_rd_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.248, 63.529%; route: 4.503, 34.684%; tC2Q: 0.232, 1.787%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -3.018
Data Arrival Time 13.846
Data Required Time 10.828
From core/mem_addr_27_s0
To core/decoded_rd_4_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4065 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_27_s0/CLK
1.095 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.332 0.237 tNET FF 1 itcm_valid_s2/I1
1.887 0.555 tINS FF 5 itcm_valid_s2/F
2.124 0.237 tNET FF 1 itcm_valid_s3/I3
2.495 0.371 tINS FF 4 itcm_valid_s3/F
2.732 0.237 tNET FF 1 u_dm/wr_cleardebint_ena_s7/I0
3.249 0.517 tINS FF 5 u_dm/wr_cleardebint_ena_s7/F
3.486 0.237 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.003 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.240 0.237 tNET FF 1 u_dm/ram_addr_2_s2/I3
4.610 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
4.847 0.237 tNET FF 1 u_dm/ram_addr_0_s0/I2
5.300 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
5.537 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2
5.990 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F
6.227 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0
6.331 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O
6.568 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0
6.671 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_1_s/O
6.908 0.237 tNET FF 1 core/mem_rdata_latched_1_s9/I0
7.425 0.517 tINS FF 1 core/mem_rdata_latched_1_s9/F
7.662 0.237 tNET FF 1 core/mem_rdata_latched_1_s7/I1
8.217 0.555 tINS FF 1 core/mem_rdata_latched_1_s7/F
8.454 0.237 tNET FF 1 core/mem_rdata_latched_1_s4/I0
8.971 0.517 tINS FF 3 core/mem_rdata_latched_1_s4/F
9.208 0.237 tNET FF 1 core/mem_rdata_latched_1_s3/I0
9.725 0.517 tINS FF 1 core/mem_rdata_latched_1_s3/F
9.962 0.237 tNET FF 1 core/mem_rdata_latched_1_s1/I1
10.517 0.555 tINS FF 35 core/mem_rdata_latched_1_s1/F
10.754 0.237 tNET FF 1 core/n5772_s7/I0
11.271 0.517 tINS FF 2 core/n5772_s7/F
11.508 0.237 tNET FF 1 core/n5706_s3/I1
12.063 0.555 tINS FF 1 core/n5706_s3/F
12.300 0.237 tNET FF 1 core/n5706_s1/I1
12.855 0.555 tINS FF 2 core/n5706_s1/F
13.092 0.237 tNET FF 1 core/n5706_s0/I0
13.609 0.517 tINS FF 1 core/n5706_s0/F
13.846 0.237 tNET FF 1 core/decoded_rd_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4065 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_rd_4_s0/CLK
10.828 -0.035 tSu 1 core/decoded_rd_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.248, 63.529%; route: 4.503, 34.684%; tC2Q: 0.232, 1.787%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -3.018
Data Arrival Time 13.846
Data Required Time 10.828
From core/mem_addr_27_s0
To core/mem_rdata_q_27_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4065 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_27_s0/CLK
1.095 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.332 0.237 tNET FF 1 itcm_valid_s2/I1
1.887 0.555 tINS FF 5 itcm_valid_s2/F
2.124 0.237 tNET FF 1 itcm_valid_s3/I3
2.495 0.371 tINS FF 4 itcm_valid_s3/F
2.732 0.237 tNET FF 1 u_dm/wr_cleardebint_ena_s7/I0
3.249 0.517 tINS FF 5 u_dm/wr_cleardebint_ena_s7/F
3.486 0.237 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.003 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.240 0.237 tNET FF 1 u_dm/ram_addr_2_s2/I3
4.610 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
4.847 0.237 tNET FF 1 u_dm/ram_addr_0_s0/I2
5.300 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
5.537 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_14_s2/I2
5.990 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_14_s2/F
6.227 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_14_s0/I0
6.331 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_14_s0/O
6.568 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_14_s/I0
6.671 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_14_s/O
6.908 0.237 tNET FF 1 core/mem_rdata_latched_30_s9/I0
7.425 0.517 tINS FF 1 core/mem_rdata_latched_30_s9/F
7.662 0.237 tNET FF 1 core/mem_rdata_latched_30_s5/I0
8.179 0.517 tINS FF 1 core/mem_rdata_latched_30_s5/F
8.416 0.237 tNET FF 1 core/mem_rdata_latched_30_s4/I0
8.933 0.517 tINS FF 4 core/mem_rdata_latched_30_s4/F
9.170 0.237 tNET FF 1 core/n5332_s7/I0
9.687 0.517 tINS FF 23 core/n5332_s7/F
9.924 0.237 tNET FF 1 core/n5752_s1/I1
10.479 0.555 tINS FF 15 core/n5752_s1/F
10.716 0.237 tNET FF 1 core/n2206_s14/I1
11.271 0.555 tINS FF 4 core/n2206_s14/F
11.508 0.237 tNET FF 1 core/n2207_s19/I0
12.025 0.517 tINS FF 1 core/n2207_s19/F
12.262 0.237 tNET FF 1 core/n2207_s2/I1
12.817 0.555 tINS FF 1 core/n2207_s2/F
13.054 0.237 tNET FF 1 core/n2207_s0/I1
13.609 0.555 tINS FF 1 core/n2207_s0/F
13.846 0.237 tNET FF 1 core/mem_rdata_q_27_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4065 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/mem_rdata_q_27_s0/CLK
10.828 -0.035 tSu 1 core/mem_rdata_q_27_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.248, 63.529%; route: 4.503, 34.684%; tC2Q: 0.232, 1.787%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -2.992
Data Arrival Time 13.820
Data Required Time 10.828
From core/mem_addr_27_s0
To core/decoded_rs1_2_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.683 0.683 tINS RR 4065 clk_in_ibuf/O
0.863 0.180 tNET RR 1 core/mem_addr_27_s0/CLK
1.095 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.332 0.237 tNET FF 1 itcm_valid_s2/I1
1.887 0.555 tINS FF 5 itcm_valid_s2/F
2.124 0.237 tNET FF 1 itcm_valid_s3/I3
2.495 0.371 tINS FF 4 itcm_valid_s3/F
2.732 0.237 tNET FF 1 u_dm/wr_cleardebint_ena_s7/I0
3.249 0.517 tINS FF 5 u_dm/wr_cleardebint_ena_s7/F
3.486 0.237 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.003 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.240 0.237 tNET FF 1 u_dm/ram_addr_2_s2/I3
4.610 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
4.847 0.237 tNET FF 1 u_dm/ram_addr_0_s0/I2
5.300 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
5.537 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_27_s2/I2
5.990 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_27_s2/F
6.227 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_27_s0/I0
6.331 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_27_s0/O
6.568 0.237 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_27_s/I0
6.671 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_27_s/O
6.908 0.237 tNET FF 1 mem_rdata_27_s6/I0
7.425 0.517 tINS FF 1 mem_rdata_27_s6/F
7.662 0.237 tNET FF 1 mem_rdata_27_s2/I2
8.115 0.453 tINS FF 2 mem_rdata_27_s2/F
8.352 0.237 tNET FF 1 core/mem_rdata_latched_11_s4/I1
8.907 0.555 tINS FF 1 core/mem_rdata_latched_11_s4/F
9.144 0.237 tNET FF 1 core/mem_rdata_latched_11_s2/I1
9.699 0.555 tINS FF 3 core/mem_rdata_latched_11_s2/F
9.936 0.237 tNET FF 1 core/n5720_s2/I0
10.453 0.517 tINS FF 5 core/n5720_s2/F
10.690 0.237 tNET FF 1 core/n5707_s2/I0
11.207 0.517 tINS FF 4 core/n5707_s2/F
11.444 0.237 tNET FF 1 core/n5713_s6/I1
11.999 0.555 tINS FF 1 core/n5713_s6/F
12.236 0.237 tNET FF 1 core/n5713_s2/I1
12.791 0.555 tINS FF 2 core/n5713_s2/F
13.028 0.237 tNET FF 1 core/n5714_s0/I1
13.583 0.555 tINS FF 1 core/n5714_s0/F
13.820 0.237 tNET FF 1 core/decoded_rs1_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.682 0.683 tINS RR 4065 clk_in_ibuf/O
10.863 0.180 tNET RR 1 core/decoded_rs1_2_s0/CLK
10.828 -0.035 tSu 1 core/decoded_rs1_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.222, 63.456%; route: 4.503, 34.753%; tC2Q: 0.232, 1.791%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%