Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.8Beta |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18C |
Created Time | Mon Jul 19 09:28:53 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_PicoRV32_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 86.328MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.166s, Peak memory usage = 86.328MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.951s, Peak memory usage = 86.328MB Optimizing Phase 1: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.72s, Peak memory usage = 86.328MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 86.328MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.357s, Peak memory usage = 86.328MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 86.328MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 86.328MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 86.328MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 86.328MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.319s, Peak memory usage = 86.328MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.624s, Peak memory usage = 86.328MB Tech-Mapping Phase 3: CPU time = 0h 0m 31s, Elapsed time = 0h 0m 31s, Peak memory usage = 95.719MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 95.719MB Generate output files: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 1s, Peak memory usage = 117.789MB |
Total Time and Memory Usage | CPU time = 0h 0m 38s, Elapsed time = 0h 0m 40s, Peak memory usage = 117.789MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 281 |
I/O Buf | 279 |
    IBUF | 89 |
    OBUF | 152 |
    TBUF | 2 |
    IOBUF | 36 |
Register | 4882 |
    DFF | 219 |
    DFFE | 1874 |
    DFFS | 18 |
    DFFSE | 120 |
    DFFR | 221 |
    DFFRE | 737 |
    DFFP | 14 |
    DFFPE | 29 |
    DFFC | 299 |
    DFFCE | 1318 |
    DFFN | 1 |
    DFFNR | 15 |
    DFFNPE | 1 |
    DFFNC | 4 |
    DFFNCE | 12 |
LUT | 7211 |
    LUT2 | 615 |
    LUT3 | 2254 |
    LUT4 | 4342 |
ALU | 746 |
    ALU | 746 |
SSRAM | 24 |
    RAM16SDP4 | 24 |
INV | 56 |
    INV | 56 |
DSP | 1 |
    MULT36X36 | 1 |
BSRAM | 32 |
    SDPB | 32 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 8157(7267 LUTs, 746 ALUs, 24 SSRAMs) / 20736 | 39% |
Register | 4882 / 16173 | 30% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 4882 / 16173 | 30% |
BSRAM | 32 / 46 | 70% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_in_ibuf/I | ||
jtag_TCK | Base | 10.000 | 100.0 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
wbspi_slave_sclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | wbspi_slave_sclk_ibuf/I | ||
n316_3 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_in | 100.0(MHz) | 55.8(MHz) | 12 | TOP |
2 | jtag_TCK | 100.0(MHz) | 124.4(MHz) | 6 | TOP |
3 | wbspi_slave_sclk | 100.0(MHz) | 478.9(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -3.954 |
Data Arrival Time | 14.782 |
Data Required Time | 10.828 |
From | rstdly_15_s1 |
To | core/cpu_state.cpu_state_shift_s4 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.688 | 0.688 | tINS | FF | 4741 | clk_in_ibuf/O |
5.924 | 0.237 | tNET | FF | 1 | rstdly_15_s1/CLK |
6.156 | 0.232 | tC2Q | FF | 49 | rstdly_15_s1/Q |
6.393 | 0.237 | tNET | FF | 1 | n624_s1/I1 |
6.948 | 0.555 | tINS | FF | 1969 | n624_s1/F |
7.185 | 0.237 | tNET | FF | 1 | core/n7354_s1/I1 |
7.740 | 0.555 | tINS | FF | 4 | core/n7354_s1/F |
7.977 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s6/I1 |
8.532 | 0.555 | tINS | FF | 24 | core/mem_rdata_latched_6_s6/F |
8.769 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s3/I1 |
9.325 | 0.555 | tINS | FF | 11 | core/mem_rdata_latched_6_s3/F |
9.562 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s4/I3 |
9.933 | 0.371 | tINS | FF | 2 | core/mem_rdata_latched_1_s4/F |
10.170 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s1/I2 |
10.623 | 0.453 | tINS | FF | 74 | core/mem_rdata_latched_1_s1/F |
10.860 | 0.237 | tNET | FF | 1 | core/n5416_s1/I1 |
11.415 | 0.555 | tINS | FF | 6 | core/n5416_s1/F |
11.652 | 0.237 | tNET | FF | 1 | core/n5306_s1/I1 |
12.207 | 0.555 | tINS | FF | 15 | core/n5306_s1/F |
12.444 | 0.237 | tNET | FF | 1 | core/n15390_s23/I0 |
12.961 | 0.517 | tINS | FF | 4 | core/n15390_s23/F |
13.198 | 0.237 | tNET | FF | 1 | core/n15393_s21/I1 |
13.753 | 0.555 | tINS | FF | 1 | core/n15393_s21/F |
13.990 | 0.237 | tNET | FF | 1 | core/n15393_s20/I1 |
14.545 | 0.555 | tINS | FF | 1 | core/n15393_s20/F |
14.782 | 0.237 | tNET | FF | 1 | core/cpu_state.cpu_state_shift_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4741 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/cpu_state.cpu_state_shift_s4/CLK |
10.828 | -0.035 | tSu | 1 | core/cpu_state.cpu_state_shift_s4 |
Clock Skew: | -0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Arrival Data Path Delay: | cell: 5.781, 65.271%; route: 2.844, 32.110%; tC2Q: 0.232, 2.619% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Path 2
Path Summary:Slack | -3.954 |
Data Arrival Time | 14.782 |
Data Required Time | 10.828 |
From | rstdly_15_s1 |
To | core/reg_op1_0_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.688 | 0.688 | tINS | FF | 4741 | clk_in_ibuf/O |
5.924 | 0.237 | tNET | FF | 1 | rstdly_15_s1/CLK |
6.156 | 0.232 | tC2Q | FF | 49 | rstdly_15_s1/Q |
6.393 | 0.237 | tNET | FF | 1 | n624_s1/I1 |
6.948 | 0.555 | tINS | FF | 1969 | n624_s1/F |
7.185 | 0.237 | tNET | FF | 1 | core/n7354_s1/I1 |
7.740 | 0.555 | tINS | FF | 4 | core/n7354_s1/F |
7.977 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s6/I1 |
8.532 | 0.555 | tINS | FF | 24 | core/mem_rdata_latched_6_s6/F |
8.769 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s3/I1 |
9.325 | 0.555 | tINS | FF | 11 | core/mem_rdata_latched_6_s3/F |
9.562 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s4/I3 |
9.933 | 0.371 | tINS | FF | 2 | core/mem_rdata_latched_1_s4/F |
10.170 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s1/I2 |
10.623 | 0.453 | tINS | FF | 74 | core/mem_rdata_latched_1_s1/F |
10.860 | 0.237 | tNET | FF | 1 | core/n5416_s1/I1 |
11.415 | 0.555 | tINS | FF | 6 | core/n5416_s1/F |
11.652 | 0.237 | tNET | FF | 1 | core/n5306_s1/I1 |
12.207 | 0.555 | tINS | FF | 15 | core/n5306_s1/F |
12.444 | 0.237 | tNET | FF | 1 | core/latched_is_lu_s5/I0 |
12.961 | 0.517 | tINS | FF | 2 | core/latched_is_lu_s5/F |
13.198 | 0.237 | tNET | FF | 1 | core/n15397_s13/I1 |
13.753 | 0.555 | tINS | FF | 34 | core/n15397_s13/F |
13.990 | 0.237 | tNET | FF | 1 | core/n15459_s12/I1 |
14.545 | 0.555 | tINS | FF | 1 | core/n15459_s12/F |
14.782 | 0.237 | tNET | FF | 1 | core/reg_op1_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4741 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/reg_op1_0_s0/CLK |
10.828 | -0.035 | tSu | 1 | core/reg_op1_0_s0 |
Clock Skew: | -0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Arrival Data Path Delay: | cell: 5.781, 65.271%; route: 2.844, 32.110%; tC2Q: 0.232, 2.619% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Path 3
Path Summary:Slack | -3.954 |
Data Arrival Time | 14.782 |
Data Required Time | 10.828 |
From | rstdly_15_s1 |
To | core/reg_op1_10_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.688 | 0.688 | tINS | FF | 4741 | clk_in_ibuf/O |
5.924 | 0.237 | tNET | FF | 1 | rstdly_15_s1/CLK |
6.156 | 0.232 | tC2Q | FF | 49 | rstdly_15_s1/Q |
6.393 | 0.237 | tNET | FF | 1 | n624_s1/I1 |
6.948 | 0.555 | tINS | FF | 1969 | n624_s1/F |
7.185 | 0.237 | tNET | FF | 1 | core/n7354_s1/I1 |
7.740 | 0.555 | tINS | FF | 4 | core/n7354_s1/F |
7.977 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s6/I1 |
8.532 | 0.555 | tINS | FF | 24 | core/mem_rdata_latched_6_s6/F |
8.769 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s3/I1 |
9.325 | 0.555 | tINS | FF | 11 | core/mem_rdata_latched_6_s3/F |
9.562 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s4/I3 |
9.933 | 0.371 | tINS | FF | 2 | core/mem_rdata_latched_1_s4/F |
10.170 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s1/I2 |
10.623 | 0.453 | tINS | FF | 74 | core/mem_rdata_latched_1_s1/F |
10.860 | 0.237 | tNET | FF | 1 | core/n5416_s1/I1 |
11.415 | 0.555 | tINS | FF | 6 | core/n5416_s1/F |
11.652 | 0.237 | tNET | FF | 1 | core/n5306_s1/I1 |
12.207 | 0.555 | tINS | FF | 15 | core/n5306_s1/F |
12.444 | 0.237 | tNET | FF | 1 | core/latched_is_lu_s5/I0 |
12.961 | 0.517 | tINS | FF | 2 | core/latched_is_lu_s5/F |
13.198 | 0.237 | tNET | FF | 1 | core/n15397_s13/I1 |
13.753 | 0.555 | tINS | FF | 34 | core/n15397_s13/F |
13.990 | 0.237 | tNET | FF | 1 | core/n15439_s12/I1 |
14.545 | 0.555 | tINS | FF | 1 | core/n15439_s12/F |
14.782 | 0.237 | tNET | FF | 1 | core/reg_op1_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4741 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/reg_op1_10_s0/CLK |
10.828 | -0.035 | tSu | 1 | core/reg_op1_10_s0 |
Clock Skew: | -0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Arrival Data Path Delay: | cell: 5.781, 65.271%; route: 2.844, 32.110%; tC2Q: 0.232, 2.619% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Path 4
Path Summary:Slack | -3.954 |
Data Arrival Time | 14.782 |
Data Required Time | 10.828 |
From | rstdly_15_s1 |
To | core/reg_op1_11_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.688 | 0.688 | tINS | FF | 4741 | clk_in_ibuf/O |
5.924 | 0.237 | tNET | FF | 1 | rstdly_15_s1/CLK |
6.156 | 0.232 | tC2Q | FF | 49 | rstdly_15_s1/Q |
6.393 | 0.237 | tNET | FF | 1 | n624_s1/I1 |
6.948 | 0.555 | tINS | FF | 1969 | n624_s1/F |
7.185 | 0.237 | tNET | FF | 1 | core/n7354_s1/I1 |
7.740 | 0.555 | tINS | FF | 4 | core/n7354_s1/F |
7.977 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s6/I1 |
8.532 | 0.555 | tINS | FF | 24 | core/mem_rdata_latched_6_s6/F |
8.769 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s3/I1 |
9.325 | 0.555 | tINS | FF | 11 | core/mem_rdata_latched_6_s3/F |
9.562 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s4/I3 |
9.933 | 0.371 | tINS | FF | 2 | core/mem_rdata_latched_1_s4/F |
10.170 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s1/I2 |
10.623 | 0.453 | tINS | FF | 74 | core/mem_rdata_latched_1_s1/F |
10.860 | 0.237 | tNET | FF | 1 | core/n5416_s1/I1 |
11.415 | 0.555 | tINS | FF | 6 | core/n5416_s1/F |
11.652 | 0.237 | tNET | FF | 1 | core/n5306_s1/I1 |
12.207 | 0.555 | tINS | FF | 15 | core/n5306_s1/F |
12.444 | 0.237 | tNET | FF | 1 | core/latched_is_lu_s5/I0 |
12.961 | 0.517 | tINS | FF | 2 | core/latched_is_lu_s5/F |
13.198 | 0.237 | tNET | FF | 1 | core/n15397_s13/I1 |
13.753 | 0.555 | tINS | FF | 34 | core/n15397_s13/F |
13.990 | 0.237 | tNET | FF | 1 | core/n15437_s12/I1 |
14.545 | 0.555 | tINS | FF | 1 | core/n15437_s12/F |
14.782 | 0.237 | tNET | FF | 1 | core/reg_op1_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4741 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/reg_op1_11_s0/CLK |
10.828 | -0.035 | tSu | 1 | core/reg_op1_11_s0 |
Clock Skew: | -0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Arrival Data Path Delay: | cell: 5.781, 65.271%; route: 2.844, 32.110%; tC2Q: 0.232, 2.619% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Path 5
Path Summary:Slack | -3.954 |
Data Arrival Time | 14.782 |
Data Required Time | 10.828 |
From | rstdly_15_s1 |
To | core/reg_op1_20_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.688 | 0.688 | tINS | FF | 4741 | clk_in_ibuf/O |
5.924 | 0.237 | tNET | FF | 1 | rstdly_15_s1/CLK |
6.156 | 0.232 | tC2Q | FF | 49 | rstdly_15_s1/Q |
6.393 | 0.237 | tNET | FF | 1 | n624_s1/I1 |
6.948 | 0.555 | tINS | FF | 1969 | n624_s1/F |
7.185 | 0.237 | tNET | FF | 1 | core/n7354_s1/I1 |
7.740 | 0.555 | tINS | FF | 4 | core/n7354_s1/F |
7.977 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s6/I1 |
8.532 | 0.555 | tINS | FF | 24 | core/mem_rdata_latched_6_s6/F |
8.769 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_6_s3/I1 |
9.325 | 0.555 | tINS | FF | 11 | core/mem_rdata_latched_6_s3/F |
9.562 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s4/I3 |
9.933 | 0.371 | tINS | FF | 2 | core/mem_rdata_latched_1_s4/F |
10.170 | 0.237 | tNET | FF | 1 | core/mem_rdata_latched_1_s1/I2 |
10.623 | 0.453 | tINS | FF | 74 | core/mem_rdata_latched_1_s1/F |
10.860 | 0.237 | tNET | FF | 1 | core/n5416_s1/I1 |
11.415 | 0.555 | tINS | FF | 6 | core/n5416_s1/F |
11.652 | 0.237 | tNET | FF | 1 | core/n5306_s1/I1 |
12.207 | 0.555 | tINS | FF | 15 | core/n5306_s1/F |
12.444 | 0.237 | tNET | FF | 1 | core/latched_is_lu_s5/I0 |
12.961 | 0.517 | tINS | FF | 2 | core/latched_is_lu_s5/F |
13.198 | 0.237 | tNET | FF | 1 | core/n15397_s13/I1 |
13.753 | 0.555 | tINS | FF | 34 | core/n15397_s13/F |
13.990 | 0.237 | tNET | FF | 1 | core/n15419_s12/I1 |
14.545 | 0.555 | tINS | FF | 1 | core/n15419_s12/F |
14.782 | 0.237 | tNET | FF | 1 | core/reg_op1_20_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.682 | 0.683 | tINS | RR | 4741 | clk_in_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | core/reg_op1_20_s0/CLK |
10.828 | -0.035 | tSu | 1 | core/reg_op1_20_s0 |
Clock Skew: | -0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 12 |
Arrival Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Arrival Data Path Delay: | cell: 5.781, 65.271%; route: 2.844, 32.110%; tC2Q: 0.232, 2.619% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |