# Mon Sep 17 18:51:48 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

@N: MO231 :"d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\lossy_ex\project\src\top.v":30:0:30:5|Found counter in view:work.TOP(verilog) instance Din[7:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -1.74ns		  55 /        27
   2		0h:00m:00s		    -1.74ns		  55 /        27

   3		0h:00m:00s		    -1.74ns		  55 /        27

   4		0h:00m:00s		    -1.74ns		  55 /        27

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 191MB)

Writing Analyst data base D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\impl\synthesize\rev_1\synwork\lossy_ex_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

@W: MT246 :"d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\lossy_ex\project\src\gw_pll\gw_pll.v":26:4:26:11|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GW_PLL|clkout_inferred_clock with period 4.12ns. Please declare a user-defined clock on net GW_PLL_inst.clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Sep 17 18:51:51 2018
#


Top view:               TOP
Requested Frequency:    242.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.727

                                 Requested      Estimated      Requested     Estimated                Clock        Clock                
Starting Clock                   Frequency      Frequency      Period        Period        Slack      Type         Group                
----------------------------------------------------------------------------------------------------------------------------------------
GW_PLL|clkout_inferred_clock     242.7 MHz      206.3 MHz      4.121         4.848         -0.727     inferred     Autoconstr_clkgroup_0
System                           2199.3 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup      
========================================================================================================================================





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------
System                        System                        |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -    
GW_PLL|clkout_inferred_clock  GW_PLL|clkout_inferred_clock  |  4.121       -0.727  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_PLL|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

             Starting                                                      Arrival           
Instance     Reference                        Type     Pin     Net         Time        Slack 
             Clock                                                                           
---------------------------------------------------------------------------------------------
cnt[5]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[5]      0.243       -0.727
cnt[4]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[4]      0.243       -0.706
cnt[9]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[9]      0.243       -0.706
cnt[8]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[8]      0.243       -0.685
cnt[1]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[1]      0.243       -0.619
cnt[6]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[6]      0.243       -0.619
ADDR[0]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_3      0.243       -0.611
cnt[0]       GW_PLL|clkout_inferred_clock     DFFC     Q       cnt[0]      0.243       -0.598
ADDR[1]      GW_PLL|clkout_inferred_clock     DFFP     Q       ADDR[1]     0.243       -0.576
ADDR[2]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[2]     0.243       -0.541
=============================================================================================


Ending Points with Worst Slack
******************************

                                                              Starting                                                         Required           
Instance                                                      Reference                        Type     Pin     Net            Time         Slack 
                                                              Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------------------------------
ADDR[8]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[8]      4.060        -0.727
ADDR[7]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[7]      4.060        -0.692
ADDR[6]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[6]      4.060        -0.657
ADDR[5]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[5]      4.060        -0.622
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[0]     4.060        -0.611
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[1]     4.060        -0.611
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[2]     4.060        -0.611
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[3]     4.060        -0.611
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[4]     4.060        -0.611
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFC     D       wbin_lm[5]     4.060        -0.611
==================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.121
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.060

    - Propagation time:                      4.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.727

    Number of logic level(s):                11
    Starting point:                          cnt[5] / Q
    Ending point:                            ADDR[8] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[5]                 DFFC     Q        Out     0.243     0.243       -         
cnt[5]                 Net      -        -       0.535     -           2         
cnt12_5                LUT4     I1       In      -         0.778       -         
cnt12_5                LUT4     F        Out     0.570     1.348       -         
cnt12_5                Net      -        -       0.535     -           8         
ADDR_3_cry_0_0_RNO     LUT3     I1       In      -         1.883       -         
ADDR_3_cry_0_0_RNO     LUT3     F        Out     0.570     2.453       -         
ADDR_3_cry_0_0_RNO     Net      -        -       0.535     -           1         
ADDR_3_cry_0_0         ALU      I0       In      -         2.988       -         
ADDR_3_cry_0_0         ALU      COUT     Out     0.549     3.537       -         
ADDR_3_cry_0           Net      -        -       0.000     -           1         
ADDR_3_cry_1_0         ALU      CIN      In      -         3.537       -         
ADDR_3_cry_1_0         ALU      COUT     Out     0.035     3.572       -         
ADDR_3_cry_1           Net      -        -       0.000     -           1         
ADDR_3_cry_2_0         ALU      CIN      In      -         3.572       -         
ADDR_3_cry_2_0         ALU      COUT     Out     0.035     3.607       -         
ADDR_3_cry_2           Net      -        -       0.000     -           1         
ADDR_3_cry_3_0         ALU      CIN      In      -         3.607       -         
ADDR_3_cry_3_0         ALU      COUT     Out     0.035     3.642       -         
ADDR_3_cry_3           Net      -        -       0.000     -           1         
ADDR_3_cry_4_0         ALU      CIN      In      -         3.642       -         
ADDR_3_cry_4_0         ALU      COUT     Out     0.035     3.677       -         
ADDR_3_cry_4           Net      -        -       0.000     -           1         
ADDR_3_cry_5_0         ALU      CIN      In      -         3.677       -         
ADDR_3_cry_5_0         ALU      COUT     Out     0.035     3.712       -         
ADDR_3_cry_5           Net      -        -       0.000     -           1         
ADDR_3_cry_6_0         ALU      CIN      In      -         3.712       -         
ADDR_3_cry_6_0         ALU      COUT     Out     0.035     3.747       -         
ADDR_3_cry_6           Net      -        -       0.000     -           1         
ADDR_3_cry_7_0         ALU      CIN      In      -         3.747       -         
ADDR_3_cry_7_0         ALU      COUT     Out     0.035     3.782       -         
ADDR_3_cry_7           Net      -        -       0.000     -           1         
ADDR_3_s_8_0           ALU      CIN      In      -         3.782       -         
ADDR_3_s_8_0           ALU      SUM      Out     0.470     4.252       -         
ADDR_3[8]              Net      -        -       0.535     -           1         
ADDR[8]                DFFC     D        In      -         4.787       -         
=================================================================================
Total path delay (propagation time + setup) of 4.848 is 2.708(55.9%) logic and 2.140(44.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.121
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.060

    - Propagation time:                      4.766
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.706

    Number of logic level(s):                11
    Starting point:                          cnt[4] / Q
    Ending point:                            ADDR[8] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[4]                 DFFC     Q        Out     0.243     0.243       -         
cnt[4]                 Net      -        -       0.535     -           2         
cnt12_5                LUT4     I0       In      -         0.778       -         
cnt12_5                LUT4     F        Out     0.549     1.327       -         
cnt12_5                Net      -        -       0.535     -           8         
ADDR_3_cry_0_0_RNO     LUT3     I1       In      -         1.862       -         
ADDR_3_cry_0_0_RNO     LUT3     F        Out     0.570     2.432       -         
ADDR_3_cry_0_0_RNO     Net      -        -       0.535     -           1         
ADDR_3_cry_0_0         ALU      I0       In      -         2.967       -         
ADDR_3_cry_0_0         ALU      COUT     Out     0.549     3.516       -         
ADDR_3_cry_0           Net      -        -       0.000     -           1         
ADDR_3_cry_1_0         ALU      CIN      In      -         3.516       -         
ADDR_3_cry_1_0         ALU      COUT     Out     0.035     3.551       -         
ADDR_3_cry_1           Net      -        -       0.000     -           1         
ADDR_3_cry_2_0         ALU      CIN      In      -         3.551       -         
ADDR_3_cry_2_0         ALU      COUT     Out     0.035     3.586       -         
ADDR_3_cry_2           Net      -        -       0.000     -           1         
ADDR_3_cry_3_0         ALU      CIN      In      -         3.586       -         
ADDR_3_cry_3_0         ALU      COUT     Out     0.035     3.621       -         
ADDR_3_cry_3           Net      -        -       0.000     -           1         
ADDR_3_cry_4_0         ALU      CIN      In      -         3.621       -         
ADDR_3_cry_4_0         ALU      COUT     Out     0.035     3.656       -         
ADDR_3_cry_4           Net      -        -       0.000     -           1         
ADDR_3_cry_5_0         ALU      CIN      In      -         3.656       -         
ADDR_3_cry_5_0         ALU      COUT     Out     0.035     3.691       -         
ADDR_3_cry_5           Net      -        -       0.000     -           1         
ADDR_3_cry_6_0         ALU      CIN      In      -         3.691       -         
ADDR_3_cry_6_0         ALU      COUT     Out     0.035     3.726       -         
ADDR_3_cry_6           Net      -        -       0.000     -           1         
ADDR_3_cry_7_0         ALU      CIN      In      -         3.726       -         
ADDR_3_cry_7_0         ALU      COUT     Out     0.035     3.761       -         
ADDR_3_cry_7           Net      -        -       0.000     -           1         
ADDR_3_s_8_0           ALU      CIN      In      -         3.761       -         
ADDR_3_s_8_0           ALU      SUM      Out     0.470     4.231       -         
ADDR_3[8]              Net      -        -       0.535     -           1         
ADDR[8]                DFFC     D        In      -         4.766       -         
=================================================================================
Total path delay (propagation time + setup) of 4.827 is 2.687(55.7%) logic and 2.140(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.121
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.060

    - Propagation time:                      4.766
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.706

    Number of logic level(s):                11
    Starting point:                          cnt[9] / Q
    Ending point:                            ADDR[8] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[9]                 DFFC     Q        Out     0.243     0.243       -         
cnt[9]                 Net      -        -       0.535     -           2         
cnt12_4                LUT2     I1       In      -         0.778       -         
cnt12_4                LUT2     F        Out     0.570     1.348       -         
cnt12_4                Net      -        -       0.535     -           8         
ADDR_3_cry_0_0_RNO     LUT3     I0       In      -         1.883       -         
ADDR_3_cry_0_0_RNO     LUT3     F        Out     0.549     2.432       -         
ADDR_3_cry_0_0_RNO     Net      -        -       0.535     -           1         
ADDR_3_cry_0_0         ALU      I0       In      -         2.967       -         
ADDR_3_cry_0_0         ALU      COUT     Out     0.549     3.516       -         
ADDR_3_cry_0           Net      -        -       0.000     -           1         
ADDR_3_cry_1_0         ALU      CIN      In      -         3.516       -         
ADDR_3_cry_1_0         ALU      COUT     Out     0.035     3.551       -         
ADDR_3_cry_1           Net      -        -       0.000     -           1         
ADDR_3_cry_2_0         ALU      CIN      In      -         3.551       -         
ADDR_3_cry_2_0         ALU      COUT     Out     0.035     3.586       -         
ADDR_3_cry_2           Net      -        -       0.000     -           1         
ADDR_3_cry_3_0         ALU      CIN      In      -         3.586       -         
ADDR_3_cry_3_0         ALU      COUT     Out     0.035     3.621       -         
ADDR_3_cry_3           Net      -        -       0.000     -           1         
ADDR_3_cry_4_0         ALU      CIN      In      -         3.621       -         
ADDR_3_cry_4_0         ALU      COUT     Out     0.035     3.656       -         
ADDR_3_cry_4           Net      -        -       0.000     -           1         
ADDR_3_cry_5_0         ALU      CIN      In      -         3.656       -         
ADDR_3_cry_5_0         ALU      COUT     Out     0.035     3.691       -         
ADDR_3_cry_5           Net      -        -       0.000     -           1         
ADDR_3_cry_6_0         ALU      CIN      In      -         3.691       -         
ADDR_3_cry_6_0         ALU      COUT     Out     0.035     3.726       -         
ADDR_3_cry_6           Net      -        -       0.000     -           1         
ADDR_3_cry_7_0         ALU      CIN      In      -         3.726       -         
ADDR_3_cry_7_0         ALU      COUT     Out     0.035     3.761       -         
ADDR_3_cry_7           Net      -        -       0.000     -           1         
ADDR_3_s_8_0           ALU      CIN      In      -         3.761       -         
ADDR_3_s_8_0           ALU      SUM      Out     0.470     4.231       -         
ADDR_3[8]              Net      -        -       0.535     -           1         
ADDR[8]                DFFC     D        In      -         4.766       -         
=================================================================================
Total path delay (propagation time + setup) of 4.827 is 2.687(55.7%) logic and 2.140(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.121
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.060

    - Propagation time:                      4.752
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.692

    Number of logic level(s):                10
    Starting point:                          cnt[5] / Q
    Ending point:                            ADDR[8] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[5]                 DFFC     Q        Out     0.243     0.243       -         
cnt[5]                 Net      -        -       0.535     -           2         
cnt12_5                LUT4     I1       In      -         0.778       -         
cnt12_5                LUT4     F        Out     0.570     1.348       -         
cnt12_5                Net      -        -       0.535     -           8         
ADDR_3_cry_1_0_RNO     LUT3     I1       In      -         1.883       -         
ADDR_3_cry_1_0_RNO     LUT3     F        Out     0.570     2.453       -         
ADDR_3_cry_1_0_RNO     Net      -        -       0.535     -           1         
ADDR_3_cry_1_0         ALU      I0       In      -         2.988       -         
ADDR_3_cry_1_0         ALU      COUT     Out     0.549     3.537       -         
ADDR_3_cry_1           Net      -        -       0.000     -           1         
ADDR_3_cry_2_0         ALU      CIN      In      -         3.537       -         
ADDR_3_cry_2_0         ALU      COUT     Out     0.035     3.572       -         
ADDR_3_cry_2           Net      -        -       0.000     -           1         
ADDR_3_cry_3_0         ALU      CIN      In      -         3.572       -         
ADDR_3_cry_3_0         ALU      COUT     Out     0.035     3.607       -         
ADDR_3_cry_3           Net      -        -       0.000     -           1         
ADDR_3_cry_4_0         ALU      CIN      In      -         3.607       -         
ADDR_3_cry_4_0         ALU      COUT     Out     0.035     3.642       -         
ADDR_3_cry_4           Net      -        -       0.000     -           1         
ADDR_3_cry_5_0         ALU      CIN      In      -         3.642       -         
ADDR_3_cry_5_0         ALU      COUT     Out     0.035     3.677       -         
ADDR_3_cry_5           Net      -        -       0.000     -           1         
ADDR_3_cry_6_0         ALU      CIN      In      -         3.677       -         
ADDR_3_cry_6_0         ALU      COUT     Out     0.035     3.712       -         
ADDR_3_cry_6           Net      -        -       0.000     -           1         
ADDR_3_cry_7_0         ALU      CIN      In      -         3.712       -         
ADDR_3_cry_7_0         ALU      COUT     Out     0.035     3.747       -         
ADDR_3_cry_7           Net      -        -       0.000     -           1         
ADDR_3_s_8_0           ALU      CIN      In      -         3.747       -         
ADDR_3_s_8_0           ALU      SUM      Out     0.470     4.217       -         
ADDR_3[8]              Net      -        -       0.535     -           1         
ADDR[8]                DFFC     D        In      -         4.752       -         
=================================================================================
Total path delay (propagation time + setup) of 4.813 is 2.673(55.5%) logic and 2.140(44.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.121
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.060

    - Propagation time:                      4.752
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.692

    Number of logic level(s):                10
    Starting point:                          cnt[5] / Q
    Ending point:                            ADDR[7] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
cnt[5]                 DFFC     Q        Out     0.243     0.243       -         
cnt[5]                 Net      -        -       0.535     -           2         
cnt12_5                LUT4     I1       In      -         0.778       -         
cnt12_5                LUT4     F        Out     0.570     1.348       -         
cnt12_5                Net      -        -       0.535     -           8         
ADDR_3_cry_0_0_RNO     LUT3     I1       In      -         1.883       -         
ADDR_3_cry_0_0_RNO     LUT3     F        Out     0.570     2.453       -         
ADDR_3_cry_0_0_RNO     Net      -        -       0.535     -           1         
ADDR_3_cry_0_0         ALU      I0       In      -         2.988       -         
ADDR_3_cry_0_0         ALU      COUT     Out     0.549     3.537       -         
ADDR_3_cry_0           Net      -        -       0.000     -           1         
ADDR_3_cry_1_0         ALU      CIN      In      -         3.537       -         
ADDR_3_cry_1_0         ALU      COUT     Out     0.035     3.572       -         
ADDR_3_cry_1           Net      -        -       0.000     -           1         
ADDR_3_cry_2_0         ALU      CIN      In      -         3.572       -         
ADDR_3_cry_2_0         ALU      COUT     Out     0.035     3.607       -         
ADDR_3_cry_2           Net      -        -       0.000     -           1         
ADDR_3_cry_3_0         ALU      CIN      In      -         3.607       -         
ADDR_3_cry_3_0         ALU      COUT     Out     0.035     3.642       -         
ADDR_3_cry_3           Net      -        -       0.000     -           1         
ADDR_3_cry_4_0         ALU      CIN      In      -         3.642       -         
ADDR_3_cry_4_0         ALU      COUT     Out     0.035     3.677       -         
ADDR_3_cry_4           Net      -        -       0.000     -           1         
ADDR_3_cry_5_0         ALU      CIN      In      -         3.677       -         
ADDR_3_cry_5_0         ALU      COUT     Out     0.035     3.712       -         
ADDR_3_cry_5           Net      -        -       0.000     -           1         
ADDR_3_cry_6_0         ALU      CIN      In      -         3.712       -         
ADDR_3_cry_6_0         ALU      COUT     Out     0.035     3.747       -         
ADDR_3_cry_6           Net      -        -       0.000     -           1         
ADDR_3_cry_7_0         ALU      CIN      In      -         3.747       -         
ADDR_3_cry_7_0         ALU      SUM      Out     0.470     4.217       -         
ADDR_3[7]              Net      -        -       0.535     -           1         
ADDR[7]                DFFC     D        In      -         4.752       -         
=================================================================================
Total path delay (propagation time + setup) of 4.813 is 2.673(55.5%) logic and 2.140(44.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                      Starting                                      Arrival           
Instance              Reference     Type     Pin        Net         Time        Slack 
                      Clock                                                           
--------------------------------------------------------------------------------------
osc_inst.osc_inst     System        OSC      OSCOUT     clk_osc     0.000       -0.080
======================================================================================


Ending Points with Worst Slack
******************************

                         Starting                                     Required           
Instance                 Reference     Type     Pin       Net         Time         Slack 
                         Clock                                                           
-----------------------------------------------------------------------------------------
GW_PLL_inst.pll_inst     System        PLL      CLKIN     clk_osc     0.455        -0.080
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      0.455
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.455

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.080

    Number of logic level(s):                0
    Starting point:                          osc_inst.osc_inst / OSCOUT
    Ending point:                            GW_PLL_inst.pll_inst / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                    Pin        Pin               Arrival     No. of    
Name                     Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
osc_inst.osc_inst        OSC      OSCOUT     Out     0.000     0.000       -         
clk_osc                  Net      -          -       0.535     -           1         
GW_PLL_inst.pll_inst     PLL      CLKIN      In      -         0.535       -         
=====================================================================================
Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

---------------------------------------
Resource Usage Report for TOP 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             55 uses
DFFC            35 uses
DFFP            1 use
GSR             1 use
MUX2_LUT5       1 use
OSC             1 use
PLL             1 use
SP              1 use
LUT2            9 uses
LUT3            2 uses
LUT4            20 uses

I/O ports: 9
I/O primitives: 9
IBUF           1 use
OBUF           8 uses

I/O Register bits:                  0
Register bits not including I/Os:   36 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 1 of 140 (0%)

Total load per clock:
   GW_PLL|clkout_inferred_clock: 37

@S |Mapping Summary:
Total  LUTs: 31 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 191MB)

Process took 0h:00m:02s realtime, 0h:00m:03s cputime
# Mon Sep 17 18:51:51 2018

###########################################################]
