#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-047

# Wed Jul 18 11:03:22 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

@N|Running in 64-bit mode

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

@N|Running in 64-bit mode
@N:: Running Verilog Compiler in System Verilog mode
@N:: Running Verilog Compiler in Multiple File Compilation Unit mode
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v" (library work)
@I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v" (library work)
@I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v" (library work)
@I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v" (library work)
@I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM_based_shift_reg_top
@N: CG364 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Synthesizing module RAM_based_shift_reg_top in library work.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jul 18 11:03:23 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

@N|Running in 64-bit mode
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jul 18 11:03:23 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jul 18 11:03:23 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Database state : D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

@N|Running in 64-bit mode
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jul 18 11:03:24 2018

###########################################################]
Premap Report

# Wed Jul 18 11:03:25 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@L: D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top_scck.rpt 
Printing clock  summary report in "D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
syn_allowed_resources : blockrams=140  set on top level netlist RAM_based_shift_reg_top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)



Clock Summary
******************

          Start                           Requested     Requested     Clock        Clock                     Clock
Level     Clock                           Frequency     Period        Type         Group                     Load 
------------------------------------------------------------------------------------------------------------------
0 -       RAM_based_shift_reg_top|clk     260.3 MHz     3.842         inferred     Autoconstr_clkgroup_0     30   
==================================================================================================================



Clock Load Summary
***********************

                                Clock     Source        Clock Pin                                Non-clock Pin     Non-clock Pin
Clock                           Load      Pin           Seq Example                              Seq Example       Comb Example 
--------------------------------------------------------------------------------------------------------------------------------
RAM_based_shift_reg_top|clk     30        clk(port)     u_RAM_based_shift_reg.ADDR_in[3:0].C     -                 -            
================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 23 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 Unconstrained_port     23         ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N|Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 191MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jul 18 11:03:26 2018

###########################################################]
Map & Optimize Report

# Wed Jul 18 11:03:27 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.01ns		  51 /        15
   2		0h:00m:01s		    -2.01ns		  49 /        15
   3		0h:00m:01s		    -2.14ns		  49 /        15

   4		0h:00m:01s		    -2.01ns		  52 /        15


   5		0h:00m:01s		    -1.06ns		  54 /        15
   6		0h:00m:01s		    -1.14ns		  55 /        15
   7		0h:00m:01s		    -1.14ns		  56 /        15

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 197MB)


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 125MB peak: 197MB)

Writing Analyst data base D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 197MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 197MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB)

@W: MT420 |Found inferred clock RAM_based_shift_reg_top|clk with period 4.75ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jul 18 11:03:31 2018
#


Top view:               RAM_based_shift_reg_top
Requested Frequency:    210.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.838

                                Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------
RAM_based_shift_reg_top|clk     210.7 MHz     179.1 MHz     4.747         5.584         -0.838     inferred     Autoconstr_clkgroup_0
System                          150.0 MHz     397.5 MHz     6.667         2.516         4.151      system       system_clkgroup      
=====================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------
System                       RAM_based_shift_reg_top|clk  |  4.747       4.151   |  No paths    -      |  No paths    -      |  No paths    -    
RAM_based_shift_reg_top|clk  System                       |  4.747       3.969   |  No paths    -      |  No paths    -      |  No paths    -    
RAM_based_shift_reg_top|clk  RAM_based_shift_reg_top|clk  |  4.747       -0.838  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: RAM_based_shift_reg_top|clk
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                         Arrival           
Instance                              Reference                       Type     Pin     Net             Time        Slack 
                                      Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[2]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[2]      0.243       -0.838
u_RAM_based_shift_reg.ADDR_in[3]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[3]      0.243       -0.747
u_RAM_based_shift_reg.ADDR_in[0]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[0]      0.243       -0.665
u_RAM_based_shift_reg.ADDR_in[1]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[1]      0.243       -0.574
u_RAM_based_shift_reg.rbin_num[4]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[4]     0.243       -0.219
u_RAM_based_shift_reg.rbin_num[3]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[3]     0.243       -0.198
u_RAM_based_shift_reg.rbin_num[2]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[2]     0.243       -0.049
u_RAM_based_shift_reg.rbin_num[1]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[1]     0.243       -0.028
u_RAM_based_shift_reg.RdEn            RAM_based_shift_reg_top|clk     DFFC     Q       RdEn            0.243       0.290 
u_RAM_based_shift_reg.rbin_num[0]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[0]     0.243       0.357 
=========================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                             Required           
Instance                              Reference                       Type     Pin        Net              Time         Slack 
                                      Clock                                                                                   
------------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.rbin_num[4]     RAM_based_shift_reg_top|clk     DFFC     D          un7_axbxc2       4.686        -0.838
u_RAM_based_shift_reg.rbin_num[3]     RAM_based_shift_reg_top|clk     DFFC     D          un7_axbxc1       4.686        -0.213
u_RAM_based_shift_reg.rbin_num[2]     RAM_based_shift_reg_top|clk     DFFC     D          un7_axbxc0       4.686        0.134 
u_RAM_based_shift_reg.rbin_num[0]     RAM_based_shift_reg_top|clk     DFFC     D          un7_axbxc0_0     4.686        0.158 
u_RAM_based_shift_reg.rbin_num[1]     RAM_based_shift_reg_top|clk     DFFC     D          un7_axbxc1_0     4.686        0.413 
u_RAM_based_shift_reg.wbin[1]         RAM_based_shift_reg_top|clk     DFFC     D          wbin_RNO[1]      4.686        3.338 
u_RAM_based_shift_reg.wbin[2]         RAM_based_shift_reg_top|clk     DFFC     D          wbin_RNO[2]      4.686        3.338 
u_RAM_based_shift_reg.wbin[3]         RAM_based_shift_reg_top|clk     DFFC     D          wbin_RNO[3]      4.686        3.338 
u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SDP      ADA[3]     wbin[0]          4.709        3.931 
u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SDP      ADA[4]     wbin[1]          4.709        3.931 
==============================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      5.523
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.838

    Number of logic level(s):                6
    Starting point:                          u_RAM_based_shift_reg.ADDR_in[2] / Q
    Ending point:                            u_RAM_based_shift_reg.rbin_num[4] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[2]              DFFC          Q        Out     0.243     0.243       -         
ADDR_in[2]                                    Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.addr_ch_0               LUT4          I2       In      -         0.778       -         
u_RAM_based_shift_reg.addr_ch_0               LUT4          F        Out     0.462     1.240       -         
g0_8_1_1                                      Net           -        -       0.535     -           8         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          I1       In      -         1.775       -         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          F        Out     0.570     2.345       -         
g0_7_1_1                                      Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     I1       In      -         2.345       -         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     O        Out     0.105     2.450       -         
g0_7_1_0                                      Net           -        -       0.535     -           1         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          I2       In      -         2.985       -         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          F        Out     0.462     3.447       -         
un7_ac0_7                                     Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.un7_axbxc2_1_0          LUT4          I1       In      -         3.982       -         
u_RAM_based_shift_reg.un7_axbxc2_1_0          LUT4          F        Out     0.570     4.552       -         
un7_axbxc2_1_0                                Net           -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_axbxc2              LUT4          I1       In      -         4.953       -         
u_RAM_based_shift_reg.un7_axbxc2              LUT4          F        Out     0.570     5.523       -         
un7_axbxc2                                    Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.rbin_num[4]             DFFC          D        In      -         5.523       -         
=============================================================================================================
Total path delay (propagation time + setup) of 5.584 is 3.043(54.5%) logic and 2.541(45.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      5.523
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.838

    Number of logic level(s):                6
    Starting point:                          u_RAM_based_shift_reg.ADDR_in[2] / Q
    Ending point:                            u_RAM_based_shift_reg.rbin_num[4] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[2]               DFFC          Q        Out     0.243     0.243       -         
ADDR_in[2]                                     Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.addr_ch_0                LUT4          I2       In      -         0.778       -         
u_RAM_based_shift_reg.addr_ch_0                LUT4          F        Out     0.462     1.240       -         
g0_8_1_1                                       Net           -        -       0.535     -           8         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          I1       In      -         1.775       -         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          F        Out     0.570     2.345       -         
g0_7_1_0_0                                     Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     I0       In      -         2.345       -         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     O        Out     0.105     2.450       -         
g0_7_1_0                                       Net           -        -       0.535     -           1         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          I2       In      -         2.985       -         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          F        Out     0.462     3.447       -         
un7_ac0_7                                      Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.un7_axbxc2_1_0           LUT4          I1       In      -         3.982       -         
u_RAM_based_shift_reg.un7_axbxc2_1_0           LUT4          F        Out     0.570     4.552       -         
un7_axbxc2_1_0                                 Net           -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_axbxc2               LUT4          I1       In      -         4.953       -         
u_RAM_based_shift_reg.un7_axbxc2               LUT4          F        Out     0.570     5.523       -         
un7_axbxc2                                     Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.rbin_num[4]              DFFC          D        In      -         5.523       -         
==============================================================================================================
Total path delay (propagation time + setup) of 5.584 is 3.043(54.5%) logic and 2.541(45.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      5.432
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.747

    Number of logic level(s):                6
    Starting point:                          u_RAM_based_shift_reg.ADDR_in[3] / Q
    Ending point:                            u_RAM_based_shift_reg.rbin_num[4] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[3]              DFFC          Q        Out     0.243     0.243       -         
ADDR_in[3]                                    Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.addr_ch_0               LUT4          I3       In      -         0.778       -         
u_RAM_based_shift_reg.addr_ch_0               LUT4          F        Out     0.371     1.149       -         
g0_8_1_1                                      Net           -        -       0.535     -           8         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          I1       In      -         1.684       -         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          F        Out     0.570     2.254       -         
g0_7_1_1                                      Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     I1       In      -         2.254       -         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     O        Out     0.105     2.359       -         
g0_7_1_0                                      Net           -        -       0.535     -           1         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          I2       In      -         2.894       -         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          F        Out     0.462     3.356       -         
un7_ac0_7                                     Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.un7_axbxc2_1_0          LUT4          I1       In      -         3.891       -         
u_RAM_based_shift_reg.un7_axbxc2_1_0          LUT4          F        Out     0.570     4.461       -         
un7_axbxc2_1_0                                Net           -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_axbxc2              LUT4          I1       In      -         4.862       -         
u_RAM_based_shift_reg.un7_axbxc2              LUT4          F        Out     0.570     5.432       -         
un7_axbxc2                                    Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.rbin_num[4]             DFFC          D        In      -         5.432       -         
=============================================================================================================
Total path delay (propagation time + setup) of 5.493 is 2.952(53.7%) logic and 2.541(46.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      5.432
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.747

    Number of logic level(s):                6
    Starting point:                          u_RAM_based_shift_reg.ADDR_in[3] / Q
    Ending point:                            u_RAM_based_shift_reg.rbin_num[4] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[3]               DFFC          Q        Out     0.243     0.243       -         
ADDR_in[3]                                     Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.addr_ch_0                LUT4          I3       In      -         0.778       -         
u_RAM_based_shift_reg.addr_ch_0                LUT4          F        Out     0.371     1.149       -         
g0_8_1_1                                       Net           -        -       0.535     -           8         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          I1       In      -         1.684       -         
u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          F        Out     0.570     2.254       -         
g0_7_1_0_0                                     Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     I0       In      -         2.254       -         
u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     O        Out     0.105     2.359       -         
g0_7_1_0                                       Net           -        -       0.535     -           1         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          I2       In      -         2.894       -         
u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          F        Out     0.462     3.356       -         
un7_ac0_7                                      Net           -        -       0.535     -           3         
u_RAM_based_shift_reg.un7_axbxc2_1_0           LUT4          I1       In      -         3.891       -         
u_RAM_based_shift_reg.un7_axbxc2_1_0           LUT4          F        Out     0.570     4.461       -         
un7_axbxc2_1_0                                 Net           -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_axbxc2               LUT4          I1       In      -         4.862       -         
u_RAM_based_shift_reg.un7_axbxc2               LUT4          F        Out     0.570     5.432       -         
un7_axbxc2                                     Net           -        -       0.000     -           1         
u_RAM_based_shift_reg.rbin_num[4]              DFFC          D        In      -         5.432       -         
==============================================================================================================
Total path delay (propagation time + setup) of 5.493 is 2.952(53.7%) logic and 2.541(46.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      5.371
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.686

    Number of logic level(s):                5
    Starting point:                          u_RAM_based_shift_reg.ADDR_in[2] / Q
    Ending point:                            u_RAM_based_shift_reg.rbin_num[4] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.ADDR_in[2]         DFFC     Q        Out     0.243     0.243       -         
ADDR_in[2]                               Net      -        -       0.535     -           3         
u_RAM_based_shift_reg.addr_ch_0          LUT4     I2       In      -         0.778       -         
u_RAM_based_shift_reg.addr_ch_0          LUT4     F        Out     0.462     1.240       -         
g0_8_1_1                                 Net      -        -       0.535     -           8         
u_RAM_based_shift_reg.un7_ac0_1_1_1      LUT2     I1       In      -         1.775       -         
u_RAM_based_shift_reg.un7_ac0_1_1_1      LUT2     F        Out     0.570     2.345       -         
g0_2_1_0                                 Net      -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_ac0_1_1        LUT4     I1       In      -         2.746       -         
u_RAM_based_shift_reg.un7_ac0_1_1        LUT4     F        Out     0.570     3.316       -         
un7_ac0_1_1                              Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.un7_axbxc2_1_0     LUT4     I0       In      -         3.851       -         
u_RAM_based_shift_reg.un7_axbxc2_1_0     LUT4     F        Out     0.549     4.400       -         
un7_axbxc2_1_0                           Net      -        -       0.401     -           1         
u_RAM_based_shift_reg.un7_axbxc2         LUT4     I1       In      -         4.801       -         
u_RAM_based_shift_reg.un7_axbxc2         LUT4     F        Out     0.570     5.371       -         
un7_axbxc2                               Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.rbin_num[4]        DFFC     D        In      -         5.371       -         
===================================================================================================
Total path delay (propagation time + setup) of 5.432 is 3.025(55.7%) logic and 2.407(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                    Starting                                     Arrival          
Instance                            Reference     Type     Pin     Net           Time        Slack
                                    Clock                                                         
--------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin_i[0]     System        INV      O       wbin_i[0]     0.000       4.151
==================================================================================================


Ending Points with Worst Slack
******************************

                                  Starting                                     Required          
Instance                          Reference     Type     Pin     Net           Time         Slack
                                  Clock                                                          
-------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[0]     System        DFFC     D       wbin_i[0]     4.686        4.151
=================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.747
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.686

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.151

    Number of logic level(s):                0
    Starting point:                          u_RAM_based_shift_reg.wbin_i[0] / O
    Ending point:                            u_RAM_based_shift_reg.wbin[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin_i[0]     INV      O        Out     0.000     0.000       -         
wbin_i[0]                           Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.wbin[0]       DFFC     D        In      -         0.535       -         
==============================================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB)

---------------------------------------
Resource Usage Report for RAM_based_shift_reg_top 

Mapping to part: gw2a_55pbga484-8
Cell usage:
DFFC            14 uses
GSR             1 use
INV             1 use
MUX2_LUT5       9 uses
MUX2_LUT6       1 use
SDP             1 use
LUT2            12 uses
LUT3            2 uses
LUT4            40 uses

I/O Register bits:                  0
Register bits not including I/Os:   14 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 1 of 140 (0%)

Total load per clock:
   RAM_based_shift_reg_top|clk: 16

@S |Mapping Summary:
Total  LUTs: 54 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 197MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Wed Jul 18 11:03:31 2018

###########################################################]
