
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

Modified Files: 3
FID:  path (prevtimestamp, timestamp)
7        E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v (2018-07-16 14:17:38, 2018-07-16 14:19:37)
8        E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v (2018-07-16 14:17:38, 2018-07-16 14:19:37)
9        E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v (2018-07-16 14:17:38, 2018-07-16 14:19:37)

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Modules that may have changed as a result of file changes: 0
MID:  lib.cell.view

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Unmodified files: 7
FID:  path (timestamp)
0        C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v (2018-01-25 16:33:05)
1        C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v (2018-01-05 14:27:43)
2        C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v (2018-05-16 00:54:34)
3        C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v (2018-05-16 00:08:32)
4        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v (2018-05-16 00:08:32)
5        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh (2018-05-16 00:08:32)
6        C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v (2018-05-16 00:08:32)

*******************************************************************
Unchanged modules: 2
MID:  lib.cell.view
0        work.RAM_based_shift_reg_top.verilog
1        work.\~RAM_based_shift_reg.RAM_based_shift_reg_top.verilog
