`timescale 1 ns / 1 ns

// Define Module for Test Fixture
module RAM_base_shift_reg_tb();


    reg   CLK;
    reg   RST;
    wire  [7:0] Dout;

//events
event	test;
	 


// Initialize Inputs
initial begin
            CLK         = 0;
            RST         = 0;
         #5 RST         = 1;
        #100 RST         = 0;
    end

initial begin
	forever
	   #20 CLK = ~CLK ;		//  this is 25 MHz
end	 


initial begin 
	->test;
	#10_0000;
	$finish;
end

initial begin
  $fsdbDumpfile("tb.fsdb");
  $fsdbDumpvars;
end


TOP u_TOP(
              .reset(RST),
              .Q(Dout)
          );


endmodule // 