@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1601:7:1601:9|Synthesizing module OSC in library work.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\gw_osc\gw_osc.v":13:7:13:12|Synthesizing module GW_OSC in library work.
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1532:7:1532:9|Synthesizing module PLL in library work.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\gw_pll\gw_pll.v":13:7:13:12|Synthesizing module GW_PLL in library work.
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v":626:7:626:29|Synthesizing module RAM_based_shift_reg_top in library work.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\TOP.v":1:7:1:9|Synthesizing module TOP in library work.
@N|Running in 64-bit mode

