
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

Modified Files: 1
FID:  path (prevtimestamp, timestamp)
8        D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_pll\gw_pll.v (2018-09-14 16:57:37, 2018-09-18 08:51:02)

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Modules that may have changed as a result of file changes: 1
MID:  lib.cell.view
1        work.GW_PLL.verilog may have changed because the following files changed:
                        D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_pll\gw_pll.v (2018-09-14 16:57:37, 2018-09-18 08:51:02) <-- (module definition)

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Unmodified files: 8
FID:  path (timestamp)
0        C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v (2018-09-04 01:31:40)
1        C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v (2018-09-04 01:02:54)
2        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v (2018-09-04 01:02:54)
3        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh (2018-09-04 01:02:54)
4        C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v (2018-09-12 15:09:22)
5        D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v (2018-09-14 15:15:21)
6        D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\TOP.v (2018-09-14 17:18:02)
7        D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_osc\gw_osc.v (2018-07-10 09:17:08)

*******************************************************************
Unchanged modules: 4
MID:  lib.cell.view
0        work.GW_OSC.verilog
2        work.RAM_based_shift_reg_top.verilog
3        work.TOP.verilog
4        work.\~RAM_based_shift_reg.RAM_based_shift_reg_top_.verilog
