<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>4</Version>
    <Device>gw2a55-000</Device>
    <FileList>
        <File type="file.verilog" enable="1" path="src/TOP.v"/>
        <File type="file.verilog" enable="1" path="src/gw_osc/gw_osc.v"/>
        <File type="file.verilog" enable="1" path="src/gw_pll/gw_pll.v"/>
        <File type="file.cst" enable="1" path="src/lossy_ex.cst"/>
        <File type="file.verilog" enable="1" path="src/RAM_based_shift_reg_top/RAM_based_shift_reg_top.v"/>
        <File type="file.gao" enable="1" path="src/lossy_ex.gao"/>
    </FileList>
</Project>
