# Fri Sep 14 17:27:21 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex_scck.rpt 
Printing clock  summary report in "D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Beginning opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 

Finished opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)







Detailed report for transparent and observable latches in design:
@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\lossless_ex_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

syn_allowed_resources : blockrams=140  set on top level netlist TOP

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start                            Requested     Requested     Clock        Clock                     Clock
Level     Clock                            Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------
0 -       System                           150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                                   
0 -       GW_PLL|clkout_inferred_clock     298.3 MHz     3.352         inferred     Autoconstr_clkgroup_0     58   
===================================================================================================================



Clock Load Summary
***********************

                                 Clock     Source                               Clock Pin       Non-clock Pin     Non-clock Pin
Clock                            Load      Pin                                  Seq Example     Seq Example       Comb Example 
-------------------------------------------------------------------------------------------------------------------------------
System                           0         -                                    -               -                 -            
                                                                                                                               
GW_PLL|clkout_inferred_clock     58        GW_PLL_inst.pll_inst.CLKOUT(PLL)     Din[7:0].C      -                 -            
===============================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 58 clock pin(s) of sequential element(s)
0 instances converted, 58 sequential instances remain driven by gated/generated clocks

========================================================= Gated/Generated Clocks ==========================================================
Clock Tree ID     Driving Element                 Drive Element Type     Unconverted Fanout     Sample Instance     Explanation            
-------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_0       GW_PLL_inst.pll_inst.CLKOUT     PLL                    58                     ADDR[8:0]           Black box on clock path
===========================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 106MB peak: 192MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Sep 14 17:27:22 2018

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