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    # Wed Jul 18 13:39:57 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  lossless_ex_scck.rpt
    Printing clock  summary report in "D:\ex\lossless_ex\impl\synthesize\rev_1\lossless_ex_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    syn_allowed_resources : blockrams=140  set on top level netlist TOP

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Clock Summary
    ******************

              Start                            Requested     Requested     Clock        Clock                     Clock
    Level     Clock                            Frequency     Period        Type         Group                     Load
    -------------------------------------------------------------------------------------------------------------------
    0 -       System                           150.0 MHz     6.667         system       system_clkgroup           0

    0 -       GW_PLL|clkout_inferred_clock     298.3 MHz     3.352         inferred     Autoconstr_clkgroup_0     58
    ===================================================================================================================

    Clock Load Summary
    ***********************

                                     Clock     Source                               Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                            Load      Pin                                  Seq Example     Seq Example       Comb Example
    -------------------------------------------------------------------------------------------------------------------------------
    System                           0         -                                    -               -                 -

    GW_PLL|clkout_inferred_clock     58        GW_PLL_inst.pll_inst.CLKOUT(PLL)     Din[7:0].C      -                 -
    ===============================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 58 clock pin(s) of sequential element(s)
    0 instances converted, 58 sequential instances remain driven by gated/generated clocks

    ========================================================= Gated/Generated Clocks ==========================================================
    Clock Tree ID     Driving Element                 Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    -------------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_1       GW_PLL_inst.pll_inst.CLKOUT     PLL                    58                     ADDR[8:0]           Black box on clock path
    ===========================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\ex\lossless_ex\impl\synthesize\rev_1\lossless_ex.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 191MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Jul 18 13:39:58 2018

    ###########################################################]

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