module RAM_based_shift_reg_top(
	clk,
	Reset,
	Din,
	ADDR,
	Q
);
input clk;
input Reset;
input [7:0] Din;
input [8:0] ADDR;
output [7:0] Q;
wire [8:0] ADDR;
wire [7:0] Din;
wire GND;
wire [7:0] Q;
wire Reset;
wire VCC;
wire clk;
wire \gowin_add_ibuf_net_ADDR[0] ;
wire \gowin_add_ibuf_net_ADDR[1] ;
wire \gowin_add_ibuf_net_ADDR[2] ;
wire \gowin_add_ibuf_net_ADDR[3] ;
wire \gowin_add_ibuf_net_ADDR[4] ;
wire \gowin_add_ibuf_net_ADDR[5] ;
wire \gowin_add_ibuf_net_ADDR[6] ;
wire \gowin_add_ibuf_net_ADDR[7] ;
wire \gowin_add_ibuf_net_ADDR[8] ;
wire \gowin_add_ibuf_net_Din[0] ;
wire \gowin_add_ibuf_net_Din[1] ;
wire \gowin_add_ibuf_net_Din[2] ;
wire \gowin_add_ibuf_net_Din[3] ;
wire \gowin_add_ibuf_net_Din[4] ;
wire \gowin_add_ibuf_net_Din[5] ;
wire \gowin_add_ibuf_net_Din[6] ;
wire \gowin_add_ibuf_net_Din[7] ;
wire gowin_add_ibuf_net_Reset;
wire gowin_add_ibuf_net_clk;
wire \gowin_add_obuf_net_Q[0] ;
wire \gowin_add_obuf_net_Q[1] ;
wire \gowin_add_obuf_net_Q[2] ;
wire \gowin_add_obuf_net_Q[3] ;
wire \gowin_add_obuf_net_Q[4] ;
wire \gowin_add_obuf_net_Q[5] ;
wire \gowin_add_obuf_net_Q[6] ;
wire \gowin_add_obuf_net_Q[7] ;
wire [7:0] \u_RAM_based_shift_reg/un1_Din ;
wire [9:0] \u_RAM_based_shift_reg/rbin_num ;
wire [8:0] \u_RAM_based_shift_reg/ADDR_in ;
wire [8:0] \u_RAM_based_shift_reg/wbin ;
wire [0:0] \u_RAM_based_shift_reg/wbin_RNITJP51 ;
wire [1:1] \u_RAM_based_shift_reg/wbin_RNIKOVP1 ;
wire [2:2] \u_RAM_based_shift_reg/un4 ;
wire [7:0] \u_RAM_based_shift_reg/wbin_cry ;
wire [8:0] \u_RAM_based_shift_reg/wbin_s ;
wire [8:8] \u_RAM_based_shift_reg/wbin_s_0_COUT ;
wire [31:8] \u_RAM_based_shift_reg/mem_mem_0_0_DO ;
wire [2:2] \u_RAM_based_shift_reg/un5_0 ;
wire [2:2] \u_RAM_based_shift_reg/un5_1 ;
wire [2:2] \u_RAM_based_shift_reg/un5_1_0 ;
wire [2:2] \u_RAM_based_shift_reg/un5_1_1 ;
wire [2:2] \u_RAM_based_shift_reg/un5_0_0 ;
wire [2:2] \u_RAM_based_shift_reg/un5_0_1 ;
wire \u_RAM_based_shift_reg/rbin_num13_RNIGB0L4 ;
wire \u_RAM_based_shift_reg/un7_4 ;
wire \u_RAM_based_shift_reg/un7_6 ;
wire \u_RAM_based_shift_reg/un7_8 ;
wire \u_RAM_based_shift_reg/un7_10 ;
wire \u_RAM_based_shift_reg/un7_12 ;
wire \u_RAM_based_shift_reg/un7_14 ;
wire \u_RAM_based_shift_reg/VCC ;
wire \u_RAM_based_shift_reg/GND ;
wire \u_RAM_based_shift_reg/RdEn ;
wire \u_RAM_based_shift_reg/un7_3 ;
wire \u_RAM_based_shift_reg/un7_5 ;
wire \u_RAM_based_shift_reg/un7_7 ;
wire \u_RAM_based_shift_reg/un7_9 ;
wire \u_RAM_based_shift_reg/un7_11 ;
wire \u_RAM_based_shift_reg/un7_13 ;
wire \u_RAM_based_shift_reg/un7_ac0_1_1 ;
wire \u_RAM_based_shift_reg/rbin_num13 ;
wire \u_RAM_based_shift_reg/un7_2 ;
wire \u_RAM_based_shift_reg/un7_cry_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_1_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_2_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_3_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_4_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_5_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_6_0_0_SUM ;
wire \u_RAM_based_shift_reg/un7_s_7_0_SUM ;
wire \u_RAM_based_shift_reg/un7_cry_0 ;
wire \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_1 ;
wire \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_2 ;
wire \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_3 ;
wire \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_4 ;
wire \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_5 ;
wire \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_0 ;
wire \u_RAM_based_shift_reg/un7_cry_6 ;
wire \u_RAM_based_shift_reg/un7_axb_7 ;
wire \u_RAM_based_shift_reg/un7_axbxc0 ;
wire \u_RAM_based_shift_reg/un7_axbxc1 ;
wire \u_RAM_based_shift_reg/un7_ac0_1 ;
wire \u_RAM_based_shift_reg/addr_ch_N_7_mux ;
wire \u_RAM_based_shift_reg/rbin_num13_5 ;
wire \u_RAM_based_shift_reg/rbin_num13_6 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ;
wire \u_RAM_based_shift_reg/un7_0 ;
wire \u_RAM_based_shift_reg/un7_axb_7_1 ;
wire \u_RAM_based_shift_reg/un7_0_1 ;
wire \u_RAM_based_shift_reg/un7_0_1_0 ;
wire \u_RAM_based_shift_reg/un7_cry_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO ;
wire \u_RAM_based_shift_reg/un7_s_7_0_COUT ;
wire \u_RAM_based_shift_reg/un7_3_0 ;
wire \u_RAM_based_shift_reg/un7_3_1 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_0 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_1 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_0 ;
wire \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_1 ;
wire \u_RAM_based_shift_reg/un7_3_1_0 ;
wire \u_RAM_based_shift_reg/un7_3_1_1 ;
wire \u_RAM_based_shift_reg/un7_3_0_0 ;
wire \u_RAM_based_shift_reg/un7_3_0_1 ;
VCC VCC_cZ (
  .V(VCC)
);
GND GND_cZ (
  .G(GND)
);
GSR GSR_INST (
	.GSRI(VCC)
);
LUT4 \u_RAM_based_shift_reg/un7_axbxc1_cZ  (
	.I0(\u_RAM_based_shift_reg/wbin_RNITJP51 [0]),
	.I1(\u_RAM_based_shift_reg/wbin_RNIKOVP1 [1]),
	.I2(\u_RAM_based_shift_reg/un7_0 ),
	.I3(\u_RAM_based_shift_reg/un7_ac0_1_1 ),
	.F(\u_RAM_based_shift_reg/un7_axbxc1 )
);
defparam \u_RAM_based_shift_reg/un7_axbxc1_cZ .INIT=16'h963C;
LUT4 \u_RAM_based_shift_reg/un7_ac0_1_cZ  (
	.I0(\u_RAM_based_shift_reg/wbin_RNITJP51 [0]),
	.I1(\u_RAM_based_shift_reg/wbin_RNIKOVP1 [1]),
	.I2(\u_RAM_based_shift_reg/un7_0 ),
	.I3(\u_RAM_based_shift_reg/un7_ac0_1_1 ),
	.F(\u_RAM_based_shift_reg/un7_ac0_1 )
);
defparam \u_RAM_based_shift_reg/un7_ac0_1_cZ .INIT=16'h2800;
LUT4 \u_RAM_based_shift_reg/un4[8]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [8]),
	.I3(\u_RAM_based_shift_reg/wbin [8]),
	.F(\u_RAM_based_shift_reg/un7_13 )
);
defparam \u_RAM_based_shift_reg/un4[8] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4[7]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [7]),
	.I3(\u_RAM_based_shift_reg/wbin [7]),
	.F(\u_RAM_based_shift_reg/un7_11 )
);
defparam \u_RAM_based_shift_reg/un4[7] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4[6]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [6]),
	.I3(\u_RAM_based_shift_reg/wbin [6]),
	.F(\u_RAM_based_shift_reg/un7_9 )
);
defparam \u_RAM_based_shift_reg/un4[6] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4[5]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [5]),
	.I3(\u_RAM_based_shift_reg/wbin [5]),
	.F(\u_RAM_based_shift_reg/un7_7 )
);
defparam \u_RAM_based_shift_reg/un4[5] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4[4]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [4]),
	.I3(\u_RAM_based_shift_reg/wbin [4]),
	.F(\u_RAM_based_shift_reg/un7_5 )
);
defparam \u_RAM_based_shift_reg/un4[4] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4[3]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [3]),
	.I3(\u_RAM_based_shift_reg/wbin [3]),
	.F(\u_RAM_based_shift_reg/un7_3 )
);
defparam \u_RAM_based_shift_reg/un4[3] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/un4_cZ[2]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [2]),
	.I3(\u_RAM_based_shift_reg/wbin [2]),
	.F(\u_RAM_based_shift_reg/un4 [2])
);
defparam \u_RAM_based_shift_reg/un4_cZ[2] .INIT=16'h3120;
LUT2 \u_RAM_based_shift_reg/un7_axbxc0_cZ  (
	.I0(\u_RAM_based_shift_reg/wbin_RNITJP51 [0]),
	.I1(\u_RAM_based_shift_reg/un7_ac0_1_1 ),
	.F(\u_RAM_based_shift_reg/un7_axbxc0 )
);
defparam \u_RAM_based_shift_reg/un7_axbxc0_cZ .INIT=4'h6;
LUT3 \u_RAM_based_shift_reg/ADDR_RNIE2LN[8]  (
	.I0(ADDR[8]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_14 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNIE2LN[8] .INIT=8'h01;
LUT3 \u_RAM_based_shift_reg/ADDR_RNID1LN[7]  (
	.I0(ADDR[7]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_12 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNID1LN[7] .INIT=8'h01;
LUT3 \u_RAM_based_shift_reg/ADDR_RNIC0LN[6]  (
	.I0(ADDR[6]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_10 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNIC0LN[6] .INIT=8'h01;
LUT3 \u_RAM_based_shift_reg/ADDR_RNIBVKN[5]  (
	.I0(ADDR[5]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_8 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNIBVKN[5] .INIT=8'h01;
LUT3 \u_RAM_based_shift_reg/ADDR_RNIAUKN[4]  (
	.I0(ADDR[4]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_6 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNIAUKN[4] .INIT=8'h01;
LUT3 \u_RAM_based_shift_reg/ADDR_RNI9TKN[3]  (
	.I0(ADDR[3]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_4 )
);
defparam \u_RAM_based_shift_reg/ADDR_RNI9TKN[3] .INIT=8'h01;
LUT4 \u_RAM_based_shift_reg/wbin_RNITJP51_cZ[0]  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [0]),
	.I3(\u_RAM_based_shift_reg/wbin [0]),
	.F(\u_RAM_based_shift_reg/wbin_RNITJP51 [0])
);
defparam \u_RAM_based_shift_reg/wbin_RNITJP51_cZ[0] .INIT=16'h3120;
LUT4 \u_RAM_based_shift_reg/RdEn_RNIF8V41  (
	.I0(ADDR[0]),
	.I1(\u_RAM_based_shift_reg/RdEn ),
	.I2(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I3(\u_RAM_based_shift_reg/rbin_num13 ),
	.F(\u_RAM_based_shift_reg/un7_ac0_1_1 )
);
defparam \u_RAM_based_shift_reg/RdEn_RNIF8V41 .INIT=16'h00C5;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/addr_ch_N_7_mux )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2 .INIT=16'h8000;
LUT4 \u_RAM_based_shift_reg/rbin_num13_cZ  (
	.I0(\u_RAM_based_shift_reg/rbin_num13_5 ),
	.I1(\u_RAM_based_shift_reg/rbin_num13_6 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [8]),
	.I3(\u_RAM_based_shift_reg/rbin_num [9]),
	.F(\u_RAM_based_shift_reg/rbin_num13 )
);
defparam \u_RAM_based_shift_reg/rbin_num13_cZ .INIT=16'h0080;
LUT4 \u_RAM_based_shift_reg/rbin_num13_5_cZ  (
	.I0(\u_RAM_based_shift_reg/rbin_num [4]),
	.I1(\u_RAM_based_shift_reg/rbin_num [5]),
	.I2(\u_RAM_based_shift_reg/rbin_num [6]),
	.I3(\u_RAM_based_shift_reg/rbin_num [7]),
	.F(\u_RAM_based_shift_reg/rbin_num13_5 )
);
defparam \u_RAM_based_shift_reg/rbin_num13_5_cZ .INIT=16'h8000;
LUT4 \u_RAM_based_shift_reg/rbin_num13_6_cZ  (
	.I0(\u_RAM_based_shift_reg/rbin_num [0]),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/rbin_num [2]),
	.I3(\u_RAM_based_shift_reg/rbin_num [3]),
	.F(\u_RAM_based_shift_reg/rbin_num13_6 )
);
defparam \u_RAM_based_shift_reg/rbin_num13_6_cZ .INIT=16'h8000;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_cZ  (
	.I0(ADDR[0]),
	.I1(ADDR[6]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [0]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [6]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_cZ .INIT=16'h8421;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_2_cZ  (
	.I0(ADDR[4]),
	.I1(ADDR[7]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [4]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [7]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_2_cZ .INIT=16'h8421;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_3_cZ  (
	.I0(ADDR[2]),
	.I1(ADDR[5]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [2]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [5]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_3_cZ .INIT=16'h8421;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[0]  (
	.I0(Din[0]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [0])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[0] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[1]  (
	.I0(Din[1]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [1])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[1] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[2]  (
	.I0(Din[2]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [2])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[2] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[3]  (
	.I0(Din[3]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [3])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[3] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[4]  (
	.I0(Din[4]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [4])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[4] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[5]  (
	.I0(Din[5]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [5])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[5] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[6]  (
	.I0(Din[6]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [6])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[6] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[7]  (
	.I0(Din[7]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [7])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[7] .INIT=4'h2;
LUT3 \u_RAM_based_shift_reg/un7_axb_7_1_cZ  (
	.I0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I1(\u_RAM_based_shift_reg/rbin_num13 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [9]),
	.F(\u_RAM_based_shift_reg/un7_axb_7_1 )
);
defparam \u_RAM_based_shift_reg/un7_axb_7_1_cZ .INIT=8'h4E;
LUT3 \u_RAM_based_shift_reg/un7_0_1_cZ  (
	.I0(\u_RAM_based_shift_reg/rbin_num13_5 ),
	.I1(\u_RAM_based_shift_reg/rbin_num13_6 ),
	.I2(\u_RAM_based_shift_reg/rbin_num [8]),
	.F(\u_RAM_based_shift_reg/un7_0_1 )
);
defparam \u_RAM_based_shift_reg/un7_0_1_cZ .INIT=8'h7F;
LUT4 \u_RAM_based_shift_reg/un7_0_cZ  (
	.I0(ADDR[1]),
	.I1(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.I2(\u_RAM_based_shift_reg/rbin_num [9]),
	.I3(\u_RAM_based_shift_reg/un7_0_1 ),
	.F(\u_RAM_based_shift_reg/un7_0 )
);
defparam \u_RAM_based_shift_reg/un7_0_cZ .INIT=16'h2220;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/un7_0_1_0 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV .INIT=16'h7FFF;
LUT4 \u_RAM_based_shift_reg/wbin_RNIKOVP1_cZ[1]  (
	.I0(\u_RAM_based_shift_reg/rbin_num13 ),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/un7_0_1_0 ),
	.I3(\u_RAM_based_shift_reg/wbin [1]),
	.F(\u_RAM_based_shift_reg/wbin_RNIKOVP1 [1])
);
defparam \u_RAM_based_shift_reg/wbin_RNIKOVP1_cZ[1] .INIT=16'h5404;
LUT2 \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_3 ),
	.I1(\u_RAM_based_shift_reg/un7_4 ),
	.F(\u_RAM_based_shift_reg/un7_cry_1_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_cZ .INIT=4'h6;
LUT2 \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_5 ),
	.I1(\u_RAM_based_shift_reg/un7_6 ),
	.F(\u_RAM_based_shift_reg/un7_cry_2_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_cZ .INIT=4'h6;
LUT2 \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_7 ),
	.I1(\u_RAM_based_shift_reg/un7_8 ),
	.F(\u_RAM_based_shift_reg/un7_cry_3_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_cZ .INIT=4'h6;
LUT2 \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_9 ),
	.I1(\u_RAM_based_shift_reg/un7_10 ),
	.F(\u_RAM_based_shift_reg/un7_cry_4_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_cZ .INIT=4'h6;
LUT2 \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_11 ),
	.I1(\u_RAM_based_shift_reg/un7_12 ),
	.F(\u_RAM_based_shift_reg/un7_cry_5_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_cZ .INIT=4'h6;
LUT2 \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_13 ),
	.I1(\u_RAM_based_shift_reg/un7_14 ),
	.F(\u_RAM_based_shift_reg/un7_cry_6_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_cZ .INIT=4'h6;
LUT3 \u_RAM_based_shift_reg/un7_axb_7_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_13 ),
	.I1(\u_RAM_based_shift_reg/un7_14 ),
	.I2(\u_RAM_based_shift_reg/un7_axb_7_1 ),
	.F(\u_RAM_based_shift_reg/un7_axb_7 )
);
defparam \u_RAM_based_shift_reg/un7_axb_7_cZ .INIT=8'h87;
LUT2 \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_11 ),
	.I1(\u_RAM_based_shift_reg/un7_12 ),
	.F(\u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_9 ),
	.I1(\u_RAM_based_shift_reg/un7_10 ),
	.F(\u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_7 ),
	.I1(\u_RAM_based_shift_reg/un7_8 ),
	.F(\u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_5 ),
	.I1(\u_RAM_based_shift_reg/un7_6 ),
	.F(\u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_3 ),
	.I1(\u_RAM_based_shift_reg/un7_4 ),
	.F(\u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_0_cZ  (
	.I0(\u_RAM_based_shift_reg/un4 [2]),
	.I1(\u_RAM_based_shift_reg/rbin_num13_RNIGB0L4 ),
	.F(\u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_0 )
);
defparam \u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_0_cZ .INIT=4'h8;
LUT2 \u_RAM_based_shift_reg/un7_cry_0_0_RNO_cZ  (
	.I0(\u_RAM_based_shift_reg/un4 [2]),
	.I1(\u_RAM_based_shift_reg/rbin_num13_RNIGB0L4 ),
	.F(\u_RAM_based_shift_reg/un7_cry_0_0_RNO )
);
defparam \u_RAM_based_shift_reg/un7_cry_0_0_RNO_cZ .INIT=4'h6;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_2  (
	.I0(ADDR[3]),
	.I1(ADDR[8]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [3]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [8]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_0 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_2 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_4  (
	.I0(ADDR[3]),
	.I1(ADDR[8]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [3]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [8]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_1 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_4 .INIT=16'h8421;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_1  (
	.I0(ADDR[3]),
	.I1(ADDR[8]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [3]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [8]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_0 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_1 .INIT=16'h8421;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_3  (
	.I0(ADDR[3]),
	.I1(ADDR[8]),
	.I2(\u_RAM_based_shift_reg/ADDR_in [3]),
	.I3(\u_RAM_based_shift_reg/ADDR_in [8]),
	.F(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_1 )
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_3 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_3  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/un5_1_0 [2])
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_3 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_1  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/un5_1_1 [2])
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_1 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_0  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/un5_0_0 [2])
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_0 .INIT=16'h7FFF;
LUT4 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_2  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_1 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_2 ),
	.I2(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_3 ),
	.I3(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 ),
	.F(\u_RAM_based_shift_reg/un5_0_1 [2])
);
defparam \u_RAM_based_shift_reg/addr_ch_m3_0_a2_1_RNIQ6IV_2 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/un7_3_RNO_2  (
	.I0(\u_RAM_based_shift_reg/rbin_num13 ),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/un7_0_1_0 ),
	.I3(\u_RAM_based_shift_reg/wbin [1]),
	.F(\u_RAM_based_shift_reg/un7_3_1_0 )
);
defparam \u_RAM_based_shift_reg/un7_3_RNO_2 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/un7_3_RNO_4  (
	.I0(\u_RAM_based_shift_reg/rbin_num13 ),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/un7_0_1_0 ),
	.I3(\u_RAM_based_shift_reg/wbin [1]),
	.F(\u_RAM_based_shift_reg/un7_3_1_1 )
);
defparam \u_RAM_based_shift_reg/un7_3_RNO_4 .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/un7_3_RNO_1  (
	.I0(\u_RAM_based_shift_reg/rbin_num13 ),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/un7_0_1_0 ),
	.I3(\u_RAM_based_shift_reg/wbin [1]),
	.F(\u_RAM_based_shift_reg/un7_3_0_0 )
);
defparam \u_RAM_based_shift_reg/un7_3_RNO_1 .INIT=16'h5555;
LUT4 \u_RAM_based_shift_reg/un7_3_RNO_3  (
	.I0(\u_RAM_based_shift_reg/rbin_num13 ),
	.I1(\u_RAM_based_shift_reg/rbin_num [1]),
	.I2(\u_RAM_based_shift_reg/un7_0_1_0 ),
	.I3(\u_RAM_based_shift_reg/wbin [1]),
	.F(\u_RAM_based_shift_reg/un7_3_0_1 )
);
defparam \u_RAM_based_shift_reg/un7_3_RNO_3 .INIT=16'h5404;
MUX2_LUT5 \u_RAM_based_shift_reg/un7_3_RNO  (
	.I0(\u_RAM_based_shift_reg/un7_3_0_0 ),
	.I1(\u_RAM_based_shift_reg/un7_3_0_1 ),
	.S0(ADDR[1]),
	.O(\u_RAM_based_shift_reg/un7_3_0 )
);
MUX2_LUT5 \u_RAM_based_shift_reg/un7_3_RNO_0  (
	.I0(\u_RAM_based_shift_reg/un7_3_1_0 ),
	.I1(\u_RAM_based_shift_reg/un7_3_1_1 ),
	.S0(ADDR[1]),
	.O(\u_RAM_based_shift_reg/un7_3_1 )
);
MUX2_LUT5 \u_RAM_based_shift_reg/ADDR_RNIP5J92_0[2]  (
	.I0(\u_RAM_based_shift_reg/un5_0_0 [2]),
	.I1(\u_RAM_based_shift_reg/un5_0_1 [2]),
	.S0(ADDR[2]),
	.O(\u_RAM_based_shift_reg/un5_0 [2])
);
MUX2_LUT5 \u_RAM_based_shift_reg/ADDR_RNIP5J92[2]  (
	.I0(\u_RAM_based_shift_reg/un5_1_0 [2]),
	.I1(\u_RAM_based_shift_reg/un5_1_1 [2]),
	.S0(ADDR[2]),
	.O(\u_RAM_based_shift_reg/un5_1 [2])
);
MUX2_LUT5 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_0 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0_1 ),
	.S0(ADDR[1]),
	.O(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0 )
);
MUX2_LUT5 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_RNO_0  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_0 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1_1 ),
	.S0(ADDR[1]),
	.O(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1 )
);
MUX2_LUT6 \u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_cZ  (
	.I0(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_0 ),
	.I1(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4_1 ),
	.S0(\u_RAM_based_shift_reg/ADDR_in [1]),
	.O(\u_RAM_based_shift_reg/addr_ch_m3_0_a2_4 )
);
MUX2_LUT6 \u_RAM_based_shift_reg/rbin_num13_RNIGB0L4_cZ  (
	.I0(\u_RAM_based_shift_reg/un5_0 [2]),
	.I1(\u_RAM_based_shift_reg/un5_1 [2]),
	.S0(\u_RAM_based_shift_reg/rbin_num13 ),
	.O(\u_RAM_based_shift_reg/rbin_num13_RNIGB0L4 )
);
MUX2_LUT6 \u_RAM_based_shift_reg/un7_3_cZ  (
	.I0(\u_RAM_based_shift_reg/un7_3_0 ),
	.I1(\u_RAM_based_shift_reg/un7_3_1 ),
	.S0(\u_RAM_based_shift_reg/addr_ch_N_7_mux ),
	.O(\u_RAM_based_shift_reg/un7_2 )
);
DFFC \u_RAM_based_shift_reg/wbin_Z[8]  (
	.D(\u_RAM_based_shift_reg/wbin_s [8]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [8])
);
defparam \u_RAM_based_shift_reg/wbin_Z[8] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[7]  (
	.D(\u_RAM_based_shift_reg/wbin_s [7]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [7])
);
defparam \u_RAM_based_shift_reg/wbin_Z[7] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[6]  (
	.D(\u_RAM_based_shift_reg/wbin_s [6]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [6])
);
defparam \u_RAM_based_shift_reg/wbin_Z[6] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[5]  (
	.D(\u_RAM_based_shift_reg/wbin_s [5]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [5])
);
defparam \u_RAM_based_shift_reg/wbin_Z[5] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[4]  (
	.D(\u_RAM_based_shift_reg/wbin_s [4]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [4])
);
defparam \u_RAM_based_shift_reg/wbin_Z[4] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[3]  (
	.D(\u_RAM_based_shift_reg/wbin_s [3]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [3])
);
defparam \u_RAM_based_shift_reg/wbin_Z[3] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[2]  (
	.D(\u_RAM_based_shift_reg/wbin_s [2]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [2])
);
defparam \u_RAM_based_shift_reg/wbin_Z[2] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[1]  (
	.D(\u_RAM_based_shift_reg/wbin_s [1]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [1])
);
defparam \u_RAM_based_shift_reg/wbin_Z[1] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[0]  (
	.D(\u_RAM_based_shift_reg/wbin_s [0]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [0])
);
defparam \u_RAM_based_shift_reg/wbin_Z[0] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/RdEn_Z  (
	.D(VCC),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/RdEn )
);
defparam \u_RAM_based_shift_reg/RdEn_Z .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[7]  (
	.D(ADDR[7]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [7])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[7] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[6]  (
	.D(ADDR[6]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [6])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[6] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[5]  (
	.D(ADDR[5]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [5])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[5] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[4]  (
	.D(ADDR[4]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [4])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[4] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[3]  (
	.D(ADDR[3]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [3])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[3] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[2]  (
	.D(ADDR[2]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [2])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[2] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[1]  (
	.D(ADDR[1]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [1])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[1] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[0]  (
	.D(ADDR[0]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [0])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[0] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[9]  (
	.D(\u_RAM_based_shift_reg/un7_s_7_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [9])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[9] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[8]  (
	.D(\u_RAM_based_shift_reg/un7_cry_6_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [8])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[8] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[7]  (
	.D(\u_RAM_based_shift_reg/un7_cry_5_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [7])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[7] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[6]  (
	.D(\u_RAM_based_shift_reg/un7_cry_4_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [6])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[6] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[5]  (
	.D(\u_RAM_based_shift_reg/un7_cry_3_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [5])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[5] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[4]  (
	.D(\u_RAM_based_shift_reg/un7_cry_2_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [4])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[4] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[3]  (
	.D(\u_RAM_based_shift_reg/un7_cry_1_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [3])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[3] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[2]  (
	.D(\u_RAM_based_shift_reg/un7_cry_0_0_SUM ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [2])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[2] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[1]  (
	.D(\u_RAM_based_shift_reg/un7_axbxc1 ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [1])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[1] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/rbin_num_Z[0]  (
	.D(\u_RAM_based_shift_reg/un7_axbxc0 ),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/rbin_num [0])
);
defparam \u_RAM_based_shift_reg/rbin_num_Z[0] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/ADDR_in_Z[8]  (
	.D(ADDR[8]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/ADDR_in [8])
);
defparam \u_RAM_based_shift_reg/ADDR_in_Z[8] .INIT=1'b0;
SDP \u_RAM_based_shift_reg/mem_mem_0_0  (
	.CLKA(clk),
	.CEA(VCC),
	.RESETA(GND),
	.WREA(VCC),
	.CLKB(clk),
	.CEB(VCC),
	.RESETB(Reset),
	.WREB(GND),
	.OCE(GND),
	.BLKSEL({GND, GND, GND}),
	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \u_RAM_based_shift_reg/un1_Din [7:0]}),
	.ADA({GND, GND, \u_RAM_based_shift_reg/wbin [8:0], GND, GND, GND}),
	.ADB({GND, GND, \u_RAM_based_shift_reg/rbin_num [8:0], GND, GND, GND}),
	.DO({\u_RAM_based_shift_reg/mem_mem_0_0_DO [31:8], Q[7:0]})
);
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .READ_MODE=1'b0;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BLK_SEL=3'b000;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BIT_WIDTH_0=8;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BIT_WIDTH_1=8;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .RESET_MODE="ASYNC";
ALU \u_RAM_based_shift_reg/un7_s_7_0  (
	.I0(\u_RAM_based_shift_reg/un7_axb_7 ),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_6 ),
	.COUT(\u_RAM_based_shift_reg/un7_s_7_0_COUT ),
	.SUM(\u_RAM_based_shift_reg/un7_s_7_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_s_7_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_6_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_6_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_6_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_5 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_6 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_6_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_6_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_5_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_5_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_5_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_4 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_5 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_5_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_5_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_4_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_4_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_4_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_3 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_4 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_4_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_4_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_3_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_3_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_3_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_2 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_3 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_3_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_3_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_2_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_2_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_2_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_1 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_2 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_2_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_2_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_1_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_1_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_cry_1_0_0_RNO_0 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_cry_0 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_1 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_1_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_1_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un7_cry_0_0  (
	.I0(\u_RAM_based_shift_reg/un7_cry_0_0_RNO ),
	.I1(\u_RAM_based_shift_reg/un7_2 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un7_ac0_1 ),
	.COUT(\u_RAM_based_shift_reg/un7_cry_0 ),
	.SUM(\u_RAM_based_shift_reg/un7_cry_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un7_cry_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_s_0[8]  (
	.I0(\u_RAM_based_shift_reg/wbin [8]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [7]),
	.COUT(\u_RAM_based_shift_reg/wbin_s_0_COUT [8]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [8])
);
defparam \u_RAM_based_shift_reg/wbin_s_0[8] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[7]  (
	.I0(\u_RAM_based_shift_reg/wbin [7]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [6]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [7]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [7])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[7] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[6]  (
	.I0(\u_RAM_based_shift_reg/wbin [6]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [5]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [6]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [6])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[6] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[5]  (
	.I0(\u_RAM_based_shift_reg/wbin [5]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [4]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [5]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [5])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[5] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[4]  (
	.I0(\u_RAM_based_shift_reg/wbin [4]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [3]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [4]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [4])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[4] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[3]  (
	.I0(\u_RAM_based_shift_reg/wbin [3]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [2]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [3]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [3])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[3] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[2]  (
	.I0(\u_RAM_based_shift_reg/wbin [2]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [1]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [2]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [2])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[2] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[1]  (
	.I0(\u_RAM_based_shift_reg/wbin [1]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [0]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [1]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [1])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[1] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[0]  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(GND),
	.I3(GND),
	.CIN(VCC),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [0]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [0])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[0] .ALU_MODE=0;
endmodule
