`

    #Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
    #install: C:\Gowin\1.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-047

    # Tue Sep 18 08:51:22 2018

    #Implementation: rev_1

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\TOP.v" (library work)
    @I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_osc\gw_osc.v" (library work)
    @I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_pll\gw_pll.v" (library work)
    @I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v" (library work)
    Verilog syntax check successful!
    File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_pll\gw_pll.v changed - recompiling
    Selecting top level module TOP
    @N:CG364 : gw2a.v(1601) | Synthesizing module OSC in library work.
    Running optimization stage 1 on OSC .......
    @N:CG364 : gw_osc.v(13) | Synthesizing module GW_OSC in library work.
    Running optimization stage 1 on GW_OSC .......
    @N:CG364 : gw2a.v(1532) | Synthesizing module PLL in library work.
    Running optimization stage 1 on PLL .......
    @N:CG364 : gw_pll.v(13) | Synthesizing module GW_PLL in library work.
    Running optimization stage 1 on GW_PLL .......
    @N:CG364 : gw2a.v(1597) | Synthesizing module GSR in library work.
    Running optimization stage 1 on GSR .......
    Running optimization stage 1 on LUT3 .......
    Running optimization stage 1 on LUT2 .......
    Running optimization stage 1 on DFFC .......
    Running optimization stage 1 on SP .......
    Running optimization stage 1 on GND .......
    Running optimization stage 1 on VCC .......
    Running optimization stage 1 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
    @N:CG364 : RAM_based_shift_reg_top.v(168) | Synthesizing module RAM_based_shift_reg_top in library work.
    Running optimization stage 1 on RAM_based_shift_reg_top .......
    @W:CL168 : RAM_based_shift_reg_top.v(201) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
    @N:CG364 : TOP.v(1) | Synthesizing module TOP in library work.
    Running optimization stage 1 on TOP .......
    @W:CL169 : TOP.v(36) | Pruning unused register cnt[9:0]. Make sure that there are no unused intermediate registers.
    Running optimization stage 2 on TOP .......
    Running optimization stage 2 on RAM_based_shift_reg_top .......
    Running optimization stage 2 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
    Running optimization stage 2 on VCC .......
    Running optimization stage 2 on GND .......
    Running optimization stage 2 on SP .......
    Running optimization stage 2 on DFFC .......
    Running optimization stage 2 on LUT2 .......
    Running optimization stage 2 on LUT3 .......
    Running optimization stage 2 on GSR .......
    Running optimization stage 2 on GW_PLL .......
    Running optimization stage 2 on PLL .......
    Running optimization stage 2 on GW_OSC .......
    Running optimization stage 2 on OSC .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Sep 18 08:51:22 2018

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

    @N: :  | Running in 64-bit mode
    File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Sep 18 08:51:22 2018

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Sep 18 08:51:22 2018

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Database state : D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\synwork\|rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

    @N: :  | Running in 64-bit mode
    File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\synwork\fixed_ex_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Sep 18 08:51:24 2018

    ###########################################################]

`
`

    # Tue Sep 18 08:51:24 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    @N:MF284 :  | Setting synthesis effort to medium for the design
    Linked File:  fixed_ex_scck.rpt
    Printing clock  summary report in "D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\fixed_ex_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.

    Beginning opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished opaque latch marking step (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Rerun analysis in 0 latches

    Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    @N:MF974 :  | Total number of latches (multibit) processed = 0
    @N:MF975 :  | Total number of latches (bit blasted) processed = 0
    @N:MF976 :  | Total number of (multibit) opaque latches found = 0
    @N:MF977 :  | Total number of (bit blasted) opaque latches found = 0

    Finished opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Detailed report for transparent and observable latches in design:
    Linked File:  fixed_ex_prem_latch_transparency_report.log

    Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    syn_allowed_resources : blockrams=140  set on top level netlist TOP

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Clock Summary
    ******************

              Start                            Requested     Requested     Clock        Clock                     Clock
    Level     Clock                            Frequency     Period        Type         Group                     Load
    -------------------------------------------------------------------------------------------------------------------
    0 -       System                           150.0 MHz     6.667         system       system_clkgroup           0

    0 -       GW_PLL|clkout_inferred_clock     491.8 MHz     2.033         inferred     Autoconstr_clkgroup_0     12
    ===================================================================================================================

    Clock Load Summary
    ***********************

                                     Clock     Source                               Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                            Load      Pin                                  Seq Example     Seq Example       Comb Example
    -------------------------------------------------------------------------------------------------------------------------------
    System                           0         -                                    -               -                 -

    GW_PLL|clkout_inferred_clock     12        GW_PLL_inst.pll_inst.CLKOUT(PLL)     Din[7:0].C      -                 -
    ===============================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 12 clock pin(s) of sequential element(s)
    0 instances converted, 12 sequential instances remain driven by gated/generated clocks

    ========================================================= Gated/Generated Clocks ==========================================================
    Clock Tree ID     Driving Element                 Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    -------------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_0       GW_PLL_inst.pll_inst.CLKOUT     PLL                    12                     Din[7:0]            Black box on clock path
    ===========================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\fixed_ex.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Sep 18 08:51:25 2018

    ###########################################################]

`
`

    # Tue Sep 18 08:51:25 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta1
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    @N:MO231 : top.v(28) | Found counter in view:work.TOP(verilog) instance Din[7:0]

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -0.78ns		  18 /         8
       2		0h:00m:00s		    -0.78ns		  18 /         8

       3		0h:00m:00s		    -0.78ns		  18 /         8

       4		0h:00m:00s		    -0.78ns		  18 /         8

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 191MB)

    Writing Analyst data base D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\synwork\fixed_ex_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 191MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

    @W:MT246 : gw_pll.v(26) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock GW_PLL|clkout_inferred_clock with period 2.21ns. Please declare a user-defined clock on net GW_PLL_inst.clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Sep 18 08:51:28 2018
    #

    Top view:               TOP
    Requested Frequency:    452.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.390

                                     Requested      Estimated      Requested     Estimated                Clock        Clock
    Starting Clock                   Frequency      Frequency      Period        Period        Slack      Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------
    GW_PLL|clkout_inferred_clock     452.0 MHz      384.2 MHz      2.213         2.603         -0.390     inferred     Autoconstr_clkgroup_0
    System                           2199.3 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup
    ========================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    System                        System                        |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -
    GW_PLL|clkout_inferred_clock  GW_PLL|clkout_inferred_clock  |  2.213       -0.390  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: GW_PLL|clkout_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                  Starting                                                      Arrival
    Instance                                                      Reference                        Type     Pin     Net         Time        Slack
                                                                  Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------
    Din[0]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[0]      0.243       -0.390
    Din[1]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[1]      0.243       -0.355
    Din[2]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[2]      0.243       -0.320
    Din[3]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[3]      0.243       -0.285
    Din[4]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[4]      0.243       -0.250
    Din[5]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[5]      0.243       -0.215
    Din[6]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[6]      0.243       -0.180
    Din[7]                                                        GW_PLL|clkout_inferred_clock     DFFC     Q       Din[7]      0.243       0.290
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFC     Q       wbin[1]     0.243       0.804
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     Q       wbin[0]     0.243       0.825
    ==============================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                Starting                                                                  Required
    Instance                                                    Reference                        Type     Pin       Net                   Time         Slack
                                                                Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------
    Din[7]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[7]              2.152        -0.390
    Din[6]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[6]              2.152        -0.355
    Din[5]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[5]              2.152        -0.320
    Din[4]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[4]              2.152        -0.285
    Din[3]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[3]              2.152        -0.250
    Din[2]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[2]              2.152        -0.215
    Din[1]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[1]              2.152        -0.180
    Din[0]                                                      GW_PLL|clkout_inferred_clock     DFFC     D         Din_s[0]              2.152        0.290
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.mem_mem_0_0     GW_PLL|clkout_inferred_clock     SP       DI[0]     \\un1_Din_cZ\[0\]     2.175        0.313
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.mem_mem_0_0     GW_PLL|clkout_inferred_clock     SP       DI[1]     \\un1_Din_cZ\[1\]     2.175        0.313
    =========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      2.213
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.152

        - Propagation time:                      2.542
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.390

        Number of logic level(s):                8
        Starting point:                          Din[0] / Q
        Ending point:                            Din[7] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    Din[0]             DFFC     Q        Out     0.243     0.243       -
    Din[0]             Net      -        -       0.535     -           2
    Din_cry_0[0]       ALU      I0       In      -         0.778       -
    Din_cry_0[0]       ALU      COUT     Out     0.549     1.327       -
    Din_cry[0]         Net      -        -       0.000     -           1
    Din_cry_0[1]       ALU      CIN      In      -         1.327       -
    Din_cry_0[1]       ALU      COUT     Out     0.035     1.362       -
    Din_cry[1]         Net      -        -       0.000     -           1
    Din_cry_0[2]       ALU      CIN      In      -         1.362       -
    Din_cry_0[2]       ALU      COUT     Out     0.035     1.397       -
    Din_cry[2]         Net      -        -       0.000     -           1
    Din_cry_0[3]       ALU      CIN      In      -         1.397       -
    Din_cry_0[3]       ALU      COUT     Out     0.035     1.432       -
    Din_cry[3]         Net      -        -       0.000     -           1
    Din_cry_0[4]       ALU      CIN      In      -         1.432       -
    Din_cry_0[4]       ALU      COUT     Out     0.035     1.467       -
    Din_cry[4]         Net      -        -       0.000     -           1
    Din_cry_0[5]       ALU      CIN      In      -         1.467       -
    Din_cry_0[5]       ALU      COUT     Out     0.035     1.502       -
    Din_cry[5]         Net      -        -       0.000     -           1
    Din_cry_0[6]       ALU      CIN      In      -         1.502       -
    Din_cry_0[6]       ALU      COUT     Out     0.035     1.537       -
    Din_cry[6]         Net      -        -       0.000     -           1
    Din_s_0[7]         ALU      CIN      In      -         1.537       -
    Din_s_0[7]         ALU      SUM      Out     0.470     2.007       -
    Din_s[7]           Net      -        -       0.535     -           1
    Din[7]             DFFC     D        In      -         2.542       -
    =============================================================================
    Total path delay (propagation time + setup) of 2.603 is 1.533(58.9%) logic and 1.070(41.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      2.213
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.152

        - Propagation time:                      2.507
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.355

        Number of logic level(s):                7
        Starting point:                          Din[1] / Q
        Ending point:                            Din[7] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    Din[1]             DFFC     Q        Out     0.243     0.243       -
    Din[1]             Net      -        -       0.535     -           2
    Din_cry_0[1]       ALU      I0       In      -         0.778       -
    Din_cry_0[1]       ALU      COUT     Out     0.549     1.327       -
    Din_cry[1]         Net      -        -       0.000     -           1
    Din_cry_0[2]       ALU      CIN      In      -         1.327       -
    Din_cry_0[2]       ALU      COUT     Out     0.035     1.362       -
    Din_cry[2]         Net      -        -       0.000     -           1
    Din_cry_0[3]       ALU      CIN      In      -         1.362       -
    Din_cry_0[3]       ALU      COUT     Out     0.035     1.397       -
    Din_cry[3]         Net      -        -       0.000     -           1
    Din_cry_0[4]       ALU      CIN      In      -         1.397       -
    Din_cry_0[4]       ALU      COUT     Out     0.035     1.432       -
    Din_cry[4]         Net      -        -       0.000     -           1
    Din_cry_0[5]       ALU      CIN      In      -         1.432       -
    Din_cry_0[5]       ALU      COUT     Out     0.035     1.467       -
    Din_cry[5]         Net      -        -       0.000     -           1
    Din_cry_0[6]       ALU      CIN      In      -         1.467       -
    Din_cry_0[6]       ALU      COUT     Out     0.035     1.502       -
    Din_cry[6]         Net      -        -       0.000     -           1
    Din_s_0[7]         ALU      CIN      In      -         1.502       -
    Din_s_0[7]         ALU      SUM      Out     0.470     1.972       -
    Din_s[7]           Net      -        -       0.535     -           1
    Din[7]             DFFC     D        In      -         2.507       -
    =============================================================================
    Total path delay (propagation time + setup) of 2.568 is 1.498(58.3%) logic and 1.070(41.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      2.213
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.152

        - Propagation time:                      2.507
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.355

        Number of logic level(s):                7
        Starting point:                          Din[0] / Q
        Ending point:                            Din[6] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    Din[0]             DFFC     Q        Out     0.243     0.243       -
    Din[0]             Net      -        -       0.535     -           2
    Din_cry_0[0]       ALU      I0       In      -         0.778       -
    Din_cry_0[0]       ALU      COUT     Out     0.549     1.327       -
    Din_cry[0]         Net      -        -       0.000     -           1
    Din_cry_0[1]       ALU      CIN      In      -         1.327       -
    Din_cry_0[1]       ALU      COUT     Out     0.035     1.362       -
    Din_cry[1]         Net      -        -       0.000     -           1
    Din_cry_0[2]       ALU      CIN      In      -         1.362       -
    Din_cry_0[2]       ALU      COUT     Out     0.035     1.397       -
    Din_cry[2]         Net      -        -       0.000     -           1
    Din_cry_0[3]       ALU      CIN      In      -         1.397       -
    Din_cry_0[3]       ALU      COUT     Out     0.035     1.432       -
    Din_cry[3]         Net      -        -       0.000     -           1
    Din_cry_0[4]       ALU      CIN      In      -         1.432       -
    Din_cry_0[4]       ALU      COUT     Out     0.035     1.467       -
    Din_cry[4]         Net      -        -       0.000     -           1
    Din_cry_0[5]       ALU      CIN      In      -         1.467       -
    Din_cry_0[5]       ALU      COUT     Out     0.035     1.502       -
    Din_cry[5]         Net      -        -       0.000     -           1
    Din_cry_0[6]       ALU      CIN      In      -         1.502       -
    Din_cry_0[6]       ALU      SUM      Out     0.470     1.972       -
    Din_s[6]           Net      -        -       0.535     -           1
    Din[6]             DFFC     D        In      -         2.507       -
    =============================================================================
    Total path delay (propagation time + setup) of 2.568 is 1.498(58.3%) logic and 1.070(41.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      2.213
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.152

        - Propagation time:                      2.472
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.320

        Number of logic level(s):                6
        Starting point:                          Din[2] / Q
        Ending point:                            Din[7] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    Din[2]             DFFC     Q        Out     0.243     0.243       -
    Din[2]             Net      -        -       0.535     -           2
    Din_cry_0[2]       ALU      I0       In      -         0.778       -
    Din_cry_0[2]       ALU      COUT     Out     0.549     1.327       -
    Din_cry[2]         Net      -        -       0.000     -           1
    Din_cry_0[3]       ALU      CIN      In      -         1.327       -
    Din_cry_0[3]       ALU      COUT     Out     0.035     1.362       -
    Din_cry[3]         Net      -        -       0.000     -           1
    Din_cry_0[4]       ALU      CIN      In      -         1.362       -
    Din_cry_0[4]       ALU      COUT     Out     0.035     1.397       -
    Din_cry[4]         Net      -        -       0.000     -           1
    Din_cry_0[5]       ALU      CIN      In      -         1.397       -
    Din_cry_0[5]       ALU      COUT     Out     0.035     1.432       -
    Din_cry[5]         Net      -        -       0.000     -           1
    Din_cry_0[6]       ALU      CIN      In      -         1.432       -
    Din_cry_0[6]       ALU      COUT     Out     0.035     1.467       -
    Din_cry[6]         Net      -        -       0.000     -           1
    Din_s_0[7]         ALU      CIN      In      -         1.467       -
    Din_s_0[7]         ALU      SUM      Out     0.470     1.937       -
    Din_s[7]           Net      -        -       0.535     -           1
    Din[7]             DFFC     D        In      -         2.472       -
    =============================================================================
    Total path delay (propagation time + setup) of 2.533 is 1.463(57.8%) logic and 1.070(42.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      2.213
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.152

        - Propagation time:                      2.472
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.320

        Number of logic level(s):                6
        Starting point:                          Din[0] / Q
        Ending point:                            Din[5] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    Din[0]             DFFC     Q        Out     0.243     0.243       -
    Din[0]             Net      -        -       0.535     -           2
    Din_cry_0[0]       ALU      I0       In      -         0.778       -
    Din_cry_0[0]       ALU      COUT     Out     0.549     1.327       -
    Din_cry[0]         Net      -        -       0.000     -           1
    Din_cry_0[1]       ALU      CIN      In      -         1.327       -
    Din_cry_0[1]       ALU      COUT     Out     0.035     1.362       -
    Din_cry[1]         Net      -        -       0.000     -           1
    Din_cry_0[2]       ALU      CIN      In      -         1.362       -
    Din_cry_0[2]       ALU      COUT     Out     0.035     1.397       -
    Din_cry[2]         Net      -        -       0.000     -           1
    Din_cry_0[3]       ALU      CIN      In      -         1.397       -
    Din_cry_0[3]       ALU      COUT     Out     0.035     1.432       -
    Din_cry[3]         Net      -        -       0.000     -           1
    Din_cry_0[4]       ALU      CIN      In      -         1.432       -
    Din_cry_0[4]       ALU      COUT     Out     0.035     1.467       -
    Din_cry[4]         Net      -        -       0.000     -           1
    Din_cry_0[5]       ALU      CIN      In      -         1.467       -
    Din_cry_0[5]       ALU      SUM      Out     0.470     1.937       -
    Din_s[5]           Net      -        -       0.535     -           1
    Din[5]             DFFC     D        In      -         2.472       -
    =============================================================================
    Total path delay (propagation time + setup) of 2.533 is 1.463(57.8%) logic and 1.070(42.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                          Starting                                      Arrival
    Instance              Reference     Type     Pin        Net         Time        Slack
                          Clock
    --------------------------------------------------------------------------------------
    osc_inst.osc_inst     System        OSC      OSCOUT     clk_osc     0.000       -0.080
    ======================================================================================

    Ending Points with Worst Slack
    ******************************

                             Starting                                     Required
    Instance                 Reference     Type     Pin       Net         Time         Slack
                             Clock
    -----------------------------------------------------------------------------------------
    GW_PLL_inst.pll_inst     System        PLL      CLKIN     clk_osc     0.455        -0.080
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.455
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.455

        - Propagation time:                      0.535
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.080

        Number of logic level(s):                0
        Starting point:                          osc_inst.osc_inst / OSCOUT
        Ending point:                            GW_PLL_inst.pll_inst / CLKIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                    Pin        Pin               Arrival     No. of
    Name                     Type     Name       Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------
    osc_inst.osc_inst        OSC      OSCOUT     Out     0.000     0.000       -
    clk_osc                  Net      -          -       0.535     -           1
    GW_PLL_inst.pll_inst     PLL      CLKIN      In      -         0.535       -
    =====================================================================================
    Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    ---------------------------------------
    Resource Usage Report for TOP

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             8 uses
    DFFC            11 uses
    GSR             1 use
    OSC             1 use
    PLL             1 use
    SP              1 use
    LUT2            8 uses
    LUT3            3 uses

    I/O ports: 9
    I/O primitives: 9
    IBUF           1 use
    OBUF           8 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   11 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 140 (0%)

    Total load per clock:
       GW_PLL|clkout_inferred_clock: 12

    @S |Mapping Summary:
    Total  LUTs: 11 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 40MB peak: 191MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Tue Sep 18 08:51:28 2018

    ###########################################################]

`