`

    #Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
    #install: C:\Gowin\1.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-047

    # Wed Jul 18 11:07:05 2018

    #Implementation: rev_1

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    @N: :  | : Running Verilog Compiler in System Verilog mode
    @N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode
    @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v" (library work)
    @I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v" (library work)
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module RAM_based_shift_reg_top
    @N:CG364 : RAM_based_shift_reg_top.v(6) | Synthesizing module RAM_based_shift_reg_top in library work.

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 73MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jul 18 11:07:06 2018

    ###########################################################]

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    File D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\layer0.srs changed - recompiling
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jul 18 11:07:06 2018

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jul 18 11:07:06 2018

    ###########################################################]

`
`

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Database state : D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\|rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    File D:\ex\lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_comp.srs changed - recompiling
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jul 18 11:07:07 2018

    ###########################################################]

`
`

    # Wed Jul 18 11:07:08 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  RAM_based_shift_reg_top_scck.rpt
    Printing clock  summary report in "D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    syn_allowed_resources : blockrams=140  set on top level netlist RAM_based_shift_reg_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Clock Summary
    ******************

              Start                           Requested     Requested     Clock        Clock                     Clock
    Level     Clock                           Frequency     Period        Type         Group                     Load
    ------------------------------------------------------------------------------------------------------------------
    0 -       RAM_based_shift_reg_top|clk     366.3 MHz     2.730         inferred     Autoconstr_clkgroup_0     25
    ==================================================================================================================

    Clock Load Summary
    ***********************

                                    Clock     Source        Clock Pin                              Non-clock Pin     Non-clock Pin
    Clock                           Load      Pin           Seq Example                            Seq Example       Comb Example
    ------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk     25        clk(port)     u_RAM_based_shift_reg.mem[7:0].CLK     -                 -
    ==============================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 18 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       clk                 Unconstrained_port     18         ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Jul 18 11:07:09 2018

    ###########################################################]

`
`

    # Wed Jul 18 11:07:09 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -1.34ns		  55 /        10
       2		0h:00m:00s		    -1.34ns		  55 /        10

       3		0h:00m:00s		    -1.34ns		  55 /        10

       4		0h:00m:00s		    -1.34ns		  55 /        10

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 191MB)

    Writing Analyst data base D:\ex\Lossy_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 191MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

    @W:MT420 :  | Found inferred clock RAM_based_shift_reg_top|clk with period 2.75ns. Please declare a user-defined clock on port clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Jul 18 11:07:12 2018
    #

    Top view:               RAM_based_shift_reg_top
    Requested Frequency:    363.8 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.485

                                    Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk     363.8 MHz     309.2 MHz     2.749         3.234         -0.485     inferred     Autoconstr_clkgroup_0
    =====================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk  RAM_based_shift_reg_top|clk  |  2.749       -0.485  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: RAM_based_shift_reg_top|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                      Starting                                                     Arrival
    Instance                          Reference                       Type     Pin     Net         Time        Slack
                                      Clock
    -----------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[0]     0.243       -0.485
    u_RAM_based_shift_reg.wbin[1]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[1]     0.243       -0.450
    u_RAM_based_shift_reg.wbin[2]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[2]     0.243       -0.415
    u_RAM_based_shift_reg.wbin[3]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[3]     0.243       -0.380
    u_RAM_based_shift_reg.wbin[4]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[4]     0.243       -0.345
    u_RAM_based_shift_reg.wbin[5]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[5]     0.243       -0.310
    u_RAM_based_shift_reg.wbin[6]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[6]     0.243       -0.275
    u_RAM_based_shift_reg.wbin[7]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[7]     0.243       -0.240
    u_RAM_based_shift_reg.wbin[8]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[8]     0.243       -0.205
    =================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                          Required
    Instance                              Reference                       Type     Pin       Net            Time         Slack
                                          Clock
    ---------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[0]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[1]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[1]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[2]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[2]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[3]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[3]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[4]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[4]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[5]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[5]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[6]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[6]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[7]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[7]     2.688        -0.485
    u_RAM_based_shift_reg.wbin[8]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_lm[8]     2.688        -0.485
    u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SP       AD[3]     wbin[0]        2.711        1.933
    ===========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      2.749
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.688

        - Propagation time:                      3.173
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.485

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
        Ending point:                            u_RAM_based_shift_reg.wbin[0] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                      Pin      Pin               Arrival     No. of
    Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]              DFFC     Q        Out     0.243     0.243       -
    wbin[0]                                    Net      -        -       0.535     -           4
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      I1       In      -         0.778       -
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      COUT     Out     0.570     1.348       -
    un1_wbin_cry_0                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      CIN      In      -         1.348       -
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      COUT     Out     0.035     1.383       -
    un1_wbin_cry_1                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      CIN      In      -         1.383       -
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      COUT     Out     0.035     1.418       -
    un1_wbin_cry_2                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      CIN      In      -         1.418       -
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      COUT     Out     0.035     1.453       -
    un1_wbin_cry_3                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      CIN      In      -         1.453       -
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      COUT     Out     0.035     1.488       -
    un1_wbin_cry_4                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      CIN      In      -         1.488       -
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      COUT     Out     0.035     1.523       -
    un1_wbin_cry_5                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      CIN      In      -         1.523       -
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      COUT     Out     0.035     1.558       -
    un1_wbin_cry_6                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      CIN      In      -         1.558       -
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      COUT     Out     0.035     1.593       -
    un1_wbin_cry_7                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      CIN      In      -         1.593       -
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      COUT     Out     0.035     1.628       -
    un1_wbin_cry_8                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      CIN      In      -         1.628       -
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      COUT     Out     0.035     1.663       -
    un1_wbin_cry_9                             Net      -        -       0.961     -           9
    u_RAM_based_shift_reg.wbin_lm_0[0]         LUT4     I0       In      -         2.624       -
    u_RAM_based_shift_reg.wbin_lm_0[0]         LUT4     F        Out     0.549     3.173       -
    wbin_lm[0]                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.wbin[0]              DFFC     D        In      -         3.173       -
    =====================================================================================================
    Total path delay (propagation time + setup) of 3.234 is 1.738(53.7%) logic and 1.496(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      2.749
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.688

        - Propagation time:                      3.173
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.485

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
        Ending point:                            u_RAM_based_shift_reg.wbin[8] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                      Pin      Pin               Arrival     No. of
    Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]              DFFC     Q        Out     0.243     0.243       -
    wbin[0]                                    Net      -        -       0.535     -           4
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      I1       In      -         0.778       -
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      COUT     Out     0.570     1.348       -
    un1_wbin_cry_0                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      CIN      In      -         1.348       -
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      COUT     Out     0.035     1.383       -
    un1_wbin_cry_1                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      CIN      In      -         1.383       -
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      COUT     Out     0.035     1.418       -
    un1_wbin_cry_2                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      CIN      In      -         1.418       -
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      COUT     Out     0.035     1.453       -
    un1_wbin_cry_3                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      CIN      In      -         1.453       -
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      COUT     Out     0.035     1.488       -
    un1_wbin_cry_4                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      CIN      In      -         1.488       -
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      COUT     Out     0.035     1.523       -
    un1_wbin_cry_5                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      CIN      In      -         1.523       -
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      COUT     Out     0.035     1.558       -
    un1_wbin_cry_6                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      CIN      In      -         1.558       -
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      COUT     Out     0.035     1.593       -
    un1_wbin_cry_7                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      CIN      In      -         1.593       -
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      COUT     Out     0.035     1.628       -
    un1_wbin_cry_8                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      CIN      In      -         1.628       -
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      COUT     Out     0.035     1.663       -
    un1_wbin_cry_9                             Net      -        -       0.961     -           9
    u_RAM_based_shift_reg.wbin_lm_0[8]         LUT4     I0       In      -         2.624       -
    u_RAM_based_shift_reg.wbin_lm_0[8]         LUT4     F        Out     0.549     3.173       -
    wbin_lm[8]                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.wbin[8]              DFFC     D        In      -         3.173       -
    =====================================================================================================
    Total path delay (propagation time + setup) of 3.234 is 1.738(53.7%) logic and 1.496(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      2.749
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.688

        - Propagation time:                      3.173
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.485

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
        Ending point:                            u_RAM_based_shift_reg.wbin[7] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                      Pin      Pin               Arrival     No. of
    Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]              DFFC     Q        Out     0.243     0.243       -
    wbin[0]                                    Net      -        -       0.535     -           4
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      I1       In      -         0.778       -
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      COUT     Out     0.570     1.348       -
    un1_wbin_cry_0                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      CIN      In      -         1.348       -
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      COUT     Out     0.035     1.383       -
    un1_wbin_cry_1                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      CIN      In      -         1.383       -
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      COUT     Out     0.035     1.418       -
    un1_wbin_cry_2                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      CIN      In      -         1.418       -
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      COUT     Out     0.035     1.453       -
    un1_wbin_cry_3                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      CIN      In      -         1.453       -
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      COUT     Out     0.035     1.488       -
    un1_wbin_cry_4                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      CIN      In      -         1.488       -
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      COUT     Out     0.035     1.523       -
    un1_wbin_cry_5                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      CIN      In      -         1.523       -
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      COUT     Out     0.035     1.558       -
    un1_wbin_cry_6                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      CIN      In      -         1.558       -
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      COUT     Out     0.035     1.593       -
    un1_wbin_cry_7                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      CIN      In      -         1.593       -
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      COUT     Out     0.035     1.628       -
    un1_wbin_cry_8                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      CIN      In      -         1.628       -
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      COUT     Out     0.035     1.663       -
    un1_wbin_cry_9                             Net      -        -       0.961     -           9
    u_RAM_based_shift_reg.wbin_lm_0[7]         LUT4     I0       In      -         2.624       -
    u_RAM_based_shift_reg.wbin_lm_0[7]         LUT4     F        Out     0.549     3.173       -
    wbin_lm[7]                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.wbin[7]              DFFC     D        In      -         3.173       -
    =====================================================================================================
    Total path delay (propagation time + setup) of 3.234 is 1.738(53.7%) logic and 1.496(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      2.749
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.688

        - Propagation time:                      3.173
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.485

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
        Ending point:                            u_RAM_based_shift_reg.wbin[6] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                      Pin      Pin               Arrival     No. of
    Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]              DFFC     Q        Out     0.243     0.243       -
    wbin[0]                                    Net      -        -       0.535     -           4
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      I1       In      -         0.778       -
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      COUT     Out     0.570     1.348       -
    un1_wbin_cry_0                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      CIN      In      -         1.348       -
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      COUT     Out     0.035     1.383       -
    un1_wbin_cry_1                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      CIN      In      -         1.383       -
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      COUT     Out     0.035     1.418       -
    un1_wbin_cry_2                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      CIN      In      -         1.418       -
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      COUT     Out     0.035     1.453       -
    un1_wbin_cry_3                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      CIN      In      -         1.453       -
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      COUT     Out     0.035     1.488       -
    un1_wbin_cry_4                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      CIN      In      -         1.488       -
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      COUT     Out     0.035     1.523       -
    un1_wbin_cry_5                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      CIN      In      -         1.523       -
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      COUT     Out     0.035     1.558       -
    un1_wbin_cry_6                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      CIN      In      -         1.558       -
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      COUT     Out     0.035     1.593       -
    un1_wbin_cry_7                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      CIN      In      -         1.593       -
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      COUT     Out     0.035     1.628       -
    un1_wbin_cry_8                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      CIN      In      -         1.628       -
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      COUT     Out     0.035     1.663       -
    un1_wbin_cry_9                             Net      -        -       0.961     -           9
    u_RAM_based_shift_reg.wbin_lm_0[6]         LUT4     I0       In      -         2.624       -
    u_RAM_based_shift_reg.wbin_lm_0[6]         LUT4     F        Out     0.549     3.173       -
    wbin_lm[6]                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.wbin[6]              DFFC     D        In      -         3.173       -
    =====================================================================================================
    Total path delay (propagation time + setup) of 3.234 is 1.738(53.7%) logic and 1.496(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      2.749
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.688

        - Propagation time:                      3.173
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.485

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
        Ending point:                            u_RAM_based_shift_reg.wbin[5] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                      Pin      Pin               Arrival     No. of
    Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.wbin[0]              DFFC     Q        Out     0.243     0.243       -
    wbin[0]                                    Net      -        -       0.535     -           4
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      I1       In      -         0.778       -
    u_RAM_based_shift_reg.un1_wbin_cry_0_0     ALU      COUT     Out     0.570     1.348       -
    un1_wbin_cry_0                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      CIN      In      -         1.348       -
    u_RAM_based_shift_reg.un1_wbin_cry_1_0     ALU      COUT     Out     0.035     1.383       -
    un1_wbin_cry_1                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      CIN      In      -         1.383       -
    u_RAM_based_shift_reg.un1_wbin_cry_2_0     ALU      COUT     Out     0.035     1.418       -
    un1_wbin_cry_2                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      CIN      In      -         1.418       -
    u_RAM_based_shift_reg.un1_wbin_cry_3_0     ALU      COUT     Out     0.035     1.453       -
    un1_wbin_cry_3                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      CIN      In      -         1.453       -
    u_RAM_based_shift_reg.un1_wbin_cry_4_0     ALU      COUT     Out     0.035     1.488       -
    un1_wbin_cry_4                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      CIN      In      -         1.488       -
    u_RAM_based_shift_reg.un1_wbin_cry_5_0     ALU      COUT     Out     0.035     1.523       -
    un1_wbin_cry_5                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      CIN      In      -         1.523       -
    u_RAM_based_shift_reg.un1_wbin_cry_6_0     ALU      COUT     Out     0.035     1.558       -
    un1_wbin_cry_6                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      CIN      In      -         1.558       -
    u_RAM_based_shift_reg.un1_wbin_cry_7_0     ALU      COUT     Out     0.035     1.593       -
    un1_wbin_cry_7                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      CIN      In      -         1.593       -
    u_RAM_based_shift_reg.un1_wbin_cry_8_0     ALU      COUT     Out     0.035     1.628       -
    un1_wbin_cry_8                             Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      CIN      In      -         1.628       -
    u_RAM_based_shift_reg.un1_wbin_cry_9_0     ALU      COUT     Out     0.035     1.663       -
    un1_wbin_cry_9                             Net      -        -       0.961     -           9
    u_RAM_based_shift_reg.wbin_lm_0[5]         LUT4     I0       In      -         2.624       -
    u_RAM_based_shift_reg.wbin_lm_0[5]         LUT4     F        Out     0.549     3.173       -
    wbin_lm[5]                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.wbin[5]              DFFC     D        In      -         3.173       -
    =====================================================================================================
    Total path delay (propagation time + setup) of 3.234 is 1.738(53.7%) logic and 1.496(46.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

    ---------------------------------------
    Resource Usage Report for RAM_based_shift_reg_top

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             28 uses
    DFFC            9 uses
    GSR             1 use
    MUX2_LUT5       1 use
    SP              1 use
    LUT2            8 uses
    LUT4            12 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   9 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 140 (0%)

    Total load per clock:
       RAM_based_shift_reg_top|clk: 10

    @S |Mapping Summary:
    Total  LUTs: 20 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 191MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Wed Jul 18 11:07:12 2018

    ###########################################################]

`