module RAM_based_shift_reg_top(
	clk,
	Reset,
	Din,
	Q
);
input clk;
input Reset;
input [7:0] Din;
output [7:0] Q;
wire [7:0] Din;
wire GND;
wire [7:0] Q;
wire Reset;
wire VCC;
wire clk;
wire [7:0] \u_RAM_based_shift_reg/un1_Din ;
wire [2:0] \u_RAM_based_shift_reg/wbin ;
wire [2:0] \u_RAM_based_shift_reg/wbin_3 ;
wire [31:8] \u_RAM_based_shift_reg/mem_mem_0_0_DO ;
VCC VCC_cZ (
  .V(VCC)
);
GND GND_cZ (
  .G(GND)
);
GSR GSR_INST (
	.GSRI(VCC)
);
LUT3 \u_RAM_based_shift_reg/wbin_3_cZ[2]  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(\u_RAM_based_shift_reg/wbin [1]),
	.I2(\u_RAM_based_shift_reg/wbin [2]),
	.F(\u_RAM_based_shift_reg/wbin_3 [2])
);
defparam \u_RAM_based_shift_reg/wbin_3_cZ[2] .INIT=8'h38;
LUT3 \u_RAM_based_shift_reg/wbin_3_cZ[1]  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(\u_RAM_based_shift_reg/wbin [1]),
	.I2(\u_RAM_based_shift_reg/wbin [2]),
	.F(\u_RAM_based_shift_reg/wbin_3 [1])
);
defparam \u_RAM_based_shift_reg/wbin_3_cZ[1] .INIT=8'h26;
LUT3 \u_RAM_based_shift_reg/wbin_3_cZ[0]  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(\u_RAM_based_shift_reg/wbin [1]),
	.I2(\u_RAM_based_shift_reg/wbin [2]),
	.F(\u_RAM_based_shift_reg/wbin_3 [0])
);
defparam \u_RAM_based_shift_reg/wbin_3_cZ[0] .INIT=8'h15;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[0]  (
	.I0(Din[0]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [0])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[0] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[1]  (
	.I0(Din[1]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [1])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[1] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[2]  (
	.I0(Din[2]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [2])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[2] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[3]  (
	.I0(Din[3]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [3])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[3] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[4]  (
	.I0(Din[4]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [4])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[4] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[5]  (
	.I0(Din[5]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [5])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[5] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[6]  (
	.I0(Din[6]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [6])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[6] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[7]  (
	.I0(Din[7]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [7])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[7] .INIT=4'h2;
DFFC \u_RAM_based_shift_reg/wbin_Z[2]  (
	.D(\u_RAM_based_shift_reg/wbin_3 [2]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [2])
);
defparam \u_RAM_based_shift_reg/wbin_Z[2] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[1]  (
	.D(\u_RAM_based_shift_reg/wbin_3 [1]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [1])
);
defparam \u_RAM_based_shift_reg/wbin_Z[1] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[0]  (
	.D(\u_RAM_based_shift_reg/wbin_3 [0]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [0])
);
defparam \u_RAM_based_shift_reg/wbin_Z[0] .INIT=1'b0;
SP \u_RAM_based_shift_reg/mem_mem_0_0  (
	.CLK(clk),
	.OCE(GND),
	.CE(VCC),
	.RESET(Reset),
	.WRE(VCC),
	.BLKSEL({GND, GND, GND}),
	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \u_RAM_based_shift_reg/un1_Din [7:0]}),
	.AD({GND, GND, GND, GND, GND, GND, GND, GND, \u_RAM_based_shift_reg/wbin [2:0], GND, GND, GND}),
	.DO({\u_RAM_based_shift_reg/mem_mem_0_0_DO [31:8], Q[7:0]})
);
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .READ_MODE=1'b0;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .WRITE_MODE=2'b10;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BLK_SEL=3'b000;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BIT_WIDTH=8;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .RESET_MODE="ASYNC";
endmodule
