Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Tool Version | v1.8.1.01Beta
Series, Device, Package, Speed, Operating Conditions | GW2A, GW2A-55, PBGA484, 8, COMMERCIAL
Design Name | TOP
Design File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\fixed_ex.vm
Timing Constraint File | ---
Timing Report File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\pnr\fixed_ex.tr.html
Created Time | Wed Sep 19 08:40:22 2018
Command Line | D:\Gowin\1.8\Pnr\bin\gowin.exe -do E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\pnr\cmd.do
Legal Announcement | Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.95V 85C
Hold Delay Model | Fast 1.05V 0C
Numbers of Paths Analyzed | 474
Numbers of Endpoints Analyzed | 1025
Numbers of Falling Endpoints | 1
Numbers of Setup Violated Endpoints | 70
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
osc_inst/osc_inst/OSCOUT.default_clk | Base | 40.000 | 25.000 | 0.000 | 20.000 |  |  |
GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Generated | 5.556 | 180.000 | 0.000 | 2.778 |  | osc_inst/osc_inst/OSCOUT.default_clk |
GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Generated | 5.556 | 180.000 | 0.000 | 2.778 |  | osc_inst/osc_inst/OSCOUT.default_clk |
GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Generated | 11.111 | 90.000 | 0.000 | 5.556 |  | osc_inst/osc_inst/OSCOUT.default_clk |
GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 |  | osc_inst/osc_inst/OSCOUT.default_clk |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | 110.636(MHz) | TOP

#### No timing paths to get frequency of osc_inst/osc_inst/OSCOUT.default_clk!

#### No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
osc_inst/osc_inst/OSCOUT.default_clk | Setup | 0.000 | 0
osc_inst/osc_inst/OSCOUT.default_clk | Hold | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Setup | -95.557 | 70
GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -3.483 | Din_Z[7]/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 5.556 | 0.000 | 8.804
2 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
3 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
4 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
5 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
6 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
7 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
8 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
9 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
10 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
11 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
12 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
13 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
14 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
15 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
16 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
17 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
18 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
19 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
20 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
21 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
22 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
23 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
24 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
25 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.347 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD5 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.465
2 | 0.347 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD4 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.465
3 | 0.427 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.438
4 | 0.428 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.439
5 | 0.474 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD3 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.592
6 | 0.554 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.565
7 | 0.557 | Din_Z[0]/Q | Din_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568
8 | 0.557 | Din_Z[2]/Q | Din_Z[2]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568
9 | 0.557 | Din_Z[6]/Q | Din_Z[6]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568
10 | 0.639 | Din_Z[3]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI3 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.888
11 | 0.674 | Din_Z[1]/Q | Din_Z[1]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.685
12 | 0.674 | Din_Z[3]/Q | Din_Z[3]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.685
13 | 0.674 | Din_Z[7]/Q | Din_Z[7]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.685
14 | 0.679 | Din_Z[4]/Q | Din_Z[4]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.690
15 | 0.679 | Din_Z[5]/Q | Din_Z[5]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.690
16 | 0.708 | Din_Z[4]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI4 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.957
17 | 0.857 | Din_Z[2]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI2 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.106
18 | 0.859 | Din_Z[7]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI7 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.108
19 | 0.862 | Din_Z[1]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI1 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.111
20 | 0.892 | Din_Z[5]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI5 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.141
21 | 0.893 | Din_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI0 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.142
22 | 1.015 | Din_Z[6]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI6 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.264
23 | 0.486 | u_la0_top/capture_window_sel_Z[0]/Q | u_la0_top/capture_window_sel_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.497
24 | 0.486 | u_la0_top/triger_level_cnt_Z[1]/Q | u_la0_top/triger_level_cnt_Z[1]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.497
25 | 0.540 | u_la0_top/capture_window_sel_Z[2]/Q | u_la0_top/capture_window_sel_Z[2]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.551

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
2 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
3 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
4 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
5 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
6 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
7 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
8 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
9 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
10 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
11 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
12 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
13 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
14 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
15 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
16 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
17 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
18 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
19 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
20 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
21 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
22 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
23 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
24 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818
25 | -0.699 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.818

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
2 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
3 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
4 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
5 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
6 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
7 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
8 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
9 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
10 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
11 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
12 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
13 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
14 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
15 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
16 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
17 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
18 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
19 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
20 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
21 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
22 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
23 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
24 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821
25 | 4.794 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.821

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[7]
2 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[5]
3 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[1]
4 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/rst_ao_syn_Z
5 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/genblk1.u_ao_match_0/match_sep
6 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/data_reg_Z[9]
7 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/data_reg_Z[10]
8 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/trigger_seq_start_Z
9 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/data_reg_Z[11]
10 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -3.483
Data Arrival Time | 11.736
Data Required Time | 8.253
From | Din_Z[7]
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.933 | 1.201 | tNET | RR | 1 | R44C39[1][A] | Din_Z[7]/CLK
3.165 | 0.232 | tC2Q | RF | 7 | R44C39[1][A] | Din_Z[7]/Q
6.424 | 3.259 | tNET | FF | 1 | R6C5[3][B] | u_la0_top/genblk1.u_ao_match_0/MATCH_BITWISE[7].match_bitwise_pre_102_0_x3/I1
6.994 | 0.570 | tINS | FR | 2 | R6C5[3][B] | u_la0_top/genblk1.u_ao_match_0/MATCH_BITWISE[7].match_bitwise_pre_102_0_x3/F
6.997 | 0.003 | tNET | RR | 1 | R6C5[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_1_cZ/I0
7.514 | 0.517 | tINS | RF | 1 | R6C5[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_1_cZ/F
8.003 | 0.490 | tNET | FF | 1 | R8C7[1][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_4_cZ/I3
8.374 | 0.371 | tINS | FF | 1 | R8C7[1][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_4_cZ/F
8.788 | 0.413 | tNET | FF | 1 | R7C6[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_2_RNIRTTH/I2
9.241 | 0.453 | tINS | FF | 2 | R7C6[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_2_RNIRTTH/F
9.902 | 0.662 | tNET | FF | 1 | R4C7[3][B] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_2/I0
10.419 | 0.517 | tINS | FF | 1 | R4C7[3][B] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_2/F
11.075 | 0.656 | tNET | FF | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_0/I0
11.624 | 0.549 | tINS | FR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_0/F
11.624 | 0.000 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO/I0
11.729 | 0.105 | tINS | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO/O
11.736 | 0.007 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
8.253 | -0.035 | tSu |  | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 5.556
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.082, 35.008%; route: 5.490, 62.357%; tC2Q: 0.232, 2.635%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
8.253 | -0.035 | tSu |  | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
8.253 | -0.035 | tSu |  | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
8.253 | -0.035 | tSu |  | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[0]
8.253 | -0.035 | tSu |  | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[0]
8.253 | -0.035 | tSu |  | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
8.253 | -0.035 | tSu |  | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R12C8[2][A] | u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R12C8[2][A] | u_la0_top/internal_reg_start_syn_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_syn_Z[0]
8.253 | -0.035 | tSu |  | 1 | R12C8[2][A] | u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[1]
8.253 | -0.035 | tSu |  | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
8.253 | -0.035 | tSu |  | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
8.253 | -0.035 | tSu |  | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
8.253 | -0.035 | tSu |  | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
8.253 | -0.035 | tSu |  | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[0]
8.253 | -0.035 | tSu |  | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path15

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/trigger_seq_start_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/trigger_seq_start_Z
8.253 | -0.035 | tSu |  | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path16

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
8.253 | -0.035 | tSu |  | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
8.253 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel[3]
8.253 | -0.035 | tSu |  | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
8.253 | -0.035 | tSu |  | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
8.253 | -0.035 | tSu |  | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_Z[1]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[1]
8.253 | -0.035 | tSu |  | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
8.253 | -0.035 | tSu |  | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
8.253 | -0.035 | tSu |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
8.253 | -0.035 | tSu |  | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[3]
8.253 | -0.035 | tSu |  | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.347
Data Arrival Time | 3.099
Data Required Time | 2.752
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q
3.099 | 0.263 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.752 | 0.118 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 0.347
Data Arrival Time | 3.099
Data Required Time | 2.752
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/Q
3.099 | 0.263 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.752 | 0.118 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 0.427
Data Arrival Time | 3.071
Data Required Time | 2.645
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q
2.839 | 0.004 | tNET | RR | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[2]/I2
3.071 | 0.232 | tINS | RF | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[2]/F
3.071 | 0.000 | tNET | FF | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]
2.645 | 0.011 | tHld |  | 1 | R39C39[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 0.428
Data Arrival Time | 3.073
Data Required Time | 2.645
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q
2.841 | 0.005 | tNET | RR | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[0]/I0
3.073 | 0.232 | tINS | RF | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[0]/F
3.073 | 0.000 | tNET | FF | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]
2.645 | 0.011 | tHld |  | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 0.474
Data Arrival Time | 3.226
Data Required Time | 2.752
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q
3.226 | 0.390 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/AD3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.752 | 0.118 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.880%; tC2Q: 0.202, 34.120%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 0.554
Data Arrival Time | 3.199
Data Required Time | 2.645
From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK
2.835 | 0.201 | tC2Q | RF | 4 | R39C39[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q
2.967 | 0.132 | tNET | FF | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[1]/I0
3.199 | 0.232 | tINS | FF | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_3_cZ[1]/F
3.199 | 0.000 | tNET | FF | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]
2.645 | 0.011 | tHld |  | 1 | R39C39[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.232, 41.082%; route: 0.132, 23.326%; tC2Q: 0.201, 35.592%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 0.557
Data Arrival Time | 3.202
Data Required Time | 2.645
From | Din_Z[0]
To | Din_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[0][B] | Din_Z[0]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[0][B] | Din_Z[0]/Q
2.838 | 0.002 | tNET | RR | 2 | R44C38[0][B] | Din_cry_0[0]/I0
3.202 | 0.364 | tINS | RF | 1 | R44C38[0][B] | Din_cry_0[0]/SUM
3.202 | 0.000 | tNET | FF | 1 | R44C38[0][B] | Din_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[0][B] | Din_Z[0]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[0]
2.645 | 0.011 | tHld |  | 1 | R44C38[0][B] | Din_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 0.557
Data Arrival Time | 3.202
Data Required Time | 2.645
From | Din_Z[2]
To | Din_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][B] | Din_Z[2]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[1][B] | Din_Z[2]/Q
2.838 | 0.002 | tNET | RR | 2 | R44C38[1][B] | Din_cry_0[2]/I0
3.202 | 0.364 | tINS | RF | 1 | R44C38[1][B] | Din_cry_0[2]/SUM
3.202 | 0.000 | tNET | FF | 1 | R44C38[1][B] | Din_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][B] | Din_Z[2]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[2]
2.645 | 0.011 | tHld |  | 1 | R44C38[1][B] | Din_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 0.557
Data Arrival Time | 3.202
Data Required Time | 2.645
From | Din_Z[6]
To | Din_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][B] | Din_Z[6]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C39[0][B] | Din_Z[6]/Q
2.838 | 0.002 | tNET | RR | 2 | R44C39[0][B] | Din_cry_0[6]/I0
3.202 | 0.364 | tINS | RF | 1 | R44C39[0][B] | Din_cry_0[6]/SUM
3.202 | 0.000 | tNET | FF | 1 | R44C39[0][B] | Din_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][B] | Din_Z[6]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[6]
2.645 | 0.011 | tHld |  | 1 | R44C39[0][B] | Din_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 0.639
Data Arrival Time | 3.522
Data Required Time | 2.883
From | Din_Z[3]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][A] | Din_Z[3]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[2][A] | Din_Z[3]/Q
3.109 | 0.274 | tNET | RR | 1 | R37C38[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[3]_cZ/I0
3.399 | 0.290 | tINS | RF | 1 | R37C38[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[3]_cZ/F
3.522 | 0.122 | tNET | FF | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.290, 32.664%; route: 0.396, 44.584%; tC2Q: 0.202, 22.752%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 0.674
Data Arrival Time | 3.319
Data Required Time | 2.645
From | Din_Z[1]
To | Din_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][A] | Din_Z[1]/CLK
2.835 | 0.201 | tC2Q | RF | 8 | R44C38[1][A] | Din_Z[1]/Q
2.955 | 0.120 | tNET | FF | 2 | R44C38[1][A] | Din_cry_0[1]/I0
3.319 | 0.364 | tINS | FF | 1 | R44C38[1][A] | Din_cry_0[1]/SUM
3.319 | 0.000 | tNET | FF | 1 | R44C38[1][A] | Din_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][A] | Din_Z[1]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[1]
2.645 | 0.011 | tHld |  | 1 | R44C38[1][A] | Din_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 0.674
Data Arrival Time | 3.319
Data Required Time | 2.645
From | Din_Z[3]
To | Din_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][A] | Din_Z[3]/CLK
2.835 | 0.201 | tC2Q | RF | 8 | R44C38[2][A] | Din_Z[3]/Q
2.955 | 0.120 | tNET | FF | 2 | R44C38[2][A] | Din_cry_0[3]/I0
3.319 | 0.364 | tINS | FF | 1 | R44C38[2][A] | Din_cry_0[3]/SUM
3.319 | 0.000 | tNET | FF | 1 | R44C38[2][A] | Din_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][A] | Din_Z[3]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[3]
2.645 | 0.011 | tHld |  | 1 | R44C38[2][A] | Din_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 0.674
Data Arrival Time | 3.319
Data Required Time | 2.645
From | Din_Z[7]
To | Din_Z[7]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[1][A] | Din_Z[7]/CLK
2.835 | 0.201 | tC2Q | RF | 7 | R44C39[1][A] | Din_Z[7]/Q
2.955 | 0.120 | tNET | FF | 2 | R44C39[1][A] | Din_s_0[7]/I0
3.319 | 0.364 | tINS | FF | 1 | R44C39[1][A] | Din_s_0[7]/SUM
3.319 | 0.000 | tNET | FF | 1 | R44C39[1][A] | Din_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[1][A] | Din_Z[7]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[7]
2.645 | 0.011 | tHld |  | 1 | R44C39[1][A] | Din_Z[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 53.119%; route: 0.120, 17.549%; tC2Q: 0.201, 29.332%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 0.679
Data Arrival Time | 3.324
Data Required Time | 2.645
From | Din_Z[4]
To | Din_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][B] | Din_Z[4]/CLK
2.835 | 0.201 | tC2Q | RF | 7 | R44C38[2][B] | Din_Z[4]/Q
2.960 | 0.125 | tNET | FF | 2 | R44C38[2][B] | Din_cry_0[4]/I0
3.324 | 0.364 | tINS | FF | 1 | R44C38[2][B] | Din_cry_0[4]/SUM
3.324 | 0.000 | tNET | FF | 1 | R44C38[2][B] | Din_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][B] | Din_Z[4]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[4]
2.645 | 0.011 | tHld |  | 1 | R44C38[2][B] | Din_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 52.740%; route: 0.125, 18.137%; tC2Q: 0.201, 29.123%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 0.679
Data Arrival Time | 3.324
Data Required Time | 2.645
From | Din_Z[5]
To | Din_Z[5]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][A] | Din_Z[5]/CLK
2.835 | 0.201 | tC2Q | RF | 8 | R44C39[0][A] | Din_Z[5]/Q
2.960 | 0.125 | tNET | FF | 2 | R44C39[0][A] | Din_cry_0[5]/I0
3.324 | 0.364 | tINS | FF | 1 | R44C39[0][A] | Din_cry_0[5]/SUM
3.324 | 0.000 | tNET | FF | 1 | R44C39[0][A] | Din_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][A] | Din_Z[5]/CLK
2.634 | 0.000 | tUnc |  |  |  | Din_Z[5]
2.645 | 0.011 | tHld |  | 1 | R44C39[0][A] | Din_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 52.740%; route: 0.125, 18.137%; tC2Q: 0.201, 29.123%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 0.708
Data Arrival Time | 3.591
Data Required Time | 2.883
From | Din_Z[4]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[2][B] | Din_Z[4]/CLK
2.836 | 0.202 | tC2Q | RR | 7 | R44C38[2][B] | Din_Z[4]/Q
3.125 | 0.289 | tNET | RR | 1 | R37C38[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[4]_cZ/I0
3.469 | 0.344 | tINS | RF | 1 | R37C38[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[4]_cZ/F
3.591 | 0.122 | tNET | FF | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.344, 35.946%; route: 0.411, 42.946%; tC2Q: 0.202, 21.108%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 0.857
Data Arrival Time | 3.740
Data Required Time | 2.883
From | Din_Z[2]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][B] | Din_Z[2]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[1][B] | Din_Z[2]/Q
3.125 | 0.289 | tNET | RR | 1 | R37C38[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[2]_cZ/I0
3.469 | 0.344 | tINS | RF | 1 | R37C38[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[2]_cZ/F
3.740 | 0.271 | tNET | FF | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.344, 31.105%; route: 0.560, 50.631%; tC2Q: 0.202, 18.265%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 0.859
Data Arrival Time | 3.742
Data Required Time | 2.883
From | Din_Z[7]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[1][A] | Din_Z[7]/CLK
2.836 | 0.202 | tC2Q | RR | 7 | R44C39[1][A] | Din_Z[7]/Q
3.097 | 0.262 | tNET | RR | 1 | R41C39[3][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[7]_cZ/I0
3.332 | 0.235 | tINS | RR | 1 | R41C39[3][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[7]_cZ/F
3.742 | 0.410 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI7

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.235, 21.204%; route: 0.671, 60.570%; tC2Q: 0.202, 18.226%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 0.862
Data Arrival Time | 3.745
Data Required Time | 2.883
From | Din_Z[1]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[1][A] | Din_Z[1]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[1][A] | Din_Z[1]/Q
3.109 | 0.274 | tNET | RR | 1 | R37C38[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[1]_cZ/I0
3.473 | 0.364 | tINS | RF | 1 | R37C38[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[1]_cZ/F
3.745 | 0.271 | tNET | FF | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.364, 32.770%; route: 0.545, 49.045%; tC2Q: 0.202, 18.185%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 0.892
Data Arrival Time | 3.775
Data Required Time | 2.883
From | Din_Z[5]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][A] | Din_Z[5]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C39[0][A] | Din_Z[5]/Q
3.082 | 0.246 | tNET | RR | 1 | R40C39[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[5]_cZ/I0
3.392 | 0.310 | tINS | RR | 1 | R40C39[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[5]_cZ/F
3.775 | 0.382 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.310, 27.172%; route: 0.629, 55.122%; tC2Q: 0.202, 17.706%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 0.893
Data Arrival Time | 3.776
Data Required Time | 2.883
From | Din_Z[0]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C38[0][B] | Din_Z[0]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C38[0][B] | Din_Z[0]/Q
3.262 | 0.426 | tNET | RR | 1 | R37C38[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[0]_cZ/I0
3.653 | 0.391 | tINS | RR | 1 | R37C38[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[0]_cZ/F
3.776 | 0.123 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.391, 34.229%; route: 0.549, 48.087%; tC2Q: 0.202, 17.684%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 1.015
Data Arrival Time | 3.898
Data Required Time | 2.883
From | Din_Z[6]
To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R44C39[0][B] | Din_Z[6]/CLK
2.836 | 0.202 | tC2Q | RR | 8 | R44C39[0][B] | Din_Z[6]/Q
3.097 | 0.262 | tNET | RR | 1 | R41C39[3][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[6]_cZ/I0
3.488 | 0.391 | tINS | RR | 1 | R41C39[3][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/un1_Din_cZ[6]_cZ/F
3.898 | 0.410 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/DI6

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLK
2.634 | 0.000 | tUnc |  |  |  | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0
2.883 | 0.249 | tHld |  | 1 | BSRAM_R36[11] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.391, 30.926%; route: 0.671, 53.097%; tC2Q: 0.202, 15.977%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 0.486
Data Arrival Time | 3.131
Data Required Time | 2.645
From | u_la0_top/capture_window_sel_Z[0]
To | u_la0_top/capture_window_sel_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/CLK
2.836 | 0.202 | tC2Q | RR | 7 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/Q
2.841 | 0.005 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_3_cZ[0]/I2
3.131 | 0.290 | tINS | RF | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_3_cZ[0]/F
3.131 | 0.000 | tNET | FF | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[0]
2.645 | 0.011 | tHld |  | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.290, 58.363%; route: 0.005, 0.984%; tC2Q: 0.202, 40.653%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 0.486
Data Arrival Time | 3.131
Data Required Time | 2.645
From | u_la0_top/triger_level_cnt_Z[1]
To | u_la0_top/triger_level_cnt_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
2.836 | 0.202 | tC2Q | RR | 4 | R6C4[2][A] | u_la0_top/triger_level_cnt_Z[1]/Q
2.841 | 0.005 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_4_cZ[1]/I2
3.131 | 0.290 | tINS | RF | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_4_cZ[1]/F
3.131 | 0.000 | tNET | FF | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[1]
2.645 | 0.011 | tHld |  | 1 | R6C4[2][A] | u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.290, 58.363%; route: 0.005, 0.984%; tC2Q: 0.202, 40.653%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 0.540
Data Arrival Time | 3.185
Data Required Time | 2.645
From | u_la0_top/capture_window_sel_Z[2]
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLK
2.836 | 0.202 | tC2Q | RR | 5 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/Q
2.841 | 0.005 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_3_cZ[2]/I0
3.185 | 0.344 | tINS | RF | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_3_cZ[2]/F
3.185 | 0.000 | tNET | FF | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLK
2.634 | 0.000 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
2.645 | 0.011 | tHld |  | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.344, 62.445%; route: 0.005, 0.887%; tC2Q: 0.202, 36.668%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
8.253 | -0.035 | tSu |  | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
8.253 | -0.035 | tSu |  | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
8.253 | -0.035 | tSu |  | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
8.253 | -0.035 | tSu |  | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
8.253 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
8.253 | -0.035 | tSu |  | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/trigger_seq_start_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/trigger_seq_start_Z
8.253 | -0.035 | tSu |  | 1 | R7C11[1][A] | u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
8.253 | -0.035 | tSu |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
8.253 | -0.035 | tSu |  | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
8.253 | -0.035 | tSu |  | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
8.253 | -0.035 | tSu |  | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
8.253 | -0.035 | tSu |  | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
8.253 | -0.035 | tSu |  | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel[3]
8.253 | -0.035 | tSu |  | 1 | R2C4[1][A] | u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path15

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[0]
8.253 | -0.035 | tSu |  | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path16

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[1]
8.253 | -0.035 | tSu |  | 1 | R4C2[1][A] | u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
8.253 | -0.035 | tSu |  | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
8.253 | -0.035 | tSu |  | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
8.253 | -0.035 | tSu |  | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
8.253 | -0.035 | tSu |  | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
8.253 | -0.035 | tSu |  | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[0]
8.253 | -0.035 | tSu |  | 1 | R8C11[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
8.253 | -0.035 | tSu |  | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
8.253 | -0.035 | tSu |  | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | -0.699
Data Arrival Time | 8.952
Data Required Time | 8.253
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.365 | 0.232 | tC2Q | FF | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
8.952 | 2.586 | tNET | FF | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.556 | 5.556 |  |  |  |  | active clock edge time
5.556 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
8.488 | 1.201 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
8.288 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
8.253 | -0.035 | tSu |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.423
Setup Relationship | 2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
2.845 | 0.011 | tHld |  | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
2.845 | 0.011 | tHld |  | 1 | R5C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
2.845 | 0.011 | tHld |  | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
2.845 | 0.011 | tHld |  | 1 | R4C2[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
2.845 | 0.011 | tHld |  | 1 | R4C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
2.845 | 0.011 | tHld |  | 1 | R7C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
2.845 | 0.011 | tHld |  | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
2.845 | 0.011 | tHld |  | 1 | R6C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
2.845 | 0.011 | tHld |  | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
2.845 | 0.011 | tHld |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
2.845 | 0.011 | tHld |  | 1 | R9C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
2.845 | 0.011 | tHld |  | 1 | R11C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
2.845 | 0.011 | tHld |  | 1 | R9C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
2.845 | 0.011 | tHld |  | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
2.845 | 0.011 | tHld |  | 1 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
2.845 | 0.011 | tHld |  | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
2.845 | 0.011 | tHld |  | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
2.845 | 0.011 | tHld |  | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
2.845 | 0.011 | tHld |  | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
2.845 | 0.011 | tHld |  | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
2.845 | 0.011 | tHld |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R3C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R3C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
2.845 | 0.011 | tHld |  | 1 | R3C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
2.845 | 0.011 | tHld |  | 1 | R5C11[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
2.845 | 0.011 | tHld |  | 1 | R3C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 4.794
Data Arrival Time | 7.638
Data Required Time | 2.845
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.778 | 2.778 |  |  |  |  | active clock edge time
2.778 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
5.818 | 0.913 | tNET | FF | 1 | R8C11[1][A] | u_la0_top/rst_ao_Z/CLK
6.020 | 0.202 | tC2Q | FR | 43 | R8C11[1][A] | u_la0_top/rst_ao_Z/Q
7.638 | 1.619 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
1.732 | 1.732 | tCL | RR | 71 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT
2.634 | 0.902 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]/CLK
2.834 | 0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
2.845 | 0.011 | tHld |  | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.406
Hold Relationship | -2.778
Logic Level | 0
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | Din_Z[7]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | Din_Z[7]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | Din_Z[7]/CLK

### MPW2

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | Din_Z[5]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | Din_Z[5]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | Din_Z[5]/CLK

### MPW3

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | Din_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | Din_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | Din_Z[1]/CLK

### MPW4

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/rst_ao_syn_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/rst_ao_syn_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/rst_ao_syn_Z/CLK

### MPW5

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/genblk1.u_ao_match_0/match_sep

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK

### MPW6

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[9]/CLK

### MPW7

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[10]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[10]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[10]/CLK

### MPW8

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/trigger_seq_start_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/trigger_seq_start_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/trigger_seq_start_Z/CLK

### MPW9

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[11]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[11]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[11]/CLK

### MPW10

MPW Summary:

Slack: | 1.056
Actual Width: | 2.056
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk
Objects: | u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
2.778 | 0.000 |  |  | active clock edge time
2.778 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT
6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.556 | 0.000 |  |  | active clock edge time
5.556 | 0.000 |  |  | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow)
7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT
8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
12 | clk | 3.435 | 1.228
4 | wbin[0] | 4.339 | 0.572
4 | wbin[1] | 4.372 | 0.419
4 | wbin[2] | 4.351 | 0.419
2 | Din[2] | 3.715 | 0.443
2 | Din[4] | 3.805 | 0.443
2 | Din[5] | 3.488 | 0.492
2 | Din[3] | 3.787 | 0.520
2 | Din[0] | 3.677 | 0.610
2 | Din[1] | 3.601 | 0.520

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R36C38 | 0.208
R44C38 | 0.153
R10C3 | 0.125
R39C39 | 0.111
R37C38 | 0.111
R44C39 | 0.097
R36C39 | 0.083
R40C39 | 0.056
R4C1 | 0.042
R41C39 | 0.042

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---