module RAM_based_shift_reg_top(
	clk,
	Reset,
	Din,
	ADDR,
	Q
);
input clk;
input Reset;
input [7:0] Din;
input [8:0] ADDR;
output [7:0] Q;
wire [8:0] ADDR;
wire [7:0] Din;
wire GND;
wire [7:0] Q;
wire Reset;
wire VCC;
wire clk;
wire [7:0] \u_RAM_based_shift_reg/un1_Din ;
wire [8:0] \u_RAM_based_shift_reg/wbin ;
wire [7:0] \u_RAM_based_shift_reg/wbin_cry ;
wire [8:0] \u_RAM_based_shift_reg/wbin_s ;
wire [8:0] \u_RAM_based_shift_reg/wbin_lm ;
wire [8:8] \u_RAM_based_shift_reg/wbin_s_0_COUT ;
wire [31:8] \u_RAM_based_shift_reg/mem_mem_0_0_DO ;
wire \u_RAM_based_shift_reg/un1_wbin_0 ;
wire \u_RAM_based_shift_reg/un1_wbin_2 ;
wire \u_RAM_based_shift_reg/un1_wbin_3 ;
wire \u_RAM_based_shift_reg/un1_wbin_4 ;
wire \u_RAM_based_shift_reg/un1_wbin_5 ;
wire \u_RAM_based_shift_reg/un1_wbin_6 ;
wire \u_RAM_based_shift_reg/un1_wbin_7 ;
wire \u_RAM_based_shift_reg/un1_wbin_8 ;
wire \u_RAM_based_shift_reg/un1_wbin_9 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_9 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_0 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_1 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_2 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_3 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_4 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_5 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_6 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_7 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_8 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_0 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_1 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_2 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_3 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_4 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_5 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_6 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_7 ;
wire \u_RAM_based_shift_reg/un1_ADDR_cry_8 ;
wire \u_RAM_based_shift_reg/wbin15_5 ;
wire \u_RAM_based_shift_reg/wbin15_6 ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_0_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_1_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_2_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_3_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_4_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_5_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_6_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_7_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_8_0_SUM ;
wire \u_RAM_based_shift_reg/un1_wbin_cry_9_0_SUM ;
wire \u_RAM_based_shift_reg/wbin15_6_0 ;
wire \u_RAM_based_shift_reg/wbin15_6_1 ;
VCC VCC_cZ (
  .V(VCC)
);
GND GND_cZ (
  .G(GND)
);
GSR GSR_INST (
	.GSRI(VCC)
);
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[0]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [0]),
	.F(\u_RAM_based_shift_reg/wbin_lm [0])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[0] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[1]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [1]),
	.F(\u_RAM_based_shift_reg/wbin_lm [1])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[1] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[2]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [2]),
	.F(\u_RAM_based_shift_reg/wbin_lm [2])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[2] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[3]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [3]),
	.F(\u_RAM_based_shift_reg/wbin_lm [3])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[3] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[4]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [4]),
	.F(\u_RAM_based_shift_reg/wbin_lm [4])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[4] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[5]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [5]),
	.F(\u_RAM_based_shift_reg/wbin_lm [5])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[5] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[6]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [6]),
	.F(\u_RAM_based_shift_reg/wbin_lm [6])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[6] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[7]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [7]),
	.F(\u_RAM_based_shift_reg/wbin_lm [7])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[7] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin_lm_0[8]  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.I1(\u_RAM_based_shift_reg/wbin15_5 ),
	.I2(\u_RAM_based_shift_reg/wbin15_6 ),
	.I3(\u_RAM_based_shift_reg/wbin_s [8]),
	.F(\u_RAM_based_shift_reg/wbin_lm [8])
);
defparam \u_RAM_based_shift_reg/wbin_lm_0[8] .INIT=16'h2A00;
LUT4 \u_RAM_based_shift_reg/wbin15_5_cZ  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(\u_RAM_based_shift_reg/wbin [1]),
	.I2(\u_RAM_based_shift_reg/wbin [2]),
	.I3(\u_RAM_based_shift_reg/wbin [3]),
	.F(\u_RAM_based_shift_reg/wbin15_5 )
);
defparam \u_RAM_based_shift_reg/wbin15_5_cZ .INIT=16'h8000;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[0]  (
	.I0(Din[0]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [0])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[0] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[1]  (
	.I0(Din[1]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [1])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[1] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[2]  (
	.I0(Din[2]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [2])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[2] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[3]  (
	.I0(Din[3]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [3])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[3] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[4]  (
	.I0(Din[4]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [4])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[4] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[5]  (
	.I0(Din[5]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [5])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[5] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[6]  (
	.I0(Din[6]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [6])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[6] .INIT=4'h2;
LUT2 \u_RAM_based_shift_reg/un1_Din_cZ[7]  (
	.I0(Din[7]),
	.I1(Reset),
	.F(\u_RAM_based_shift_reg/un1_Din [7])
);
defparam \u_RAM_based_shift_reg/un1_Din_cZ[7] .INIT=4'h2;
LUT4 \u_RAM_based_shift_reg/wbin15_6_RNO  (
	.I0(\u_RAM_based_shift_reg/wbin [5]),
	.I1(\u_RAM_based_shift_reg/wbin [6]),
	.I2(\u_RAM_based_shift_reg/wbin [7]),
	.I3(\u_RAM_based_shift_reg/wbin [8]),
	.F(\u_RAM_based_shift_reg/wbin15_6_0 )
);
defparam \u_RAM_based_shift_reg/wbin15_6_RNO .INIT=16'h0000;
LUT4 \u_RAM_based_shift_reg/wbin15_6_RNO_0  (
	.I0(\u_RAM_based_shift_reg/wbin [5]),
	.I1(\u_RAM_based_shift_reg/wbin [6]),
	.I2(\u_RAM_based_shift_reg/wbin [7]),
	.I3(\u_RAM_based_shift_reg/wbin [8]),
	.F(\u_RAM_based_shift_reg/wbin15_6_1 )
);
defparam \u_RAM_based_shift_reg/wbin15_6_RNO_0 .INIT=16'h8000;
MUX2_LUT5 \u_RAM_based_shift_reg/wbin15_6_cZ  (
	.I0(\u_RAM_based_shift_reg/wbin15_6_0 ),
	.I1(\u_RAM_based_shift_reg/wbin15_6_1 ),
	.S0(\u_RAM_based_shift_reg/wbin [4]),
	.O(\u_RAM_based_shift_reg/wbin15_6 )
);
DFFC \u_RAM_based_shift_reg/wbin_Z[8]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [8]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [8])
);
defparam \u_RAM_based_shift_reg/wbin_Z[8] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[7]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [7]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [7])
);
defparam \u_RAM_based_shift_reg/wbin_Z[7] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[6]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [6]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [6])
);
defparam \u_RAM_based_shift_reg/wbin_Z[6] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[5]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [5]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [5])
);
defparam \u_RAM_based_shift_reg/wbin_Z[5] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[4]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [4]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [4])
);
defparam \u_RAM_based_shift_reg/wbin_Z[4] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[3]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [3]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [3])
);
defparam \u_RAM_based_shift_reg/wbin_Z[3] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[2]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [2]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [2])
);
defparam \u_RAM_based_shift_reg/wbin_Z[2] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[1]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [1]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [1])
);
defparam \u_RAM_based_shift_reg/wbin_Z[1] .INIT=1'b0;
DFFC \u_RAM_based_shift_reg/wbin_Z[0]  (
	.D(\u_RAM_based_shift_reg/wbin_lm [0]),
	.CLK(clk),
	.CLEAR(Reset),
	.Q(\u_RAM_based_shift_reg/wbin [0])
);
defparam \u_RAM_based_shift_reg/wbin_Z[0] .INIT=1'b0;
SP \u_RAM_based_shift_reg/mem_mem_0_0  (
	.CLK(clk),
	.OCE(GND),
	.CE(VCC),
	.RESET(Reset),
	.WRE(VCC),
	.BLKSEL({GND, GND, GND}),
	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \u_RAM_based_shift_reg/un1_Din [7:0]}),
	.AD({GND, GND, \u_RAM_based_shift_reg/wbin [8:0], GND, GND, GND}),
	.DO({\u_RAM_based_shift_reg/mem_mem_0_0_DO [31:8], Q[7:0]})
);
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .READ_MODE=1'b0;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .WRITE_MODE=2'b10;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BLK_SEL=3'b000;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .BIT_WIDTH=8;
defparam \u_RAM_based_shift_reg/mem_mem_0_0 .RESET_MODE="ASYNC";
ALU \u_RAM_based_shift_reg/un1_wbin_cry_9_0  (
	.I0(VCC),
	.I1(\u_RAM_based_shift_reg/un1_ADDR_cry_8 ),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_8 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_9 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_9_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_9_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_8_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_9 ),
	.I1(\u_RAM_based_shift_reg/wbin [8]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_7 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_8 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_8_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_8_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_7_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_8 ),
	.I1(\u_RAM_based_shift_reg/wbin [7]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_6 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_7 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_7_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_7_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_6_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_7 ),
	.I1(\u_RAM_based_shift_reg/wbin [6]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_5 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_6 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_6_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_6_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_5_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_6 ),
	.I1(\u_RAM_based_shift_reg/wbin [5]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_4 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_5 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_5_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_5_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_4_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_5 ),
	.I1(\u_RAM_based_shift_reg/wbin [4]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_3 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_4 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_4_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_4_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_3_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_4 ),
	.I1(\u_RAM_based_shift_reg/wbin [3]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_2 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_3 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_3_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_3_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_2_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_3 ),
	.I1(\u_RAM_based_shift_reg/wbin [2]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_1 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_2 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_2_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_2_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_1_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_2 ),
	.I1(\u_RAM_based_shift_reg/wbin [1]),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_wbin_cry_0 ),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_1 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_1_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_1_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_wbin_cry_0_0  (
	.I0(\u_RAM_based_shift_reg/un1_wbin_0 ),
	.I1(\u_RAM_based_shift_reg/wbin [0]),
	.I3(GND),
	.CIN(GND),
	.COUT(\u_RAM_based_shift_reg/un1_wbin_cry_0 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_cry_0_0_SUM )
);
defparam \u_RAM_based_shift_reg/un1_wbin_cry_0_0 .ALU_MODE=1;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_8_0  (
	.I0(ADDR[8]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_7 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_8 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_9 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_8_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_7_0  (
	.I0(ADDR[7]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_6 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_7 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_8 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_7_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_6_0  (
	.I0(ADDR[6]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_5 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_6 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_7 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_6_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_5_0  (
	.I0(ADDR[5]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_4 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_5 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_6 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_5_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_4_0  (
	.I0(ADDR[4]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_3 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_4 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_5 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_4_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_3_0  (
	.I0(ADDR[3]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_2 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_3 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_4 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_3_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_2_0  (
	.I0(ADDR[2]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_1 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_2 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_3 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_2_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_1_0  (
	.I0(ADDR[1]),
	.I1(VCC),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/un1_ADDR_cry_0 ),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_1 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_2 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_1_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/un1_ADDR_cry_0_0  (
	.I0(ADDR[0]),
	.I1(VCC),
	.I3(GND),
	.CIN(GND),
	.COUT(\u_RAM_based_shift_reg/un1_ADDR_cry_0 ),
	.SUM(\u_RAM_based_shift_reg/un1_wbin_0 )
);
defparam \u_RAM_based_shift_reg/un1_ADDR_cry_0_0 .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_s_0[8]  (
	.I0(\u_RAM_based_shift_reg/wbin [8]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [7]),
	.COUT(\u_RAM_based_shift_reg/wbin_s_0_COUT [8]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [8])
);
defparam \u_RAM_based_shift_reg/wbin_s_0[8] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[7]  (
	.I0(\u_RAM_based_shift_reg/wbin [7]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [6]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [7]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [7])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[7] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[6]  (
	.I0(\u_RAM_based_shift_reg/wbin [6]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [5]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [6]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [6])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[6] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[5]  (
	.I0(\u_RAM_based_shift_reg/wbin [5]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [4]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [5]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [5])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[5] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[4]  (
	.I0(\u_RAM_based_shift_reg/wbin [4]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [3]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [4]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [4])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[4] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[3]  (
	.I0(\u_RAM_based_shift_reg/wbin [3]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [2]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [3]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [3])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[3] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[2]  (
	.I0(\u_RAM_based_shift_reg/wbin [2]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [1]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [2]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [2])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[2] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[1]  (
	.I0(\u_RAM_based_shift_reg/wbin [1]),
	.I1(GND),
	.I3(GND),
	.CIN(\u_RAM_based_shift_reg/wbin_cry [0]),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [1]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [1])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[1] .ALU_MODE=0;
ALU \u_RAM_based_shift_reg/wbin_cry_0[0]  (
	.I0(\u_RAM_based_shift_reg/wbin [0]),
	.I1(GND),
	.I3(GND),
	.CIN(VCC),
	.COUT(\u_RAM_based_shift_reg/wbin_cry [0]),
	.SUM(\u_RAM_based_shift_reg/wbin_s [0])
);
defparam \u_RAM_based_shift_reg/wbin_cry_0[0] .ALU_MODE=0;
endmodule
