#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep  3 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-047

# Fri Sep 14 17:27:19 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\TOP.v" (library work)
@I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\gw_pll\gw_pll.v" (library work)
@I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\gw_osc\gw_osc.v" (library work)
@I::"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v" (library work)
Verilog syntax check successful!
File C:\Gowin\1.8\SynplifyPro\bin64\c_ver.exe changed - recompiling
File C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v changed - recompiling
File C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v changed - recompiling
File C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v changed - recompiling
File C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v changed - recompiling
File C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh changed - recompiling
File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\TOP.v changed - recompiling
Selecting top level module TOP
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1601:7:1601:9|Synthesizing module OSC in library work.
Running optimization stage 1 on OSC .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\gw_osc\gw_osc.v":13:7:13:12|Synthesizing module GW_OSC in library work.
Running optimization stage 1 on GW_OSC .......
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1532:7:1532:9|Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\gw_pll\gw_pll.v":13:7:13:12|Synthesizing module GW_PLL in library work.
Running optimization stage 1 on GW_PLL .......
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on SDP .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v":1084:7:1084:29|Synthesizing module RAM_based_shift_reg_top in library work.
Running optimization stage 1 on RAM_based_shift_reg_top .......
@W: CL168 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v":1120:6:1120:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\src\TOP.v":1:7:1:9|Synthesizing module TOP in library work.
Running optimization stage 1 on TOP .......
Running optimization stage 2 on TOP .......
Running optimization stage 2 on RAM_based_shift_reg_top .......
Running optimization stage 2 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on SDP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on GW_PLL .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on GW_OSC .......
Running optimization stage 2 on OSC .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 14 17:27:19 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N|Running in 64-bit mode
File C:\Gowin\1.8\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 14 17:27:20 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 14 17:27:20 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Database state : D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep  3 2018 10:06:59

@N|Running in 64-bit mode
File C:\Gowin\1.8\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
File D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\lossless_ex_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Sep 14 17:27:21 2018

###########################################################]
Premap Report

# Fri Sep 14 17:27:21 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex_scck.rpt 
Printing clock  summary report in "D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Beginning opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 

Finished opaque latch detection (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)







Detailed report for transparent and observable latches in design:
@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\lossless_ex_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

syn_allowed_resources : blockrams=140  set on top level netlist TOP

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start                            Requested     Requested     Clock        Clock                     Clock
Level     Clock                            Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------
0 -       System                           150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                                   
0 -       GW_PLL|clkout_inferred_clock     298.3 MHz     3.352         inferred     Autoconstr_clkgroup_0     58   
===================================================================================================================



Clock Load Summary
***********************

                                 Clock     Source                               Clock Pin       Non-clock Pin     Non-clock Pin
Clock                            Load      Pin                                  Seq Example     Seq Example       Comb Example 
-------------------------------------------------------------------------------------------------------------------------------
System                           0         -                                    -               -                 -            
                                                                                                                               
GW_PLL|clkout_inferred_clock     58        GW_PLL_inst.pll_inst.CLKOUT(PLL)     Din[7:0].C      -                 -            
===============================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 58 clock pin(s) of sequential element(s)
0 instances converted, 58 sequential instances remain driven by gated/generated clocks

========================================================= Gated/Generated Clocks ==========================================================
Clock Tree ID     Driving Element                 Drive Element Type     Unconverted Fanout     Sample Instance     Explanation            
-------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_0       GW_PLL_inst.pll_inst.CLKOUT     PLL                    58                     ADDR[8:0]           Black box on clock path
===========================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 106MB peak: 192MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Sep 14 17:27:22 2018

###########################################################]
Map & Optimize Report

# Fri Sep 14 17:27:23 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep  4 2018 10:03:38


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

@N: MO231 :"d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\lossless_ex\project\src\top.v":30:0:30:5|Found counter in view:work.TOP(verilog) instance Din[7:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.56ns		  99 /        27
   2		0h:00m:00s		    -2.56ns		  99 /        27

   3		0h:00m:00s		    -2.56ns		  99 /        27

   4		0h:00m:00s		    -2.56ns		  99 /        27

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 191MB)

Writing Analyst data base D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\synwork\lossless_ex_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

@W: MT246 :"d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\lossless_ex\project\src\gw_pll\gw_pll.v":26:4:26:11|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GW_PLL|clkout_inferred_clock with period 6.06ns. Please declare a user-defined clock on net GW_PLL_inst.clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Sep 14 17:27:26 2018
#


Top view:               TOP
Requested Frequency:    165.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.069

                                 Requested      Estimated      Requested     Estimated                Clock        Clock                
Starting Clock                   Frequency      Frequency      Period        Period        Slack      Type         Group                
----------------------------------------------------------------------------------------------------------------------------------------
GW_PLL|clkout_inferred_clock     165.1 MHz      140.4 MHz      6.055         7.124         -1.069     inferred     Autoconstr_clkgroup_0
System                           2199.3 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup      
========================================================================================================================================





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------
System                        System                        |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -    
GW_PLL|clkout_inferred_clock  GW_PLL|clkout_inferred_clock  |  6.055       -1.069  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GW_PLL|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                  Starting                                                          Arrival           
Instance                                                          Reference                        Type     Pin     Net             Time        Slack 
                                                                  Clock                                                                               
------------------------------------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[1]     0.243       -1.069
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[0]     0.243       -1.048
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[5]     0.243       -1.048
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[4]     0.243       -1.027
ADDR[8]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[8]         0.243       -1.005
ADDR[7]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[7]         0.243       -0.994
ADDR[3]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[3]         0.243       -0.984
ADDR[4]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[4]         0.243       -0.973
ADDR[6]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[6]         0.243       -0.973
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[2]     0.243       -0.961
======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                  Starting                                                                Required           
Instance                                                          Reference                        Type     Pin     Net                   Time         Slack 
                                                                  Clock                                                                                      
-------------------------------------------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_s_7_0_SUM         5.994        -1.069
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[8\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_6_0_0_SUM     5.994        -1.034
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[7\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_5_0_0_SUM     5.994        -0.999
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[6\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_4_0_0_SUM     5.994        -0.964
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_3_0_0_SUM     5.994        -0.929
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_2_0_0_SUM     5.994        -0.894
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_1_0_0_SUM     5.994        -0.859
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_0_0_SUM       5.994        -0.637
ADDR[8]                                                           GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[8]             5.994        1.207 
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc0_cZ         5.994        1.230 
=============================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.055
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.994

    - Propagation time:                      7.063
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.069

    Number of logic level(s):                12
    Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
    Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]      DFFC     Q        Out     0.243     0.243       -         
rbin_num[1]                                                        Net      -        -       0.535     -           6         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     I1       In      -         0.778       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     F        Out     0.570     1.348       -         
rbin_num13_6                                                       Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I1       In      -         1.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.570     2.453       -         
rbin_num13                                                         Net      -        -       0.657     -           22        
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.110       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.680       -         
\\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.215       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.764       -         
un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.299       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.848       -         
un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.848       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.883       -         
un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.918       -         
un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.918       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.953       -         
un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.953       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.988       -         
un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.988       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.023       -         
un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.023       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.058       -         
un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.058       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.528       -         
un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.063       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 7.124 is 3.792(53.2%) logic and 3.332(46.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.055
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.994

    - Propagation time:                      7.049
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.055

    Number of logic level(s):                11
    Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
    Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                  Pin      Pin               Arrival     No. of    
Name                                                                   Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]          DFFC     Q        Out     0.243     0.243       -         
rbin_num[1]                                                            Net      -        -       0.535     -           6         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ            LUT4     I1       In      -         0.778       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ            LUT4     F        Out     0.570     1.348       -         
rbin_num13_6                                                           Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ              LUT4     I1       In      -         1.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ              LUT4     F        Out     0.570     2.453       -         
rbin_num13                                                             Net      -        -       0.657     -           22        
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]              LUT4     I1       In      -         3.110       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]              LUT4     F        Out     0.570     3.680       -         
\\un4_cZ\[2\]                                                          Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0_cZ     LUT2     I0       In      -         4.215       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0_cZ     LUT2     F        Out     0.549     4.764       -         
un7_cry_1_0_0_RNO_0_cZ                                                 Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0              ALU      I1       In      -         5.299       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0              ALU      COUT     Out     0.570     5.869       -         
un7_cry_1_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0              ALU      CIN      In      -         5.869       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0              ALU      COUT     Out     0.035     5.904       -         
un7_cry_2_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0              ALU      CIN      In      -         5.904       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0              ALU      COUT     Out     0.035     5.939       -         
un7_cry_3_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0              ALU      CIN      In      -         5.939       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0              ALU      COUT     Out     0.035     5.974       -         
un7_cry_4_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0              ALU      CIN      In      -         5.974       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0              ALU      COUT     Out     0.035     6.009       -         
un7_cry_5_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0              ALU      CIN      In      -         6.009       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0              ALU      COUT     Out     0.035     6.044       -         
un7_cry_6_0_0_COUT                                                     Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                  ALU      CIN      In      -         6.044       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                  ALU      SUM      Out     0.470     6.514       -         
un7_s_7_0_SUM                                                          Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]          DFFC     D        In      -         7.049       -         
=================================================================================================================================
Total path delay (propagation time + setup) of 7.110 is 3.778(53.1%) logic and 3.332(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.055
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.994

    - Propagation time:                      7.042
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.048

    Number of logic level(s):                12
    Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\] / Q
    Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]      DFFC     Q        Out     0.243     0.243       -         
rbin_num[0]                                                        Net      -        -       0.535     -           3         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     I0       In      -         0.778       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     F        Out     0.549     1.327       -         
rbin_num13_6                                                       Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I1       In      -         1.862       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.570     2.432       -         
rbin_num13                                                         Net      -        -       0.657     -           22        
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.089       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.659       -         
\\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.194       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.743       -         
un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.278       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.827       -         
un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.827       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.862       -         
un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.862       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.897       -         
un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.897       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.932       -         
un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.932       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.967       -         
un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.967       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.002       -         
un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.002       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.037       -         
un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.037       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.507       -         
un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.042       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.055
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.994

    - Propagation time:                      7.042
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.048

    Number of logic level(s):                12
    Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\] / Q
    Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]      DFFC     Q        Out     0.243     0.243       -         
rbin_num[5]                                                        Net      -        -       0.535     -           3         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_5_cZ        LUT4     I1       In      -         0.778       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_5_cZ        LUT4     F        Out     0.570     1.348       -         
rbin_num13_5                                                       Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I0       In      -         1.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.549     2.432       -         
rbin_num13                                                         Net      -        -       0.657     -           22        
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.089       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.659       -         
\\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.194       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.743       -         
un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.278       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.827       -         
un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.827       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.862       -         
un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.862       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.897       -         
un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.897       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.932       -         
un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.932       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.967       -         
un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.967       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.002       -         
un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.002       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.037       -         
un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.037       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.507       -         
un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.042       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.055
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.994

    - Propagation time:                      7.028
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.034

    Number of logic level(s):                11
    Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
    Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
    The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
    The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]        DFFC     Q        Out     0.243     0.243       -         
rbin_num[1]                                                          Net      -        -       0.535     -           6         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ          LUT4     I1       In      -         0.778       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ          LUT4     F        Out     0.570     1.348       -         
rbin_num13_6                                                         Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ            LUT4     I1       In      -         1.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ            LUT4     F        Out     0.570     2.453       -         
rbin_num13                                                           Net      -        -       0.657     -           22        
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4\[3\]               LUT4     I1       In      -         3.110       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4\[3\]               LUT4     F        Out     0.570     3.680       -         
\\un4\[3\]                                                           Net      -        -       0.535     -           2         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_cZ     LUT2     I0       In      -         4.215       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_cZ     LUT2     F        Out     0.549     4.764       -         
un7_cry_1_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0            ALU      I0       In      -         5.299       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0            ALU      COUT     Out     0.549     5.848       -         
un7_cry_1_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0            ALU      CIN      In      -         5.848       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0            ALU      COUT     Out     0.035     5.883       -         
un7_cry_2_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0            ALU      CIN      In      -         5.883       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0            ALU      COUT     Out     0.035     5.918       -         
un7_cry_3_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0            ALU      CIN      In      -         5.918       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0            ALU      COUT     Out     0.035     5.953       -         
un7_cry_4_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0            ALU      CIN      In      -         5.953       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0            ALU      COUT     Out     0.035     5.988       -         
un7_cry_5_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0            ALU      CIN      In      -         5.988       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0            ALU      COUT     Out     0.035     6.023       -         
un7_cry_6_0_0_COUT                                                   Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                ALU      CIN      In      -         6.023       -         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                ALU      SUM      Out     0.470     6.493       -         
un7_s_7_0_SUM                                                        Net      -        -       0.535     -           1         
u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]        DFFC     D        In      -         7.028       -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.089 is 3.757(53.0%) logic and 3.332(47.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                      Starting                                      Arrival           
Instance              Reference     Type     Pin        Net         Time        Slack 
                      Clock                                                           
--------------------------------------------------------------------------------------
osc_inst.osc_inst     System        OSC      OSCOUT     clk_osc     0.000       -0.080
======================================================================================


Ending Points with Worst Slack
******************************

                         Starting                                     Required           
Instance                 Reference     Type     Pin       Net         Time         Slack 
                         Clock                                                           
-----------------------------------------------------------------------------------------
GW_PLL_inst.pll_inst     System        PLL      CLKIN     clk_osc     0.455        -0.080
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      0.455
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.455

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.080

    Number of logic level(s):                0
    Starting point:                          osc_inst.osc_inst / OSCOUT
    Ending point:                            GW_PLL_inst.pll_inst / CLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                    Pin        Pin               Arrival     No. of    
Name                     Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
osc_inst.osc_inst        OSC      OSCOUT     Out     0.000     0.000       -         
clk_osc                  Net      -          -       0.535     -           1         
GW_PLL_inst.pll_inst     PLL      CLKIN      In      -         0.535       -         
=====================================================================================
Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB)

---------------------------------------
Resource Usage Report for TOP 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             44 uses
DFFC            55 uses
DFFP            1 use
GSR             1 use
MUX2_LUT5       6 uses
MUX2_LUT6       3 uses
OSC             1 use
PLL             1 use
SDP             1 use
LUT1            1 use
LUT2            23 uses
LUT3            11 uses
LUT4            40 uses

I/O ports: 9
I/O primitives: 9
IBUF           1 use
OBUF           8 uses

I/O Register bits:                  0
Register bits not including I/Os:   56 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 1 of 140 (0%)

Total load per clock:
   GW_PLL|clkout_inferred_clock: 58

@S |Mapping Summary:
Total  LUTs: 75 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 40MB peak: 191MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Fri Sep 14 17:27:26 2018

###########################################################]
