i GW_PLL_inst.clkout_i
m 0 0
u 5 12
n ckid0_0 {t:Din[7:0].C} Black box on clock path
p {t:GW_PLL_inst.pll_inst.CLKOUT}{t:GW_PLL_inst.clkout_inferred_clock.I[0]}{t:GW_PLL_inst.clkout_inferred_clock.OUT[0]}{p:GW_PLL_inst.clkout}{t:GW_PLL_inst.clkout}{t:Din[7:0].C}
e ckid0_0 {t:Din[7:0].C} dffr
d ckid0_0 {t:GW_PLL_inst.pll_inst.CLKOUT} PLL Black box on clock path
i GW_PLL_inst.lock_o
m 0 0
u 0 0
d ckid0_1 {t:GW_PLL_inst.pll_inst.LOCK} PLL Black box on clock path
i GW_PLL_inst.clkoutd3_o
m 0 0
u 0 0
d ckid0_2 {t:GW_PLL_inst.pll_inst.CLKOUTD3} PLL Black box on clock path
i GW_PLL_inst.clkoutd_o
m 0 0
u 0 0
d ckid0_3 {t:GW_PLL_inst.pll_inst.CLKOUTD} PLL Black box on clock path
i GW_PLL_inst.clkoutp_o
m 0 0
u 0 0
d ckid0_4 {t:GW_PLL_inst.pll_inst.CLKOUTP} PLL Black box on clock path
l 0 0 0 0 0
r 0 0 0 0 0 0 0 0
