#OPTIONS:"|-layerid|0|-orig_srs|D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\impl\\synthesize\\rev_1\\synwork\\lossy_ex_comp.srs|-top|TOP|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-infer_seqShift|-I|D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\impl\\synthesize\\|-I|C:\\Gowin\\1.8\\SynplifyPro\\lib|-sysv|-devicelib|C:\\Gowin\\1.8\\SynplifyPro\\lib\\generic\\gw2a.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\bin64\\c_ver.exe":1535994508
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\lib\\generic\\gw2a.v":1535995900
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\lib\\vlog\\hypermods.v":1535994174
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\lib\\vlog\\umr_capim.v":1536736162
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1535994174
#CUR:"C:\\Gowin\\1.8\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1535994174
#CUR:"D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\src\\TOP.v":1536917054
#CUR:"D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\src\\gw_osc\\gw_osc.v":1531378228
#CUR:"D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\src\\gw_pll\\gw_pll.v":1537181465
#CUR:"D:\\user-bak\\Users\\FDELL\\Desktop\\Gowin_RAM_Based_Shift_Register_IP_RefDesign\\Lossy_ex\\project\\src\\RAM_based_shift_reg_top\\RAM_based_shift_reg_top.v":1531883234
0			"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\TOP.v" verilog
1			"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\gw_osc\gw_osc.v" verilog
2			"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\gw_pll\gw_pll.v" verilog
3			"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossy_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v" verilog
#Dependency Lists(Uses List)
0 3 2 1
1 -1
2 -1
3 -1
#Dependency Lists(Users Of)
0 -1
1 0
2 0
3 0
#Design Unit to File Association
module work \~RAM_based_shift_reg.RAM_based_shift_reg_top_ 3
module work TOP 0
module work RAM_based_shift_reg_top 3
module work GW_PLL 2
module work GW_OSC 1
