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    # Tue Jul 10 18:03:17 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    @N:MO231 : top.v(30) | Found counter in view:work.TOP(verilog) instance Din[7:0]

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -2.22ns		  87 /        22
       2		0h:00m:00s		    -2.22ns		  87 /        22

       3		0h:00m:00s		    -2.22ns		  87 /        22

       4		0h:00m:00s		    -2.22ns		  87 /        22

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 190MB)

    Writing Analyst data base D:\ex\lossy_ex\impl\synthesize\rev_1\synwork\lossy_ex_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 190MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 190MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 190MB)

    @W:MT246 : gw_pll.v(26) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock GW_PLL|clkout_inferred_clock with period 5.37ns. Please declare a user-defined clock on net GW_PLL_inst.clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Jul 10 18:03:20 2018
    #

    Top view:               TOP
    Requested Frequency:    186.1 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.948

                                     Requested      Estimated      Requested     Estimated                Clock        Clock
    Starting Clock                   Frequency      Frequency      Period        Period        Slack      Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------
    GW_PLL|clkout_inferred_clock     186.1 MHz      158.2 MHz      5.374         6.322         -0.948     inferred     Autoconstr_clkgroup_0
    System                           2199.3 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup
    ========================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    System                        System                        |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -
    System                        GW_PLL|clkout_inferred_clock  |  5.374       4.766   |  No paths    -      |  No paths    -      |  No paths    -
    GW_PLL|clkout_inferred_clock  System                        |  5.374       4.547   |  No paths    -      |  No paths    -      |  No paths    -
    GW_PLL|clkout_inferred_clock  GW_PLL|clkout_inferred_clock  |  5.374       -0.948  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: GW_PLL|clkout_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                      Starting                                                          Arrival
    Instance                                                          Reference                        Type     Pin     Net             Time        Slack
                                                                      Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[3]                                                       GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_rrr[3]     0.292       -0.948
    ADDR_rrr[2]                                                       GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_rrr[2]     0.292       -0.923
    ADDR_rrr[1]                                                       GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_rrr[1]     0.292       -0.829
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\ADDR_in_Z\[2\]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_in[2]      0.292       -0.819
    ADDR_rrr[0]                                                       GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_rrr[0]     0.292       -0.743
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\ADDR_in_Z\[3\]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_in[3]      0.292       -0.710
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\ADDR_in_Z\[0\]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_in[0]      0.292       -0.638
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\ADDR_in_Z\[1\]      GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR_in[1]      0.292       -0.529
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[4]     0.292       -0.157
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[3]     0.292       -0.132
    ======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                      Starting                                                              Required
    Instance                                                          Reference                        Type     Pin     Net                 Time         Slack
                                                                      Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc2_cZ       5.301        -0.948
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc1_cZ       5.301        -0.221
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc0_cZ       5.301        0.137
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc0_0_cZ     5.301        0.224
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc1_0_cZ     5.301        0.423
    ADDR_rrr[1]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_rrr_3[1]       5.301        1.352
    ADDR_rrr[2]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_rrr_3[2]       5.301        1.482
    ADDR_rrr[3]                                                       GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_rrr_3[3]       5.301        1.725
    cnt[8]                                                            GW_PLL|clkout_inferred_clock     DFFC     D       cnt_3[8]            5.301        1.764
    cnt[7]                                                            GW_PLL|clkout_inferred_clock     DFFC     D       cnt_3[7]            5.301        1.806
    ===========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      6.249
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.948

        Number of logic level(s):                6
        Starting point:                          ADDR_rrr[3] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                    Pin      Pin               Arrival     No. of
    Name                                                                Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[3]                                                         DFFC          Q        Out     0.292     0.292       -
    ADDR_rrr[3]                                                         Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0               LUT4          I1       In      -         0.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0               LUT4          F        Out     0.684     1.511       -
    g0_8_1_1                                                            Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          I1       In      -         2.046       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          F        Out     0.684     2.730       -
    g0_7_1_1                                                            Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     I1       In      -         2.730       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     O        Out     0.126     2.856       -
    g0_7_1_0                                                            Net           -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          I2       In      -         3.391       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          F        Out     0.554     3.945       -
    rbin_num13_RNIJ6N54                                                 Net           -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ       LUT4          I1       In      -         4.480       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ       LUT4          F        Out     0.684     5.164       -
    un7_axbxc2_1_0_cZ                                                   Net           -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ           LUT4          I1       In      -         5.565       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ           LUT4          F        Out     0.684     6.249       -
    un7_axbxc2_cZ                                                       Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]       DFFC          D        In      -         6.249       -
    ===================================================================================================================================
    Total path delay (propagation time + setup) of 6.322 is 3.781(59.8%) logic and 2.541(40.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      6.249
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.948

        Number of logic level(s):                6
        Starting point:                          ADDR_rrr[3] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                     Pin      Pin               Arrival     No. of
    Name                                                                 Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[3]                                                          DFFC          Q        Out     0.292     0.292       -
    ADDR_rrr[3]                                                          Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0                LUT4          I1       In      -         0.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0                LUT4          F        Out     0.684     1.511       -
    g0_8_1_1                                                             Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          I1       In      -         2.046       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          F        Out     0.684     2.730       -
    g0_7_1_0_0                                                           Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     I0       In      -         2.730       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     O        Out     0.126     2.856       -
    g0_7_1_0                                                             Net           -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          I2       In      -         3.391       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          F        Out     0.554     3.945       -
    rbin_num13_RNIJ6N54                                                  Net           -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ        LUT4          I1       In      -         4.480       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ        LUT4          F        Out     0.684     5.164       -
    un7_axbxc2_1_0_cZ                                                    Net           -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ            LUT4          I1       In      -         5.565       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ            LUT4          F        Out     0.684     6.249       -
    un7_axbxc2_cZ                                                        Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]        DFFC          D        In      -         6.249       -
    ====================================================================================================================================
    Total path delay (propagation time + setup) of 6.322 is 3.781(59.8%) logic and 2.541(40.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      6.224
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.923

        Number of logic level(s):                6
        Starting point:                          ADDR_rrr[2] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                    Pin      Pin               Arrival     No. of
    Name                                                                Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[2]                                                         DFFC          Q        Out     0.292     0.292       -
    ADDR_rrr[2]                                                         Net           -        -       0.535     -           10
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0               LUT4          I0       In      -         0.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0               LUT4          F        Out     0.659     1.485       -
    g0_8_1_1                                                            Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          I1       In      -         2.020       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41      LUT4          F        Out     0.684     2.704       -
    g0_7_1_1                                                            Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     I1       In      -         2.704       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2      MUX2_LUT5     O        Out     0.126     2.830       -
    g0_7_1_0                                                            Net           -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          I2       In      -         3.365       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54     LUT4          F        Out     0.554     3.920       -
    rbin_num13_RNIJ6N54                                                 Net           -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ       LUT4          I1       In      -         4.455       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ       LUT4          F        Out     0.684     5.139       -
    un7_axbxc2_1_0_cZ                                                   Net           -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ           LUT4          I1       In      -         5.540       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ           LUT4          F        Out     0.684     6.224       -
    un7_axbxc2_cZ                                                       Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]       DFFC          D        In      -         6.224       -
    ===================================================================================================================================
    Total path delay (propagation time + setup) of 6.297 is 3.756(59.6%) logic and 2.541(40.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      6.224
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.923

        Number of logic level(s):                6
        Starting point:                          ADDR_rrr[2] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                     Pin      Pin               Arrival     No. of
    Name                                                                 Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[2]                                                          DFFC          Q        Out     0.292     0.292       -
    ADDR_rrr[2]                                                          Net           -        -       0.535     -           10
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0                LUT4          I0       In      -         0.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0                LUT4          F        Out     0.659     1.485       -
    g0_8_1_1                                                             Net           -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          I1       In      -         2.020       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_0_RNIKDV41_0     LUT4          F        Out     0.684     2.704       -
    g0_7_1_0_0                                                           Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     I0       In      -         2.704       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1_RNITVRB2       MUX2_LUT5     O        Out     0.126     2.830       -
    g0_7_1_0                                                             Net           -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          I2       In      -         3.365       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_RNIJ6N54      LUT4          F        Out     0.554     3.920       -
    rbin_num13_RNIJ6N54                                                  Net           -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ        LUT4          I1       In      -         4.455       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ        LUT4          F        Out     0.684     5.139       -
    un7_axbxc2_1_0_cZ                                                    Net           -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ            LUT4          I1       In      -         5.540       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ            LUT4          F        Out     0.684     6.224       -
    un7_axbxc2_cZ                                                        Net           -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]        DFFC          D        In      -         6.224       -
    ====================================================================================================================================
    Total path delay (propagation time + setup) of 6.297 is 3.756(59.6%) logic and 2.541(40.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      6.130
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.829

        Number of logic level(s):                5
        Starting point:                          ADDR_rrr[1] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                             Pin      Pin               Arrival     No. of
    Name                                                              Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    ADDR_rrr[1]                                                       DFFC     Q        Out     0.292     0.292       -
    ADDR_rrr[1]                                                       Net      -        -       0.596     -           11
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1             LUT4     I1       In      -         0.888       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.addr_ch_1             LUT4     F        Out     0.684     1.572       -
    g0_8_1_0                                                          Net      -        -       0.535     -           8
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_ac0_1_1_1         LUT2     I0       In      -         2.107       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_ac0_1_1_1         LUT2     F        Out     0.659     2.765       -
    g0_2_1_0                                                          Net      -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_ac0_1_1_cZ        LUT4     I1       In      -         3.167       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_ac0_1_1_cZ        LUT4     F        Out     0.684     3.851       -
    un7_ac0_1_1_cZ                                                    Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ     LUT4     I0       In      -         4.386       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_1_0_cZ     LUT4     F        Out     0.659     5.044       -
    un7_axbxc2_1_0_cZ                                                 Net      -        -       0.401     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ         LUT4     I1       In      -         5.446       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_axbxc2_cZ         LUT4     F        Out     0.684     6.130       -
    un7_axbxc2_cZ                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     DFFC     D        In      -         6.130       -
    ============================================================================================================================
    Total path delay (propagation time + setup) of 6.203 is 3.734(60.2%) logic and 2.468(39.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                     Starting                                        Arrival
    Instance                                                         Reference     Type     Pin        Net           Time        Slack
                                                                     Clock
    -----------------------------------------------------------------------------------------------------------------------------------
    osc_inst                                                         System        OSC      OSCOUT     clk_osc       0.000       -0.080
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_i_cZ\[0\]     System        INV      O          wbin_i[0]     0.000       4.766
    ===================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                  Starting                                       Required
    Instance                                                      Reference     Type     Pin       Net           Time         Slack
                                                                  Clock
    --------------------------------------------------------------------------------------------------------------------------------
    GW_PLL_inst.pll_inst                                          System        PLL      CLKIN     clk_osc       0.455        -0.080
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[0\]     System        DFFC     D         wbin_i[0]     5.301        4.766
    ================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.455
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.455

        - Propagation time:                      0.535
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.080

        Number of logic level(s):                0
        Starting point:                          osc_inst / OSCOUT
        Ending point:                            GW_PLL_inst.pll_inst / CLKIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                    Pin        Pin               Arrival     No. of
    Name                     Type     Name       Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------
    osc_inst                 OSC      OSCOUT     Out     0.000     0.000       -
    clk_osc                  Net      -          -       0.535     -           1
    GW_PLL_inst.pll_inst     PLL      CLKIN      In      -         0.535       -
    =====================================================================================
    Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.374
        - Setup time:                            0.073
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.301

        - Propagation time:                      0.535
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 4.766

        Number of logic level(s):                0
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_i_cZ\[0\] / O
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[0\] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                            Pin      Pin               Arrival     No. of
    Name                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_i_cZ\[0\]     INV      O        Out     0.000     0.000       -
    wbin_i[0]                                                        Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\wbin_Z\[0\]        DFFC     D        In      -         0.535       -
    ===========================================================================================================================
    Total path delay (propagation time + setup) of 0.608 is 0.073(12.0%) logic and 0.535(88.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    ---------------------------------------
    Resource Usage Report for TOP

    Mapping to part: gw2a_55pbga1156-6
    Cell usage:
    ALU             18 uses
    DFFC            36 uses
    GSR             1 use
    INV             1 use
    MUX2_LUT5       9 uses
    MUX2_LUT6       1 use
    OSC             1 use
    PLL             1 use
    SDP             1 use
    LUT2            13 uses
    LUT3            3 uses
    LUT4            54 uses

    I/O ports: 9
    I/O primitives: 9
    IBUF           1 use
    OBUF           8 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   36 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 140 (0%)

    Total load per clock:
       GW_PLL|clkout_inferred_clock: 38

    @S |Mapping Summary:
    Total  LUTs: 70 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 39MB peak: 190MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Tue Jul 10 18:03:20 2018

    ###########################################################]

`