# Fri Sep 14 15:15:16 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1138R, Built Jul 26 2018 09:55:40


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -0.49ns		  19 /         4



Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 118MB peak: 191MB)

Writing Analyst data base D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 191MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

@W: MT420 |Found inferred clock RAM_based_shift_reg_top|clk with period 1.20ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Sep 14 15:15:19 2018
#


Top view:               RAM_based_shift_reg_top
Requested Frequency:    834.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.211

                                Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------
RAM_based_shift_reg_top|clk     834.9 MHz     709.7 MHz     1.198         1.409         -0.211     inferred     Autoconstr_clkgroup_0
=====================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------
RAM_based_shift_reg_top|clk  RAM_based_shift_reg_top|clk  |  1.198       -0.211  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: RAM_based_shift_reg_top|clk
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                     Arrival           
Instance                          Reference                       Type     Pin     Net         Time        Slack 
                                  Clock                                                                          
-----------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[1]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[1]     0.243       -0.211
u_RAM_based_shift_reg.wbin[0]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[0]     0.243       -0.190
u_RAM_based_shift_reg.wbin[2]     RAM_based_shift_reg_top|clk     DFFC     Q       wbin[2]     0.243       -0.103
=================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                         Required           
Instance                              Reference                       Type     Pin       Net           Time         Slack 
                                      Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[0]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_3[0]     1.137        -0.211
u_RAM_based_shift_reg.wbin[1]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_3[1]     1.137        -0.211
u_RAM_based_shift_reg.wbin[2]         RAM_based_shift_reg_top|clk     DFFC     D         wbin_3[2]     1.137        -0.211
u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SP       AD[3]     wbin[0]       1.160        0.382 
u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SP       AD[4]     wbin[1]       1.160        0.382 
u_RAM_based_shift_reg.mem_mem_0_0     RAM_based_shift_reg_top|clk     SP       AD[5]     wbin[2]       1.160        0.382 
==========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1.198
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.137

    - Propagation time:                      1.348
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.211

    Number of logic level(s):                1
    Starting point:                          u_RAM_based_shift_reg.wbin[1] / Q
    Ending point:                            u_RAM_based_shift_reg.wbin[0] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[1]       DFFC     Q        Out     0.243     0.243       -         
wbin[1]                             Net      -        -       0.535     -           4         
u_RAM_based_shift_reg.wbin_3[0]     LUT3     I1       In      -         0.778       -         
u_RAM_based_shift_reg.wbin_3[0]     LUT3     F        Out     0.570     1.348       -         
wbin_3[0]                           Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.wbin[0]       DFFC     D        In      -         1.348       -         
==============================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.874(62.0%) logic and 0.535(38.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1.198
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.137

    - Propagation time:                      1.348
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.211

    Number of logic level(s):                1
    Starting point:                          u_RAM_based_shift_reg.wbin[1] / Q
    Ending point:                            u_RAM_based_shift_reg.wbin[1] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[1]       DFFC     Q        Out     0.243     0.243       -         
wbin[1]                             Net      -        -       0.535     -           4         
u_RAM_based_shift_reg.wbin_3[1]     LUT3     I1       In      -         0.778       -         
u_RAM_based_shift_reg.wbin_3[1]     LUT3     F        Out     0.570     1.348       -         
wbin_3[1]                           Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.wbin[1]       DFFC     D        In      -         1.348       -         
==============================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.874(62.0%) logic and 0.535(38.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1.198
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.137

    - Propagation time:                      1.348
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.211

    Number of logic level(s):                1
    Starting point:                          u_RAM_based_shift_reg.wbin[1] / Q
    Ending point:                            u_RAM_based_shift_reg.wbin[2] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[1]       DFFC     Q        Out     0.243     0.243       -         
wbin[1]                             Net      -        -       0.535     -           4         
u_RAM_based_shift_reg.wbin_3[2]     LUT3     I1       In      -         0.778       -         
u_RAM_based_shift_reg.wbin_3[2]     LUT3     F        Out     0.570     1.348       -         
wbin_3[2]                           Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.wbin[2]       DFFC     D        In      -         1.348       -         
==============================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.874(62.0%) logic and 0.535(38.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      1.198
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.137

    - Propagation time:                      1.327
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.190

    Number of logic level(s):                1
    Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
    Ending point:                            u_RAM_based_shift_reg.wbin[0] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[0]       DFFC     Q        Out     0.243     0.243       -         
wbin[0]                             Net      -        -       0.535     -           4         
u_RAM_based_shift_reg.wbin_3[0]     LUT3     I0       In      -         0.778       -         
u_RAM_based_shift_reg.wbin_3[0]     LUT3     F        Out     0.549     1.327       -         
wbin_3[0]                           Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.wbin[0]       DFFC     D        In      -         1.327       -         
==============================================================================================
Total path delay (propagation time + setup) of 1.388 is 0.853(61.5%) logic and 0.535(38.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      1.198
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.137

    - Propagation time:                      1.327
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.190

    Number of logic level(s):                1
    Starting point:                          u_RAM_based_shift_reg.wbin[0] / Q
    Ending point:                            u_RAM_based_shift_reg.wbin[1] / D
    The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
    The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_RAM_based_shift_reg.wbin[0]       DFFC     Q        Out     0.243     0.243       -         
wbin[0]                             Net      -        -       0.535     -           4         
u_RAM_based_shift_reg.wbin_3[1]     LUT3     I0       In      -         0.778       -         
u_RAM_based_shift_reg.wbin_3[1]     LUT3     F        Out     0.549     1.327       -         
wbin_3[1]                           Net      -        -       0.000     -           1         
u_RAM_based_shift_reg.wbin[1]       DFFC     D        In      -         1.327       -         
==============================================================================================
Total path delay (propagation time + setup) of 1.388 is 0.853(61.5%) logic and 0.535(38.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 191MB)

---------------------------------------
Resource Usage Report for RAM_based_shift_reg_top 

Mapping to part: gw2a_55pbga484-8
Cell usage:
DFFC            3 uses
GSR             1 use
SP              1 use
LUT2            8 uses
LUT3            3 uses

I/O Register bits:                  0
Register bits not including I/Os:   3 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 1 of 140 (0%)

Total load per clock:
   RAM_based_shift_reg_top|clk: 4

@S |Mapping Summary:
Total  LUTs: 11 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 40MB peak: 191MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Sep 14 15:15:19 2018

###########################################################]
