#--  Synopsys, Inc.
#--  Version N-2018.03G-Beta6
#--  Project file E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\run_options.txt
#--  Written on Mon Jul 16 14:19:52 2018


#project files
add_file -verilog "C:/Gowin/1.8/IDE/ipcore/RAMBasedShiftRegister/data/RAM_based_shift_reg_top.v"
add_file -verilog "C:/Gowin/1.8/IDE/ipcore/RAMBasedShiftRegister/data/RAM_based_shift_reg.v"



#implementation: "rev_1"
impl -add rev_1 -type fpga

#
#implementation attributes

set_option -vlog_std sysv
set_option -project_relative_includes 1
set_option -include_path {E:/ide_prj/lossless_ex/src/RAM_based_shift_reg_top/temp/RAM_Based_Shift_Register;C:/Gowin/1.8/IDE/ipcore/RAMBasedShiftRegister/data}

#device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_55
set_option -package PBGA484
set_option -speed_grade -8
set_option -part_companion ""

#compilation/mapping options

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW2A
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/RAM_based_shift_reg_top.vm"
impl -active "rev_1"
