`

    # Wed Jul 18 13:39:58 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    @N:MO231 : top.v(30) | Found counter in view:work.TOP(verilog) instance Din[7:0]

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -2.60ns		  99 /        27
       2		0h:00m:00s		    -2.60ns		  99 /        27

       3		0h:00m:00s		    -2.60ns		  99 /        27

       4		0h:00m:00s		    -2.60ns		  99 /        27

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 190MB)

    Writing Analyst data base D:\ex\lossless_ex\impl\synthesize\rev_1\synwork\lossless_ex_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 190MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    @W:MT246 : gw_pll.v(26) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock GW_PLL|clkout_inferred_clock with period 6.06ns. Please declare a user-defined clock on net GW_PLL_inst.clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Jul 18 13:40:01 2018
    #

    Top view:               TOP
    Requested Frequency:    165.1 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.069

                                     Requested      Estimated      Requested     Estimated                Clock        Clock
    Starting Clock                   Frequency      Frequency      Period        Period        Slack      Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------
    GW_PLL|clkout_inferred_clock     165.1 MHz      140.4 MHz      6.055         7.124         -1.069     inferred     Autoconstr_clkgroup_0
    System                           2199.3 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup
    ========================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    System                        System                        |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -
    GW_PLL|clkout_inferred_clock  GW_PLL|clkout_inferred_clock  |  6.055       -1.069  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: GW_PLL|clkout_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                      Starting                                                          Arrival
    Instance                                                          Reference                        Type     Pin     Net             Time        Slack
                                                                      Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[1]     0.243       -1.069
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[0]     0.243       -1.048
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[5]     0.243       -1.048
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[4]     0.243       -1.027
    ADDR[8]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[8]         0.243       -1.005
    ADDR[7]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[7]         0.243       -0.994
    ADDR[3]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[3]         0.243       -0.984
    ADDR[4]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[4]         0.243       -0.973
    ADDR[6]                                                           GW_PLL|clkout_inferred_clock     DFFC     Q       ADDR[6]         0.243       -0.973
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     Q       rbin_num[2]     0.243       -0.961
    ======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                      Starting                                                                Required
    Instance                                                          Reference                        Type     Pin     Net                   Time         Slack
                                                                      Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_s_7_0_SUM         5.994        -1.069
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[8\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_6_0_0_SUM     5.994        -1.034
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[7\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_5_0_0_SUM     5.994        -0.999
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[6\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_4_0_0_SUM     5.994        -0.964
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_3_0_0_SUM     5.994        -0.929
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[4\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_2_0_0_SUM     5.994        -0.894
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[3\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_1_0_0_SUM     5.994        -0.859
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[2\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_cry_0_0_SUM       5.994        -0.637
    ADDR[8]                                                           GW_PLL|clkout_inferred_clock     DFFC     D       ADDR_3[8]             5.994        1.207
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]     GW_PLL|clkout_inferred_clock     DFFC     D       un7_axbxc0_cZ         5.994        1.230
    =============================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.063
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.069

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                              Pin      Pin               Arrival     No. of
    Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]      DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                                                        Net      -        -       0.535     -           6
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                                                       Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.570     2.453       -
    rbin_num13                                                         Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.680       -
    \\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.764       -
    un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.299       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.848       -
    un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.848       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.883       -
    un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.918       -
    un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.918       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.953       -
    un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.953       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.988       -
    un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.988       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.023       -
    un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.023       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.058       -
    un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.058       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.528       -
    un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.063       -
    =============================================================================================================================
    Total path delay (propagation time + setup) of 7.124 is 3.792(53.2%) logic and 3.332(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.049
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.055

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                  Pin      Pin               Arrival     No. of
    Name                                                                   Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]          DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                                                            Net      -        -       0.535     -           6
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ            LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ            LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                                                           Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ              LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ              LUT4     F        Out     0.570     2.453       -
    rbin_num13                                                             Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]              LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]              LUT4     F        Out     0.570     3.680       -
    \\un4_cZ\[2\]                                                          Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0_cZ     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0_cZ     LUT2     F        Out     0.549     4.764       -
    un7_cry_1_0_0_RNO_0_cZ                                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0              ALU      I1       In      -         5.299       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0              ALU      COUT     Out     0.570     5.869       -
    un7_cry_1_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0              ALU      CIN      In      -         5.869       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0              ALU      COUT     Out     0.035     5.904       -
    un7_cry_2_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0              ALU      CIN      In      -         5.904       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0              ALU      COUT     Out     0.035     5.939       -
    un7_cry_3_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0              ALU      CIN      In      -         5.939       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0              ALU      COUT     Out     0.035     5.974       -
    un7_cry_4_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0              ALU      CIN      In      -         5.974       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0              ALU      COUT     Out     0.035     6.009       -
    un7_cry_5_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0              ALU      CIN      In      -         6.009       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0              ALU      COUT     Out     0.035     6.044       -
    un7_cry_6_0_0_COUT                                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                  ALU      CIN      In      -         6.044       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                  ALU      SUM      Out     0.470     6.514       -
    un7_s_7_0_SUM                                                          Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]          DFFC     D        In      -         7.049       -
    =================================================================================================================================
    Total path delay (propagation time + setup) of 7.110 is 3.778(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.042
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.048

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                              Pin      Pin               Arrival     No. of
    Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[0\]      DFFC     Q        Out     0.243     0.243       -
    rbin_num[0]                                                        Net      -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     I0       In      -         0.778       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ        LUT4     F        Out     0.549     1.327       -
    rbin_num13_6                                                       Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I1       In      -         1.862       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.570     2.432       -
    rbin_num13                                                         Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.089       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.659       -
    \\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.194       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.743       -
    un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.278       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.827       -
    un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.862       -
    un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.862       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.897       -
    un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.897       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.932       -
    un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.932       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.967       -
    un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.967       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.002       -
    un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.002       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.037       -
    un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.037       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.507       -
    un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.042       -
    =============================================================================================================================
    Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.042
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.048

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                              Pin      Pin               Arrival     No. of
    Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[5\]      DFFC     Q        Out     0.243     0.243       -
    rbin_num[5]                                                        Net      -        -       0.535     -           3
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_5_cZ        LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_5_cZ        LUT4     F        Out     0.570     1.348       -
    rbin_num13_5                                                       Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     I0       In      -         1.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ          LUT4     F        Out     0.549     2.432       -
    rbin_num13                                                         Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     I1       In      -         3.089       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4_cZ\[2\]          LUT4     F        Out     0.570     3.659       -
    \\un4_cZ\[2\]                                                      Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     I0       In      -         4.194       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0_RNO_cZ     LUT2     F        Out     0.549     4.743       -
    un7_cry_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      I0       In      -         5.278       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_0_0            ALU      COUT     Out     0.549     5.827       -
    un7_cry_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      CIN      In      -         5.827       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0          ALU      COUT     Out     0.035     5.862       -
    un7_cry_1_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      CIN      In      -         5.862       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0          ALU      COUT     Out     0.035     5.897       -
    un7_cry_2_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      CIN      In      -         5.897       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0          ALU      COUT     Out     0.035     5.932       -
    un7_cry_3_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      CIN      In      -         5.932       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0          ALU      COUT     Out     0.035     5.967       -
    un7_cry_4_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      CIN      In      -         5.967       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0          ALU      COUT     Out     0.035     6.002       -
    un7_cry_5_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      CIN      In      -         6.002       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0          ALU      COUT     Out     0.035     6.037       -
    un7_cry_6_0_0_COUT                                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      CIN      In      -         6.037       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0              ALU      SUM      Out     0.470     6.507       -
    un7_s_7_0_SUM                                                      Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]      DFFC     D        In      -         7.042       -
    =============================================================================================================================
    Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.028
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.034

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\] / Q
        Ending point:                            u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\] / D
        The start point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK
        The end   point is clocked by            GW_PLL|clkout_inferred_clock [rising] on pin CLK

    Instance / Net                                                                Pin      Pin               Arrival     No. of
    Name                                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[1\]        DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                                                          Net      -        -       0.535     -           6
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ          LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_6_cZ          LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                                                         Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ            LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.rbin_num13_cZ            LUT4     F        Out     0.570     2.453       -
    rbin_num13                                                           Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4\[3\]               LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\un4\[3\]               LUT4     F        Out     0.570     3.680       -
    \\un4\[3\]                                                           Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_cZ     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_cZ     LUT2     F        Out     0.549     4.764       -
    un7_cry_1_0_0_RNO_cZ                                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0            ALU      I0       In      -         5.299       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_1_0_0            ALU      COUT     Out     0.549     5.848       -
    un7_cry_1_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0            ALU      CIN      In      -         5.848       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_2_0_0            ALU      COUT     Out     0.035     5.883       -
    un7_cry_2_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0            ALU      CIN      In      -         5.883       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_3_0_0            ALU      COUT     Out     0.035     5.918       -
    un7_cry_3_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0            ALU      CIN      In      -         5.918       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_4_0_0            ALU      COUT     Out     0.035     5.953       -
    un7_cry_4_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0            ALU      CIN      In      -         5.953       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_5_0_0            ALU      COUT     Out     0.035     5.988       -
    un7_cry_5_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0            ALU      CIN      In      -         5.988       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_cry_6_0_0            ALU      COUT     Out     0.035     6.023       -
    un7_cry_6_0_0_COUT                                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                ALU      CIN      In      -         6.023       -
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.un7_s_7_0                ALU      SUM      Out     0.470     6.493       -
    un7_s_7_0_SUM                                                        Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.u_RAM_based_shift_reg.\\rbin_num_Z\[9\]        DFFC     D        In      -         7.028       -
    ===============================================================================================================================
    Total path delay (propagation time + setup) of 7.089 is 3.757(53.0%) logic and 3.332(47.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                      Arrival
    Instance     Reference     Type     Pin        Net         Time        Slack
                 Clock
    -----------------------------------------------------------------------------
    osc_inst     System        OSC      OSCOUT     clk_osc     0.000       -0.080
    =============================================================================

    Ending Points with Worst Slack
    ******************************

                             Starting                                     Required
    Instance                 Reference     Type     Pin       Net         Time         Slack
                             Clock
    -----------------------------------------------------------------------------------------
    GW_PLL_inst.pll_inst     System        PLL      CLKIN     clk_osc     0.455        -0.080
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.455
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.455

        - Propagation time:                      0.535
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.080

        Number of logic level(s):                0
        Starting point:                          osc_inst / OSCOUT
        Ending point:                            GW_PLL_inst.pll_inst / CLKIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                    Pin        Pin               Arrival     No. of
    Name                     Type     Name       Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------
    osc_inst                 OSC      OSCOUT     Out     0.000     0.000       -
    clk_osc                  Net      -          -       0.535     -           1
    GW_PLL_inst.pll_inst     PLL      CLKIN      In      -         0.535       -
    =====================================================================================
    Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 190MB)

    ---------------------------------------
    Resource Usage Report for TOP

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             44 uses
    DFFC            55 uses
    DFFP            1 use
    GSR             1 use
    MUX2_LUT5       6 uses
    MUX2_LUT6       3 uses
    OSC             1 use
    PLL             1 use
    SDP             1 use
    LUT1            1 use
    LUT2            23 uses
    LUT3            11 uses
    LUT4            40 uses

    I/O ports: 9
    I/O primitives: 9
    IBUF           1 use
    OBUF           8 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   56 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 140 (0%)

    Total load per clock:
       GW_PLL|clkout_inferred_clock: 58

    @S |Mapping Summary:
    Total  LUTs: 75 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 39MB peak: 190MB)

    Process took 0h:00m:02s realtime, 0h:00m:03s cputime
    # Wed Jul 18 13:40:01 2018

    ###########################################################]

`