module TOP (
  reset,
  Q
);

parameter DSIZE = 8;//输入数据位宽
//parameter WDEPTH = 512;//对应的max shift
parameter ASIZE = 9;//log2(WDEPTH)

input reset;
wire clk ;
wire clk_osc;

output [DSIZE-1:0] Q ;
reg [DSIZE-1:0] Din ;
reg [ASIZE-1:0] ADDR ;
reg [DSIZE-1:0] Q ;

reg [9:0] cnt;

GW_OSC osc_inst (
    .oscout(clk_osc)
);

GW_PLL GW_PLL_inst(
    .clkout(clk),
    .clkin(clk_osc)
);

always @(posedge clk or posedge reset) 
 begin 
  if (reset) 
      Din <= 0;
  else 
      Din <= Din + 1;
 end

always @(posedge clk or posedge reset)
begin 
   if (reset)
     begin 
       cnt  <= 0;
       ADDR <= 2;
     end
   else if (cnt == 499) 
     begin 
       cnt <= 0;
       ADDR <= ADDR + 3;
     end
      else 
       cnt <= cnt + 1;
end

RAM_based_shift_reg_top u_RAM_based_shift_reg (
	.clk(clk),
	.Reset(reset),
	.Din(Din),
	.ADDR(ADDR),
	.Q(Q)
);

endmodule