Selecting top level module TOP
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1601:7:1601:9|Synthesizing module OSC in library work.
Running optimization stage 1 on OSC .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_osc\gw_osc.v":13:7:13:12|Synthesizing module GW_OSC in library work.
Running optimization stage 1 on GW_OSC .......
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1532:7:1532:9|Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\gw_pll\gw_pll.v":13:7:13:12|Synthesizing module GW_PLL in library work.
Running optimization stage 1 on GW_PLL .......
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on SP .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v":168:7:168:29|Synthesizing module RAM_based_shift_reg_top in library work.
Running optimization stage 1 on RAM_based_shift_reg_top .......
@W: CL168 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\RAM_based_shift_reg_top\RAM_based_shift_reg_top.v":201:6:201:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N: CG364 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\TOP.v":1:7:1:9|Synthesizing module TOP in library work.
Running optimization stage 1 on TOP .......
@W: CL169 :"D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\src\TOP.v":36:0:36:5|Pruning unused register cnt[9:0]. Make sure that there are no unused intermediate registers.
Running optimization stage 2 on TOP .......
Running optimization stage 2 on RAM_based_shift_reg_top .......
Running optimization stage 2 on \~RAM_based_shift_reg.RAM_based_shift_reg_top_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on SP .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on GW_PLL .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on GW_OSC .......
Running optimization stage 2 on OSC .......

For a summary of runtime and memory usage per design unit, please see file:
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@L: D:\user-bak\Users\FDELL\Desktop\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\synthesize\rev_1\synwork\layer0.rt.csv

