//
// Written by Synplify Pro 
// Product Version "O-2018.09G-Beta1"
// Program "Synplify Pro", Mapper "mapgw, Build 1167R"
// Tue Sep 18 08:51:28 2018
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\c:\gowin\1.8\synplifypro\lib\generic\gw2a.v "
// file 1 "\c:\gowin\1.8\synplifypro\lib\vlog\hypermods.v "
// file 2 "\c:\gowin\1.8\synplifypro\lib\vlog\umr_capim.v "
// file 3 "\c:\gowin\1.8\synplifypro\lib\vlog\scemi_objects.v "
// file 4 "\c:\gowin\1.8\synplifypro\lib\vlog\scemi_pipes.svh "
// file 5 "\d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\fixed_ex\project\src\top.v "
// file 6 "\d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\fixed_ex\project\src\gw_osc\gw_osc.v "
// file 7 "\d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\fixed_ex\project\src\gw_pll\gw_pll.v "
// file 8 "\d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\fixed_ex\project\src\ram_based_shift_reg_top\ram_based_shift_reg_top.v "
// file 9 "\c:\gowin\1.8\synplifypro\lib\nlconst.dat "

`timescale 100 ps/100 ps
module GW_OSC (
  clk_osc
)
;
output clk_osc ;
wire clk_osc ;
wire GND ;
wire VCC ;
// @6:17
  OSC osc_inst (
	.OSCOUT(clk_osc)
);
defparam osc_inst.FREQ_DIV=10;
defparam osc_inst.DEVICE="GW2A-55";
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* GW_OSC */

module GW_PLL (
  clk_osc,
  clk
)
;
input clk_osc ;
output clk ;
wire clk_osc ;
wire clk ;
wire clkoutp_o ;
wire clkoutd_o ;
wire clkoutd3_o ;
wire lock_o ;
wire GND ;
wire VCC ;
//@5:23
// @7:26
  PLL pll_inst (
	.CLKOUT(clk),
	.CLKOUTP(clkoutp_o),
	.CLKOUTD(clkoutd_o),
	.CLKOUTD3(clkoutd3_o),
	.LOCK(lock_o),
	.CLKIN(clk_osc),
	.CLKFB(GND),
	.FBDSEL({GND, GND, GND, GND, GND, GND}),
	.IDSEL({GND, GND, GND, GND, GND, GND}),
	.ODSEL({GND, GND, GND, GND, GND, GND}),
	.DUTYDA({GND, GND, GND, GND}),
	.PSDA({GND, GND, GND, GND}),
	.FDLY({GND, GND, GND, GND}),
	.RESET(GND),
	.RESET_P(GND),
	.RESET_I(GND),
	.RESET_S(GND)
);
defparam pll_inst.FCLKIN="25";
defparam pll_inst.DYN_IDIV_SEL="false";
defparam pll_inst.IDIV_SEL=4;
defparam pll_inst.DYN_FBDIV_SEL="false";
defparam pll_inst.FBDIV_SEL=35;
defparam pll_inst.DYN_ODIV_SEL="false";
defparam pll_inst.ODIV_SEL=4;
defparam pll_inst.PSDA_SEL="0000";
defparam pll_inst.DYN_DA_EN="true";
defparam pll_inst.DUTYDA_SEL="1000";
defparam pll_inst.CLKOUT_FT_DIR=1'b1;
defparam pll_inst.CLKOUTP_FT_DIR=1'b1;
defparam pll_inst.CLKOUT_DLY_STEP=0;
defparam pll_inst.CLKOUTP_DLY_STEP=0;
defparam pll_inst.CLKFB_SEL="internal";
defparam pll_inst.CLKOUT_BYPASS="false";
defparam pll_inst.CLKOUTP_BYPASS="false";
defparam pll_inst.CLKOUTD_BYPASS="false";
defparam pll_inst.DYN_SDIV_SEL=2;
defparam pll_inst.CLKOUTD_SRC="CLKOUT";
defparam pll_inst.CLKOUTD3_SRC="CLKOUT";
defparam pll_inst.DEVICE="GW2A-55";
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* GW_PLL */

`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="Synplify encryptP1735.pl"
`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"

`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="Synplicity"
`pragma protect key_keyname="SYNP05_001"
`pragma protect key_method="rsa"
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`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
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`pragma protect key_keyname="GoWin2016"
`pragma protect key_method="rsa"
`pragma protect key_block
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`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
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`pragma protect end_protected
module RAM_based_shift_reg_top (
  Q_c,
  Din,
  reset_c,
  clk
)
;
output [7:0] Q_c ;
input [7:0] Din ;
input reset_c ;
input clk ;
wire reset_c ;
wire clk ;
wire VCC ;
wire GND ;
// @8:195
  \~RAM_based_shift_reg.RAM_based_shift_reg_top__  u_RAM_based_shift_reg (
	.clk(clk),
	.Reset(reset_c),
	.Din(Din[7:0]),
	.Q(Q_c[7:0])
);
// @8:191
  GSR GSR_INST (
	.GSRI(VCC)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* RAM_based_shift_reg_top */

module TOP (
  reset,
  Q
)
;

/*  Synopsys
.origName=TOP
.langParams="DSIZE"
DSIZE=8
 */
input reset ;
output [7:0] Q ;
wire reset ;
wire [7:0] Din;
wire [7:0] Q_c;
wire [6:0] Din_cry;
wire [7:0] Din_s;
wire [7:7] Din_s_0_COUT;
wire clk_osc ;
wire clk ;
wire VCC ;
wire GND ;
wire reset_c ;
// @5:28
  DFFC \Din_Z[7]  (
	.Q(Din[7]),
	.D(Din_s[7]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[6]  (
	.Q(Din[6]),
	.D(Din_s[6]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[5]  (
	.Q(Din[5]),
	.D(Din_s[5]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[4]  (
	.Q(Din[4]),
	.D(Din_s[4]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[3]  (
	.Q(Din[3]),
	.D(Din_s[3]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[2]  (
	.Q(Din[2]),
	.D(Din_s[2]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[1]  (
	.Q(Din[1]),
	.D(Din_s[1]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:28
  DFFC \Din_Z[0]  (
	.Q(Din[0]),
	.D(Din_s[0]),
	.CLK(clk),
	.CLEAR(reset_c)
);
// @5:9
  IBUF reset_ibuf (
	.O(reset_c),
	.I(reset)
);
// @5:15
  OBUF \Q_obuf[0]  (
	.O(Q[0]),
	.I(Q_c[0])
);
// @5:15
  OBUF \Q_obuf[1]  (
	.O(Q[1]),
	.I(Q_c[1])
);
// @5:15
  OBUF \Q_obuf[2]  (
	.O(Q[2]),
	.I(Q_c[2])
);
// @5:15
  OBUF \Q_obuf[3]  (
	.O(Q[3]),
	.I(Q_c[3])
);
// @5:15
  OBUF \Q_obuf[4]  (
	.O(Q[4]),
	.I(Q_c[4])
);
// @5:15
  OBUF \Q_obuf[5]  (
	.O(Q[5]),
	.I(Q_c[5])
);
// @5:15
  OBUF \Q_obuf[6]  (
	.O(Q[6]),
	.I(Q_c[6])
);
// @5:15
  OBUF \Q_obuf[7]  (
	.O(Q[7]),
	.I(Q_c[7])
);
// @5:28
  ALU \Din_s_0[7]  (
	.CIN(Din_cry[6]),
	.I0(Din[7]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_s_0_COUT[7]),
	.SUM(Din_s[7])
);
defparam \Din_s_0[7] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[6]  (
	.CIN(Din_cry[5]),
	.I0(Din[6]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[6]),
	.SUM(Din_s[6])
);
defparam \Din_cry_0[6] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[5]  (
	.CIN(Din_cry[4]),
	.I0(Din[5]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[5]),
	.SUM(Din_s[5])
);
defparam \Din_cry_0[5] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[4]  (
	.CIN(Din_cry[3]),
	.I0(Din[4]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[4]),
	.SUM(Din_s[4])
);
defparam \Din_cry_0[4] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[3]  (
	.CIN(Din_cry[2]),
	.I0(Din[3]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[3]),
	.SUM(Din_s[3])
);
defparam \Din_cry_0[3] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[2]  (
	.CIN(Din_cry[1]),
	.I0(Din[2]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[2]),
	.SUM(Din_s[2])
);
defparam \Din_cry_0[2] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[1]  (
	.CIN(Din_cry[0]),
	.I0(Din[1]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[1]),
	.SUM(Din_s[1])
);
defparam \Din_cry_0[1] .ALU_MODE=0;
// @5:28
  ALU \Din_cry_0[0]  (
	.CIN(VCC),
	.I0(Din[0]),
	.I1(GND),
	.I3(GND),
	.COUT(Din_cry[0]),
	.SUM(Din_s[0])
);
defparam \Din_cry_0[0] .ALU_MODE=0;
// @5:19
  GW_OSC osc_inst (
	.clk_osc(clk_osc)
);
// @5:23
  GW_PLL GW_PLL_inst (
	.clk_osc(clk_osc),
	.clk(clk)
);
// @5:50
  RAM_based_shift_reg_top u_RAM_based_shift_reg (
	.Q_c(Q_c[7:0]),
	.Din(Din[7:0]),
	.reset_c(reset_c),
	.clk(clk)
);
  GND GND_cZ (
	.G(GND)
);
  VCC VCC_cZ (
	.V(VCC)
);
endmodule /* TOP */

