`

    #Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
    #install: C:\Gowin\1.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-047

    # Mon Jul 16 14:19:52 2018

    #Implementation: rev_1

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    @N: :  | : Running Verilog Compiler in System Verilog mode
    @N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode
    @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v" (library work)
    @I:"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":"E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v" (library work)
    @I::"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v" (library work)
    Verilog syntax check successful!
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v changed - recompiling
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v changed - recompiling
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v changed - recompiling
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_define.v changed - recompiling
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_name.v changed - recompiling
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\shift_reg_parameter.v changed - recompiling
    Selecting top level module RAM_based_shift_reg_top
    @N:CG364 : RAM_based_shift_reg_top.v(6) | Synthesizing module RAM_based_shift_reg_top in library work.

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 74MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Jul 16 14:19:52 2018

    ###########################################################]

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\layer0.srs changed - recompiling
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Jul 16 14:19:52 2018

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Jul 16 14:19:52 2018

    ###########################################################]

`
`

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Database state : E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\|rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11

    @N: :  | Running in 64-bit mode
    File E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_comp.srs changed - recompiling
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
    @N:NF107 : RAM_based_shift_reg_top.v(6) | Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Jul 16 14:19:54 2018

    ###########################################################]

`
`

    # Mon Jul 16 14:19:54 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  RAM_based_shift_reg_top_scck.rpt
    Printing clock  summary report in "E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    syn_allowed_resources : blockrams=140  set on top level netlist RAM_based_shift_reg_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Clock Summary
    ******************

              Start                           Requested     Requested     Clock        Clock                     Clock
    Level     Clock                           Frequency     Period        Type         Group                     Load
    ------------------------------------------------------------------------------------------------------------------
    0 -       RAM_based_shift_reg_top|clk     226.8 MHz     4.409         inferred     Autoconstr_clkgroup_0     45
    ==================================================================================================================

    Clock Load Summary
    ***********************

                                    Clock     Source        Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                           Load      Pin           Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk     45        clk(port)     u_RAM_based_shift_reg.ADDR_in[8:0].C     -                 -
    ================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 38 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       clk                 Unconstrained_port     38         ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\RAM_based_shift_reg_top.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 191MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Jul 16 14:19:55 2018

    ###########################################################]

`
`

    # Mon Jul 16 14:19:56 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: N-2018.03G-Beta6
    Install: C:\Gowin\1.8\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-047

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -2.47ns		  66 /        30
       2		0h:00m:01s		    -2.41ns		  64 /        30

       3		0h:00m:01s		    -2.41ns		  64 /        30
       4		0h:00m:01s		    -2.68ns		  66 /        30

       5		0h:00m:01s		    -2.54ns		  66 /        30

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 192MB)

    Writing Analyst data base E:\ide_prj\lossless_ex\src\RAM_based_shift_reg_top\temp\RAM_Based_Shift_Register\rev_1\synwork\RAM_based_shift_reg_top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 192MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 192MB)

    Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 192MB)

    @W:MT420 :  | Found inferred clock RAM_based_shift_reg_top|clk with period 6.06ns. Please declare a user-defined clock on port clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Mon Jul 16 14:19:59 2018
    #

    Top view:               RAM_based_shift_reg_top
    Requested Frequency:    165.1 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.069

                                    Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk     165.1 MHz     140.4 MHz     6.055         7.124         -1.069     inferred     Autoconstr_clkgroup_0
    =====================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------------------------
    RAM_based_shift_reg_top|clk  RAM_based_shift_reg_top|clk  |  6.055       -1.069  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: RAM_based_shift_reg_top|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                         Arrival
    Instance                              Reference                       Type     Pin     Net             Time        Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[1]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[1]     0.243       -1.069
    u_RAM_based_shift_reg.rbin_num[0]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[0]     0.243       -1.048
    u_RAM_based_shift_reg.rbin_num[5]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[5]     0.243       -1.048
    u_RAM_based_shift_reg.rbin_num[4]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[4]     0.243       -1.027
    u_RAM_based_shift_reg.rbin_num[2]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[2]     0.243       -0.961
    u_RAM_based_shift_reg.rbin_num[6]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[6]     0.243       -0.940
    u_RAM_based_shift_reg.ADDR_in[3]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[3]      0.243       -0.897
    u_RAM_based_shift_reg.ADDR_in[4]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[4]      0.243       -0.886
    u_RAM_based_shift_reg.rbin_num[3]     RAM_based_shift_reg_top|clk     DFFC     Q       rbin_num[3]     0.243       -0.870
    u_RAM_based_shift_reg.ADDR_in[0]      RAM_based_shift_reg_top|clk     DFFC     Q       ADDR_in[0]      0.243       -0.865
    =========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                               Required
    Instance                              Reference                       Type     Pin     Net                   Time         Slack
                                          Clock
    --------------------------------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[9]     RAM_based_shift_reg_top|clk     DFFC     D       un7_s_7_0_SUM         5.994        -1.069
    u_RAM_based_shift_reg.rbin_num[8]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_6_0_0_SUM     5.994        -1.034
    u_RAM_based_shift_reg.rbin_num[7]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_5_0_0_SUM     5.994        -0.999
    u_RAM_based_shift_reg.rbin_num[6]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_4_0_0_SUM     5.994        -0.964
    u_RAM_based_shift_reg.rbin_num[5]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_3_0_0_SUM     5.994        -0.929
    u_RAM_based_shift_reg.rbin_num[4]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_2_0_0_SUM     5.994        -0.894
    u_RAM_based_shift_reg.rbin_num[3]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_1_0_0_SUM     5.994        -0.859
    u_RAM_based_shift_reg.rbin_num[2]     RAM_based_shift_reg_top|clk     DFFC     D       un7_cry_0_0_SUM       5.994        -0.637
    u_RAM_based_shift_reg.rbin_num[0]     RAM_based_shift_reg_top|clk     DFFC     D       un7_axbxc0            5.994        1.230
    u_RAM_based_shift_reg.rbin_num[1]     RAM_based_shift_reg_top|clk     DFFC     D       un7_axbxc1            5.994        1.230
    ================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.063
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.069

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.rbin_num[1] / Q
        Ending point:                            u_RAM_based_shift_reg.rbin_num[9] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                     Pin      Pin               Arrival     No. of
    Name                                      Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[1]         DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                               Net      -        -       0.535     -           7
    u_RAM_based_shift_reg.rbin_num13_6        LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.rbin_num13_6        LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                              Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.rbin_num13          LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.rbin_num13          LUT4     F        Out     0.570     2.453       -
    rbin_num13                                Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.un4[2]              LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.un4[2]              LUT4     F        Out     0.570     3.680       -
    un4[2]                                    Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     F        Out     0.549     4.764       -
    un7_cry_0_0_RNO                           Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      I0       In      -         5.299       -
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      COUT     Out     0.549     5.848       -
    un7_cry_0                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      CIN      In      -         5.848       -
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      COUT     Out     0.035     5.883       -
    un7_cry_1                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      CIN      In      -         5.883       -
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      COUT     Out     0.035     5.918       -
    un7_cry_2                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      CIN      In      -         5.918       -
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      COUT     Out     0.035     5.953       -
    un7_cry_3                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      CIN      In      -         5.953       -
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      COUT     Out     0.035     5.988       -
    un7_cry_4                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      CIN      In      -         5.988       -
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      COUT     Out     0.035     6.023       -
    un7_cry_5                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      CIN      In      -         6.023       -
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      COUT     Out     0.035     6.058       -
    un7_cry_6                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_s_7_0           ALU      CIN      In      -         6.058       -
    u_RAM_based_shift_reg.un7_s_7_0           ALU      SUM      Out     0.470     6.528       -
    un7_s_7_0_SUM                             Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.rbin_num[9]         DFFC     D        In      -         7.063       -
    ====================================================================================================
    Total path delay (propagation time + setup) of 7.124 is 3.792(53.2%) logic and 3.332(46.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.049
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.055

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.rbin_num[1] / Q
        Ending point:                            u_RAM_based_shift_reg.rbin_num[9] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                         Pin      Pin               Arrival     No. of
    Name                                          Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[1]             DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                                   Net      -        -       0.535     -           7
    u_RAM_based_shift_reg.rbin_num13_6            LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.rbin_num13_6            LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                                  Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.rbin_num13              LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.rbin_num13              LUT4     F        Out     0.570     2.453       -
    rbin_num13                                    Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.un4[2]                  LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.un4[2]                  LUT4     F        Out     0.570     3.680       -
    un4[2]                                        Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.un7_cry_1_0_0_RNO_0     LUT2     F        Out     0.549     4.764       -
    un7_cry_1_0_0_RNO_0                           Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.un7_cry_1_0_0           ALU      I1       In      -         5.299       -
    u_RAM_based_shift_reg.un7_cry_1_0_0           ALU      COUT     Out     0.570     5.869       -
    un7_cry_1                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_2_0_0           ALU      CIN      In      -         5.869       -
    u_RAM_based_shift_reg.un7_cry_2_0_0           ALU      COUT     Out     0.035     5.904       -
    un7_cry_2                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_3_0_0           ALU      CIN      In      -         5.904       -
    u_RAM_based_shift_reg.un7_cry_3_0_0           ALU      COUT     Out     0.035     5.939       -
    un7_cry_3                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_4_0_0           ALU      CIN      In      -         5.939       -
    u_RAM_based_shift_reg.un7_cry_4_0_0           ALU      COUT     Out     0.035     5.974       -
    un7_cry_4                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_5_0_0           ALU      CIN      In      -         5.974       -
    u_RAM_based_shift_reg.un7_cry_5_0_0           ALU      COUT     Out     0.035     6.009       -
    un7_cry_5                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_6_0_0           ALU      CIN      In      -         6.009       -
    u_RAM_based_shift_reg.un7_cry_6_0_0           ALU      COUT     Out     0.035     6.044       -
    un7_cry_6                                     Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_s_7_0               ALU      CIN      In      -         6.044       -
    u_RAM_based_shift_reg.un7_s_7_0               ALU      SUM      Out     0.470     6.514       -
    un7_s_7_0_SUM                                 Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.rbin_num[9]             DFFC     D        In      -         7.049       -
    ========================================================================================================
    Total path delay (propagation time + setup) of 7.110 is 3.778(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.042
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.048

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.rbin_num[0] / Q
        Ending point:                            u_RAM_based_shift_reg.rbin_num[9] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                     Pin      Pin               Arrival     No. of
    Name                                      Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[0]         DFFC     Q        Out     0.243     0.243       -
    rbin_num[0]                               Net      -        -       0.535     -           3
    u_RAM_based_shift_reg.rbin_num13_6        LUT4     I0       In      -         0.778       -
    u_RAM_based_shift_reg.rbin_num13_6        LUT4     F        Out     0.549     1.327       -
    rbin_num13_6                              Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.rbin_num13          LUT4     I1       In      -         1.862       -
    u_RAM_based_shift_reg.rbin_num13          LUT4     F        Out     0.570     2.432       -
    rbin_num13                                Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.un4[2]              LUT4     I1       In      -         3.089       -
    u_RAM_based_shift_reg.un4[2]              LUT4     F        Out     0.570     3.659       -
    un4[2]                                    Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     I0       In      -         4.194       -
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     F        Out     0.549     4.743       -
    un7_cry_0_0_RNO                           Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      I0       In      -         5.278       -
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      COUT     Out     0.549     5.827       -
    un7_cry_0                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      CIN      In      -         5.827       -
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      COUT     Out     0.035     5.862       -
    un7_cry_1                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      CIN      In      -         5.862       -
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      COUT     Out     0.035     5.897       -
    un7_cry_2                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      CIN      In      -         5.897       -
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      COUT     Out     0.035     5.932       -
    un7_cry_3                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      CIN      In      -         5.932       -
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      COUT     Out     0.035     5.967       -
    un7_cry_4                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      CIN      In      -         5.967       -
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      COUT     Out     0.035     6.002       -
    un7_cry_5                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      CIN      In      -         6.002       -
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      COUT     Out     0.035     6.037       -
    un7_cry_6                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_s_7_0           ALU      CIN      In      -         6.037       -
    u_RAM_based_shift_reg.un7_s_7_0           ALU      SUM      Out     0.470     6.507       -
    un7_s_7_0_SUM                             Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.rbin_num[9]         DFFC     D        In      -         7.042       -
    ====================================================================================================
    Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.042
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.048

        Number of logic level(s):                12
        Starting point:                          u_RAM_based_shift_reg.rbin_num[5] / Q
        Ending point:                            u_RAM_based_shift_reg.rbin_num[9] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                     Pin      Pin               Arrival     No. of
    Name                                      Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[5]         DFFC     Q        Out     0.243     0.243       -
    rbin_num[5]                               Net      -        -       0.535     -           3
    u_RAM_based_shift_reg.rbin_num13_5        LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.rbin_num13_5        LUT4     F        Out     0.570     1.348       -
    rbin_num13_5                              Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.rbin_num13          LUT4     I0       In      -         1.883       -
    u_RAM_based_shift_reg.rbin_num13          LUT4     F        Out     0.549     2.432       -
    rbin_num13                                Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.un4[2]              LUT4     I1       In      -         3.089       -
    u_RAM_based_shift_reg.un4[2]              LUT4     F        Out     0.570     3.659       -
    un4[2]                                    Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     I0       In      -         4.194       -
    u_RAM_based_shift_reg.un7_cry_0_0_RNO     LUT2     F        Out     0.549     4.743       -
    un7_cry_0_0_RNO                           Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      I0       In      -         5.278       -
    u_RAM_based_shift_reg.un7_cry_0_0         ALU      COUT     Out     0.549     5.827       -
    un7_cry_0                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      CIN      In      -         5.827       -
    u_RAM_based_shift_reg.un7_cry_1_0_0       ALU      COUT     Out     0.035     5.862       -
    un7_cry_1                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      CIN      In      -         5.862       -
    u_RAM_based_shift_reg.un7_cry_2_0_0       ALU      COUT     Out     0.035     5.897       -
    un7_cry_2                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      CIN      In      -         5.897       -
    u_RAM_based_shift_reg.un7_cry_3_0_0       ALU      COUT     Out     0.035     5.932       -
    un7_cry_3                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      CIN      In      -         5.932       -
    u_RAM_based_shift_reg.un7_cry_4_0_0       ALU      COUT     Out     0.035     5.967       -
    un7_cry_4                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      CIN      In      -         5.967       -
    u_RAM_based_shift_reg.un7_cry_5_0_0       ALU      COUT     Out     0.035     6.002       -
    un7_cry_5                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      CIN      In      -         6.002       -
    u_RAM_based_shift_reg.un7_cry_6_0_0       ALU      COUT     Out     0.035     6.037       -
    un7_cry_6                                 Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_s_7_0           ALU      CIN      In      -         6.037       -
    u_RAM_based_shift_reg.un7_s_7_0           ALU      SUM      Out     0.470     6.507       -
    un7_s_7_0_SUM                             Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.rbin_num[9]         DFFC     D        In      -         7.042       -
    ====================================================================================================
    Total path delay (propagation time + setup) of 7.103 is 3.771(53.1%) logic and 3.332(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.055
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.994

        - Propagation time:                      7.028
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.034

        Number of logic level(s):                11
        Starting point:                          u_RAM_based_shift_reg.rbin_num[1] / Q
        Ending point:                            u_RAM_based_shift_reg.rbin_num[9] / D
        The start point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK
        The end   point is clocked by            RAM_based_shift_reg_top|clk [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    u_RAM_based_shift_reg.rbin_num[1]           DFFC     Q        Out     0.243     0.243       -
    rbin_num[1]                                 Net      -        -       0.535     -           7
    u_RAM_based_shift_reg.rbin_num13_6          LUT4     I1       In      -         0.778       -
    u_RAM_based_shift_reg.rbin_num13_6          LUT4     F        Out     0.570     1.348       -
    rbin_num13_6                                Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.rbin_num13            LUT4     I1       In      -         1.883       -
    u_RAM_based_shift_reg.rbin_num13            LUT4     F        Out     0.570     2.453       -
    rbin_num13                                  Net      -        -       0.657     -           22
    u_RAM_based_shift_reg.un4[3]                LUT4     I1       In      -         3.110       -
    u_RAM_based_shift_reg.un4[3]                LUT4     F        Out     0.570     3.680       -
    un7_3                                       Net      -        -       0.535     -           2
    u_RAM_based_shift_reg.un7_cry_1_0_0_RNO     LUT2     I0       In      -         4.215       -
    u_RAM_based_shift_reg.un7_cry_1_0_0_RNO     LUT2     F        Out     0.549     4.764       -
    un7_cry_1_0_0_RNO                           Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.un7_cry_1_0_0         ALU      I0       In      -         5.299       -
    u_RAM_based_shift_reg.un7_cry_1_0_0         ALU      COUT     Out     0.549     5.848       -
    un7_cry_1                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_2_0_0         ALU      CIN      In      -         5.848       -
    u_RAM_based_shift_reg.un7_cry_2_0_0         ALU      COUT     Out     0.035     5.883       -
    un7_cry_2                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_3_0_0         ALU      CIN      In      -         5.883       -
    u_RAM_based_shift_reg.un7_cry_3_0_0         ALU      COUT     Out     0.035     5.918       -
    un7_cry_3                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_4_0_0         ALU      CIN      In      -         5.918       -
    u_RAM_based_shift_reg.un7_cry_4_0_0         ALU      COUT     Out     0.035     5.953       -
    un7_cry_4                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_5_0_0         ALU      CIN      In      -         5.953       -
    u_RAM_based_shift_reg.un7_cry_5_0_0         ALU      COUT     Out     0.035     5.988       -
    un7_cry_5                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_cry_6_0_0         ALU      CIN      In      -         5.988       -
    u_RAM_based_shift_reg.un7_cry_6_0_0         ALU      COUT     Out     0.035     6.023       -
    un7_cry_6                                   Net      -        -       0.000     -           1
    u_RAM_based_shift_reg.un7_s_7_0             ALU      CIN      In      -         6.023       -
    u_RAM_based_shift_reg.un7_s_7_0             ALU      SUM      Out     0.470     6.493       -
    un7_s_7_0_SUM                               Net      -        -       0.535     -           1
    u_RAM_based_shift_reg.rbin_num[9]           DFFC     D        In      -         7.028       -
    ======================================================================================================
    Total path delay (propagation time + setup) of 7.089 is 3.757(53.0%) logic and 3.332(47.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

    Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB)

    ---------------------------------------
    Resource Usage Report for RAM_based_shift_reg_top

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             17 uses
    DFFC            29 uses
    GSR             1 use
    MUX2_LUT5       6 uses
    MUX2_LUT6       3 uses
    SDP             1 use
    LUT2            22 uses
    LUT3            9 uses
    LUT4            33 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   29 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 140 (0%)

    Total load per clock:
       RAM_based_shift_reg_top|clk: 31

    @S |Mapping Summary:
    Total  LUTs: 64 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 192MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Mon Jul 16 14:19:59 2018

    ###########################################################]

`