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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Tool: Synplify Pro (R)
Build: N-2018.03G-1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-047

Implementation : rev_1

# Written on Fri Sep 14 15:15:14 2018

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                           Requested     Requested     Clock        Clock                     Clock
Level     Clock                           Frequency     Period        Type         Group                     Load 
------------------------------------------------------------------------------------------------------------------
0 -       RAM_based_shift_reg_top|clk     427.1 MHz     2.341         inferred     Autoconstr_clkgroup_0     19   
==================================================================================================================


Clock Load Summary
******************

                                Clock     Source        Clock Pin                              Non-clock Pin     Non-clock Pin
Clock                           Load      Pin           Seq Example                            Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------------
RAM_based_shift_reg_top|clk     19        clk(port)     u_RAM_based_shift_reg.mem[7:0].CLK     -                 -            
==============================================================================================================================
